LTC6601IUF-2PBF_技术文档

LTC6601-2

Low Power, Low Distortion,

5MHz to 27MHz, Pin Conﬁgurable

Filter/ADC Driver

FEATURES

DESCRIPTION

The LTC^®6601-2 is a low power, low distortion, very

easy-to-use fully differential 2nd order active broadband

RC ﬁlter and driver. On-chip resistors, capacitors, and

ampliﬁer bandwidth are trimmed to provide consistent

and repeatable ﬁlter characteristics.

n

Pin Conﬁgurable Gain and Filter Response

Up to 27MHz

n

Low Power: 16mA at 3V

n

Low Distortion (2V

)

P-P

1MHz: –96dBc 2nd, –112dBc 3rd

10MHz: –65dBc 2nd, –78dBc 3rd

Theﬁltercharacteristicsarepin-strapconﬁgurable. Cutoff

frequencies range from 5MHz to 27MHz. Gain is pin-strap

programmable between –17dB and +17dB.

n

Few External Components Required

Resistors Trimmed to 0.5% Accuracy Typical

Capacitors Trimmed to 0.5% Accuracy Typical

Adjustable Output Common Mode Voltage

Rail-to-Rail Output Swing

Power Conﬁgurability and Low Power Shutdown

Tiny 0.75mm 20-Lead (4mm × 4mm) QFN Package

A three-state BIAS pin is provided to adjust ampliﬁer

power consumption. Select between low power (50%

power reduction), high performance and standby modes

with the BIAS pin.

The LTC6601 family comes in two options which trade

off distortion and noise. The LTC6601-2 offers the lowest

distortion at high frequencies. The LTC6601-1 is conﬁg-

ured for lowest noise. Both are available in pin-compatible

packages.

APPLICATIONS

n

Differential A/D Converter Driver

n

Antialiasing/Reconstruction Filter

n

Single-Ended to Differential Conversion/Ampliﬁcation

The LTC6601-2 is available in a compact 4mm × 4mm

20-pin leadless QFN package.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 6271719.

n

Low Voltage, Low Noise, Differential Signal

Processing

Common Mode Voltage Translation

n

Portable Instrumentation

TYPICAL APPLICATION

Distortion Comparison Between LTC6601-1 and LTC6602-2

15MHz Filter, Single-Ended Input, Low Power Mode

25MHz Filter, Single-Ended Input, Low Power Mode

–40

–50

–60

–70

–80

–90

–60

–70

–80

–90

–100

–110

–120

LTC6601-1 HD2

LTC6601-2 HD2

LTC6601-1 HD3

LTC6601-2 HD3

LTC6601-1 HD2

LTC6601-2 HD2

–110

LTC6601-1 HD3

LTC6601-2 HD3

–120

1

10

FREQUENCY (MHz)

100

1

10

100

FREQUENCY (MHz)

66012 TA01b

66012 TA01a

66012f

1

LTC6601-2

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

+

–

Total Supply Voltage (V to V )...............................5.5V

TOP VIEW

+

–

Input Voltage (Any Pin) (Note 2)..V + 0.3V to V –0.3V

Input Current (V , BIAS).................................. 10mA

20 19 18 17 16

OCM

Input Current (Pins 1, 5) (Note 2)........................ 20mA

Input Current (Pins 2, 4) (Note 2)........................ 30mA

Input Current (Pins 6, 20) (Note 2)...................... 15mA

Input Current (Pins 7, 8, 9, 10, 16, 17, 18, 19)

(Note 2)................................................................ 10mA

Output Short-Circuit Duration (Note 3) ............ Indeﬁnite

Operating Temperature Range (Note 4)....–40°C to 85°C

Speciﬁed Temperature Range (Note 5) ....–40°C to 85°C

Junction Temperature ........................................... 150°C

Storage Temperature Range...................–65°C to 150°C

+

–

IN2

IN1

OUT

1

2

3

4

5

15

14

13

12

11

+

V

–

BIAS

V

21

8

–

IN1

V

OCM

+

–

IN2

OUT

6

7

9 10

UF PACKAGE

20-LEAD (4mm s 4mm) PLASTIC QFN

T

= 150°C, θ = 37°C/W, θ = 4.3°C/W

JA JC

JMAX

–

EXPOSED PAD (PIN 21) IS V , MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC6601CUF-2#PBF

LTC6601IUF-2#PBF

LTC6601CUF-2#TRPBF

LTC6601IUF-2#TRPBF

66012

20-Lead (4mm × 4mm) Plastic QFN

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

DC ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V⁺= 3V, V^–= 0V, V_INCM= V_OCM= mid-supply, BIAS tied to V⁺or ﬂoating,

I_LOAD= 0, R_BAL= 100k. The ﬁlter is conﬁgured for a gain of 1 unless otherwise noted. V_Sis deﬁned as (V⁺– V^–). V_OUTCMis deﬁned as

(V_OUT⁺+ V_OUT^–)/2. V_INCMis deﬁned as (V_INP+ V_INM)/2. V_OUTDIFFis deﬁned as (V_OUT⁺– V_OUT^–). V_INDIFFis deﬁned as (V_INP– V_INM). See

Figure 1.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

(Note 6)

Ampliﬁer Differential Offset Voltage (Input

Referred)

V = 2.7V to 5.25V, BIAS = Floating

0.25

2

1.25

mV

OSDIFF

S

+

BIAS = V

Ampiﬁer Differential Offset Voltage Drift

(Input Referred)

V = 2.7V to 5.25V

S

1

μV/°C

ΔV

/ΔT

OSDIFF

(Note 6)

+

R

IN

(Note 14)

Input Resistance, BIAS = V

Single Ended Input Resistance, Pin 2 or Pin 4 V = 3V

Differential Input Resistance

133

200

Ω

S

V = 3V

S

66012f

2

LTC6601-2

DC ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V⁺= 3V, V^–= 0V, V_INCM= V_OCM= mid-supply, BIAS tied to V⁺or ﬂoating,

I_LOAD= 0, R_BAL= 100k. The ﬁlter is conﬁgured for a gain of 1 unless otherwise noted. V_Sis deﬁned as (V⁺– V^–). V_OUTCMis deﬁned as

(V_OUT⁺+ V_OUT^–)/2. V_INCMis deﬁned as (V_INP+ V_INM)/2. V_OUTDIFFis deﬁned as (V_OUT⁺– V_OUT^–). V_INDIFFis deﬁned as (V_INP– V_INM). See

Figure 1.

SYMBOL

ΔR (Note 14)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

Input Resistance Match, BIAS = V

Single Ended Input Resistance, Pin 2 or Pin 4 V = 3V

IN

l

0.25

Ω

S

l

I (Note 7)

B

Internal Ampliﬁer Input Bias

V = 2.7V to 5V

S

BIAS = Floating

–25

–50

–12.5

–25

0

μA

+

BIAS = V

l

I

OS

(Note 7)

Internal Ampliﬁer Input Offset

V = 2.7V to 5V

S

BIAS = Floating

1

5

10

μA

+

BIAS = V

V

(Note 8)

Input Signal Common Mode Range

INCM

(V + V )/2

INP

INM

+

l

BIAS = V , V

= 2.5V

= 1.5V

V = 5V

0

4.7

1.7

V

OCM

S

+

BIAS = V , V

V = 3V

S

l

BIAS Pin Floating, V

= 2.5V

= 1.5V

V = 5V

S

0

4.8

1.8

V

OCM

S

V = 3V

CMRRI

(Notes 9, 14)

Input Common Mode Rejection Ratio

(Ampliﬁer Input Referred) ΔV /ΔV

INCM

OSDIFF

ΔV

= 2.5V

V = 5V

74

70

dB

S

CMRRO

(Notes 9, 14)

Output Common Mode Rejection Ratio

(Ampliﬁer Input Referred) ΔV /ΔV

OCM

OSDIFF

ΔV

= 1V

V = 5V

S

PSRR (Note 10)

Power Supply Rejection Ratio

(Ampliﬁer Input Referred) ΔV /ΔV

S

OSDIFF

l

BIAS Pin Floating

V = 2.7V to 5V

58

94

81

dB

S

+

BIAS = V

V = 2.7V to 5V

S

PSRRCM (Note 10) Common Mode Power Supply Rejection Ratio

(ΔV /ΔV

l

)

V = 2.7V to 5V

40

51

1

dB

V/V

%

S

OSCM

S

g

cm

Common Mode Gain (ΔV

OCM

/ΔV

OUTCM

)

OCM

V = 5V

S

ΔV

= 2V

Common Mode Gain Error = 100 • (g – 1)

cm

l

ΔV

OCM

= 2V

V = 5V

S

0.3

1.0

BAL

Output Balance (ΔV

Single-Ended Input

Differential Input

/ΔV

OUTCM

)

ΔV

S

V = 5V

S

= 2V

OUTDIFF

l

–58

–62

–40

dB

V = 5V

l

V

OSCM

Common Mode Offset Voltage

(V – V

V = 2.7V to 5V

S

BIAS = Floating

15

30

mV

S

+

)

V = 2.7V to 5V

BIAS = V

OUTCM

OCM

l

Common Mode Offset Voltage Drift

(V – V

V = 2.7V to 5V

S

BIAS = Floating

20

μV/°C

ΔV /ΔT

OSCM

S

+

)

V = 2.7V to 5V

BIAS = V

OUTCM

OCM

V

(Note 8) Output Signal Common Mode Range

OUTCMR

l

(Voltage Range for the V

Pin)

V = 3V

BIAS Pin Floating

1.1

1.8

4

1.7

4

V

OCM

S

V = 5V

S

+

V = 3V

BIAS = V

S

+

V = 5V

BIAS = V

S

l

R

Input Resistance, V

V = 3V

5

7

9

kꢀ

V

INVOCM

OCM

S

V

Voltage at the V

V = 3V

S

1.475

1.5

1.525

MID

OCM

66012f

3

LTC6601-2

DC ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V⁺= 3V, V^–= 0V, V_INCM= V_OCM= mid-supply, BIAS tied to V⁺or ﬂoating,

I_LOAD= 0, R_BAL= 100k. The ﬁlter is conﬁgured for a gain of 1 unless otherwise noted. V_Sis deﬁned as (V⁺– V^–). V_OUTCMis deﬁned as

(V_OUT⁺+ V_OUT^–)/2. V_INCMis deﬁned as (V_INP+ V_INM)/2. V_OUTDIFFis deﬁned as (V_OUT⁺– V_OUT^–). V_INDIFFis deﬁned as (V_INP– V_INM). See

Figure 1.

SYMBOL

PARAMETER

CONDITIONS

V = 3V, I = 0mA, BIAS Pin Floating

MIN

TYP

MAX

UNITS

l

V

Output Voltage, High, Either Output Pin

(Note 11)

240

290

470

370

430

650

450

525

850

675

775

1100

mV

OUT

S

L

V = 3V, I = –5mA, BIAS Pin Floating

S

L

V = 3V, I = –20mA, BIAS Pin Floating

S

L

V = 5V, I = 0mA, BIAS Pin Floating

S

L

V = 5V, I = –5mA, BIAS Pin Floating

S

L

V = 5V, I = –20mA, BIAS Pin Floating

S

L

+

l

V = 3V, I = 0mA

BIAS = V

245

285

415

350

390

550

450

525

750

625

700

1000

mV

S

L

V = 3V, I = –5mA BIAS = V

S

L

V = 3V, I = –20mA BIAS = V

S

L

V = 5V, I = 0mA

BIAS = V

V = 5V, I = –5mA BIAS = V

S

L

S

L

V = 5V, I = –20mA BIAS = V

S

L

l

Output Voltage, Low, Either Output Pin

(Note 11)

V = 3V, I = 0mA, BIAS Pin Floating

110

120

170

150

170

225

200

225

300

270

300

400

mV

S

L

V = 3V, I = 5mA, BIAS Pin Floating

S

L

V = 3V, I = 20mA, BIAS Pin Floating

S

L

V = 5V, I = 0mA, BIAS Pin Floating

S

L

V = 5V, I = 5mA, BIAS Pin Floating

S

L

V = 5V, I = 20mA, BIAS Pin Floating

S

L

+

l

V = 3V, I = 0mA

BIAS = V

120

135

195

175

200

270

225

250

350

325

360

475

mV

S

L

V = 3V, I = 5mA

S

L

V = 3V, I = 20mA BIAS = V

S

L

V = 5V, I = 0mA

BIAS = V

S

L

V = 5V, I = 5mA

S

L

V = 5V, I = 20mA BIAS = V

S

L

l

I

SC

Output Short-Circuit Current,

Either Output Pin (Note 12)

V = 3V

S

45

60

65

90

mA

S

V = 5V

l

V

S

Supply Voltage Range

2.7

5.25

V

l

I

Supply Current, BIAS Pin Floating

V = 2.7V

15.8

16

23

mA

S

V = 3V

23.5

24.5

S

V = 5V

16.7

S

+

l

Supply Current, BIAS Pin Tied to V

V = 2.7V

32

32.2

33

41

41.5

43

mA

S

V = 3V

S

V = 5V

S

–

l

I

Supply Current, BIAS Pin Tied to V

V = 2.7V

0.4

0.45

0.65

1

1.1

1.8

mA

SHDN

S

V = 3V

S

V = 5V

S

–

l

V

BIAS Input Pin Range for Shutdown

(Note 13) BIAS Input for Low Power Operation

BIAS Input for High Performance Operation

BIAS Input Resistance

V = 2.7V to 5V

S

V

V + 0.4

V

BIASSD

BIASLP

BIASHP

–

V = 2.7V to 5V

S

V + 1.0

V + 1.5

–

+

V = 2.7V to 5V

S

V + 2.3

V

R

V = 2.7V to 5V

S

100

150

–

200

kꢀ

V

BIAS

–

V

BIAS Float Voltage

V = 2.7V to 5V

S

V + 1.05 V + V + 1.25

1.15

t

Turn-On Time

Turn-Off Time

V = 3V, V

= 0.25V to 3V

= 3V to 0.25V

400

ns

ON

S

SHDN

V = 3V, V

OFF

S

SHDN

66012f

4

LTC6601-2

AC ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V⁺= 3V, V^–= 0V, V_INCM= V_OCM= mid-supply, V_BIASis tied to V⁺or

+

ﬂoating, unless otherwise noted. (See Figure 2 for the AC test conﬁguration.) V_Sis deﬁned as (V⁺– V^–). V_OUTCMis deﬁned as (V_OUT

+

V_OUT^–)/2. V_ICMis deﬁned as (V_INP+ V_INM)/2. V_OUTDIFFis deﬁned as (V_OUT⁺– V_OUT^–). V_INDIFFis deﬁned as (V_INP– V_INM).

SYMBOL

PARAMETER

CONDITIONS

ΔV 0.25V, f

MIN

TYP

MAX

UNITS

l

GAIN

Filter Gain, See Figure 2,

BIAS Pin Floating (Remaining AC

Measurements Relative to 1MHz)

–0.25

0.05

0

0.02

0.11

–0.34

–2.50

–6.55

0.25

dB

=

= DC (Note 14)

TEST

IN

V

= 600mV , f

= 1MHz

IN

P-P TEST

–0.08

–0.01

–0.54

–3.00

–7.55

0.12

0.23

–0.14

–2.00

–5.55

= 600mV , f

= 2MHz

= 5MHz

= 10MHz

= 14.45MHz

= 20MHz

= 50MHz

= 600mV , f

P-P TEST

= 600mV , f

P-P TEST

= 600mV , f

P-P TEST

= 600mV , f

P-P TEST

–23.55 –21.55 –19.55

= 600mV , f

P-P TEST

l

PHASE

Filter Phase, See Figure 2,

BIAS Pin Floating

0

Deg

ΔV

=

0.25V, f

= DC

TEST

IN

–6.0

–12.5

–31.8

–70.1

–103.5

–5.5

–4.8

–10.1

–26.8

–60.1

–91.5

V

= 600mV , f

= 1MHz

IN

P-P TEST

–11.3

–29.3

–65.2

–97.5

= 600mV , f

= 2MHz

= 5MHz

= 10MHz

= 14.45MHz

= 20MHz

= 50MHz

= 600mV , f

–130.7 –125.1 –120.7

–173.6

= 600mV , f

NOISE

SNR

Output Noise, See Figure 2,

BIAS Pin Floating

BW = 100MHz

BW = 20MHz

154

135

μV

RMS

BIAS Pin Floating

BW = 100MHz

BW = 20MHz

73

74

dB

Distortion

V

IN

= 2V , 10MHz, BIAS Pin Floating

HD2, Single-Ended Input

HD3, Single-Ended Input

HD2, Differential Input

HD3, Differential Input

–60

–79

–65

–77

dBc

P-P

f TC

Cutoff Frequency Temperature Coefﬁcient

Filter Gain, See Figure 2,

–120

ppm/°C

O

l

GAIN

–0.25

0.05

0

0.02

0.11

–0.34

–2.35

–6.24

0.25

dB

ΔV

=

0.25V, f

= DC (Note 14)

TEST

IN

+

BIAS Pin Tied to V ,

V

= 600mV , f

= 1MHz

IN

P-P TEST

AC Gain Measurements Relative to 1MHz

–0.08

–0.01

–0.54

–2.75

–7.14

0.12

0.23

–0.14

–1.95

–5.34

= 600mV , f

= 2MHz

= 5MHz

= 10MHz

= 14.45MHz

= 20MHz

= 50MHz

= 600mV , f

–23.70 –21.70 –19.70

= 600mV , f

l

PHASE

Filter Phase, See Figure 2,

0

Deg

ΔV

=

0.25V, f

= DC

TEST

IN

+

BIAS Pin Tied to V

–6.0

–12.2

–31.2

–68.8

–101.5

–5.4

–11

–4.8

–9.8

–26.2

–58.8

–89.5

V

= 600mV , f

= 1MHz

IN

P-P TEST

= 600mV , f

= 2MHz

= 5MHz

= 10MHz

= 14.45MHz

= 20MHz

= 50MHz

–28.7

–63.8

–95.5

= 600mV , f

–128.4 –123.4 –118.4

–169.3

= 600mV , f

NOISE

SNR

Wide Band Output Noise, 14.45MHz Cutoff,

BW = 100MHz

BW = 20MHz

108

97

μV

RMS

+

BIAS Pin Tied to V

+

BIAS Pin Tied to V

BW = 100MHz

BW = 20MHz

76

77

dB

+

DISTORTION V = 2V , 10MHz, BIAS Pin Tied to V

HD2, Single-Ended Input

HD3, Single-Ended Input

HD2, Differential Input

HD3, Differential Input

–67.5

–90

–70

–90

dBc

IN

P-P

f TC

O

Cutoff Frequency Temperature Coefﬁcient

–120

ppm/°C

66012f

5

LTC6601-2

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under the Absolute Maximum

Ratings may cause permanent damage to the device. Exposure to any

Absolute Maximum Rating condition for extended periods may affect

device reliability and lifetime.

the mid-supply common mode input case by more than 1%, and the

common mode offset (V ) has not deviated from the mid-supply

common mode offset by more than 20mV.

OCMOS

The voltage range for the output common mode range is tested using the

test circuit of Figure 1 by measuring the differential DC gain with V

=

Note 2: All pins are protected by steering diodes to either supply. If any

pin is driven beyond the part’s supply voltage, the excess input current

(current in excess of what it takes to drive that pin to the supply rail)

should be limited to less than 10mA.

OCM

mid-supply, and again with a voltage set on the V

pin at the Electrical

OCM

Characteristics table limits, checking the differential gain has not deviated

from the mid-supply common mode input case by more than 1%, and that

the common mode offset (V

from the mid-supply case.

Note 9: Input CMRR is deﬁned as the ratio of the change in the input

common mode voltage at the ampliﬁer input to the change in differential

input referred voltage offset. Output CMRR is deﬁned as the ratio of the

change in the voltage at the V

referred voltage offset.

Note 10: Power supply rejection (PSRR) is deﬁned as the ratio of the

change in supply voltage to the change in differential input referred voltage

offset. Common mode power supply rejection (PSRRCM) is deﬁned as the

ratio of the change in supply voltage to the change in the common mode

) has not deviated by more than 20mV

OCMOS

Note 3: A heat sink may be required to keep the junction temperature

below the Absolute Maximum Rating when the output is shorted

indeﬁnitely. Long-term application of output currents in excess of the

Absolute Maximum Ratings may impair the life of the device.

Note 4: The LTC6601C/LTC6601I are guaranteed functional over the

operating temperature range –40°C to 85°C.

Note 5: The LTC6601C is guaranteed to meet speciﬁed performance from

0°C to 70°C. The LTC6601C is designed, characterized, and expected

to meet speciﬁed performance from –40°C to 85°C but is not tested or

QA sampled at these temperatures. The LTC6601I is guaranteed to meet

speciﬁed performance from –40°C to 85°C.

Note 6: Output referred voltage offset is a function of the low frequency

gain of the LTC6601. To determine output referred voltage offset, or output

voltage offset drift, multiply this speciﬁcation by the noise gain (1 + GAIN).

See Applications Information for more details.

pin to the change in differential input

OCM

offset, V

/V

.

OUTCM OCM

Note 11: Output swings are measured as differences between the output

and the respective power supply rail.

Note 12: Extended operation with the output shorted may cause junction

temperatures to exceed the 150°C limit and is not recommended.

Note 7: Input bias current is deﬁned as the average of the currents

ﬂowing into the noninverting and inverting inputs of the internal ampliﬁer

and is calculated from measurements made at the pins of the IC. Input

offset current is deﬁned as the difference of the currents ﬂowing into the

noninverting and inverting inputs of the internal ampliﬁer and is calculated

from measurements made at the pins of the IC.

Note 13: Floating the BIAS pin will reliably place the part into the half-

power mode. The pin does not have to be driven. Care should be taken,

however, to prevent external leakage currents in or out of this pin from

pulling the pin into an undesired state.

Note 14: The variable contact resistance of the high speed test equipment

limits the accuracy of this test. These parameters only show a typical

value, or conservative minimum and maximum value.

Note 8: Input common mode range is tested using the test circuit of

Figure 1 by measuring the differential DC gain with V

= mid-supply, and

ICM

with V

at the input common mode range limits listed in the Electrical

ICM

Characteristics table, verifying the differential gain has not deviated from

66012f

6

LTC6601-2

TYPICAL PERFORMANCE CHARACTERISTICS

High Performance Supply Current

vs Temperature and

Shutdown Supply Current

vs Temperature and

Supply Voltage

Low Power Supply Current

vs Temperature and

Supply Voltage

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

18.0

17.5

17.0

16.5

16.0

15.5

15.0

35

34

33

32

31

30

V

= V

= MID-SUPPLY

OCM

V

= V

= MID-SUPPLY

V

= V

= MID-SUPPLY

OCM

INCM

OCM

INCM

–

+

BIAS PIN TIED TO V

BIAS PIN FLOATING

BIAS PIN TIED TO V

5V

3V

2.7V

3V

2.7V

3V

2.7V

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

66012 G03

66012 G01

66012 G02

Shutdown Supply Current

vs Supply Voltage and Temperature

Supply Current vs Bias Pin

Voltage and Temperature

Low Power Mode Supply Current

vs Supply Voltage and Temperature

50

40

30

20

10

0

1

0.1

100

10

V

= V

= MID-SUPPLY

OCM

INCM

S

= 3V

125°C

–40°C

25°C

1

–40°C

25°C

0.1

0.01

0.001

–40°C

25°C

125°C

0.01

0.001

V

= V

= MID-SUPPLY

OCM

V

= V

= MID-SUPPLY

OCM

INCM

–

BIAS PIN TIED TO V

BIAS PIN FLOATING

0

0.5

1

1.5

2

2.5

3

0

1

2

3

4

5

0

1

2

3

4

5

–

BIAS PIN VOLTAGE WITH RESPECT TO V (V)

SUPPLY VOLTAGE (V)

66012 G04

66012 G05

66012 G06

High Performance Supply Current

vs Supply Voltage and Temperature

High Performance Mode

Differential V_OSvs Temperature

Low Power Mode Differential V_OS

vs Temperature

100

10

1.00

0.75

1.00

0.75

V

= 3V

INCM

BIAS PIN TIED TO V

V

= 3V

S

INCM

BIAS PIN FLOATING

S

= V

= MID-SUPPLY

= V

= MID-SUPPLY

OCM

125°C

+

5 REPRESENTATIVE UNITS

0.50

–40°C

0.25

1

0.00

0.1

–0.25

–0.50

–0.75

–1.00

–0.25

–0.50

–0.75

–1.00

25°C

0.01

0.001

V

= V

= MID-SUPPLY

OCM

INCM

+

BIAS PIN TIED TO V

0

1

2

3

4

5

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

66012 G07

66012 G08

66012 G09

66012f

7

LTC6601-2

TYPICAL PERFORMANCE CHARACTERISTICS

High Performance Common Mode

V_OSvs Temperature

Low Power Common Mode V_OS

vs Temperature

Internal Ampliﬁer Input Bias

Current vs Temperature

–5

–10

–15

–20

–25

–30

10

5

15

10

5

LOW POWER MODE

(BIAS PIN FLOATING)

0

HIGH PERFORMANCE MODE

+

(BIAS PIN TIED TO V )

–5

–10

–15

–5

V

= 3V

INCM

BIAS PIN TIED TO V

V

= 3V

INCM

BIAS PIN FLOATING

S

= V

= MID-SUPPLY

OCM

= V

= MID-SUPPLY

OCM

+

V

= 3V

INCM

S

= V

= MID-SUPPLY

OCM

0

5 REPRESENTATIVE UNITS

–10

–50 –25

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

66012 G12

66012 G10

66012 G11

BIAS Pin Float Voltage

vs Temperature

Filter Input Resistance

vs Temperature

BIAS Pin Input Resistance

vs Temperature

1.20

1.15

1.10

1.05

1.00

1.0050

1.0025

1.0000

0.9975

0.9950

200

175

150

125

100

V

= 3V

S

INCM

NOMINAL

V

= 3V

INCM

V

= 3V

INCM

S

= V = MID-SUPPLY

= V

= MID-SUPPLY

OCM

= V

= MID-SUPPLY

OCM

R

= 200Ω DIFFERENTIAL

= 133.3Ω SINGLE-ENDED

SEE FIGURE 1 FOR CONFIGURATION

SINGLE-ENDED

DIFFERENTIAL

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

66012 G14

66012 G15

66012 G13

High Performance Mode

Frequency Response of 12

Possible Filter Conﬁgurations

Low Power Mode Frequency

Response of 12 Possible Filter

Conﬁgurations

Low Frequency Gain

vs Temperature

1.010

1.005

1.000

0.995

0.990

V

= 3V

INCM

S

= V

= MID-SUPPLY

OCM

10

0

10

0

5 REPRESENTATIVE UNITS

–10

–20

–30

–10

–20

–30

V

= 3V

INCM

BIAS PIN TIED TO V

V

= 3V

S

INCM

BIAS PIN FLOATING

S

= V

= MID-SUPPLY

= V

= MID-SUPPLY

OCM

+

–50 –25

0

25

50

75 100 125

0.1

1

10

100

0.1

1

10

100

TEMPERATURE (°C)

FREQUENCY (MHz)

66012 G16

66012 G17

66012 G18

66012f

8

LTC6601-2

TYPICAL PERFORMANCE CHARACTERISTICS

High Performance Mode Gain

and Phase Repeatability of 10

Random Units

Low Power Mode Gain and Phase

Repeatability of 10 Random Units

0.20

0.15

0.10

0.05

0

4

0.20

0.15

0.10

0.05

0

4

V

= 3V

INCM

V

= 3V

S

INCM

S

= V

= MID-SUPPLY

= V

= MID-SUPPLY

OCM

3

+

BIAS PIN TIED TO V

SEE FIGURE 1

BIAS PIN FLOATING

SEE FIGURE 1

2

J

– J

AVERAGE

J

– J

AVERAGE

MAX

1

MAX – AVERAGE

0

MIN – AVERAGE

–0.05

–0.10

–0.15

–0.20

–1

–2

–3

–4

–0.05

–0.10

–0.15

–0.20

–1

–2

–3

J

– J

MIN

AVERAGE

J

MIN

– J

AVERAGE

–4

0.1

1

10

100

0.1

1

10

100

FREQUENCY (MHz)

66012 G19

66012 G20

Low Power Mode Gain Error of

10 Random Units Normalized to

1MHz

High Performance Mode Gain Error

of 10 Random Units Normalized to

1MHz

High Performance Mode Phase

Error of 10 Random Units

3

2

8

6

3

2

V

= 3V

ICM

BIAS PIN FLOATING

V

= 3V

ICM

BIAS PIN TIED TO V+

V

T

= V

= MID-SUPPLY

OCM

S

ICM

S

A

S

= V

= MID-SUPPLY

OCM

= V

= MID-SUPPLY

= 3V

OCM

= 25°C

10 RANDOM UNITS PLOTTED

4

T

= 25°C

T

= 25°C

A

+SPECIFICATION

1

2

+SPECIFICATION

0

–2

–4

–6

–8

–1

–2

–3

–1

–2

–3

–SPECIFICATION

BIAS PIN TIED TO V+

10 RANDOM UNITS PLOTTED

1

10

100

1

10

100

1

10

100

FREQUENCY (MHz)

66012 G22

66012 G23

66012 G21

Low Power Mode Phase Error of

10 Random Units

Turn On and Turn Off Transient

Response

Pulse Response

5

4

1.6

2

8

6

V

= 5V

V

= V

= MID-SUPPLY

V = 3V

S

ICM

S

A

OCM

BIAS PIN

= 3V

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

T

= 25°C

3

1

0

4

2

+SPECIFICATION

2

1

0

–1

–2

–3

–4

–5

–2

–4

–6

–8

–SPECIFICATION

–1

–2

V

OUTDIFF

1

BIAS PIN FLOATING

10 RANDOM UNITS PLOTTED

0

2

3

4

5

6

0

1

2

3

4

5

6

7

8

1

10

100

TIME (μs)

FREQUENCY (MHz)

66012 G25

66012 G26

66012 G24

66012f

9

LTC6601-2

TYPICAL PERFORMANCE CHARACTERISTICS

Distortion vs Frequency

Differential Output Noise

Distortion vs Frequency

100

10

1

1000

100

10

–60

–70

–50

–60

V

= 5V

V

= 3V

V

= 5V

S

HD2

S

HD2

SPECTRAL DENSITY,

= 2V INPUT

P-P

= 2V INPUT

IN

ICM

P-P

IN

ICM

+

= V

= MID-SUPPLY

BIAS TIED TO V

OCM

= V

OCM

BIAS PIN TIED TO V+

= MID-SUPPLY

–80

–70 BIAS PIN FLOATING

SPECTRAL DENSITY,

BIAS PIN FLOATING

–90

–80

–90

HD3

–100

–110

–120

–130

INTEGRATED NOISE,

+

BIAS TIED TO V

–100

–110

–120

INTEGRATED NOISE,

BIAS PIN FLOATING

SINGLE ENDED INPUT

DIFFERENTIAL INPUT

SINGLE ENDED INPUT

DIFFERENTIAL INPUT

0.1

1

0.001

0.01

0.1

1

10

100

0.1

1

10

100

0.1

1

10

100

FREQUENCY (MHz)

66012 G27

66012 G28

66012 G29

Gain Error Relative to 1MHz

vs Temperature

Passband Gain and Phase

vs Temperature

% Change of f_Ovs Temperature

3

2

0.5

0

0.5

0

V

= 3V

ICM

S

= V

= MID-SUPPLY

OCM

–15

BIAS PIN TIED TO V+

TEMPERATURES PLOTTED:

–45°C, –10°C, 25°C,

70°C, 95°C, 125°C

GAIN

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–30

–45

–60

–75

–90

–105

1

PHASE

–0.5

–1.0

–1.5

–2.0

+SPECIFICATION

0

–1

–2

–3

V

= 3V

ICM

BIAS PIN TIED TO V+

–SPECIFICATION

S

= V

= MID-SUPPLY

OCM

TEMPERATURES PLOTTED:

–45°C, –10°C, 25°C, 70°C, 95°C, 125°C

1

10

100

–50 –25

0

25

50

75 100 125

1

10

FREQUENCY (MHz)

TEMPERATURE (°C)

FREQUENCY (MHz)

66012 G32

66012 G30

66012 G31

Phase Error vs Temperature

Normalized 100Ω Resistor Trim

Normalized 125Ω Resistor Trim

15

10

5

900

800

700

600

500

400

300

200

100

0

1000

900

800

700

600

500

400

300

200

100

0

AVERAGE = 100ꢀ

STD. DEV = 0.19ꢀ

V

= 3V

ICM

AVERAGE = 125ꢀ

STD. DEV = 0.22ꢀ

S

= V

= MID-SUPPLY

OCM

BIAS PIN TIED TO V+

TEMPERATURES PLOTTED:

–45°C, –10°C, 25°C,

70°C, 95°C, 125°C

+SPECIFICATION

0

–5

–10

–15

–SPECIFICATION

1

10

100

0.993

0.997

1.001

1.005

1.009

0.99

0.994 0.998 1.002 1.006

NORMALIZED RESISTANCE

1.01

FREQUENCY (MHz)

NORMALIZED RESISTANCE

66012 G33

66012 G34

66012 G35

66012f

10

LTC6601-2

TYPICAL PERFORMANCE CHARACTERISTICS

Normalized Feedback 400Ω

Resistor Trim

Normalized Input 400Ω

Resistor Trim

Normalized 200Ω Resistor Trim

1000

900

800

700

600

500

400

300

200

100

0

1000

900

800

700

600

500

400

300

200

100

0

900

800

700

600

500

400

300

200

100

0

AVERAGE = 200ꢀ

STD. DEV = 0.37ꢀ

AVERAGE = 400.01ꢀ

STD. DEV = 0.87ꢀ

AVERAGE = 400.01ꢀ

STD. DEV = 1.0ꢀ

0.99

0.994 0.998 1.002 1.006

NORMALIZED RESISTANCE

1.01

0.99

0.994 0.998 1.002 1.006

NORMALIZED RESISTANCE

1.01

0.99

0.994 0.998 1.002 1.006

NORMALIZED RESISTANCE

1.01

66012 G36

66012 G38

66012 G37

Normalized 33.3pF

Capacitor Trim

Normalized 48.2pF

Capacitor Trim

Normalized 21.1pF Capacitor Trim

1000

900

800

700

600

500

400

300

200

100

0

1200

1000

800

600

400

200

0

1200

1000

800

600

400

200

0

AVERAGE = 33.3pF

STD. DEV = 0.09pF

AVERAGE = 21.1pF

STD. DEV = 0.07pF

AVERAGE = 48.2pF

STD. DEV = 0.08pF

0.988 0.993 0.999 1.005 1.010 1.016

0.984 0.990 0.997 1.003 1.009 1.015

0.992 0.995 0.998 1.001 1.004 1.007 1.010

NORMALIZED CAPACITANCE

66012 G40

66012 G39

66012 G41

Normalized 10.55pF

Capacitor Trim

Normalized 16.1pF

Capacitor Trim

Normalized 81.5pF

Capacitor Trim

350

300

250

200

150

100

50

1000

900

800

700

600

500

400

300

200

100

0

400

350

300

250

200

150

100

50

AVERAGE = 16.1pF

STD. DEV = 0.05pF

AVERAGE = 81.5pF

STD. DEV = 0.1pF

AVERAGE = 10.55pF

STD. DEV = 0.03pF

0

0.988 0.992 0.995 0.999 1.003 1.006 1.010 1.014

0.993 0.996 0.999 1.002 1.004 1.007 1.010

0.987 0.991 0.996 1.000 1.005 1.009 1.014

NORMALIZED CAPACITANCE

66012 G44

66012 G42

66012 G43

66012f

11

LTC6601-2

PIN FUNCTIONS ^{(Refer to the Block Diagram)}

+

IN1 , IN2 , IN4 (Pins2, 1, 20):Inputtoatrimmed100ꢀ,

C3, C4 (Pins 9, 10): Input to a trimmed 10.55pF, 21.1pF

200ꢀ,400ꢀresistorwhichfeedsanoninvertingsumming

node.Canacceptaninputsignal,beﬂoatedortiedtoOUT .

capacitor which feeds the ampliﬁer inverting summing

–

+

node. Typically, either ﬂoat or tie to OUT . For best per-

Forbestperformance, straycapacitanceshouldbekeptas

low as possible by keeping printed circuit connections as

short and direct as possible. If necessary, strip back the

surrounding ground plane away from these pins.

formance,itishighlyrecommendedthatstraycapacitance

be kept to as low as possible by keeping printed circuit

connections as short and direct as possible, and if nec-

essary, stripping back nearby surrounding ground plane

away from these pins.

BIAS (Pin 3): Input to a three-state comparator whose

three states allow the user to tailor ampliﬁer power. The

pin impedance appears as a 150k resistor whose default

+

–

OUT , OUT (Pins 11, 15): Output Pins. Besides driving

the internal feedback network, each pin can drive an ad-

ditional 50ꢀ to ground with typical short-circuit current

limitingof 65mA. Capacitiveloadingofthesepinsshould

be minimized by resistively decoupling the outputs from

the load with at least 25ꢀ.

–

open-circuitpotentialis1.15VwithrespecttotheV power

–

supply. IfBIASisdriventowithin0.4VoftheV supply, the

ampliﬁer is placed into a low power shutdown, consum-

ing typically 450μA. When BIAS is ﬂoated, the ampliﬁer

operates in its low power active state. Forcing the pin 2.3V

V

(Pin 12): Output Common Mode Reference Voltage.

OCM

ThevoltageonV

–

above V places the part into the high performance active

setstheoutputcommonmodevoltage

OCM

state. See Applications Information for more detail.

level (which is deﬁned as the average of the voltages on

–

+

–

IN1 , IN2 , IN4 (Pins 4, 5, 6): Input to a trimmed 100ꢀ,

200ꢀ, 400ꢀ resistor which feeds an inverting summing

node. Can accept an input signal, be ﬂoated or tied to

the OUT and OUT pins). The V

pin is the midpoint

OCM

of an internal resistive voltage divider between the sup-

plies, developing a (default) mid-supply voltage potential

+

OUT . For best performance, it is highly recommended

to maximize output signal swing. The V

pin can be

OCM

that stray capacitance be kept to as low as possible by

keeping printed circuit connections as short and direct

as possible, and if necessary, stripping back nearby sur-

rounding ground plane away from these pins.

overdriven by an external voltage reference capable of

driving the input impedance presented by the V pin.

OCM

The V

pin has an input resistance of approximately 7k

OCM

to a mid-supply potential. It should be bypassed with a

highqualityceramicbypasscapacitor(forinstanceofX7R

dielectric) of at least 0.01ꢁF, (unless using symmetrical

split supplies, then connect directly to a low impedance,

lownoisegroundplane)tominimizecommonmodenoise

from being converted to differential noise by impedance

mismatches both externally and internally to the IC.

C1, C2 (Pins 7, 8): Input to a trimmed 16.1pF, 33.3pF

capacitor which feeds a noninverting summing node.

–

Typically, either ﬂoat or tie to OUT . If either of these

–

pins is tied to a low impedance source other than OUT ,

a resistance of at least 25ꢀ should be placed in series.

For best performance, it is highly recommended that stray

capacitancebekepttoaslowaspossiblebykeepingprinted

circuit connections as short and direct as possible, and

if necessary, stripping back nearby surrounding ground

plane away from these pins.

66012f

12

LTC6601-2

PIN FUNCTIONS ^{(Refer to the Block Diagram)}

+

–

C5, C6 (Pins 19, 18): Input to a trimmed 16.1pF, 33.3pF

V , V (Pins 14, 13): Power Supply Pins. It is critical that

close attention be paid to supply bypassing. For single

supplyapplications(Pin13grounded), itisrecommended

that a high quality 0.1ꢁF surface mount ceramic bypass

capacitor (X7R dielectric for instance) be placed between

Pins 14 and 13, with direct short connections. Pin 13

should be tied directly to a low impedance ground plane

with minimal routing. For dual (split) power supplies, it

is recommended that at least two additional high quality

capacitor which feeds an inverting summing node. Typi-

+

cally, either ﬂoat or tie to OUT . If either of these pins are

+

tied to a low impedance source other than OUT , a re-

sistance of at least 25ꢀ should be placed in series. For

best performance, it is highly recommended that stray

capacitancebekepttoaslowaspossiblebykeepingprinted

circuit connections as short and direct as possible, and if

necessary, stripping back nearby surrounding reference

plane away from these pins.

+

0.1ꢁF ceramic capacitors are used to bypass V to ground

and V to ground, again with minimal routing. For driving

large loads (< 200ꢀ), additional bypass capacitance may

beaddedforoptimalperformance.Keepinmindthatsmall

geometry (e.g., 0603) surface mount ceramic capacitors

have a much lower ESL than do leaded capacitors, and

perform best in high speed applications.

–

Exposed Pad (Pin 21): Always tie the underlying Exposed

–

Pad to V (Pin 13). If split supplies are used, do not tie

–

the pad to ground. Tie it to V .

C7, C8 (Pins 17, 16): Input to a trimmed 10.55pF, 21.1pF

capacitor which feeds the ampliﬁer noninverting sum-

–

ming node. Typically, either ﬂoat or tie to OUT . For best

performance, stray capacitance should be kept as low as

possible by keeping printed circuit connections as short

and direct as possible.If necessary, strip back the sur-

rounding ground plane away from these pins.

66012f

13

LTC6601-2

BLOCK DIAGRAM

20

IN4

19

C5

18

C6

17

C7

16

C8

+

16.1pF

33.3pF

400Ω

81.5pF

400Ω

+

200Ω

IN2

10.55pF

1

2

–

OUT

15

14

13

12

21.1pF

48.2pF

+

100Ω

–

IN1

+

V

+ 2.3V

860Ω

180k

125Ω

–

60k

+

–

BIAS

3

860Ω

14k

180k

48.2pF

21.1pF

10.55pF

V

OCM

–

100Ω

200Ω

IN1

4

5

+

OUT

11

–

400Ω

IN2

81.5pF

33.3pF

C2

400Ω

16.1pF

–

IN4

C1

C3

C4

10

6

7

8

9

66012 BD

66012f

14

LTC6601-2

TEST CIRCUITS

20

19

18

17 16

LTC6601-2

I

L

1

2

–

25Ω

V

OUT

15

14

+

V

R

BAL

V

INP

0.1μF

–

0.1μF

+

–

BIAS

3

V

OUT(CM)

13

12

11

0.1μF

V

INM

+

V

BAL

OCM

0.01μF

I

L

4

5

+

25Ω

V

OUT

6

7

8

9

10

66012 F01

Figure 1. DC Test Circuit

20

19

18

17 16

LTC6601-2

5V

6

9 10 11 12

LT6411

1μF

1

2

–

100Ω

1μF

V

OUT

13

15

14

V

14

15

16

8

IN

COILCRAFT

TTWB-4-B

V

INP

5

+

V

0.1μF

1

2

3 7 17

+

–

50Ω

BIAS

1μF

3

V

13

12

11

0.1μF

–5V

V

OCM

0.01μF

V

INM

4

5

1μF

+

100Ω

V

OUT

6

7

8

9

10

66012 F02

Figure 2. AC Test Circuit (Frequency Response Testing)

66012f

15

LTC6601-2

APPLICATIONS INFORMATION

FUNCTIONAL DESCRIPTION

Figure 3 shows the basic ﬁlter architecture. The Laplace

transfer function from V to V is given by the

INDIFF

OUTDIFF

The LTC6601 is designed to make the implementation of

high frequency fully-differential ﬁltering functions very

easy.Averylownoiseampliﬁerissurroundedby8precision

matched resistors and 12 precision matched capacitors

so that a myriad of ﬁlter transfer functions limited only by

possiblecombinationsandimaginationcanbeconﬁgured

by hard wiring pins. The ampliﬁer itself is a wide band, low

noiseandlowdistortionfully-differentialampliﬁerwithac-

curateoutputphasebalancing.Itisoptimizedfordrivinglow

voltage, single-supply, differential input, analog-to-digital

converters (ADCs). The LTC6601’s outputs are capable

of swinging rail-to-rail on supplies as low as 2.7V, which

makestheampliﬁeridealforconvertinggroundreferenced,

following generalized equation for a 2nd order lowpass

ﬁlter:

V_OUTDIFF

Gain

=

s²

V

s

INDIFF

1+

+

2

2πf_O•Q

2πf

(

)

O

BothGainandQoftheﬁlterarebasedoncomponentratios,

which match and track extremely well over temperature.

The corner frequency of the ﬁlter is a function of an RC

product. This RC product is trimmed to 1% (typical) and

is not expected to drift by more than 1% from nominal

over the entire temperature range –40°C to 85°C. As a

result, fully differential ﬁlters with tight magnitude, phase

tolerance and repeatability are achieved.

single-ended signals into V

referenced differential

OCM

signals. Unlike traditional op amps which have a single

output, the LTC6601 has two outputs to process signals

differentially. This allows for two times the signal swing

in low voltage systems when compared to single-ended

output ampliﬁers. The balanced differential nature of the

ampliﬁer and matched surrounding components provide

even-order harmonic distortion cancellation, and less

susceptibility to common mode noise (like power supply

noise). The LTC6601 can be used as a single-ended input

to differential output ampliﬁer, or as a differential input to

differential output ampliﬁer.

Although Figure 3 implies a differential input, the LTC6601

easily accepts single-ended inputs to either input, and will

faithfully replicate the signal at the output in differential

form.

The LTC6601’s output common mode voltage, deﬁned as

the average of the two output voltages, is independent of

theinputcommonmodevoltage, andisadjustedbyapply-

ing a voltage on the V

pin. If the pin is left open, there

OCM

is an internal resistive voltage divider, which develops a

R2

1

C2

C1

f

=

O

2P R2 • R3 • C1• C2

C2 R3

•

1

Q =

R1

R3

R3 C2

R2 C1

C1 R2

1+ 1+ GAIN

•

–

ꢀ

ꢁ

R2

R1

GAIN =

+

–

+

V

OUT(DIFF)

IN(DIFF)

R1

ꢁ

ꢄ

f_O

•

6089 • 3568 • Q⁴ꢀ 1788 • Q²+ 447 + 1.287 • 10⁵• 2 • Q²ꢀ 1

(

)

(

)

ꢃ

ꢆ

ꢂ

ꢅ

f_3dB

=

C1

C2

R2

507.6 • Q

R3

ꢁ

ꢄ

4

2

0.2236 • f_O

•

2.109 • 10⁵

•

9.891• 10¹²• f_3dBꢀ 5.486 • 10⁹• f_O+ 120 • 5.526 • 10⁹• f_3dB+ 3.082 • 10⁶• f_O

(

)

(

)

ꢃ

ꢆ

ꢂ

ꢅ

Q =

2

4

16 • f_O• 8.29 • 10⁹• f_3dB+ 4.127 • 10⁹• f_Oꢀ 6.638 • 10¹⁰• f_3dB

(

)

(

)

66012 F03

Figure 3. Basic Filter Topology and Equations

66012f

16

LTC6601-2

APPLICATIONS INFORMATION

+

–

(seetheElectricalCharacteristicstable), andcanbedriven

by an external source keeping in mind its equivalent input

impedance and equivalent input voltage. If the BIAS pin is

ﬂoated, care should be taken to control external leakage

currents to this pin to under 1ꢁA to prevent putting the

LTC6601 an undesired state.

potential halfway between the V and V pins. Whenever

this pin is not hard tied to a low impedance ground plane,

a high quality ceramic capacitor should be used to bypass

theV

pintoalowimpedancegroundplane(seeLayout

OCM

Considerations). The LTC6601’s internal common mode

feedback path forces accurate output phase balancing to

reduce even order harmonics, and centers each individual

If BIAS is tied to the positive supply, the LTC6601 dif-

ferential ﬁlter will be in a fully active state conﬁgured for

highestperformance(lowestnoiseandlowestdistortion).

If the BIAS pin is ﬂoated or left unconnected, the LTC6601

ﬁlter will be in a fully active state, with ampliﬁer currents

reduced and performance scaled back to preserve power

consumption. If the BIAS pin is tied to the most negative

output about the potential set by the V

pin.

OCM

–

V_OUT⁺+ V_OUT

V_OUTCM= V_OCM

=

2

+

–

The outputs (OUT and OUT ) of the LTC6601 are capable

of swinging rail-to-rail. They can source or sink up to ap-

proximately 75mA of current. Load capacitances should

be decoupled with at least 25ꢀ of series resistance from

each output.

–

supply (V ), the LTC6601 will be placed into a low power

shutdown mode with ampliﬁer outputs disabled. In this

state, the LTC6601 draws approximately 450μA.

Inlowpowershutdown,allinternalbiasingcurrentsources

The LTC6601 Electrical Characteristics table speciﬁes an

inputreferredoffset.Thisspeciﬁcationactuallylumpsvolt-

+

–

areshutoff, andtheoutputpins, OUT andOUT , willeach

appear as open collectors with a non-linear capacitor in

parallel and steering diodes to either supply. The turn-on

and turn-off time constant between states are on the order

of 0.4ꢁs. Using this function to wire-OR outputs together

is not recommended.

age offsets due to offset bias currents (I ), and ampliﬁer

OS

voltageoffsetintoonespeciﬁcation.Toreferthisspeciﬁca-

tion to the output, you simply multiply the speciﬁcation

by the noise gain the LTC6601 is conﬁgured in:

V

= 1 + Gain

OSODIFF

General Design and Usage

where Gain is the closed loop gain in the particular ﬁlter

application:

As levels of integration have increased and correspond-

ingly, system supply voltages decreased, there has been

a need for ADCs to process signals differentially in order

to maintain good signal-to-noise ratios. These ADCs are

typically supplied from a single supply voltage which

can be as low as 3V (2.7V min), and will have an optimal

commonmodeinputrangenearmid-supply.TheLTC6601

makes interfacing to these ADCs easy, by providing anti-

alias ﬁltering, single-ended to differential conversion and

common mode level shifting (translation). Figure 3 shows

a general application of this. The low frequency gain to

R2

Gain =

R1

COMPONENT INPUT PIN PROTECTION

+

–

All of the LTC6601 pins with the exception of V and V are

protected with steering diodes to either power supply. In

the event that a pin is driven beyond the supply rails, the

excesscurrentshouldbelimitedtounder10mAtoprevent

damage to the IC.

V

from V is simply:

OUTDIFF

IN

BIAS Pin

R2

R1

+

–

V_OUTDIFF= V_OUT– V_OUT

≈

• V

INDIFF

The LTC6601 has a BIAS pin (Pin 3) whose function is to

tailor both performance and power of the LTC6601. The

pinhasaTheveninequivalentimpedanceofapproximately

150kꢀ to a voltage source whose potential is 1.15V above

–

Thedifferentialoutputvoltage(V

–V

)iscompletely

OUT

independent of input and output common mode voltages,

or the voltage at the common mode pin. This makes the

66012f

–

the V supply. This pin has ﬁxed logic levels relative to V

17

LTC6601-2

APPLICATIONS INFORMATION

LTC6601 ideally suited for pre-ampliﬁcation, level shift-

ing and conversion of single-ended signals to differential

output signals for driving differential input ADCs.

Input and Output Common Mode Voltage Range

The input common mode voltage is deﬁned as the average

of the two inputs:

V

_INP+ V

INM

INPUT IMPEDANCE

V

=

INCM

2

Calculating the low frequency input impedance of the

LTC6601 depends on how the inputs are driven (whether

they are driven from a single-ended or a differential

source).

The lower limit of the input common mode range is dic-

tated by the ESD protection diodes at the input. While it

–

is possible for the inputs to swing below V , the diodes

–

will conduct if the inputs are taken a diode drop below V .

Figure 4 shows a simpliﬁed low frequency equivalent

The upper limit of the input common mode range varies

circuit of the LTC6601. For balanced input sources (V

INP

as a function of the ﬁlter conﬁguration (GAIN), V

po-

OCM

= –V ), the low frequency input impedance is given by

INM

tential, and whether or not the inputs are single-ended or

differential. While it is possible to exceed the upper limit

of the common mode range, doing so will degrade ﬁlter

linearity. Referring to Figure 4, for linear operation, the

summing junction where R1, R2 and R3 merge together

should be prevented from swinging to within 1.4V of the

the equation:

R

= R

= R1

INP

INM

The differential input impedance is simply:

= 2 • R1

R

INDIFF

+

V power supply.

For single-ended inputs (V

= 0), the input impedance

INM

actually increases over the balanced differential case due

For the general case, the upper input common mode volt-

age limit should be constrained to:

to the fact the summing node (at the junction of R1, R2

and R3) moves in phase with V to bootstrap the input

INP

R1

R1+R2

R2

R1+R2

V_OCM

•

+ V

•

INCM

≤ V⁺–1.4V

impedance. Referring to Figure 4 with V

impedance looking into either input is:

= 0, the input

INM

R1

Or equivalently:

R_INP=R_INM

⎛

⎞

1

1– •

2

R2

⎛

⎞

R1

R2

R1

R2

⎛

⎞

V

≤ 1+

V⁺−1.4V −

• V_OCM

⎜

⎝

⎟

⎠

⎜

⎝

⎟

⎠

(

)

⎜

⎟

⎠

INCM

R1+R2

⎝

Thespeciﬁcationsforinputcommonmoderange(V

)

INCMR

are based on these constraints with R1 = R2 = 100Ω, and

= mid-supply. Substituting the numbers for a single

R2

R

INP

V

R1

OCM

–

V

+

–

OUT

3V power supply, (V = 3V, V = 0V) with V

=1.5V, and

–

OCM

R3

V

INP

+

R1 = R2 = 100Ω, into the above equation, the input com-

mon mode range (V ) is between the two limits:

–

V

OUTDIFF

R3

INCMR

–

V

INM

+

0V ≤ V

≤ 1.7V

+

INCM

+

V

OUT

R2

R

INM

V

OCM

which is as is speciﬁed for a 3V supply.

0.1μF

66012 F04

Figure 4. Input Impedance

66012f

18

LTC6601-2

APPLICATIONS INFORMATION

Likewise, substituting the numbers for a single 5V power

common mode voltage, it can be directly tied to the V

OCM

+

–

supply, (V = 5V, V = 0V) with V

= 2.5V, and R1 = R2

pin, but must be capable of driving the input impedance of

the V pin (R ). This impedance can be assumed

OCM

= 100Ω, into the above equation, the input common mode

OCM

VOCM

range (V

) is between the two limits:

to be connected to a mid-supply potential. If an external

reference drives the V pin, it should still be bypassed

INCMR

OCM

0V ≤ V

≤ 4.7V

INCM

with a high quality 0.01ꢁF or higher capacitor to a low

impedance ground plane to ﬁlter any thermal noise and

to prevent common mode signals on this pin from being

inadvertently converted to differential signals.

The output common mode voltage is deﬁned as the aver-

age of the two outputs:

–

V_OUT⁺+ V_OUT

V_OUTCM= V_OCM

The V

=

2

Noise Considerations

pin sets this average by an internal common

mode feedback loop which internally forces V + =

When comparing the LTC6601 noise to other ampliﬁers,

be sure to compare similar speciﬁcations. Competing

devices often specify noise referred to the inputs of the

ampliﬁer.TheinputreferredvoltagenoiseoftheLTC6601-2

is 4.7nV/√Hz.

OCM

OUT

–V –. The output common mode range extends from

OUT

–

+

1.1 V above V to 1V below V . The V

pin sits in the

OCM

middle of a voltage divider which sets the default mid-

supply open circuit potential.

In addition to the noise generated by the ampliﬁer, the

surrounding feedback resistors also contribute noise. A

noise model is shown in Figure 5. The output spot noise

generated by both the ampliﬁer and the feedback compo-

nents is governed by the equation:

In single supply applications, where the LTC6601 is used

to interface to an ADC, the optimal common mode input

to the ADC is often determined by the ADC’s reference. If

the ADC makes a reference available for setting the input

2

⎛

⎞

⎟

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎝

⎞

⎛

⎞

⎛

⎝

⎞

R2

R1

R2

R1

R2

R1

R2

R1

⎛

⎝

⎞

⎛

⎝

⎞

⎛

⎞

⎛

⎝

⎞

2

e_no= e • 1+

+ 2• I • R2²+R3²• 1+

+ 2• e

•

+ 2 e_nR3• 1+

+ 2•e_nR2

⎜

⎟

⎠

⎜

⎟

⎠

⎜

⎝

⎟

⎠

⎜

⎟

⎠

ni

n

nR1

⎜

⎟

⎠

⎜

⎝

⎟

⎠

⎟

⎠

⎜

⎝

⎟

⎠

Substituting the equation for Johnson noise of a resistor (e = 4kTR), and simplifying:

nR

2

⎛

⎞

⎟

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎞

⎟

⎠

⎛

⎝

⎞

R2

R1

R2

R1

R2

R1

R2

R1

⎛

⎝

⎞

⎛

⎝

⎞

⎛

⎝

⎞

⎛

⎝

⎞

2

e_no= e • 1+

+ 2• I • R2²+R3²• 1+

+ 8 •k • T R2 1+

+R3 1+

⎜

⎟

⎠

⎜

⎟

⎠

⎜

⎟

⎠

⎜

⎟

⎠

ni

n

⎜

⎟

⎠

⎜

⎝

⎟

⎠

⎝

66012f

19

LTC6601-2

APPLICATIONS INFORMATION

2

e

nR2

R2

*

2

e

nR1

+

2

R1

I

n

2

e

ni

nR3

*

R3

+

–

*

2

e

no

nR3

R3

2

e

nR1

*

R1

–

2

n

*

2

e

nR2

R2

66012 F05

*

Figure 5. Differential Noise Model of the LTC6601

+

Table 1 lists the ampliﬁer input referred noise for the

LTC6601-2.Tables2to10listthenoisereferredtotheinput

pinsoftheICforcommonconﬁgurationsoftheLTC6601-2.

To determine the spot noise at the output, simply multiply

the noise by the Gain = R2/R1. To estimate the integrated

noise at the output, multiply the noise by the gain, and the

square root of the noise bandwidth. The noise bandwidth

depends on the ﬁlter conﬁguration. For Figure 2, the noise

bandwidth is 100MHz, or approximately 7 times the ﬁlter

bandwidth. Improvements in SNR can be made by adding

an additional RC ﬁlter at the output to band limit wide band

noise before feeding ADCs. See the section “Interfacing

the LTC6601 to ADC Converters” for more detail.

ceramic capacitor be used to bypass pin V to ground

–

and V to ground, again with minimal routing. For driv-

ing large differential loads (<200ꢀ), additional bypass

capacitance may be needed between V and V for opti-

mal performance. Note that small geometry (e.g., 0603)

surface mount ceramic capacitors have a much higher

self resonant frequency than capacitors with leads, and

perform best in high speed applications.

+

–

The V

pin should be bypassed to ground with a high

OCM

quality ceramic capacitor whose value exceeds 0.01ꢁF,

withdirect,shortconnections.Insplitsupplyapplications,

the V

pin can be either bypassed to ground or directly

OCM

hardwired to ground. Be careful not to violate the output

common mode range speciﬁcations for the V pin.

Table 1. Ampliﬁer (Input Referred) Noise Characteristics for the

OCM

LTC6601-2

Stray parasitic capacitances to unused component pins

that set up the ﬁlter’s characteristics, should be kept to an

absoluteminimum.Thispreventsdeviationsfromtheideal

frequencyresponse. Anideallayouttechniquewouldbeto

remove the solder pads for the unused component pins,

and strip away the ground plane underneath these pins to

lowercapacitancetoanabsoluteminimum.Floatingunused

component pins which set up the ﬁlter characteristics will

not reduce the reliability of the LTC6601.

+

BIAS PIN PULLED TO V

BIAS PIN FLOATING

e

i

e

i

n

ni

n

ni

nV/√Hz

pA/√Hz

nV/√Hz

pA/√Hz

4.7

3

5.2

2.1

LAYOUT CONSIDERATIONS

Because the LTC6601 is a very high speed ampliﬁer, it is

sensitive to both stray capacitance and stray inductance.

It is critical that close attention be paid to supply bypass-

ing. For single supply applications, it is recommended

that a high quality 0.1ꢁF surface mount ceramic bypass

capacitor be placed between Pins 14 and 13 with direct

short connections. Pin 13 and the Exposed Pad, Pin 21,

should be tied directly to a low impedance ground plane

with minimal routing. For dual (split) power supplies, it

is recommended that an additional high quality, 0.1ꢁF

Attheoutput,alwayskeepinmindthedifferentialnatureof

theLTC6601, andthatitiscriticalthattheloadimpedances

seenbybothoutputs(strayorintended), shouldbeasbal-

anced and symmetric as possible. This will help preserve

the natural balance of the LTC6601, which minimizes the

generation of even order harmonics and preserves the

rejection of common mode signals and noise.

66012f

20

LTC6601-2

APPLICATIONS INFORMATION

INTERFACING THE LTC6601 TO ADC CONVERTERS

often be much greater than that of the LTC6601, so hav-

ing this discrete RC ﬁlter will give the additional beneﬁt

of band limiting broadband output noise.

TheLTC6601’srail-to-raildifferentialoutputandadjustable

output common mode voltage make the LTC6601 ideal

for interfacing to low voltage, single supply, differential

input ADCs. The sampling process of ADCs creates a

sampling transient that is caused by the switching-in

of the ADC sampling capacitor. The switching-in of this

samplingcapacitormomentarily“shorts”theoutputofthe

ampliﬁer as charge is transferred between ampliﬁer and

sampling capacitor. The ampliﬁer must recover and settle

from this load transient before this acquisition period has

ended, for a valid representation of the input signal. The

LTC6601 will settle much more quickly from these peri-

odic load impulses than it does from a 2V input step, but

it is a good idea to add an RC network after the outputs

of the LTC6601 to decouple the sampling transient of the

ADC (See Figure 6). The capacitance of the decoupling

network serves to provide the bulk of the charge during

the sampling process, while the two resistors of the ﬁlter

network are used to dampen and attenuate any transient

induced by the ADC. The ADC’s sampling bandwidth will

The selection of the RC time constant is trial and error

for a given ADC, but the following guidelines are recom-

mended. Choose an RC pole frequency greater than the

cutoff frequency of the LTC6601. 80MHz RC ﬁlters are

good for ﬁltering broadband noise. Lower frequency RC

ﬁlters improve SNR at the expense of settling time. The

resistorsinthedecouplingnetworkshouldbeatleast25ꢀ.

Too much resistance in the decoupling network leaves

insufﬁcient settling time and will create a voltage divider

between the dynamic input impedance of the ADC and the

decoupling resistors. Using insufﬁcient resistance might

prevent proper dampening of the load transient caused by

the sampling process, and prolong the time required for

settling. In 16-bit applications, this will typically require

a minimum of 11 RC time constants. It is recommended

that the capacitor is chosen with low dielectric absorption

(such as a C0G multilayer ceramic capacitor).

20

19

18

17 16

LTC6601-2

C1

1

2

–

R

V

OUT

15

14

+

CONTROL

V

IN

3V

–

0.1μF

D15

+

–

•

+

–

A

IN

1μF

BIAS

3

D0

C2

C1

13

12

3.3V

1μF

V

GND

CM

1μF

V

1μF

OCM

10nF

2.2μF

4

5

+

R

V

OUT

11

66012 F06

t = R • (C1 + 2 • C2)

6

7

8

9

10

Figure 6. Interfacing the LTC6601 to A/D Converters

66012f

21

LTC6601-2

APPLICATIONS INFORMATION

A GALLERY OF BASIC FILTER TOPOLOGIES

these topologies range from 1V/V to 7V/V. The Qs listed

are within the range of 0.54 and 1.72. The f s listed are

O

Tables2through10list(sortedbyGain)ahundredpossible

ﬁlter topologies that can be easily implemented with the

LTC6601. The tables also list the LTC6601-2 approximate

in the range of 6.96MHz and 22.71MHz, and the –3dB

frequencies listed range from 5.5MHz to 27.5MHz. For

all ﬁlters listed, R3 = 125ꢀ. Figures 7 to 10 show how to

pin-strap each ﬁlter conﬁguration.

midband (1MHz) spot noise e referred to the input re-

in

+

sistor, R1 (with the BIAS pin pulled to V ). The gains for

Table 2. Gain of 7 Filter Conﬁgurations

GAIN

e

in

V/V

7.0

dB

f (MHz)

f

(MHz)

–3dB

Q

R1 (Ω)

57.14

R2 (Ω)

400.00

C1 (pF)

48.2

C2 (pF)

97.6

(nV/√Hz)

O

16.902

10.38

9.57

8.96

8.12

7.43

0.539

0.771

1.175

0.656

6.1

10.36

12.10

7.49

48.2

114.8

130.9

6.1

48.2

6.1

58.75

6.1

Table 3. Gain of 6 Filter Conﬁgurations

GAIN

e

in

V/V

6.0

dB

f (MHz)

f

(MHz)

Q

R1 (Ω)

66.67

R2 (Ω)

400.00

C1 (pF)

48.2

C (pF)

(nV/√Hz)

O

–3dB

2

15.563

10.38

9.57

8.67

8.12

7.47

10.03

12.52

7.67

0.684

1.071

0.634

0.870

0.592

97.6

114.8

130.9

6.2

48.2

6.2

58.75

69.3

6.2

9.59

6.2

6.07

6.2

Table 4. Gain of 5 Filter Conﬁgurations

GAIN

e

in

V/V

5.0

dB

f (MHz)

f

(MHz)

–3dB

Q

R1 (Ω)

80.00

R2 (Ω)

400.00

C1 (pF)

48.2

C2 (pF)

81.5

nV/√Hz

o

13.979

11.36

10.38

9.40

8.67

8.12

7.98

7.47

6.96

9.67

12.78

7.67

0.614

0.936

0.594

0.849

1.290

0.591

0.779

0.579

6.5

48.2

97.6

6.5

58.75

69.3

97.6

6.5

10.07

11.25

6.46

114.8

130.9

114.8

130.9

6.5

8.16

69.3

6.5

5.50

79.85

6.5

66012f

22

LTC6601-2

APPLICATIONS INFORMATION

Table 5. Gain of 4 Filter Conﬁgurations

GAIN

e

in

V/V

4.0

dB

f (MHz)

f

MHz

–3dB

Q

R1 (Ω)

100.00

R2 (Ω)

400.00

C1 (pF)

48.2

C2 (pF)

81.5

nV/√Hz

O

12.041

11.36

10.38

9.40

8.67

8.65

7.98

7.43

7.47

6.96

13.05

0.834

1.480

0.799

1.284

0.575

0.794

0.596

1.141

0.775

6.8

14.80

10.47

12.00

6.76

48.2

97.6

6.8

58.75

69.3

97.6

6.8

114.8

97.6

6.8

8.84

69.3

114.8

130.9

6.8

6.09

79.85

69.3

6.8

10.00

7.57

6.8

79.85

6.8

Table 6. Gain of 3 Filter Conﬁgurations

GAIN

e

in

V/V

3.0

dB

f (MHz)

f

(MHz)

–3dB

Q

R1 (Ω)

66.67

R2 (Ω)

200.00

400.00

200.00

400.00

200.00

400.00

200.00

C1 (pF)

48.2

C2 (pF)

81.5

(nV/√Hz)

O

9.542

16.06

14.68

13.53

13.29

12.26

11.36

11.48

11.29

10.29

10.57

9.40

12.36

0.568

0.763

1.091

0.554

0.715

1.300

0.928

0.552

0.763

0.674

1.224

0.788

0.601

1.212

0.825

1.172

0.544

7.1

15.74

17.83

9.88

66.67

48.2

97.6

7.1

66.67

48.2

114.8

97.6

7.1

66.67

58.75

48.2

7.1

12.39

15.77

14.07

8.34

66.67

114.8

81.5

7.1

133.33

66.67

7.4

58.75

69.3

130.9

114.8

81.5

7.1

66.67

7.1

11.04

10.06

12.85

9.54

133.33

66.67

58.75

69.3

7.4

130.9

97.6

7.1

133.33

66.67

58.75

69.3

7.4

8.65

97.6

7.4

8.06

6.69

79.85

69.3

97.6

7.4

7.98

10.88

8.48

114.8

130.9

7.4

7.43

79.85

7.4

6.96

9.40

7.4

9.85

7.13

7.1

66012f

23

LTC6601-2

APPLICATIONS INFORMATION

Table 7. Gain of 2 Filter Conﬁgurations

GAIN

e

in

V/V

2.0

dB

f (MHz)

f

(MHz)

–3dB

Q

R1 (Ω)

100.00

200.00

100.00

200.00

100.00

200.00

R2 (Ω)

200.00

400.00

200.00

400.00

200.00

400.00

C1 (pF)

48.2

C2 (pF)

81.5

(nV/√Hz)

O

6.021

16.06

14.55

14.68

13.29

12.24

12.26

11.29

10.29

10.51

10.57

9.47

18.95

0.868

0.626

1.323

0.840

0.640

1.200

0.835

1.197

0.660

1.102

0.796

0.819

0.616

1.254

0.864

1.341

8.1

12.69

20.46

15.34

10.96

16.66

12.98

13.97

9.76

58.75

48.2

81.5

8.1

97.6

8.1

58.75

69.3

97.6

8.1

97.6

8.1

58.75

69.3

114.8

81.5

8.1

58.75

79.85

69.3

8.5

114.8

130.9

81.5

8.1

13.97

10.52

11.17

7.55

8.1

69.3

8.5

9.85

79.85

69.3

130.9

81.5

8.1

8.82

8.5

8.65

11.91

9.48

97.6

8.5

8.06

79.85

97.6

8.5

7.43

10.40

114.8

8.5

Table 8. Gain of 1.667 Filter Conﬁgurations

GAIN

e

in

V/V

dB

f (MHz)

O

f

MHz

–3dB

Q

R1 (Ω)

80.00

R2 (Ω)

133.33

C1 (pF)

48.2

C2 (pF)

81.5

nV/√Hz

1.667

4.437

19.67

17.97

16.57

16.28

15.01

14.33

13.82

12.94

12.06

19.35

22.12

23.16

15.60

17.80

18.58

13.19

14.77

11.32

0.696

0.934

1.336

0.679

0.875

1.046

0.676

0.826

0.666

8.5

48.2

97.6

8.5

48.2

114.8

97.6

8.5

58.75

69.3

8.5

114.8

126

8.5

114.8

130.9

8.5

69.3

8.5

79.85

8.5

66012f

24

LTC6601-2

APPLICATIONS INFORMATION

Table 9. Gain of 1.333 Filter Conﬁgurations

GAIN

e

in

V/V

dB

f (MHz)

O

f

MHz

–3dB

Q

R1 (Ω)

100.00

R2 (Ω)

133.33

C1 (pF)

48.2

C2 (pF)

81.5

nV/√Hz

1.333

2.499

19.67

17.82

17.97

16.28

14.99

15.01

14.06

13.82

12.88

12.94

12.06

22.73

0.841

0.633

1.185

0.818

0.646

1.097

1.506

0.814

0.663

1.025

0.801

9.4

15.77

24.34

18.44

13.58

19.82

20.12

15.61

12.03

16.64

13.45

58.75

48.2

81.5

9.4

97.6

9.4

58.75

69.3

97.6

9.4

97.6

9.4

58.75

69.3

114.8

130.9

114.8

130.9

9.4

79.85

69.3

9.4

79.85

9.4

Table 10. Gain of 1 Filter Conﬁgurations

GAIN

e

in

V/V

1.0

dB

0.0

f (MHz)

f

MHz

–3dB

Q

R1 (Ω)

100.0

200.0

100.0

200.0

100.0

200.0

400.0

R2 (Ω)

100.0

200.0

100.0

200.0

100.0

200.0

400.0

C1 (pF)

48.2

C2 (pF)

81.5

nV/√Hz

10.7

11

O

22.71

20.75

20.57

19.14

18.80

17.31

17.33

16.23

15.96

14.55

14.87

14.95

13.39

13.92

12.48

12.24

11.40

11.29

10.51

9.47

25.40

27.23

17.86

27.50

20.62

15.35

22.15

22.58

17.45

19.09

13.57

18.59

14.90

15.04

11.38

16.25

13.27

16.47

14.17

13.26

10.86

11.57

0.804

1.079

0.623

1.543

0.784

0.634

1.011

1.312

0.781

1.079

0.650

0.954

0.798

0.769

0.650

1.115

0.850

1.715

1.167

1.350

0.935

1.535

48.2

97.6

58.75

48.2

81.5

114.8

97.6

58.75

69.3

97.6

58.75

69.3

114.8

130.9

114.8

81.5

58.75

79.85

69.3

114.8

130.9

81.5

10.7

11

69.3

79.85

69.3

130.9

81.5

10.7

11

97.6

11

79.85

69.3

97.6

11

114.8

81.5

11

79.85

69.3

11

11.8

8.82

79.85

81.5

8.06

97.6

66012f

25

LTC6601-2

APPLICATIONS INFORMATION

20

19

18

17

16

20

19

18

17

16

LTC6601-2

1

2

15

1

2

15

11

+

R1

57.14Ω

R1

66.66Ω

4

5

4

5

–

11

6

7

8

9

10

16

6

7

8

9

10

16

20

19

18

17

20

19

18

17

LTC6601-2

1

2

15

11

1

2

15

11

+

R1

80Ω

R1

100Ω

4

5

4

5

–

6

7

8

9

10

16

6

7

8

9

10

16

20

19

18

17

20

19

18

17

LTC6601-2

1

2

15

11

1

2

15

11

+

R1

133.33Ω

R1

200Ω

4

5

4

5

–

6

7

8

9

10

6

7

8

9

10

20

19

18

17

16

LTC6601-2

1

15

11

+

2

R1

400Ω

4

5

–

66012 F07

6

7

8

9

10

Figure 7. Pin-Strap Hookup for a Particular R1

66012f

26

LTC6601-2

APPLICATIONS INFORMATION

20

19

18

17

16

20

19

18

17

16

LTC6601-2

1

2

15

1

2

15

11

+

R2

100Ω

R2

133Ω

4

5

4

5

–

11

6

7

8

9

10

16

6

7

8

9

10

16

20

19

18

17

20

19

18

17

LTC6601-2

1

2

15

11

1

2

15

11

+

R2

200Ω

R2

400Ω

4

5

4

5

–

66012 F08

6

7

8

9

10

6

7

8

9

10

Figure 8. Pin-Strap Hookup for a Particular R2

20

19

18

17

16

20

19

18

17

16

LTC6601-2

1

2

15

11

1

2

15

11

+

C1

48.2pF

C1

58.75pF

4

5

4

5

–

6

7

8

9

10

16

6

7

8

9

10

16

20

19

18

17

20

19

18

17

LTC6601-2

1

2

15

11

1

2

15

11

+

C1

69.3pF

C1

79.85pF

4

5

4

5

–

6

7

8

9

10

6

7

8

9

10

66012 F09

Figure 9. Pin-Strap Hookup for a Particular C1

66012f

27

LTC6601-2

APPLICATIONS INFORMATION

20

19

18

17

16

20

19

18

17

16

LTC6601-2

1

2

15

1

2

15

11

+

C2

81.5pF

C2

114.8pF

4

5

4

5

–

11

6

7

8

9

10

16

6

7

8

9

10

16

20

19

18

17

20

19

18

17

LTC6601-2

1

2

15

11

1

2

15

11

+

C2

97.6pF

C2

130.9pF

4

5

4

5

–

6

7

8

9

10

6

7

8

9

10

66012 F10

Figure 10. Pin-Strap Hookup for a Particular C2

66012f

28

LTC6601-2

APPLICATIONS INFORMATION

Example Filter Conﬁgurations of Basic 2nd Order

Filters

Figure 11 shows some simpliﬁed component hookups of

a selection of ﬁlters taken from Tables 7, 9 and 10. For

simplicity, V

pin bypass and power supply bypass

OCM

are not shown.

20

19

18

17

16

20

19

18

17

16

LTC6601-2

1

2

15

11

1

2

15

11

+

V

IN

OUT(DIFF)

IN

OUT(DIFF)

4

5

4

5

–

6

7

8

9

10

16

6

7

8

9

10

16

GAIN = 0dB

= 13.92MHz

GAIN = 0dB

f = 22.71MHz

O

Q = 0.804

f

O

Q = 0.769

20

19

18

17

20

19

18

17

LTC6601-2

1

2

15

11

1

2

15

11

+

OUT(DIFF)

4

5

4

5

–

6

7

8

9

10

16

6

7

8

9

10

16

GAIN = 6dB

= 9.85MHz

GAIN = 6dB

f = 16.06MHz

O

Q = 0.868

f

O

Q = 0.819

20

19

18

17

20

19

18

17

LTC6601-2

1

2

15

11

1

2

15

11

+

OUT(DIFF)

4

5

4

5

–

6

7

8

9

10

6

7

8

9

10

66012 F11

GAIN = 2.5dB

= 12.06MHz

GAIN = 2.5dB

f = 19.67MHz

O

Q = 0.841

f

O

Q = 0.801

Figure 11. Basic 2nd Order Filter Conﬁgurations

66012f

29

LTC6601-2

APPLICATIONS INFORMATION

Figure 12 shows some simpliﬁed component hookups

of a selection of ﬁlters taken from Tables 4, 5, and 6. For

simplicity, V

pin bypass and power supply bypass

OCM

are not shown.

20

19

18

17

16

20

19

18

17

16

LTC6601-2

1

2

15

11

1

2

15

11

+

V

IN

OUT(DIFF)

IN

OUT(DIFF)

4

5

4

5

–

6

7

8

9

10

16

6

7

8

9

10

16

GAIN = 12dB

= 6.96MHz

GAIN = 12dB

f = 11.36MHz

O

Q = 0.834

f

O

Q = 0.775

20

19

18

17

20

19

18

17

LTC6601-2

1

2

15

11

1

2

15

11

+

OUT(DIFF)

4

5

4

5

–

6

7

8

9

10

16

6

7

8

9

10

16

GAIN = 14dB

= 6.96MHz

GAIN = 14dB

f = 11.36MHz

O

Q = 0.614

f

O

Q = 0.579

20

19

18

17

20

19

18

17

LTC6601-2

1

2

15

11

1

2

15

11

+

OUT(DIFF)

4

5

4

5

–

6

7

8

9

10

6

7

8

9

10

66012 F12

GAIN = 9.54dB

= 9.85MHz

GAIN = 9.54dB

f = 16.06MHz

O

Q = 0.568

f

O

Q = 0.544

Figure 12. Basic 2nd Order Filter Conﬁgurations

66012f

30

LTC6601-2

APPLICATIONS INFORMATION

COMPLEX FILTER CONFIGURATIONS

Figures 14 to 17 show additional circuits highlighting the

use of R4 or C3 in the modiﬁed second order cicuit to

A Modiﬁed 2nd Order Lowpass Filter Topology

set the f

frequency to 13MHz, 19MHz, 22.7MHz and

3dB

24.6MHz respectively.

The basic ﬁlter topology of Figure 3 can be modiﬁed as

shown in Figure 13. The Figure 13 circuit includes an

impedance path between the two summing nodes (the

circuit nodes common to resistors R1, R2 and R3). A

resistor and/or a capacitor connection between the sum-

ming nodes provide even more ﬂexibility, and enhance

The design procedure for a speciﬁed f

as follows:

frequency is

3dB

1 Using the chosen C1, C2 and C3 values calculate the

f value.

O

the ﬁlter design options (the f and Q equations shown

2. Using f of step 1 and the speciﬁed f

calculate the

3dB

O

in Figure 13 reduce to equations of Figure 3 if C3 is zero

Q value.

and R4 is inﬁnite).

3. Calculate the R4 value using the Q value of step 3.

4. Calculate the required external resistor R value for

The modiﬁed second order ﬁlter topology provides for

setting the Q value (with R4) without changing the f

EXT

O

the R4 value in step 3. Example, in Figure 14 the Q

value and increasing the passband gain to greater than

one without changing the Q value (in the Q equation of

Figure 13 the value of Q does not change if the value of

the [1 + GAIN + 2(R2/R4)] denominator factor does not

change). Using R4 to set the Q value allows the option

value for f = 5MHz is 0.54, the required R4 resistor

3dB

is 350ꢀ, the R4A and R4B resistors are the internal

100ꢀ and the R resistor is 150ꢀ [R = R4 – (R4A

EXT

+ R4B)].

Note: The modiﬁed second order ﬁlter topology requires

the use of at least two of the three input resistor pairs (two

of the three 400ꢀ, 200ꢀ and 100ꢀ pairs).

to design the –3dB frequency (f ). If the Q value varies

3dB

and the f value is constant then the f

ies in a second order lowpass function (refer to the f

frequency var-

O

3dB

equation of Figure 13).

66012f

31

LTC6601-2

APPLICATIONS INFORMATION

R2

C2

C1

R1

R3

R4A

+

–

C3A

–

+

V

R

IN(DIFF)

EXT

V

49.9Ω

C3B

OUT(DIFF)

R4B

C1

C2

R1

R3

R2

66012 F13

R4 = R4A + R4B + R

EXT

C3 = C3A/2 (C3A = C3B)

ꢁ

ꢄ

f_O

•

6089 • 3568 • Q⁴ꢀ 1788 • Q²+ 447 + 1.287 • 10⁵• 2 • Q²ꢀ 1

(

)

(

)

ꢃ

ꢆ

ꢂ

ꢅ

f_3dB

=

507.6 • Q

ꢁ

ꢄ

4

2

0.2236 • f_O

•

2.109 • 10⁵

•

9.891• 10¹²• f_3dB⁴ꢀ 5.486 • 10⁹• f_O+ 120 • 5.526 • 10⁹• f_3dB²+ 3.082 • 10⁶• f_O

(

)

(

)

ꢃ

ꢆ

ꢂ

ꢅ

Q =

2

4

16 • f_O• 8.29 • 10⁹• f_3dB²+ 4.127 • 10⁹• f_Oꢀ 6.638 • 10¹⁰• f_3dB

(

)

(

)

1.25 • 10⁴• C1• Q • R2

R4 =

ꢁ C2 + 2 • C3ꢄ

559 • C1• R2 •

ꢀ 50 • Q • C1• 125 • GAIN + R2 + 125 ꢀ C2 • R2

ꢆ

ꢅ

(

)

(

)

ꢃ

ꢂ

C1

GAIN

R2 • R3 • C1• C2 + 2 • C3

V_OUT(DIFF)

(

)

= –

V

R1• R2 • 2 •R3 + R4 + R3 • R4 + R2 • R3 • R4

(

)

IN(DIFF)

(

)

1

S²

+

• S +

R1•R2 •R3 •R4 • C2 + 2 • C3

R2 • R3 • C1• C2 + 2 • C3

(

)

(

)

V_OUT(DIFF)

R2

R1

GAIN = –

= –

V

IN(DIFF)

ꢁR3ꢄ

ꢂR2ꢅ

ꢁ C2

ꢂ C1

C3ꢄ

C1ꢅ

•

+ 2 •

ꢃ

ꢆ

ꢃ

ꢆ

1

f_O

=

Q =

ꢁ

R2ꢄ R3 C2

R4ꢅ R2 C1

2 • ꢀ • R2 •R3 • C1• C2 + 2 • C3

(

)

1+ 1+|GAIN|+2•

•

ꢆ

–

ꢃ

ꢂ

Figure 13. Modiﬁed Filter Topology and Equations

66012f

32

LTC6601-2

APPLICATIONS INFORMATION

20

19

18

17

16

20

19

18

17

16

LTC6601-2

1

2

15

1

2

15

11

+

V

IN(DIFF)

= 400Ω

IN(DIFF)

= 200Ω

200Ω

V

OUT(DIFF)

Z

IN(DIFF)

4

5

4

5

–

11

6

7

8

9

10

6

7

8

9

10

66012 F14a

GAIN = 1

= 11.28MHz

GAIN = 2

f = 11.28MHz

O

Q = 0.835

f

O

Q = 0.835

f

= 10MHz

= 13MHz

f

= 10MHz

= 13MHz

–1dB

–3dB

–1dB

–3dB

Gain Magnitude vs Frequency (Gain = 1)

Passband Phase and Group Delay

30

0

5

0

PHASE

–30

–60

–5

–10

–15

–20

–25

–30

–35

–40

–90

–120

50

40

30

20

10

0

GROUP DELAY

0

100k

4M

8M

12M

16M

100k

1M

10M

100M

FREQUENCY (Hz)

66012 F14c

66012 F14b

Figure 14. Modiﬁed Filter Conﬁguration Using a Resistor Between Summing Nodes (f_–3dB= 13MHz)

66012f

33

LTC6601-2

APPLICATIONS INFORMATION

20

19

18

17

16

20

19

18

17

16

LTC6601-2

1

2

15

1

2

15

11

+

V

Z

IN(DIFF)

V

IN(DIFF)

V

OUT(DIFF)

200Ω

= 200Ω

OUT(DIFF)

Z

= 400Ω

4

5

4

5

–

11

6

7

8

9

10

6

7

8

9

10

66012 F15a

GAIN = 1

= 16MHz

GAIN = 2

f = 16MHz

O

Q = 0.868

f

O

Q = 0.868

f

= 15.4MHz

= 19MHz

f

= 15.4MHz

= 19MHz

–1dB

–3dB

–1dB

–3dB

Gain Magnitude vs Frequency (Gain = 1)

Passband Phase and Group Delay

5

30

0

PHASE

0

–5

–30

–60

–10

–15

–20

–25

–30

–35

–40

–90

–120

50

40

30

20

10

0

GROUP DELAY

0

100k

1M

10M

100M

100k

4M

8M

12M

16M

20M

FREQUENCY (Hz)

66012 F15b

66012 F15c

Figure 15. Modiﬁed Filter Conﬁguration Using a Resistor Between Summing Nodes (f_–3dB= 19MHz)

66012f

34

LTC6601-2

APPLICATIONS INFORMATION

20

19

18

17

16

20

19

18

17

16

33.2Ω

LTC6601-2

1

2

15

1

2

15

+

V

Z

V

Z

IN(DIFF)

V

= 266Ω

= 200Ω

OUT(DIFF)

4

5

4

5

–

33.2Ω

11

6

7

8

9

10

6

7

8

9

10

66012 F16a

GAIN = 1

= 19.7MHz

GAIN = 1.33

f = 19.7MHz

O

f

O

Q = 0.84

f

= 19MHz

= 22.7MHz

f

= 19MHz

= 22.7MHz

–1dB

–3dB

–1dB

–3dB

Gain Magnitude vs Frequency (Gain = 1)

Passband Phase and Group Delay

5

30

0

PHASE

0

–5

–30

–60

–90

–120

–10

–15

–20

–25

–30

–35

–40

50

40

30

20

10

0

GROUP DELAY

0

100k

1M

10M

100M

100k

4.6M

9.2M 13.8M 18.4M

FREQUENCY (Hz)

23M

FREQUENCY (Hz)

66012 F16b

66012 F16c

Figure 16. Modiﬁed Filter Conﬁguration Using a Resistor Between Summing Nodes (f_–3dB= 22.7MHz)

66012f

35

LTC6601-2

APPLICATIONS INFORMATION

Passband Gain vs Frequency

1.0

0.5

20

19

18

17

16

LTC6601-2

1

2

15

0.0

+

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

V

IN(DIFF)

49.9Ω

V

OUT(DIFF)

Z

= 200Ω

4

5

–

11

6

7

8

9

10

100k

1M

10M

40M

66012 F17a

GAIN = 1

= 20.7MHz

FREQUENCY (Hz)

f

O

66012 F17b

Q = 0.88

f

= 20.5MHz

= 24.6MHz

–1dB

–3dB

Gain Magnitude vs Frequency (Gain = 1)

Passband Phase and Group Delay

5

30

0

PHASE

0

–5

–30

–60

–90

–120

–10

–15

–20

–25

–30

–35

50

40

30

20

10

0

GROUP DELAY

0

100k

1M

10M

100M

100k

5.2M 10.4M 15.6M 20.8M

FREQUENCY (Hz)

26M

FREQUENCY (Hz)

66012 F17c

66012 F17d

Figure 17. Modiﬁed Filter Conﬁguration Using a Capacitor Between Summing Nodes (f_–3dB= 24.6MHz)

66012f

36

LTC6601-2

APPLICATIONS INFORMATION

DC1251A Demonstration Board

additional ﬁltering (a lowpass ﬁlter up to a 5th order can

be implemented with a DC1251A demonstration circuit).

The DC1251A has SMA connectors for the differential

input and output of the LTC6601. An on board 106MHz

lowpass RC ﬁlters the LTC6601 output.

TheDC1251AdemonstrationcircuitcontainsanLTC6601-2

(DC1251A-B). On a DC1251A the LTC6601 programming

pins can be connected through 0603 resistor jumpers. In

addition, optionalsurfacemountcapacitorsandinductors

at the LTC6601 input and/or output can be installed for

DC1251A Top Silk Screen

66012f

37

LTC6601-2

APPLICATIONS INFORMATION

66012f

38

LTC6601-2

PACKAGE DESCRIPTION

UF Package

20-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1710)

0.70 p0.05

4.50 p 0.05

3.10 p 0.05

2.45 p 0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 p0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH

R = 0.30 TYP

R = 0.115

TYP

0.75 p 0.05

4.00 p 0.10

(4 SIDES)

19 20

0.38 p 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

2.45 p 0.10

(4-SIDES)

(UF20) QFN 10-04

0.200 REF

0.25 p 0.05

0.50 BSC

0.00 – 0.05

NOTE:

1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220

VARIATION (WGGD-1)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

66012f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

39

LTC6601-2

TYPICAL APPLICATION

5th Order, 20MHz, Lowpass Filter

20

19

18

17

16

LTC6601-2

33.2Ω

1

2

15

220nH*

+

82pF

V

Z

IN(DIFF)

= 266Ω

82pF

270pF

V

OUT(DIFF)

4

5

–

33.2Ω

11

*COILCRAFT

0603CS

6

7

8

9

10

66012 TA02a

Gain Magnitude vs Frequency

Passband Gain vs Frequency

1.0

10

0.5

0

–10

–20

–30

–40

–50

–60

–70

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

100k

1M

10M

100k

1M

10M

100M

FREQUENCY (Hz)

66012 TA02c

66012 TA02b

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

Up to 10MHz Filters, SNR = 92dB, THD = –84dBc at 2MHz

LT^®1568

Very Low Noise, High Frequency, Active RC,

Filter Building Block

LT1993-2/LT1993-4/

LT1993-10

800MHz/900MHz/700MHz Low Distortion, Low Noise

Differential Ampliﬁer/ADC Driver

A = 2V/V / A = 4V/V / A = 10V/V, NF = 12.3dB/14.5dB/12.7dB,

V V V

OIP3 = 38dBm/40dBm/40dBm at 70MHz

LT1994

Low Noise, Low Distortion Fully differential Input/Output

Ampliﬁer/Driver

Low Distortion, 2V , 1MHz: –94dBc, 13mA, Low Noise: 3nV/√Hz

P-P

LT6402-6/LT6402-12/ 300MHz Low Distortion, Low Noise Differential Ampliﬁer/

A = 6dB/A = 12dB/A = 20dB, NF = 18.6dB/15dB/12.4dB,

V V V

LT6402-20

LTC6404-1

LTC6404-2

LTC6404-4

ADC Driver

OIP3 = 49dBm/43dBm/51dBm at 20MHz

Fully Differential Ampliﬁer, GBW = 500MHz

Fully Differential Ampliﬁer, GBW = 900MHz

Fully Differential Ampliﬁer, GBW = 1700MHz

Very Low Distortion, (2V , 10MHz): –91dBc

P-P

Very Low Distortion, (2V , 10MHz): –96dBc

P-P

Very Low Distortion, (2V , 10MHz): –101dBc

P-P

LT6600-2.5/LT6600-5/ Very Low Noise, Fully Differential Ampliﬁer and Filter

LT6600-10/LT6600-20

2.5MHz/5MHz/10MHz/20MHz Integrated Filter, 3V Supply,

SO-8 Package

LTC6601-1

LTC6602

Low Noise, Pin-Conﬁgurable Filter

Dual, Matched Bandpass Filter

5MHz to 27MHz Bandwidth, Second Order Differential Filter

Programmable Gain and Bandwidth for RFID Applications

(40kHz to 1MHz)

LTC6603

Dual, Matched Lowpass Filter

Programmable Gain and Bandwidth (25kHz to 2.5MHz)

2.5MHz, 5MHz, 10MHz and 15MHz

LT6604-X

LTC6605-X

7MHz, 10MHz and 14MHz

66012f

LT 0309 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

40

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC6601IUF-2PBF
厂家：	Linear
描述：	Low Power, Low Distortion, 5MHz to 27MHz, Pin Confi gurable Filter/ADC Driver 低功耗，低失真， 5MHz至27MHz的，引脚可配置的配过滤器/ ADC驱动器驱动器过滤器
文件：	总40页 (文件大小：477K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC6601IUF-2PBF [Linear]

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