LTC6602IUF-TRPBF [Linear]
Dual Matched, High Frequency Bandpass/Lowpass Filters; 双路匹配，高频带通/低通滤波器
| 型号： | LTC6602IUF-TRPBF |
| 厂家： | 
Linear |
| 描述： | Dual Matched, High Frequency Bandpass/Lowpass Filters |
| 文件： | 总28页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6602
Dual Matched, High
Frequency Bandpass/Lowpass Filters
DESCRIPTION
FEATURES
TheLTC®6602isadual,matched,programmablebandpass
orlowpassfilteranddifferentialdriver.Theselectivityofthe
LTC6602, combined with its phase matching and dynamic
range, make it ideal for filtering in RFID systems. With two
degreephasematchingbetweenchannels,theLTC6602can
be used in applications requiring highly matched filters,
such as transceiver I and Q channels. Gain programmabil-
ity, and the fully differential inputs and outputs, simplify
implementation in most systems.
n
Matched Dual Filter/Driver, Ideal for RFID Readers
Guaranteed Phase Matching to Within 2 Degrees
Guaranteed Gain Matching to Within 0.2dB
Configurable as Lowpass or Bandpass
Programmable 5th Order Lowpass: 42kHz to 900kHz
Programmable 4th Order Highpass: 4.2kHz to 90kHz
Programmable Gain: 1×, 4×, 16×, 32×
Simple Pin Programming or SPI Interface
Low Noise: –145dBm/Hz (Input Referred)
Low Distortion: –75dBc at 200kHz
n
n
n
n
n
n
n
n
n
n
n
n
Both channels of the LTC6602 consist of a programmable
lowpass and highpass filter. For bandpass functionality,
the lowpass filters are programmed for the upper cutoff
frequency. For lowpass functionality, the highpass filters
can be bypassed. The filter cutoff frequencies can be set
with a guaranteed accuracy of 3% with the use of a single
resistor. Alternatively, the filter cutoff frequencies can be
controlled with an external clock.
Differential, Rail-to-Rail Inputs and Outputs
Input Range Extends from 0V to 5V
Low Voltage Operation: 2.7V to 3.6V
Shutdown Mode
4mm × 4mm QFN Package
APPLICATIONS
n
Multiprotocol RFID Readers:
The LTC6602 operates on a single 2.7V to 3.6V supply
and features a low power shutdown mode.
EPC-GEN2, ISD and IPX
n
IDEN, PHS, GSM Basestations
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners..
n
Repeaters, Radio Links, and Modems
n
Wireless Telemetry
JTRS
n
TYPICAL APPLICATION
UHF RFID Reader Dual Baseband Filter and Dual ADC
Gain vs Frequency
3V
20
10
EXTERNAL CLOCK = 90MHz
0.1μF
0.1μF
+
100Ω
100Ω
15kHz-150kHz BPF
90kHz-900kHz BPF
A
IN
0
100pF
100pF
14-BIT
ADC
V+
V+
A
V+
D
100pF
IN
–10
–20
–30
–40
–50
–60
–
A
–OUTA
+OUTA
–OUTB
+OUTB
CLKIO
SER
IN
IN
+INA
–INA
+INB
–INB
I INPUT
Q INPUT
0.1μF
I OUTPUT
Q OUTPUT
V
CM
2.2μF
LTC2297
+
100Ω
100Ω
LTC6602
B
R
BIAS
OCM
45kHz-300kHz BPF
38.3k
100pF
100pF
V
14-BIT
ADC
100pF
CLKCNTL
HPF0(SDO)
HPF1(SDI)
LPF0(SCLK)
LPF1(CS)
1k
10k
100k
1M
10M
MUTE
GAIN0(D0)
GAIN1
GND
–
B
IN
FREQUENCY (Hz)
6602 TA01b
MUTE
INPUT
FROM
CLK IN
6602 TA01
TRANSMITTER
GND
÷4
CS SCLK SDI
SPI CONTROL INPUT
CLOCK INPUT
24MHz TO 128MHz
(COVERS THE TAG BACKSCATTER LINK FREQUENCY RANGE OF 40kHz to 640kHz
OF THE CLASS 1 GENERATION 2 UHF RFID COMMUNICATION PROTOCOL)
6602fa
1
LTC6602
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V+ to GND................................................................6V
IN
V+ V+ to GND .........................................................4V
A,
D
Filter Inputs to GND ....................... –0.3V to V+ + 0.3V
IN
24 23 22 21 20 19
All Other Pins to GND.............. –0.3V to V+ , V+ + 0.3V
A
D
Maximum Input Current....................................... 10mA
Output Short Circuit Duration........................... Indefinite
Operating Temperature Range (Note 2)
V+
1
2
3
4
5
6
18 –OUTA
IN
V+
SER
17
16
A
V
V+
D
OCM
BIAS
25
R
15 CLKIO
GND
LTC6602CUF ........................................ –40°C to 85°C
LTC6602IUF ......................................... –40°C to 85°C
Specified Temperature Range (Note 3)
CLKCNTL
14
13 +OUTB
LPF1(CS)
7
8
9 10 11 12
LTC6602CUF ............................................ 0°C to 70°C
LTC6602IUF ......................................... –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
T
= 150°C, θ = 37°C/W
JA
JMAX
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO THE PCB.
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL
PART MARKING*
6602
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
LTC6602CUF#PBF
LTC6602IUF#PBF
LTC6602CUF#TRPBF
LTC6602IUF#TRPBF
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
6602
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which app ly over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =
300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 45kHz,
Gain = 0dB
Lowpass Filter Cutoff = 300kHz, V = 3.6V
IN P-P
l
l
l
l
l
f
f
f
f
f
= 22.5kHz
= 45kHz
–32
–1.2
0.5
–30
–0.8
0.8
–1.2
–43
dB
dB
dB
dB
dB
IN
IN
IN
IN
IN
–1.8
0.1
–2.7
= 150kHz
= 300kHz
= 900kHz
–2
–44
Matching of Filter Gain
External Clock = 90MHz, Highpass Filter Cutoff = 45kHz,
Lowpass Filter Cutoff = 300kHz, V = 3.6V
IN
P-P
l
l
l
f
f
f
= 45kHz
0.2
0.2
0.2
dB
dB
dB
IN
IN
IN
= 150kHz
= 300kHz
6602fa
2
LTC6602
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =
300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Filter Phase
Either Channel
External Clock = 90MHz, V = 3.6V , Highpass Filter Cutoff = 45kHz,
IN
P-P
Lowpass Filter Cutoff = 300kHz
l
l
f
IN
f
IN
= 50kHz
= 250kHz
125
–134
130
–130
134
–126
deg
deg
Matching of Filter Phase External Clock = 90MHz, V = 3.6V , Highpass Filter Cutoff = 45kHz,
IN
P-P
Lowpass Filter Cutoff = 300kHz
l
l
f
f
= 50kHz
2
1.5
deg
deg
IN
IN
= 250kHz
Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 15kHz,
Gain = 0dB
Lowpass Filter Cutoff = 150kHz, V = 3.6V
IN P-P
l
l
l
l
l
f
IN
f
IN
f
IN
f
IN
f
IN
= 7.5kHz
= 15kHz
= 50kHz
= 150kHz
= 450kHz
–32
–1.2
0.7
–1.9
–44
–30
–0.8
0.9
–1.3
–43
dB
dB
dB
dB
dB
–1.6
0.4
–2.3
Matching of Filter Gain
External Clock = 90MHz, V = 3.6V , Highpass Filter Cutoff = 15kHz,
IN
P-P
Lowpass Filter Cutoff = 150kHz
l
l
l
f
IN
f
IN
f
IN
= 15kHz
= 50kHz
= 150kHz
0.2
0.2
0.2
dB
dB
dB
Filter Phase Either
Channel
External Clock = 90MHz, V = 3.6V , Highpass Filter Cutoff = 15kHz,
IN
P-P
Lowpass Filter Cutoff = 150kHz
l
l
f
IN
f
IN
= 16.5kHz
= 125kHz
137
–142
142
–138
146
–134
deg
deg
Matching of Filter Phase External Clock = 90MHz, V = 3.6V , Highpass Filter Cutoff = 15kHz,
IN
P-P
Lowpass Filter Cutoff = 150kHz
l
l
f
f
= 16.5kHz
= 125kHz
2
1
deg
deg
IN
IN
Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 90kHz,
Gain = 0dB
Lowpass Filter Cutoff = 900kHz, V = 3.6V
IN P-P
l
l
l
l
l
f
IN
f
IN
f
IN
f
IN
f
IN
= 45kHz
–29
–1.2
0.6
–1.1
–45
–27
–0.7
1.2
–0.5
–44
dB
dB
dB
dB
dB
= 90kHz
–1.8
–0.1
–2.1
= 300kHz
= 900kHz
= 2700kHz
Matching of Filter Gain
External Clock = 90MHz, Highpass Filter Cutoff = 90kHz,
Lowpass Filter Cutoff = 900kHz, V = 3.6V
IN
P-P
l
l
l
f
f
f
= 90kHz
0.3
0.6
0.4
dB
dB
dB
IN
IN
IN
= 300kHz
= 900kHz
Filter Phase Either Chanel External Clock = 90MHz, V = 3.6V , Highpass Filter Cutoff = 90kHz,
IN
P-P
Lowpass Filter Cutoff = 900kHz
l
l
f
f
= 100kHz
= 750kHz
136
–136
141
–131
145
–127
deg
deg
IN
IN
Matching of Filter Phase External Clock = 90MHz, V = 3.6V , Highpass Filter Cutoff = 90kHz,
IN
P-P
Lowpass Filter Cutoff = 900kHz
l
l
f
f
= 100kHz
= 750kHz
2
1.5
deg
deg
IN
IN
Filter Cutoff Accuracy
when Self Clocked
CLKCNTL = 3V (Note 4)
l
l
R
R
= 200k, Output Clock = 24.705MHz
= 54.9k, Output Clock = 90MHz
3
3
%
%
BIAS
BIAS
6602fa
3
LTC6602
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =
300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PGA Gain
Lowpass Cutoff = 150kHz, Highpass Filter Bypassed,
Measured at DC, 0.6V to 2.4V Each Output
Gain Setting = 0dB
l
l
l
l
0.4
0.8
12
23.8
29.6
1.2
dB
dB
dB
dB
Gain Setting = 12dB
11.6
23.5
29.1
12.4
24.1
30.1
Gain Setting = 24dB
Gain Setting = 30dB
PGA Gain Matching
Lowpass Cutoff = 150kHz, Highpass Filter Bypassed,
Measured at DC, 0.6V to 2.4V Each Output
Gain Setting = 0dB
l
l
l
l
0.2
0.2
0.3
0.3
dB
dB
dB
dB
Gain Setting = 12dB
Gain Setting = 24dB
Gain Setting = 30dB
Noise At 200kHz
Integrated Noise
Voltage Noise Referred to the Input
Gain = 0dB
–119
–131
–142
–146
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
Gain = 12dB
Gain = 24dB
Gain = 30dB
Noise Bandwidth = 1.57MHz (Note 5), Referred to the Input
Gain = 0dB
Gain = 12dB
Gain = 24dB
Gain = 30dB
–62
–74
–85
–89
dBm
dBm
dBm
dBm
THD
V
= 1.5V , f = 100kHz
–75
dB
IN
P-P IN
Input Impedance
Differential
Common Mode
16
20
kΩ
kΩ
l
l
l
V
OS
Differential
Differential Offset Voltage at Either Output
Differential Offset Voltage at Either Output HPF Bypassed, Lowest LPF Cutoff
Differential Offset Voltage at Either Output HPF Bypassed, Highest LPF Cutoff
7
10
10
15
30
30
mV
mV
mV
V
Common Mode Offset Voltage
OSCM
l
V
V
= 1.5V, Supplies = 3V
–40
75
20
70
mV
OCM
OSCM
= V
– V
OCM
OUT-CM
CMR Differential
ΔV /ΔV
Common Mode Input from 0 to 3V
l
V+ = 3V
95
dB
INCM
OUTDIFF
IN
Common Mode Input from 0 to 5V
l
l
l
V+ = 5V
IN
75
1.2
300
95
1.4
400
dB
V
V
V
Pin Voltage
Pin Input
V+ = V+ = 3V, Pin 3 Open
1.6
OCM
OCM
A
D
V+ = V+ = 3V, Pin 3 Open
700
Ω
A
D
Impedance
Output Swing
Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC
Source 1mA, V High, Relative to V+
l
l
200
200
500
500
mV
mV
OUT
A
Sink 1mA, V
Low, Relative to GND
OUT
Short-Circuit Current
Supply Current
Lowpass Cutoff = 150kHz, Highpass Filter Bypassed
l
l
Sourcing
Sinking
4
10
15
25
25
50
mA
mA
Internal Clock (R
IN
= 54.9k); Sum of the Currents into V+ , V+ , and
D A
BIAS
V+ All Supplies Set to 3V
l
l
l
HPF = 15k, LPF = 150k
HPF = 45k, LPF = 300k
HPF = 90k, LPF = 900k
65
100
105
80
125
130
mA
mA
mA
6602fa
4
LTC6602
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =
300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted.
PARAMETER
CONDITIONS
Sum of the Currents into V+ , V+ , and V+ ; All Supplies Set to 3V
MIN
TYP
MAX
UNITS
Supply Current,
Shutdown Mode
D
A
IN
l
Shutdown Via Serial Interface, Control Bit D1 = 1.
170
235
μA
l
l
Supply Voltage
V+ , V+ Relative to GND
IN
2.7
2.7
3.6
5.5
V
V
D
A
V+ Relative to GND
l
l
PSR
V+ = V+ = V+ , All from 2.7V to 3.6V
50
80
60
95
dB
dB
D
A
IN
V+ = V+ = 3.0V, V+ from 4.5V to 5.5V
D
A
IN
l
R
R
Resistor Range
Pin Voltage
Clock Frequency Error ≤ 3%, CLKCNTL = 3V
54.9k < R < 200k
54.9
200
kΩ
V
BIAS
1.17
40
BIAS
BIAS
Clock Frequency Drift
Over Temperature
R
BIAS
= 54.9k, CLKCNTL Pin Open
ppm/ºC
l
l
Clock Frequency Change V+ , V+ from 2.7V to 3.6V, R
= 54.9k, CLKCNTL Pin Open
–0.6
25
0.1
50
0.6
75
%/V
A
D
BIAS
Over Supply
Output Clock Duty Cycle
R
BIAS
= 54.9k
%
V
CLKIO Pin High Level
Input Voltage
CLKCNTL = 0V (Note 6)
V
– 0.3
+D
CLKIO Pin Low Level
Input Voltage
CLKCNTL = 0V (Note 6)
0.3
10
V
CLKIO Pin Input Current CLKCNTL = 0V
CLKIO = 0V (Note 7)
CLKIO = V+
l
l
–1
μA
μA
D
CLKIO Pin High Level
Output Voltage
V+ = V+ = 3V, CLKCNTL = 3V
A
D
I
I
= –1mA
2.95
2.9
V
V
OH
OH
= –4mA
CLKIO Pin Low Level
Output Voltage
V+ = V+ = 3V, CLKCNTL = 3V
A
D
I
I
= 1mA
0.05
0.1
V
V
OL
OL
= 4mA
CLKIO Rise Time
CLKIO Fall Time
V+ = V+ = CLKCNTL = 3V, 20%/80%, C
= 5pF
= 5pF
0.3
0.3
ns
ns
V
A
D
LOAD
V+ = V+ = CLKCNTL = 3V, 20%/80%, C
A
D
LOAD
l
l
SER, MUTE
High Level Input Voltage
Pins 17, 20
V
V
– 0.3
+D
SER, MUTE
Low Level Input Voltage
Pins 17, 20
0.3
2
V
l
l
SER, MUTE
Input Current
Pin 17 or Pin 20 = 0V (Note 7)
–10
– 0.5
μA
μA
Pin 17 or Pin 20 = V+
D
l
CLKCNTL High Level
Input Voltage
Pin 5
V
+D
CLKCNTL Low Level
Input Voltage
Pin 5
0.5
25
V
l
l
CLKCNTL Input Current
CLKCNTL = 0V (Note 7)
CLKCNTL = V+
–25
–15
15
μA
μA
D
6602fa
5
LTC6602
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Specifications apply to pins 6, 9-11, 21 and 22.
Pin Programmable Control Mode Specifications
SYMBOL
V+ = 2.7V to 3.6V
PARAMETER
CONDITIONS
MIN
2
TYP
MAX
UNITS
D
l
l
l
V
IH
V
IL
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
Pins 6, 9-11, 21, 22
V
V
Pins 6, 9-11, 21, 22
0.8
1
I
IN
Pins 6, 9-11, 21, 22 (Note 7)
–1
μA
Serial Port DC and Timing Specifications
SYMBOL
V+ = 2.7V to 3.6V
PARAMETER
CONDITIONS
MIN
2
TYP
MAX
UNITS
D
l
l
l
l
l
l
l
l
l
l
l
l
l
l
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
Digital Output High Voltage
Digital Output Low Voltage
SDI Valid to SCLK Setup
SDI Valid to SCLK Hold
SCLK Low
Pins 6, 9, 10
V
V
IH
IL
Pins 6, 9, 10
0.8
1
I
Pins 6, 9, 10 (Note 7)
Pins 11, 21 Sourcing 500μA
Pins 11, 21 Sinking 500μA
(Note 6)
–1
μA
V
IN
V
V
V
-0.3
OH
OL
SUPPLY
0.3
V
t
t
t
t
t
t
t
t
t
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
(Note 6)
2
3
4
5
6
7
8
9
100
100
60
SCLK High
CS Pulse Width
LSB SCLK to CS
(Note 6)
(Note 6)
60
CS Low to SCLK
30
SDO Output Delay
C = 15pF
L
125
SCLK Low to CS Low
(Note 6)
0
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: This test measures the internal oscillator accuracy (deviation from
the f
equation). Variations in the internal oscillator frequency cause
variations in the filter cutoff frequency. See the “Applications Information”
section.
CLK
Note 2: LTC6602C and LTC6602I are guaranteed functional over the
operating temperature range of –40°C to 85°C.
Note 5: 1.57MHz is the equivalent noise bandwidth of a 1MHz 1st order
RC lowpass filter.
Note 3: LTC6602C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6602C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LTC6602I is guaranteed to meet the
specified performance limits from –40°C to 85°C.
Note 6: Guaranteed by design, not subject to test.
Note 7: To conform to the Logic IC standard, current out of a pin is
arbitrarily given a negative value.
6602fa
6
LTC6602
TYPICAL PERFORMANCE CHARACTERISTICS
Gain vs Frequency
Distortion vs Input Frequency
Distortion vs Output Voltage
20
10
–70
–75
–80
–85
–90
–30
–40
–50
–60
–70
–80
–90
–100
T
= 25°C
= 3V
T
= 25°C, V = 3V, DIFFERENTIAL INPUT,
S
A
S
T
= 25°C
= 3V
A
A
S
V
V
= 1.5V , 12.4-82.4kHz BPF, R
= 200k
BIAS
V
f
IN
P-P
EXTERNAL CLOCK
15kHz-150kHz BPF
90kHz-900kHz BPF
45kHz-300kHz BPF, R
= 54.9k, GAIN = 0dB
= 100kHz
BIAS
IN
R
= 54.9k
BIAS
DIFFERENTIAL INPUT
0
GAIN = 0dB
HD3
R
R
= 54.9k
BIAS
BIAS
12kHz-82kHz BPF
= 45kHz-300kHz BPF
–10
–20
–30
–40
–50
–60
GAIN = 0dB
HD2
45kHz-300kHz BPF
HD2
HD3
HD2
12kHz-82kHz BPF
HD3
45kHz-300kHz BPF
45kHz-300kHz BPF
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
50
100
150
200
250
300
0
1
2
3
4
5
6
INPUT FREQUENCY (kHz)
OUTPUT VOLTAGE (V
)
P-P
6602 G01
66062 G02
66062 G03
Distortion vs Highpass
Cutoff Frequency
Distortion vs Lowpass
Cutoff Frequency
Distortion vs Gain
–70
–75
–80
–85
–90
–70
–75
–80
–85
–90
–70
–75
–80
–85
–90
T
= 25°C
= 3V
T
= 25°C
S
A
S
A
V
V
f
= 3V
= 100kHz
f
= 100kHz
IN
IN
DIFFERENTIAL INPUT, V
= 1.5V
P-P
DIFFERENTIAL INPUT, V = 1.5V
OUT
IN
P-P
= 54.9k
R
= 54.9k
R
f
BIAS
BIAS
45kHz-300kHz BPF
= 300kHz
LP
GAIN = 0dB
HD3
HD2
HD3
HD2
HD3
HD2
T
= 25°C
S
A
V
= 3V
f
= 100kHz
IN
DIFFERENTIAL INPUT, V = 1.5V
IN
P-P
= 54.9k
= 45kHz
R
BIAS
HP
f
GAIN = 0dB
750 900
LOWPASS CUTOFF FREQUENCY (kHz)
0
15
30
45
60
75
90
0
6
12
18
24
30
0
150
300
450
600
HIGHPASS CUTOFF FREQUENCY (kHz)
GAIN (dB)
6602 G05
6602 G04
6602 G06
Filter Cutoff Accuracy
vs Supply Voltage
Filter Cutoff Accuracy
vs Temperature
Common Mode Rejection
0.10
0.05
120
110
100
90
0.4
0.3
R
= 54.9k
V
= 3V
BIAS
CMR = ΔV
/ΔV
OUT-DIFF
BIAS
S
IN-CM
45kHz-300kHz BPF
GAIN = 0dB
R
= 54.9k
45kHz-300kHz BPF
GAIN = 0dB
0.2
–40°C
85°C
0.1
80
5 TYPICAL UNITS
70
0.0
GAIN = 0dB
60
GAIN = 12dB
–0.1
–0.2
–0.3
–0.4
25°C
T
V
V
ΔV
R
= 25°C
= 3V
0.00
A
S
50
GAIN = 24dB
GAIN = 30dB
= 0V
IN-CM
IN-CM
40
= 1.25V
P-P
30
= 54.9k
BIAS
45kHz-300kHz BPF
–0.05
20
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
1k
10k
100k
1M
10M
–40 –20
0
20
40
60
80
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
TEMPERATURE (°C)
6602 G07
6602 G09
6602 G08
6602fa
7
LTC6602
TYPICAL PERFORMANCE CHARACTERISTICS
Common Mode Rejection Ratio
Common Mode Rejection
Common Mode Rejection
120
110
100
90
120
110
100
90
120
110
100
90
T
V
R
= 25°C, V = 3V,
S
CMR = ΔV
/ΔV
OUT-DIFF
A
IN-CM
= 0V, ΔV
= 1.25V
IN-CM
IN-CM P-P,
= 54.9k, 90kHz-900kHz BPF
BIAS
GAIN = 30dB
GAIN = 12dB
GAIN = 0dB
GAIN = 24dB
80
80
80
GAIN = 24dB
GAIN = 30dB
70
70
70
GAIN = 0dB
60
60
GAIN = 12dB
60
T
V
V
ΔV
R
= 25°C
= 3V
GAIN = 0dB
A
S
50
50
50
GAIN = 24dB
GAIN = 12dB
= 0V
IN-CM
IN-CM
40
40
40
T
V
R
= 25°C, V = 3V,
S
IN-CM P-P,
= 54.9k, 45kHz-300kHz BPF
= 1.25V
A
P-P
= 0V, ΔV
= 1.25V
30
= 54.9k
30
30
IN-CM
BIAS
GAIN = 30dB
1M 10M
CMR = ΔV
/ΔV
OUT-DIFF
15kHz-150kHz BPF
IN-CM
BIAS
20
20
20
1k
10k
100k
1M
10k
100k
FREQUENCY (Hz)
1k
10k
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
6602 G10
6602 G11
6602 G12
OIP3 vs Average Signal
Frequency, fC
Common Mode Rejection Ratio
Common Mode Rejection Ratio
120
110
100
90
48
46
44
42
40
38
120
110
100
90
T
V
V
ΔV
R
= 25°C
= 3V
T
= 25°C
= 3V
A
S
A
V
f
S
GAIN = 30dB
= 0V
= f –5kHz, f = f +5kHz
IN-CM
IN-CM
1
C
2
C
GAIN = 24dB
= 1.25V
V
= 6dBm PER TONE FOR 2-TONE TEST
= 54.9k
P-P
OUT
= 54.9k
R
BIAS
BIAS
90kHz-900kHz BPF
45kHz-300kHz BPF
80
80
GAIN = 24dB
GAIN = 12dB
GAIN = 24dB
GAIN = 30dB
GAIN = 12dB
70
70
GAIN = 0dB
60
60
GAIN = 12dB
GAIN = 0dB
50
50
GAIN = 30dB
GAIN = 0dB
40
40
T
V
R
= 25°C, V = 3V,
A
S
= 0V, ΔV
= 1.25V
30
30
IN-CM
IN-CM P-P,
= 54.9k, 15kHz-150kHz BPF
BIAS
20
20
10k
100k
1M
10M
0
50 100 150 200 250 300 350
1k
10k
100k
1M
FREQUENCY (Hz)
CENTER SIGNAL FREQUENCY, f (kHz)
C
FREQUENCY (Hz)
6602 G14
6602 G15
6602 G13
OIP3 vs Average Signal
Frequency, fC
OIP3 vs Average Signal
Frequency, fC
OIP3 vs Temperature
50
48
46
44
42
40
48
46
44
42
40
38
48
46
44
42
40
38
V
V
= 3V
OUT
T
f
= 25°C, V = 3V
S
GAIN = 30dB
S
A
1
V
= 6dBm PER TONE
= f –10kHz, f = f +10kHz
C
2
C
FOR 2-TONE TEST
= 54.9k
GAIN = 12dB
GAIN = 24dB
= 6dBm PER TONE
OUT
GAIN = 12dB
R
FOR 2-TONE TEST
= 54.9k
BIAS
GAIN = 30dB
R
BIAS
f
IN
= 95kHz, 105kHz
15kHz-150kHz BPF
90kHz-900kHz BPF
GAIN = 0dB
f
= 145kHz, 155kHz
IN
T
= 25°C
S
C
C
A
45kHz-300kHz BPF
V
= 3V
f
1
f
2
= f –5kHz
= f +5kHz
GAIN = 24dB
GAIN = 30dB
V
= 6dBm PER TONE
FOR 2-TONE TEST
OUT
f
= 590kHz, 610kHz
IN
90kHz-900kHz BPF
R
BIAS
= 54.9k
GAIN = 0dB
15kHz-150kHz BPF
20 40 60 80 100 120 140 160
CENTER SIGNAL FREQUENCY, f (kHz)
–40–30–20–10 0 10 20 30 40 50 60 70 80 90
0
0
100 200 300 400 500 600 700 800 9001000
CENTER SIGNAL FREQUENCY, f (kHz)
TEMPERATURE (°C)
C
C
6602 G18
6602 G16
6602 G17
6602fa
8
LTC6602
TYPICAL PERFORMANCE CHARACTERISTICS
Output Impedance vs Frequency
Supply Current vs Supply Voltage
Supply Current vs Temperature
110
105
100
95
100
10
1
120
100
80
60
40
20
0
CLKCNTL PIN FLOATING
T
= 25°C
= 3V
BIAS
A
S
90kHz-900kHz BPF
45kHz-300kHz BPF
R
BIAS
= 54.9k
V
45kHz-300kHz BPF
GAIN = 0dB
R
= 54.9k
85°C
15kHz-150kHz BPF
90kHz-900kHz BPF
15kHz-150kHz BPF
25°C
–40°C
900kHz LPF
V
= 3V
S
CLKCNTL PIN FLOATING
= 54.9k
R
BIAS
45kHz-300kHz BPF
GAIN = 0dB
90
0.1
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–40–30–20–10 0 10 20 30 40 50 60 70 80 90
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
6602 G20
6602 G19
6602 G21
Clock Output Operating at 90MHz
RBIAS Pin Voltage vs IRBIAS
1.25
1.20
1.15
1.10
T
= 25°C
= 3V
A
S
V
1V/DIV
0V
6602 G22
0
5
10
15
20
25
2.5ns/DIV
I
(μA)
RBIAS
6602 G23
Input Referred Noise Density
Input Referred Noise Density
Input Referred Noise Density
1000
100
10
1000
100
10
1000
100
10
GAIN = 0dB INTEGRATED NOISE = 304.2μV
GAIN = 0dB
INTEGRATED
GAIN = 0dB INTEGRATED NOISE = 189μV
RMS
RMS
GAIN = 12dB INTEGRATED NOISE
NOISE = 186.5μV
= 77.6μV
RMS
RMS
GAIN = 12dB
INTEGRATED NOISE
= 47.1μV
RMS
GAIN = 12dB
INTEGRATED
GAIN = 24dB
INTEGRATED
GAIN = 24dB
INTEGRATED
NOISE = 12.6μV
NOISE= 47.8μV
RMS
GAIN = 24dB
INTEGRATED NOISE = 12.5μV
NOISE = 20.7μV
GAIN = 30dB
INTEGRATED
NOISE = 7.5μV
RMS
RMS
RMS
GAIN = 30dB
INTEGRATED NOISE = 17.5μV
GAIN = 30dB INTEGRATED NOISE = 7.2μV
RMS
RMS
RMS
1
1
1
1k
10k
100k
1M
10k
100k
1M
10M
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6602 G24
6602 G26
6602 G25
T
= 25°C, V = 3V, EXTERNAL CLOCK
S
BIAS
T
= 25°C, V = 3V, EXTERNAL CLOCK
A
S
BIAS
T
= 25°C, V = 3V, EXTERNAL CLOCK
S
BIAS
A
R
A
R
= 54.9k, 45kHz-300kHz BPF
R
= 54.9k, 90kHz-900kHz BPF
= 54.9k, 15kHz-150kHz BPF
INTEGRATED NOISE BW = 1.57MHz
INTERNAL NOISE BW = 2.5MHz
INTERNAL NOISE BW = 400kHz
6602fa
9
LTC6602
PIN FUNCTIONS
V+ (Pin 1): Input Voltage Supply (2.7V ≤ V ≤ 5.5V). This
This is realized with two internal current sources, one tied
IN
supply must be kept free from noise and ripple. It should
to V+ and CLKCNTL and the other one tied to ground
D
be bypassed directly to a ground plane with a 0.1μF ca-
and CLKCNTL. Therefore, driving the CLKCNTL pin high
requires sourcing approximately 15μA. Likewise, driving
the CLKCNTL pin low requires sinking 15μA. When the
CLKCNTL pin is floated, preferably it should be bypassed
by a 1nF capacitor to ground or it should be surrounded
by a ground shield to prevent excessive coupling from
other PCB traces.
pacitor unless it is tied to V+ (Pin 2). The bypass should
A
be as close as possible to the IC, but is not as critical as
the bypassing of V+ and V+ (Pin16).
A
D
V+ (Pin 2): Analog Voltage Supply (2.7V ≤ V ≤ 3.6V). This
A
supplymustbekeptfreefromnoiseandripple.Itshouldbe
bypassed directly to a ground plane with a 0.1μF capacitor.
The bypass should be as close as possible to the IC.
LPF1(CS)(Pin6):LogicInput.Wheninpin programmable
control mode, this pin is the MSB of the lowpass cutoff
frequency control code; in serial control mode, this pin is
the chip select input (active low).
V
(Pin 3): Output common mode voltage reference. If
OCM
floated, aninternalresistivedividersetsthevoltageonthis
pin to half the supply voltage (typically 1.5V), maximizing
the dynamic range of the filter. If this pin is floated, it must
be bypassed with a quality 0.1μF capacitor to ground.
This pin has a typical input impedance of 400Ω and may
be overdriven. Driving this pin to a voltage other than the
default value will reduce the signal range the filter can
handle before clipping.
+INB, –INB (Pins 7, 8): Channel B differential inputs.
The input range and input resistance are described in the
Applications Information section. Input voltages which
exceed V+ (Pin 1) should be avoided.
IN
LPF0(SCLK) (Pin 9): Logic Input. When in pin program-
mable control mode, this pin is the LSB of the lowpass
cutoff frequency control code; in serial control mode, this
pin is the clock of the serial interface.
R
BIAS
(Pin4):OscillatorFrequency-SettingResistorInput.
The value of the resistor connected between this pin and
ground determines the frequency of the master oscillator,
and sets the bias currents for the filter networks. The volt-
age on this pin is held by the LTC6602 to approximately
1.17V. For best performance, use a precision metal film
resistor with a value between 54.9k and 200k and limit the
capacitance on this pin to less than 10pF. This resistor is
necessary even if an external clock is used.
HPF1(SDI) (Pin 10): Logic Input. When in pin program-
mable control mode, this pin is the MSB of the highpass
cutoff frequency control code; in serial control mode, this
pin is the serial data input.
HPF0(SDO) (Pin 11): Logic Input. When in pin program-
mable control mode, this pin is the LSB of the highpass
cutoff frequency control code; in serial control mode, this
pin is the serial data output.
CLKCNTL (Pin 5): Clock Control Input. This three-state
input selects the function of CLKIO (Pin 15). Tying the
CLKCNTL pin to ground allows the CLKIO pin to be driven
by an external clock (CLKIO is the master clock input).
If the CLKCNTL pin is floated, the internal oscillator is
enabled, but the master clock is not present at the CLKIO
pin (CLKIO is a no-connect). If the CLKCNTL pin is tied
–OUTB, +OUTB (Pins 12, 13): Channel B differential filter
outputs. These pins can drive 1k and/or 50pF loads. For
larger capacitive loads, an external 100Ω series resistor
is recommended for each output. The common mode
voltage of the filter outputs is the same as the voltage at
V
OCM
(Pin 3).
to V+ (Pin 16), the internal oscillator is enabled and the
D
master clock is present at the CLKIO pin (CLKIO is the
master clock output). To detect a floating CLKCNTL pin,
the LTC6602 attempts to pull the pin toward mid-supply.
GND (Pin 14): Ground. Connect to a ground plane for
best performance.
6602fa
10
LTC6602
PIN FUNCTIONS
CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground,
CLKIOisthemasterclockinput.WhenCLKCNTLisfloated,
CLKIO is pulled to ground by a weak, 5μA pulldown. When
larger capacitive loads, an external 100Ω series resistor
is recommended for each output. The common mode
voltage of the filter outputs is the same as the voltage at
CLKCNTListiedtoV+ (Pin16), CLKIOisthemasterclock
V
(Pin 3).
D
OCM
output. When configured as a clock output, this pin can
drive 1k and/or 5pF loads. Heavier loads may cause inac-
curacies due to supply bounce at high frequencies.
MUTE (Pin 20): MUTEX input. Drive to ground to discon-
nect and mute the inputs. Float or drive to V+ (Pin 16)
D
for normal operation.
V+ (Pin 16): Digital Voltage Supply (2.7V ≤ V ≤ 3.6V).
D
GAIN0(D0) (Pin 21): Logic Input. When in pin program-
mable control mode, this pin is the LSB of the gain control
code; in serial control mode, this pin is the LSB of the
serial control register, an output.
This supply must be kept free from noise and ripple. It
shouldbebypasseddirectlytoagroundplanewitha0.1μF
capacitor. The bypass should be as close as possible to
the IC.
GAIN1 (Pin 22): Logic Input. When in pin programmable
control mode, this pin is the MSB of the gain control code;
in serial control mode, this pin is a no-connect.
SER (Pin 17): Interface Selection Input. When tied to V
+D
(Pin16),theinterfaceisinpinprogrammablecontrolmode,
i.e. the filter gain and cutoff frequencies are programmed
by the GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0 pin
connections. When SER is tied to ground, the filter gain,
the filter cutoff frequencies and shutdown mode are pro-
grammed by the serial interface.
–INA, +INA (Pins 23, 24): Channel A differential inputs.
The input range and input resistance are described in the
Applications Information section. Input voltage levels can
range from GND to the V+ supply rail.
IN
Exposed Pad (Pin 25): Ground. The Exposed Pad must
be soldered to PCB.
–OUTA, +OUTA (Pins 18, 19): Channel A differential filter
outputs. These pins can drive 1k and/or 50pF loads. For
6602fa
11
LTC6602
BLOCK DIAGRAM
+INA
–INA
23
GAIN1
22
GAIN0(D0)
21
MUTE
+OUTA
19
24
20
V+
1
18
17
–OUTA
IN
CHANNEL A
LPF
PGA
HPF
CLK
V+
SER
2
3
A
CONTROL
BIAS
V
DDA
1.6k
1.6k
V
16 V+
OCM
D
CLOCK
GENERATOR
CONTROL
LOGIC
BIAS/OSC
GND
R
4
5
6
15
CLKIO
BIAS
BIAS
PGA
CONTROL
LPF
CLK
HPF
CLKCNTL
14 GND
CHANNEL B
+OUTB
13
LPF1(CS)
7
8
9
10
11
12
+INB
–INB
LPF0(SCLK)
HPF1(SDI)
HPF0(SDO)
–OUTB
6602 BD
6602fa
12
LTC6602
TIMING DIAGRAM
Timing Diagram of the Serial Interface
t
4
t
1
t
6
t
2
t
t
7
3
SCLK
SDI
CS
t
9
D3
D2
D1
D0
D7 • • • • D4
D3
t
5
t
8
D4
D3
D2
D1
D0
D7 • • • • D4
D3
SDO
PREVIOUS BYTE
CURRENT BYTE
6602 TD
6602fa
13
LTC6602
APPLICATIONS INFORMATION
Theory of Operation (Refer to Block Diagram)
Pin Programmable Interface
The LTC6602 features two matched filter channels, each
containing gain control, lowpass, and highpass networks
thatarecontrolledbyasinglecontrolblockandclockedby
a single clock generator. The gain, lowpass and highpass
sections can be independently programmed. The two
channelsarenotindependent, i.e. ifthegainissetto24dB,
then both channels have a gain of 24dB. The filter can also
be programmed to bypass the highpass filter networks,
giving a lowpass response. The filter can be clocked with
an external clock source, or using the internal oscillator. A
As shown in Figure 1, connecting SER to V+ allows the
D
filtertobedirectlycontrolledthroughthepinprogrammable
control lines GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0.
The HPF0(SDO) and GAIN0(D0) pins are bidirectional (in-
puts in pin programmable control mode, outputs in serial
mode). In pin programmable control mode, the voltages
at HPF0(SDO) and GAIN0(D0) cannot exceed V+ ; oth-
D
erwise, large currents can be injected to V+ through the
D
internal diodes (see Figure 2). Connecting a 10k resistor
at the HPF0(SDO) and GAIN0(D0) pins (see Figure 1) is
recommendedforcurrentlimiting,tolessthan10mA.SER
resistor connected to the R
pin sets the bias currents
BIAS
for the filter networks and the internal oscillator frequency
(unless driven by an external clock). Altering the clock
frequency changes the filter bandwidths. This allows the
filters to be “tuned” to many different bandwidths.
has an internal pull-up to V . None of the logic inputs
+D
have an internal pull-up or pull-down.
3.3V
3.3V
LTC6602
0.1μF
LTC6602
0.1μF
V+
V+
V+
V+
V+
V+
IN
IN
A
A
D
D
+
V
–
+
V
–
+
+
+INA
+OUTA
–OUTA
+INA
+OUTA
–OUTA
V
V
OUT
OUT
IN
IN
–INA
–INA
–
–
SER
SER
LPF1
LPF1(CS)
LPF0(SCLK)
HPF1(SDI)
HPF0(SDO)
GAIN1
LPF1(CS)
LPF0(SCLK)
HPF1(SDI)
HPF0(SDO)
GAIN1
LPF0
HPF1
HPF0
GAIN1
GAIN0
μP
10k
10k
GAIN0(D0)
GND
GAIN0(D0)
GND
LOWPASS CUTOFF = 900kHz (f
= 90MHz)
= 90MHz)
GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR.
10k RESISTORS ON HPF0(SDO) AND GAIN0(D0)
CLK
HIGHPASS CUTOFF = 90kHz (f
GAIN = 16
CLK
PROTECT THE DEVICE IF V
> V+ OR
HPF0
D
V
GAIN0
> V+
D
6602 F01
Figure 1. Filter in Pin Programmable Control Mode
6602fa
14
LTC6602
APPLICATIONS INFORMATION
V+
D
SHUTDOWN
OUT
6-BIT GAIN, BW
CONTROL CODE
8-BIT LATCH
CS
HPF0(SDO)
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
D
IN
SHIFT-REGISTER
(INTERNAL
NODE)
6602 F02
SDO
SCLK
6602 F03
Figure 2. Bidirectional Design of
HPFO(SDO) and GAIN0(D0) Pins
Figure 3. Diagram of Serial Interface (MSB First Out)
3.3V
3.3V
LTC6602
0.1μF
LTC6602
#2
0.1μF
V+
V+
V+
#1
V+
V+
V+
IN
IN
A
A
D
D
+
+OUTA
–OUTA
+
+OUTA
–OUTA
+
V
–
+
V
–
+INA
+INA
V
V
IN1
OUT1
IN2
OUT2
–
–INA
–
–INA
SER
SER
LPF1(CS)
LPF1(CS)
LPF0(SCLK)
HPF1(SDI)
GND
LPF1(CS)
LPF0(SCLK)
HPF1(SDI)
GND
SCLK
SDI
μP
GAIN0(D0)
HPF0(SDO)
GAIN0(D0)
HPF0(SDO)
OUT1
OUT2
SDO
SCLK
SDI
CS
D15
D11
D10
D9
D8
D7
D3
D2
D1
D0
SHUTDOWN FOR #2
SHUTDOWN FOR #1
GAIN, BW CONTROL WORD FOR #1
GAIN, BW CONTROL WORD FOR #2
6602 F04
Figure 4. Two Filters in a Daisy Chain
Serial Control Register Definition
D7
D6
D5
D4
D3
D2
D1
D0
OUT
GAIN0
GAIN1
LPF0
LPF1
HPF0
HPF1
SHDN
6602fa
15
LTC6602
APPLICATIONS INFORMATION
Serial Interface
Self-Clocking Operation
ConnectingSERtogroundallowsthefiltertobecontrolled
through the SPI serial interface. When CS is low, the serial
data on SDI is shifted into an 8-bit shift-register on the
rising edge of the clock (SCLK), with the MSB transferred
first (see Figure 3). Serial data on SDO is shifted out on
the clock’s falling edge. A high CS will load the 8 bits of
the shift-register into an 8-bit D-latch, which is the serial
control register. The clock is disabled internally when
CS is pulled high. Note: SCLK must be low before CS is
pulled low to avoid an extra internal clock pulse. SDO is
always active in serial mode (never tri-stated) and cannot
be “wire-or’ed” to other SPI outputs. In addition, SDO is
not forced to zero when CS is pulled high.
TheLTC6602featuresauniqueinternaloscillatorwhichsets
the filter cutoff frequency using a single external resistor
connected to the R
pin. The clock frequency is deter-
BIAS
mined by the following simple formula (see Figure 5):
f
= 494.1MHz • 10k/R
CLK
BIAS
Note: R
≤ 200k.
BIAS
200
175
150
125
100
75
An LTC6602 may be daisy chained with other LTC6602s
or other devices having serial interfaces. Daisy chain-
ing is accomplished by connecting the SDO of the lead
chip to the SDI of the next chip, while SCLK and CS
remain common to all chips in the daisy chain. The se-
rial data is clocked to all the chips then the CS signal
is pulled high to update all of them simultaneously.
Figure 4 shows an example of two LTC6602s in a daisy
chained SPI configuration.
50
20
30
40
50
60
70
80
90
DESIRED CLOCK FREQUENCY (MHz)
6602 F05
Figure 5. RBIAS vs Desired Clock Frequency
The design is optimized for V+ , V+ = 3V, f = 90MHz,
A
D
CLK
GAIN1 and GAIN0 are the gain control bits (register bits
D6 and D7 when in serial mode). Their function is shown
in Table 1. In serial mode, register bit D1 can be set to
‘1’ to put the device into a low power shutdown mode.
Register bit D0 is a general purpose output (Pin 21) when
in serial mode.
where the filter cutoff frequency error is typically <3%
when a 0.1% external 54.9k resistor is used. With differ-
ent resistor values and cutoff frequency control settings
(HPF1, HPF0, LPF1 and LPF0), the highpass and lowpass
cutofffrequenciescanbeaccuratelyvariedfrom4.1175kHz
to 90kHz and from 41.175kHz to 900kHz, respectively.
Table 2 summarizes the cutoff frequencies that can be
Table 1. Gain Control
PASSBAND GAIN
obtained with an external resistor (R
) value of 54.9k.
BIAS
Note that the cutoff frequencies scale with the clock fre-
quency. For example, if HPF1, HPF0, LPF1 and LPF0 are
GAIN 1
GAIN 0
(dB)
0
0
1
1
0
1
0
1
0
all equal to zero, and R
is increased from 54.9k to
BIAS
12
24
30
200k, f
will decrease from 90MHz to 24.705MHz, the
CLK
lowpass cutoff frequency will be reduced from 150kHz
to 41.175kHz, and the highpass cutoff frequency will be
reduced from 15kHz to 4.1175Hz. The cutoff frequencies
thatcanbeobtainedwithanexternalresistorvalueof200k
6602fa
16
LTC6602
APPLICATIONS INFORMATION
are shown in Table 3. When the LTC6602 is programmed
forthelowestlowpasscutofffrequency(LPF1,LPF0=‘0’),
the power is automatically reduced by about 35%.
Table 3. Cutoff Frequency Control, RBIAS = 200k, fCLK = 24.705MHz
Lowpass
BW (kHz)
Highpass
BW (kHz)
LPF1
LPF0
HPF1
HPF0
0
0
1
1
0
1
0
1
41.175
82.35
0
0
1
1
0
1
0
1
4.1175
12.3525
Table 2. Cutoff Frequency Control, RBIAS = 54.9k, fCLK = 90MHz
Lowpass
BW (kHz)
Highpass
BW (kHz)
247.05
247.05
24.705
LPF1
LPF0
HPF1
HPF0
Bypass HPF
0
0
1
1
0
1
0
1
150
300
900
900
0
0
1
1
0
1
0
1
15
45
The following graphs show a few of the possible combina-
tions of highpass and lowpass filters.
90
Bypass HPF
Gain and Group Delay vs Frequency
(15kHz to 150kHz Bandpass Response)
Gain and Group Delay vs Frequency
(45kHz to 300kHz Bandpass Response)
40
20
40
60
54
48
42
36
30
24
18
12
6
T
= 25°C
= 3V
T
= 25°C
= 3V
GAIN = 30dB
GAIN = 24dB
A
S
A
S
GAIN = 30dB
V
30
18
30
V
EXTERNAL
CLOCK
R
EXTERNAL
CLOCK
R
20
16
14
12
10
8
20
GAIN = 24dB
GAIN = 12dB
GAIN = 12dB
GAIN = 0dB
= 54.9k
= 54.9k
BIAS
BIAS
10
10
0
0
GAIN = 0dB
–10
–20
–30
–40
–50
–60
–10
–20
–30
–40
–50
–60
6
4
GROUP
DELAY
GROUP
DELAY
2
0
0
1k
10k
100k
FREQUENCY (Hz)
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
6602 G28
6602 G29
Gain and Group Delay vs Frequency
(90kHz to 900kHz Bandpass Response)
Gain and Group Delay vs Frequency
(900kHz Lowpass Response)
40
30
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
40
10
T
= 25°C
S
A
GAIN = 30dB
GAIN = 30dB
GAIN = 24dB
GAIN = 12dB
V
= 3V
30
9
8
7
6
5
4
3
2
1
0
EXTERNAL
CLOCK
20
20
GAIN = 24dB
GAIN = 12dB
R
BIAS
= 54.9k
10
10
0
0
GAIN = 0dB
GAIN = 0dB
–10
–20
–30
–40
–50
–60
–10
–20
–30
–40
–50
–60
GROUP DELAY
T
= 25°C
= 3V
A
S
V
GROUP
EXTERNAL CLOCK
R
DELAY
= 54.9k
BIAS
1k
10k
100k
1M
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
6602 G28
6602 G30
6602fa
17
LTC6602
APPLICATIONS INFORMATION
Preserving Oscillator Accuracy
Figure 7 shows the LTC6602’s oscillator configured as
a VCO. A voltage source is connected in series with the
The oscillator is sensitive to transients on the positive
supply. The IC should be soldered to the PC board and
the PCB layout should include a 0.1μF ceramic capacitor
R
resistor. The clock frequency, f , will vary with
BIAS
CONTROL
between the current out of the R
of the R
The clock frequency, however, will increase monotonically
with decreasing V
CLK
V
. Again, this circuit decouples the relationship
pin and the voltage
BIAS
between V+ (Pin 2) and ground, as close as possible to
A
pin; the frequency accuracy will be degraded.
BIAS
the IC to minimize inductance. The PCB layout should also
include an additional 0.1μF ceramic capacitor between
.
CONTROL
V+ (Pin 16) and ground. Avoid parasitic capacitance on
D
BIAS
R
(Pin 4) and avoid routing noisy signals near R
.
BIAS
Operation Using an External Clock
Use a ground plane connected to Pin 14 and the Exposed
Pad (Pin 25).
The LTC6602 may be clocked by an external oscillator
for tighter bandwidth control by pulling CLKCNTL (Pin 5)
to ground and driving a clock into CLKIO (Pin 15). If an
Alternative Methods of Setting the Clock Frequency of
the LTC6602
external clock is used, the R
resistor is still necessary.
BIAS
The value of R
must be no larger than the value that
BIAS
The oscillator may be programmed by any method that
would be required for using the internal oscillator. For
example,a100kresistorwouldprogramtheinternaloscil-
lator for 49.41MHz, so an external oscillator frequency of
sinks a current out of the R
pin. The circuit in Figure 6
BIAS
setstheclockfrequencybyusingaprogrammablecurrent
source and in the expression for f , the resistor R
CLK
BIAS
49.41MHz would require an R
resistance of no more
BIAS
is replaced by the ratio of 1.17V/I
. Because the
CONTROL
than 100k. If the value of R
is too large, the filters will
BIAS
voltage of the R
pin is approximately 1.17V 5%, the
BIAS
not receive a large enough bias current, possibly causing
errors due to insufficient settling.
Figure 6 circuit is less accurate than if a resistor controls
the clock frequency.
R
BIAS
R
BIAS
R
BIAS
+
–
I
V
CONTROL
CONTROL
f
= 10k • (494.1MHz/1.17V) • I
(A)
f
= 494.1MHz • (10k/R
) • (1 – V /1.17V)
CONTROL
CLK
CONTROL
CLK
BIAS
6602 F06
6602 F07
Figure 7. Voltage Controlled Clock Frequency
Figure 6. Current Controlled Clock Frequency
6602fa
18
LTC6602
APPLICATIONS INFORMATION
–70
–70
–75
–80
–85
–90
T
f
= 25°C
T
f
= 25°C
A
IN
A
IN
= 100kHz
= 100kHz
DIFFERENTIAL INPUT, V = 1.5V
DIFFERENTIAL INPUT, V = 1.5V
IN
P-P
IN
P-P
R
= 54.9k
R
= 54.9k
BIAS
BIAS
–75
–80
–85
–90
45kHz-300kHz BPF
GAIN = 0dB
45kHz-300kHz BPF
GAIN = 0dB
HD3
HD2
HD3
HD2
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
COMMON MODE INPUT VOLTAGE (V)
COMMON MODE INPUT VOLTAGE (V)
6602 F08
6602 F09
Figure 8. Distortion vs Common Mode Input Voltage (3V)
Figure 9. Distortion vs Common Mode Input Voltage (5V)
Input Common Mode and Differential Voltage Range
by half to 45MHz, the impedances would be doubled. The
typical part to part variation in dynamic input impedance
for a given clock frequency is –20% to +35%.
The input signal range extends from zero to the V+ sup-
IN
ply voltage. This input supply can be tied to V+ and V+ ,
A
D
or driven up to 5.5V for increased input common mode
Table 4. Differential, Common Mode Input Impedances,
fCLK = 90MHz
voltage range. Figures 8 and 9 show the distortion of the
Differential Input
Impedance (kΩ)
Common Mode Input
Impedance (kΩ)
filter versus common mode input voltage with a 1.5V
differential input signal.
P-P
GAIN1 GAIN0 LPF1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
6
20
6.7
20
For best performance, the inputs should be driven dif-
ferentially. For single ended signals, connect the unused
8
input to V
(Pin 3) or to a quiet DC reference voltage.
OCM
2.8
2.6
1.8
2.4
1.3
6.7
20
To achieve the best distortion performance, the input
signal should be centered around the DC voltage of the
unused input.
6.7
20
Refer to the Typical Performance Characteristics section
to estimate the distortion for a given input level.
6.7
Dynamic Input Impedance
Output Common Mode and Differential Voltage Range
The unique input sampling structure of the LTC6602 has a
dynamicinputimpedancewhichdependsontheconfigura-
tionandtheclockfrequency.Thisdynamicinputimpedance
has both a differential component and a common mode
component. The common mode input impedance is a
function of the clock frequency and the control bit LPF1.
The differential input impedance is a function of the clock
frequency and the control bits LPF1, GAIN1 and GAIN0.
Table 4 shows the typical input impedances for a clock
frequency of 90MHz. These input impedances are all pro-
The output voltage is a fully differential signal with a
common mode level equal to the voltage at V
. Any of
OCM
the filter outputs may be used as single-ended outputs,
although this will degrade the performance. The output
voltage range is typically 0.5V to V+ – 0.5V (V+ = 2.7V
A
A
to 3.6V).
The common mode output voltage can be adjusted by
overdriving the voltage present on V . To maximize
OCM
the undistorted peak-to-peak signal swing of the filter,
the V
voltage should be set to V+ /2. Note that the
portional to 1/f , so if the clock frequency were reduced
OCM
A
CLK
6602fa
19
LTC6602
APPLICATIONS INFORMATION
V
–20
–30
–40
–50
–60
SUPPLY
LTC6602
0.1μF
V+
V+
V+
IN
A
D
+OUTA
–OUTA
V
V
+
–
+INA
–INA
OUT
T
= 25°C
OUT
A
HD3
HD2
–70
–80
–90
f
= 100kHz
IN
V
V
R
= 1.5V
OCM
IN
P-P
= 54.9k
+
–
+
–
V
IN
+
V
1μF
IN
–
BIAS
GND
45kHz-300kHz BPF
GAIN = 0dB
0.5
1.0
1.5
2.0
2.5
DC COUPLED INPUT
V
V
COMMON MODE OUTPUT VOLTAGE (V)
(COMMON MODE) = (V + + V –)/2
IN
IN IN
6602 F10
(COMMON MODE) = (V + + V –)/2 = V
/2
OUT
OUT OUT SUPPLY
6602 F11
Figure 10. Distortion vs Common Mode Output Voltage
Figure 11. DC Coupled Inputs
V
V
SUPPLY
V
V
SUPPLY
SUPPLY
SUPPLY
LTC6602
LTC6602
0.1μF
0.1μF
V+
V+
V+
V+
V+
V+
IN
IN
R
R
1.87k
1.87k
1.87k
PULL-UP
0.1μF
PULL-UP
A
A
0.1μF
D
0.1μF
D
–OUTA
–OUTB
–OUTA
–OUTB
+INA
–INA
+INA
–INA
1.87k
V
+
+
–
+
+
–
V
OCM
V
OCM
V +
IN
V
+
IN
0.1μF
V
IN
IN
–
–
–
–
1μF
1μF
GND
GND
6602 F12b
6602 F12a
AC COUPLED INPUT
(COMMON MODE) = V
RCM • V
SUPPLY
2 • RCM + 1.87k
=
=
COMMON MODE AT +INA AND –INA
AC COUPLED INPUT
V
/2
SUPPLY
IN
(a) Fixed Lowpass Cutoff Frequency
(b) Variable Lowpass Cutoff Frequency
Figure 12. AC Coupled Inputs
output common mode voltages of the two channels are
not independent as they are both set by the V pin.
frequency, connecting resistors between each input and
V+ will pull the input common mode voltage up, increas-
OCM
IN
Figure 10 illustrates the distortion versus output common
ing the input signal swing (Figure 12a). The resistance,
mode voltage for a 1.5V differential input voltage and a
R
, necessary to set the input common mode
ICM
P-P
PULL-UP
common mode input voltage that is equal to mid-supply.
voltage, V , to any desired level can be calculated by
ꢁ
ꢄ
VSUPPLY
Interfacing to the LTC6602
R
PULLꢀUP =RCM
ꢀ1
ꢃ
ꢆ
V
ꢂ
ꢅ
ICM
The input and output common mode voltages of the
LTC6602 are independent. The input common mode volt-
age is set by the signal source if DC coupled, as shown in
Figure 11. If the inputs are AC coupled, the input com-
mon mode voltage will pulled to ground by an equivalent
where
R
CM
R
CM
= 20k • 90MHz/f
for LPFI = 0
for LPFI = 1
CLK
= 6.7k • 90MHz/f
CLK
resistance of R , shown in Table 4. This does not affect
CM
For example, if the lowpass cutoff frequency is set to
300kHz, 20k resistors connected between each input
and V+ will set the input common mode voltage to
the filter’s performance as long as the input amplitude
is less than 0.5V . At low filter gain settings, a larger
P-P
IN
input voltage swing may be desired. Figure 12 shows two
mid-supply.
circuits with AC coupled inputs. In a fixed lowpass cutoff
6602fa
20
LTC6602
APPLICATIONS INFORMATION
3.3V
3.3V
LTC6602
MASTER
LTC6602
SLAVE
0.1μF
0.1μF
R
R
BIAS
V+
V+
V+
V+
V+
V+
BIAS
IN
A
IN
A
R
R
BIAS
BIAS
D
D
+
+
+
+
+INA
–INA
+OUTA
–OUTA
+INA
–INA
+OUTA
–OUTA
V
V
OUT2
V
V
OUT1
IN1
IN2
–
–
–
–
CLKCNTL
CLKIO
GND
CLKCNTL
CLKIO
GND
6602 F13
Figure 13. Two Filters in a Master/Slave Configuration
If the lowpass cutoff frequency varies then the Figure 12b
circuit must be used.
Similarly, two LTC6602s can be connected in a master/
slave configuration as shown in Figure 13. This results
in four matched filter channels, all synchronized to the
same clock. The master has its CLKCNTL pin pulled to
The output common mode voltage is equal to the voltage
of the V
pin. The V
pin is biased to one half of the
OCM
OCM
V+ , configuring its CLKIO pin as an output, while the
D
supply voltage by an internal resistive divider (see Block
Diagram).Toalterthecommonmodeoutputvoltage,V
slave has its CLKCNTL pin pulled to ground, configuring
its CLKIO pin as an input.
OCM
can be driven with an external voltage source or resistor
network. If external resistors are used, it is important to
note that the internal 1.6k resistors can vary 30% (their
ratio varies only 1%). The filter outputs can also be AC
coupled.
Output Drive
Thefilteroutputscandrive1kand/or50pFloadsconnected
to AC ground with a 0.5V to 2.5V signal (corresponding
to a 4V differential signal). For differential loads (loads
P-P
TheLTC6602canbeinterfacedtoanA/Dconverterbypull-
connected between +OUTA and –OUTA or +OUTB and
ingCLKCNTL(Pin5)toV+ .ThisconfiguresCLKIO(Pin15)
D
–OUTB) the outputs can produce a 4V signal across 2k
P-P
as a clock output, which can be used to drive the clock
input of the A/D converter. This allows the A/D converter
to be synchronized with the filter sampling clock, avoiding
“beat frequencies” and simplifying the board layout. Any
routing attached to the CLKIO pin should be as short as
possible, in order to minimize ringing.
and/or25pF.Forsmallersignalamplitudes,theoutputscan
drive correspondingly heavier loads. For larger capacitive
loads, an external 50Ω series resistor is recommended
for each output.
6602fa
21
LTC6602
APPLICATIONS INFORMATION
Mute Function
A ground plane should be used. Noisy signals should be
isolated from the filter input pins.
The LTC6602 features a mute function which is asserted
bypullingMUTE(Pin20)toground. Thisbreaksthesignal
path that leads from the input pins to the filter networks,
attenuating the input signal by at least 20dB. The mute
function can be used to protect the filter inputs from large
transients. The filter clock continues to run when the filter
is muted, allowing for a fast recovery time when MUTE
is de-asserted. Typically, the recovery time is less than
5μs, as shown in Figure 14. When the mute function is
asserted, the differential input impedance becomes very
high, but the common mode input impedance to ground
remains the same. This keeps the input common mode
voltage stable when muted, even when the inputs are
AC coupled. Connecting GAIN0(D0) to MUTE allows for
serial control of the mute function. MUTE has an internal
TheoutputDCoffsettypicallychangeslessthan 2mVwhen
theclockfrequencyvariesfrom24.705MHzto90MHz.The
offset is measured by connecting the inputs to V
and
OCM
measuring the differential voltage at the filter’s output.
Aliasing
Aliasingisaninherentphenomenonofsampleddatafilters.
Significant aliasing only occurs when the frequency of the
input signal approaches the sampling frequency or mul-
tiples of the sampling frequency. The ratio of the LTC6602
input sampling frequency to the clock frequency, f , is
CLK
determined by the state of control bit LPF1. If LPF1 is set
to ‘0’, the input sampling frequency is equal to f /3. If
CLK
LPF1 is set to ‘1’, the input sampling frequency is equal to
pull-up to V+ .
D
f .Inputsignalswithfrequenciesneartheinputsampling
CLK
frequency will be aliased to the passband of the filter and
appear at the output unattenuated.
MUTE (2V/DIV)
AsimpleLCanti-aliasingfilterisrecommendedatthefilter
inputs to attenuate frequencies near the input sampling
frequencythatwillbealiasedtothepassband.Forexample,
if the clock frequency is set to 90MHz and the lowpass
cutoff frequency of the filter is set to it’s maximum (LPF1
= ‘1’), the lowest frequency that would be aliased to the
V
OUT
(1V/DIV)
6602 F14
4μs/DIV
passband would be f – f
, i.e. 90MHz – 900kHz =
CLK CUTOFF
Figure 14. Mute Function Recovery Time
89.1MHz. In order to attenuate this frequency by 40dB, an
LCfilterwithacutofffrequencyof8.91MHzorlowerwould
be required at the filter inputs. The capacitor connected
between the LTC6602 filter inputs should be at least 150pF
to provide sufficient charge to the input sampler. If there
is no anti-aliasing filter, the LTC6602 filter inputs should
be driven by a low impedance source (<100Ω).
Clock Feedthrough
ClockfeedthroughisdefinedastheRMSvalueoftheclock
frequency and its harmonics that are present at the filter’s
output. The clock feedthrough is measured with +INA and
–INA (or +INB, –INB) tied to V
and depends on the PC
OCM
board layout and the power supply decoupling. The clock
feedthrough can be reduced with a simple RC post filter.
Wideband Noise
The wideband noise of the filter is the RMS value of the
device’soutputnoisespectraldensity.Thewidebandnoise
voltage is used to determine the operating signal-to-noise
ratio at a given distortion level. The wideband noise is
nearly independent of the value of the clock frequency
andexcludestheclockfeedthrough. Mostofthewideband
noise is concentrated in the filter passband and cannot be
removed with post filtering.
DC Offset
The output DC offset of the LTC6602 is less than 15mV.
To obtain optimum DC offset performance, appropriate
PC board layout techniques should be used. The filter
IC should be soldered to the PC board. The power sup-
plies should be well decoupled including 0.1μF ceramic
capacitors from V+ (Pin 16) and V+ (Pin 2) to ground.
D
A
6602fa
22
LTC6602
APPLICATIONS INFORMATION
100
120
100
80
60
40
20
0
T
= 25°C
= 3V
A
S
V
CLKCNTL PIN FLOATING
HPF1 = 0
HPF0 = 1
GAIN = 0dB
LPF1 = 1
HPF1 = 0
LPF1 = 0
LPF0 = 1
HPF1 = 0
HPF0 = 1
HPF0 = 0
LPF1 = 0
LPF0 = 0
LPF1 = 0 LPF1 = 1
LPF0 = 1
HPF1 = 1
HPF0 = 0
LPF1 = 0
LPF0 = 0
10
1k
10k
100k
1M
10k
100k
1M
FILTER CUTOFF FREQUENCY (Hz)
LOWPASS CUTOFF FREQUENCY (Hz)
6602 F15
6602 F16
Figure 15. fCLK vs Filter Cutoff Frequencies
Figure 16. Supply Current vs Lowpass Cutoff Frequency
Table 5. Total Input Referred Integrated Noise Voltage (Passband Gain = 30dB)
LPF1
LPF0
HPF1
HPF0
Noise Voltage
–90dBm
0
0
1
0
1
X
0
0
1
0
1
0
–89dBm
–82dBm
Power Supply Current
frequency from 24.705MHz to 90MHz. Both lowpass
and highpass corner frequencies are proportional to the
clock frequency (internal or external). To extend the filter’s
operational frequency range, the master clock is divided
downbeforereachingthefilter. LPF1andLPF0setthedivi-
sion ratio of the lowpass clock while HPF1 and HPF0 set
the division ratio of the highpass clock. Figure 15 shows
The power supply current depends on the state of the
lowpass cutoff frequency controls (LPF1, LPF0) and the
value of R . When the LTC6602 is programmed for the
BIAS
lowest lowpass cutoff frequency (LPF1 = LPF0 = ‘0’), the
supply current is reduced by about 35% relative to the
supply current for the higher bandwidth settings. Power
supply current vs. cutoff frequency for various bandwidth
settingsisshowninthe“TypicalPerformanceCharacteris-
tics”section.TheLTC6602canbeprogrammedthroughthe
serial interface to enter into a low power shutdown mode
as described in the Serial Interface section. The power
supply current during shutdown is less than 235μA.
the possible cutoff frequencies versus f , HPF1, HPF0,
CLK
LPF1andLPF0. Overlappingfrequencyrangesallowmore
than one possible choice of bandwidth settings for some
cutoff frequencies. Figure 16 shows supply current as a
function of the lowpass cutoff frequency, LPF1 and LPF0.
Note that the higher bandwidth setting always gives the
minimum supply current for a given cutoff frequency. The
total integrated noise voltage for a passband gain of 30dB
is shown in Table 5. Note that the noise is higher for the
higherbandwidthsettings.Thiscreatesatradeoffbetween
supply current and noise. For a given cutoff frequency,
using the highest possible bandwidth setting gives the
minimum supply current at the expense of higher noise.
Supply Current versus Noise Tradeoff
The passband of the LTC6602 is determined by the master
clock frequency (which is set by R
oscillator is used), HPF1, HPF0, LPF1 and LPF0. The
LTC6602 is optimized for use with R having a value
between 200k and 54.9k to set the internal oscillation
when the internal
BIAS
BIAS
6602fa
23
LTC6602
APPLICATIONS INFORMATION
The LTC6602, an Adaptable Baseband Filter for an
RFID Reader
Certified C1G2 UHF RFID readers can adapt to a great
variety of operating conditions. To achieve operating
flexibility a reader’s baseband circuits must include an
adaptable bandwidth filter. Figure 17 shows an LTC6602
based filter circuit that uses SPI control to vary the filter’s
bandwidthtoadjustfortheC1G2complexsetofdatarates,
encoding and modulation. The filter’s clock frequency is
set by the SPI control of 8-bit LTC2630 DAC (digital to
analog converter). The DAC voltage through a resistive
Aradio-frequencyidentification(RFID)systemisanauto-id
technology that identifies any object that contains a coded
tag. An RFID system consists of a reader (or interrogator)
and a tag. An RFID system capable of identifying multiple
tags at a maximum operating distance operates in the
UHF frequency range. A UHF reader transmits informa-
tion to a tag by modulating an RF signal in the 860MHz
to 960MHz frequency range. Typically a tag is passive,
meaning that it receives all of its operating energy from a
reader that transmits a continuous wave (CW) RF signal
to power a tag. A tag responds by modulating the reflec-
tion coefficient of its antenna, thereby backscattering an
information signal to the reader. Reliable detection of a
tag signal requires communication protocols that define
the physical and operating interaction between readers
and tags. The latest UHF RFID protocol, the Electronic
ProductCode™(EPC)globalclass-1generation2standard
(C1G2), have been accepted worldwide and is also known
as ISO 18000-6C. The C1G2 standard defines a reader to
tag and a tag to reader communication using a flexible
set of signal modulation, data encoding, data rates and
commandprocedures. C1G2specifiesreaderandtagdata
symbols using pulse-interval encoding. Tag signal detec-
tion requires measuring the time interval between signal
transitions (a data “1” symbol has a longer interval than
a data “0” symbol). The reader initiates a tag inventory by
sending a signal that instructs a tag to set its backscatter
data rate and encoding. C1G2 certified RFID readers can
operate in an RF environment where many readers are in
closeproximity.ThethreeoperatingmodesofC1G2,single
interrogator, multiple interrogator and dense interrogator,
define the spectral limits of reader and tag signals for an
optimum balance of reliable multitag detection and high
data throughput (for more information on C1G2, consult
the references at the end of this design note). The advan-
tages of C1G2 complex protocols can be realized by using
a reader whose receiver contains a high linearity direct
conversion I and Q demodulator, a low noise amplifier, a
dual baseband filter with variable gain and bandwidth and
a dual analog to digital converter (ADC).
pin. The
divider sets the current into the LTC6602 R
BIAS
resistive divider sets the clock frequency range for a DAC
voltage range 0V to 3V. For the resistor values in Figure 17
(191k and 61.9k) the clock frequency range is 40MHz to
100MHz (234.4kHz per bit). The lowpass and highpass
division ratio is set by the SPI control of the LTC6602. The
cutoffrangeforthehighpassfilteris6.7kHzto100kHzand
for the lowpass filter is 66.7kHz to 1MHz. The optimum
filter bandwidth setting can be adjusted by a software
algorithm and is a function of the reader’s data clock, data
rate, encoding and modulation. The filter bandwidth must
be sufficiently narrow to maximize the dynamic range to
the ADC input and wide enough to preserve signal transi-
tions and pulse width. If the filter setting is optimum then
a DSP algorithm can reliably detect tag data. Figure 18a
shows the filter’s time response to a typical tag symbol
sequence (a “short” pulse interval followed by a “long”
pulse interval). The lowpass cutoff frequency is set equal
to the reciprocal of the shortest interval (f
= 1/10μs
CUTOFF
= 100kHz). If the lowpass cutoff frequency is lower the
signal transition and time interval will be distorted beyond
recognitionbyanytagsignaldetectionalgorithm. Theset-
ting of the highpass cutoff frequency is more qualitative
thanspecific.Thehighpasscutofffrequencymustbelower
than the reciprocal of the longest interval (for Figure 18
example, highpass f
< 1/20μs < 50kHz) and as
CUTOFF
high as possible to decrease the receiver’s low frequency
noise(basebandamplifieranddown-convertedphaseand
amplitude noise). Figures 18a and 18b show the filter’s
total response (lowpass plus highpass filter). The filter’s
output is shown with 30kHz and a 10kHz highpass cutoff
frequency setting. Comparing the filter outputs with a
10kHzanda30kHzhighpasssetting, thesignaltransitions
and time intervals of the 10kHz output are adequate for
6602fa
24
LTC6602
APPLICATIONS INFORMATION
detecting the symbol sequence (in an RFID environment,
noise will be superimposed on the output signal). In
the highpass f
“enhances” signal transitions and
CUTOFF
intervals and increases filter output noise.
general, increasingthelowpassf
and/ordecreasing
CUTOFF
5V
3V
0.1μF
0.1μF
1
2
16
V+
V+
V+
A
IN
D
24
18
19
+INA
–INA
+INB
–INB
–OUTA
+OUTA
–OUTB
+OUTB
CLKIO
SER
SPI CONTROL OF DAC
SETS THE LTC6602
CLOCK FREQUENCY
40MHz TO 100MHz
I CHANNEL INPUT
Q CHANNEL INPUT
23
7
I CHANNEL OUTPUT
12
13
15
17
Q CHANNEL OUTPUT
LTC6602
8
174k
1
2
3
6
5
4
4
CS
V
R
OUT
BIAS
OCM
0.1μF
3
68.1k
0.1μF
SCLK
SDI
GND
V
5
+
20
21
22
14
V
3V
MUTE
CLKCNTL
11
10
9
GAIN0(D0) HPFO(SDO)
3V
TRANSMITTER MUTE INPUT
LTC2630
8-BIT DAC
GAIN1
GND
HPFI(SDI)
LPFO(SCLK)
LPF1(CS)
SPI CONTROL OF LTC6602
DAC V
OUT
SETS THE FILTER GAIN AND THE
LOWPASS AND HIGHPASS
DIVISION RATIO
RANGE 0V TO 2.5V
25
6
(USING THE LTC2630
INTERNAL REFERENCE)
GND
ADC VCOM INPUT
CS1 SCK SDI CS2
6602 F17
Figure 17. An Adaptable RFID Baseband Filter with SPI Control
LOWPASS ONLY FILTER
100kHz LOWPASS + 30kHz HIGHPASS FILTER
100kHz LOWPASS + 10kHz HIGHPASS FILTER
100kHZ
LOWPASS
TYPICAL TAG
SYMBOL
SEQUENCE
0
10 20 30 40 50 60 70 80 90 100110120
0
10 20 30 40 50 60 70 80 90 100110120
0
10 20 30 40 50 60 70 80 90 100110120
(μs)
(μs)
(μs)
6602 F19b
6602 F19c
6602 F19a
(c)
(b)
(a)
Figure 18. Filter Transient Response to a Tag Symbol Sequence
6602fa
25
LTC6602
TYPICAL APPLICATIONS
Switching the RBIAS Resistor
3V
PARALLEL CONTROL
1
2
16
V+
0.1μF
V+
V+
IN
A
D
24
23
7
18
19
12
13
15
17
–OUTA
+OUTA
–OUTB
+OUTB
CLKIO
SER
+INA
–INA
+INB
–INB
LTC6602
8
4
R
BIAS
OCM
0.1μF
3
R3
SOT-363
R2
R1
V
5
20
21
22
14
CLKCNTL
HPF0(SDO)
HPF1(SDI)
LPF0(SCLK)
LPF1(CS)
3V
MUTE
GAIN0(D0)
GAIN1
GND
11
10
9
25
6
GND
DIODES INC
DMN2004DMK
V
OCM
MUTE
CLK1
CLK0
0
0
1
1
0
1
0
1
R
BIAS1
R
BIAS2
R
BIAS3
R
BIAS4
f
f
f
f
CLK1
CLK2
CLK3
CLK4
CLK1 CLK0
GAIN1 GAIN0 LPF1 LPF0 HPF1 HPF0
R
R
> R
OR R
BIAS2 BIAS3
BIAS1
DESIGN PROCEDURE
1. CHOOSE f , f
BIAS1 BIAS2 BIAS3
3. CALCULATE R2, R3 AND R
= 4941
BIAS
AND f
f
CLK1 CLK2
CLK3
CLK
2. CALCULALTE R
, R
AND R
R
IN k
IN MHz
BIAS1
BIAS4
f
CLK
R1 = R
R2 = R
R
• R
– R
R3 = R
R
• R
– R
R =
BIAS4
R1 • R2 • R3
R1 • (R2 + R3) + R2 • R3
BIAS1
BIAS1
BIAS1
BIAS2
BIAS1
BIAS1
BIAS3
BIAS2
BIAS3
3V
SERIAL CONTROL
1
2
16
V+
0.1μF
V+
V+
A
IN
D
24
18
19
12
13
15
17
–OUTA
+OUTA
–OUTB
+OUTB
CLKIO
SER
+INA
–INA
+INB
–INB
23
7
DAC V
RANGE, 0V TO 2.5V
OUT
(USING LTC2630 INTERNAL REFERENCE)
LTC6602
8
R2
1
2
3
6
5
4
4
CS
V
OUT
R
BIAS
0.1μF
3
R1
V
OCM
SCLK
SDI
GND
V+
0.1μF
5
20
21
22
14
CLKCNTL
HPF0(SDO)
HPF1(SDI)
LPF0(SCLK)
LPF1(CS)
3V
MUTE
GAIN0(D0)
GAIN1
GND
11
10
9
LTC2630
3V
LTC6602 f
8-BIT DAC
25
6
DAC V
0V
OUT
CLK
GND
f
CLKHI
2.5V
f
CLKLO
V
OCM
MUTE
13
13
R2 = 1.056 • 10
– f
R1 =
1.056 • 10
1.137 • f
f
+ f
CS1 SCLK
SDI
CS2
SDO
CLKHI CLKLO
CLKHI CLKLO
6602 TA02
6602fa
26
LTC6602
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 p0.05
4.50 p 0.05
3.10 p 0.05
2.45 p 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.115
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 s 45o CHAMFER
0.75 p 0.05
4.00 p 0.10
(4 SIDES)
TYP
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
1
2
2.45 p 0.10
(4-SIDES)
(UF24) QFN 0105
0.200 REF
0.25 p 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6602fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC6602
TYPICAL APPLICATION
Direct Conversion Demodulator and Programmable Baseband Filter
RF IN
5V
3V
4.7pF
0.1μF
0.1μF
270nH*
270nH*
10pF
10pF
270pF
1
2
16
V+
4
3
2
RF
1
GND
V+
V+
A
GND GND
IN
D
16
24 +INA
–OUTA 18
10pF
10pF
5
6
EN
I INPUT
19 I OUTPUT
23
7
–INA
+INB
–INB
+OUTA
–OUTB
+OUTB
CLKIO
SER
15
14
V
V
V
CC
CC
CC
12
13
15
17
LT5575
7
8
LTC6602
Q INPUT
Q OUTPUT
5V
8
10pF
10pF
4
CLOCK
INPUT
R
BIAS
OCM
38.3k
1μF
0.1μF
1000pF
270nH*
270nH*
13
3
V
GND LO GND V
CC
10 11 12
5
10pF
10pF
20
21
22
14
MUTE
CLKCNTL
17
9
270pF
0.1μF
11
10
9
GAIN0(D0) HPF0(SDO)
GAIN1
GND
HPF1(SDI)
LPF0(SCLK)
LPF1(CS)
1000pF
MUTE INPUT FROM TRANSMITTER
LO IN
25
6
GND
4.7pF
CS SCLK SDI
SPI CONTROL INPUT
VOCM INPUT FROM ADC
*COILCRAFT 0603HP-R27X
6602 TA03
RELATED PARTS
PART NUMBER
LTC1563
DESCRIPTION
4th Order Filter Building Block
COMMENTS
Lowpass or Bandpass Filter, 256Hz to 256kHz
No External Components, Low Offset, SO8 Pkg
No External Components, Low Noise, SO8 Pkg
Differential Rail-to-Rail Output, MSOP Pkg
LTC1565-31
LTC1566-1
LT®1567
7th Order, Fully Differential 650kHz Lowpass Filter
7th Order, Fully Differential 2.3MHz Lowpass
Low Noise, Filter Building Block Up to 5MHz
LT1568
4th Order Filter Building Block, Configurable as 2 Matched
Lowpass, Bandpass or 4-Pole Lowpass
200kHz ≤ f ≤ 5MHz, Low Noise, Rail-to-Rail
c
Input/Output, Programmable Gain, Shutdown Mode
LTC2291
LTC2296
LT5516
LT5575
Dual 12-Bit, 25 Msps A/D Converter
Low Power (150mW), Single 3V Supply; 71.4dB SNR, 90dB SFDR
Low Power (150mW), Single 3V Supply; 74.5dB SNR, 90dB SFDR
21.5dBm IIP3; 12.8dB NF
Dual 14-Bit, 25 Msps A/D Converter
800MHz to 1.5GHz Direct Conversion I/Q Demodulator
800MHz to 2.7GHz Direct Conversoin I/Q Demodulator
28dBm IIP3 at 900MHz; 13.2dBm P1dB; Integrated RF Input
Balance Transformer
LT6600-
2.5/5/10/15/20
Fully Differential Amplifier and Lowpass Filter
Cutoff Frequencies: 2.5MHz/5MHz/10MHz/20MHz
Programmable Gain, Adjustable Output CM Voltage,
Specified for 3V, 5V, 5V
6602fa
LT 0908 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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