LTC6603 [Linear]
Dual Adjustable Lowpass Filter; 可调式双低通滤波器
| 型号： | LTC6603 |
| 厂家： | 
Linear |
| 描述： | Dual Adjustable Lowpass Filter |
| 文件： | 总24页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6603
Dual Adjustable
Lowpass Filter
FEATURES
DESCRIPTION
The LTC®6603 is a dual, matched, programmable lowpass
filter for communications receivers and transmitters. The
selectivity of the LTC6603, combined with its linear phase,
phase matching and dynamic range, make it suitable for
filtering in many communications systems. With 1.5°
phase matching between channels, the LTC6603 can be
used in applications requiring pairs of matched filters,
such as transceiver I and Q channels. Furthermore, the
differential inputs and outputs provide a simple interface
for most communications systems.
n
Guaranteed Phase and Gain Matching Specs
n
Programmable BW Up to 2.5MHz
n
Programmable Gain (0dB/6dB/12dB/24dB)
n
9th Order Linear Phase Response
n
Differential, Rail-to-Rail Inputs and Outputs
n
Low Noise: –145dBm/Hz (Input Referred)
n
Low Distortion: –75dBc at 200kHz
n
Simple Pin Programming or SPI Interface
n
Set the Max Speed/Power with an External R
n
Operates from 2.7V to 3.6V
n
Input Range from 0V to 5.5V
The sampled data filter does not require an external clock
yet its cutoff frequency can be set with a single external
resistor with an accuracy of 3.5% or better. The external
resistor programs an internal oscillator whose frequency
is divided prior to being applied to the filter networks.
This allows up to three cutoff frequencies that can be
obtained for each external resistor value, allowing the
cutoff frequency to be programmed over a range of more
than six octaves. Alternatively, the cutoff frequency can
be set with an external clock. The filter gain can also be
programmed to 1, 2, 4 or 16.
n
4mm × 4mm QFN Package
APPLICATIONS
n
Small/Low Cost Basestations:
IDEN, PHS, TD-SCDMA, CDMA2000, WCDMA,
UMTS
n
Low Cost Repeaters, Radio Links, and Modems
n
802.11x Receivers
JTRS
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
The LTC6603 features a low power shutdown mode that
can be programmed through the serial interface and is
available in a 24-pin 4mm × 4mm QFN package.
TYPICAL APPLICATION
2.5MHz I and Q Lowpass Filter and Dual ADC
5V
3V
LTC2297
100nH*
49.9Ω
Phase Matching
0.1μF
0.1μF
180pF
180pF
10pF
10pF
60
I OUTPUT
14-BIT
ADC
V
= 3V, BW = 156.25kHz
S
f = 125kHz, T = 25°C
V+
V+
V+
D
A
IN
A
50 1000 UNITS
100nH*
49.9Ω
+INA
–INA
+INB
–INB
+OUTA
–OUTA
+OUTB
–OUTB
CLKIO
I
IN
40
30
20
10
0
100nH*
49.9Ω
Q
IN
LTC6603
R
180pF
180pF
10pF
10pF
BIAS
0.1μF
0.1μF
Q OUTPUT
100nH*
14-BIT
ADC
30.9k
V
SER
OCM
49.9Ω
V
CM
3V
3V
CAP
CLKCNTL
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
2.2μF
GAIN1
GAIN0
SDO
SDI
MISMATCH (DEG)
6603 TA01b
GND
GND
LPFO
LPF1
*COILCRAFT 0603HP
BASEBAND
GAIN CONTROL
6603 TA01a
6603f
1
LTC6603
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V+ to GND................................................................6V
IN
V+ , V+ to GND.........................................................4V
A
D
V+ to V+ .............................................. –0.3V to +0.3V
A
D
24 23 22 21 20 19
Filter Inputs to GND ....................... –0.3V to V+ + 0.3V
IN
V+
IN
1
2
3
4
5
6
18 –OUTA
Pins 3, 4 to GND ............................. –0.3V to V+ + 0.3V
A
V+
A
SER
17
16
Pins 5, 6, 9-11,
V
V+
D
OCM
BIAS
25
15, 17, 21, 22 to GND.................–0.3V to V+ + 0.3V
R
15 CLKIO
GND
D
CLKCNTL
14
13 +OUTB
Maximum Input Current....................................... 10mA
Output Short Circuit Duration........................... Indefinite
Operating Temperature Range (Note 2)
LPF1(CS)
7
8
9 10 11 12
LTC6603CUF .......................................–40°C TO 85°C
LTC6603IUF ........................................–40°C TO 85°C
Specified Temperature Range (Note 3)
LTC6603CUF ...........................................0°C TO 70°C
LTC6603IUF ........................................–40°C TO 85°C
Storage Temperature Range................... –65°C to 150°C
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
T
= 150°C, θ = 37°C/W, θ = 4.3°C/W
JA JC
JMAX
EXPOSED PAD (PIN 25) IS GND. MUST BE SOLDERED TO THE PCB.
ORDER INFORMATION
LEAD FREE FINISH
LTC6603CUF#PBF
LTC6603IUF#PBF
TAPE AND REEL
PART MARKING*
6603
PACKAGE DESCRIPTION
24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C
24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C
SPECIFIED TEMPERATURE RANGE
LTC6603CUF#TRPBF
LTC6603IUF#TRPBF
6603
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =
2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.
PARAMETER
CONDITIONS
External Clock = 80MHz, Filter Cutoff (f )= 156.25kHz, V = 3.6V Pin 3 Open
MIN
TYP
MAX
UNITS
Filter Gain Either
Channel
C
IN
P-P,
DC Gain, Gain Set = 0dB
l
l
l
l
l
f
f
f
f
= 62.5kHz (0.4 • f ), Relative to DC Gain
0.25
–0.5
0.4
0.4
–0.3
0.6
–0.4
–32
0.55
–0.1
0.8
–0.2
–29.5
dB
dB
dB
dB
dB
IN
IN
IN
IN
C
= 125kHz (0.8 • f ), Relative to DC Gain
C
= 156.25kHz (f ), Relative to DC Gain
C
= 234.375kHz (1.5 • f ), Relative to DC Gain
–0.6
C
Matching of Filter
Gain
External Clock = 80MHz, Filter Cutoff (f )= 156.25kHz, V = 3.6V Pin 3 Open
C IN P-P,
l
l
l
l
DC Gain, Gain Set = 0dB
0.03
0.03
0.03
0.03
0.1
0.1
dB
dB
dB
dB
f
f
f
= 62.5kHz (0.4 • f )
IN
IN
IN
C
= 125kHz (0.8 • f )
0.1
C
= 156.25kHz (f )
0.15
C
6603f
2
LTC6603
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =
2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.
PARAMETER
CONDITIONS
External Clock = 80MHz, Filter Cutoff (f )= 156.25kHz, V = 3.6V Pin 3 Open
MIN
TYP
MAX
UNITS
Filter Phase Either
Channel
C
IN
P-P,
l
l
l
f
f
f
= 62.5kHz (0.4 • f )
158
–44
–152
161
–39
–146
163
–36
–142
deg
deg
deg
IN
IN
IN
C
C
= 125kHz (0.8 • f )
= 156.25kHz (f )
C
Matching of Filter
Phase
External Clock = 80MHz, Filter Cutoff (f )= 156.25kHz, V = 3.6V Pin 3 Open
C IN P-P,
l
l
l
f
f
f
= 62.5kHz (0.4 • f )
0.2
0.4
0.5
1.5
3
4
deg
deg
deg
IN
IN
IN
C
C
= 125kHz (0.8 • f )
= 156.25kHz (f )
C
Filter Gain Either
Channel
External Clock = 80MHz, Filter Cutoff (f )= 2.5MHz, V = 3.6V Pin 3 Open
C IN P-P,
l
l
l
l
l
DC Gain, Gain Set = 0dB
0
0.5
–0.8
0.4
1.2
–0.1
1.5
dB
dB
dB
dB
dB
f
f
f
f
= 1MHz (0.4 • f ), Relative to DC Gain
–2
IN
IN
IN
IN
C
= 2MHz (0.8 • f ), Relative to DC Gain
–0.7
–1.1
C
= 2.5MHz (f ), Relative to DC Gain
0.1
1
C
= 4MHz (1.5 • f ), Relative to DC Gain
–43
–32.6
C
Matching of Filter
Gain
External Clock = 80MHz, Filter Cutoff (f )= 2.5MHz, V = 3.6V Pin 3 Open
C
IN
P-P,
l
l
f
f
= 2MHz (0.8 • f )
0.05
0.2
0.2
0.4
dB
dB
IN
IN
C
= 2.5MHz (f )
C
Filter Phase
Either Channel
External Clock = 80MHz, Filter Cutoff (f )= 2.5MHz, V = 3.6V Pin 3 Open
C IN P-P,
l
l
l
f
f
f
= 1MHz (0.4 • f )
150
–45
–152
155
–39
–141
159
–28
–126
deg
deg
deg
IN
IN
IN
C
C
= 2MHz (0.8 • f )
= 2.5MHz (f )
C
Matching of Filter
Phase
External Clock = 80MHz, Filter Cutoff (f )= 2.5MHz, V = 3.6V Pin 3 Open
C IN P-P,
l
l
l
f
f
f
= 1MHz (0.4 • f )
2.5
4
4
deg
deg
deg
IN
IN
IN
C
C
= 2MHz (0.8 • f )
= 2.5MHz (f )
C
Filter Cutoff Accuracy CLKCNTL = 3V (Note 4)
l
l
l
when Self Clocked
R
BIAS
R
BIAS
R
BIAS
= 200k
= 54.9k
= 30.9k
3
3
3.5
%
%
%
DC Gain
Filter Cutoff (f ) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open
C
l
l
l
l
Gain Setting = 0dB
Gain Setting = 6dB
Gain Setting = 12dB
Gain Setting = 24dB
0
0.5
6
11.8
23.2
1.2
6.6
12.5
24
dB
dB
dB
dB
5.6
11.2
22.5
DC Gain Matching
Noise At 200kHz
Integrated Noise
Filter Cutoff (f ) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open
C
l
l
l
l
Gain Setting = 0dB
Gain Setting = 6dB
Gain Setting = 12dB
Gain Setting = 24dB
0.1
0.05
0.05
0.1
0.2
0.1
0.15
0.2
dB
dB
dB
dB
Voltage Noise Referred to the Input
Gain = 0dB
–124
–129
–135
–145
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
Gain = 6dB
Gain = 12dB
Gain = 24dB
Noise Bandwidth = 5MHz, Referred to the Input
Gain = 0dB
Gain = 6dB
Gain = 12dB
Gain = 24dB
–53
–59
–65
–76
dBm
dBm
dBm
dBm
THD
V
= 2V , f = 200kHz, Gain Setting = 24dB
–75
dB
IN
P-P IN
Input Impedance
Gain = 24dB, R
= 30.9k, Filter Cutoff (f ) = 2.5MHz
BIAS C
Differential
1.6
5
kꢀ
kꢀ
Common Mode
6603f
3
LTC6603
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =
2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.
PARAMETER
Differential
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Referred Differential Offset Voltage at Either Output
Lowest Cutoff Frequency, Gain Setting = 24dB
Highest Cutoff Frequency, Gain Setting = 24dB
Lowest Cutoff Frequency, Gain Setting = 0dB
Highest Cutoff Frequency, Gain Setting = 0dB
OS
l
l
l
l
8
mV
mV
mV
mV
14
40
60
CMRR Differential
f = 625kHz
C
l
l
Common Mode Input from 0 to 3V, V+ = 3V
60
60
90
90
dB
dB
IN
Common Mode Input from 0 to 5V, V+ = 5V
IN
l
l
V
V
Pin Voltage
Pin Input
V+ = V+ = 3V, Pin 3 Open
1.3
2.5
1.45
3.4
1.5
4.5
V
OCM
A
D
V+ = V+ = 3V, Pin 3 Open
kꢀ
OCM
Impedance
A
D
l
V
OSCM
Common Mode Offset Voltage, V
= 1.5V, Supplies = 3V
100
185
mV
OCM
V
= V
– V
OSCM
OUT-CM OCM
l
l
Output Swing
Source 1mA, Relative to V+
Sink 1mA, Relative to GND
200
150
500
400
mV
mV
A
l
l
Short-Circuit Current Sourcing
Sinking
7
11
25
30
mA
mA
Supply Current
Internal Clock (R
= 30.9k); Sum of the Currents into V+ , V+ , and V+ All
BIAS D A IN
Supplies Set to 3V
f = 156.25kHz
l
l
l
88
121
162
96
130
175
mA
mA
mA
C
f = 625kHz
C
f = 2.5MHz
C
Supply Current,
Shutdown Mode
Sum of the Currents into V+ , V+ , and V+ ; All Supplies Set to 3V
D
A
IN
l
Shutdown Via Serial Interface
170
235
μA
l
l
Supply Voltage
V+ , V+ Relative to GND
IN
2.7
2.7
3.6
5.5
V
V
D
A
V+ Relative to GND
l
l
PSRR
V+ = V+ = V+ , All from 2.7V to 3.6V
40
65
50
85
dB
dB
D
A
IN
V+ = V+ = 3V, V+ from 4.5V to 5.5V
D
A
IN
R
R
Resistor Range CLKCNTL = 3V
BIAS
BIAS
l
l
Clock Frequency Error < 3.5%
Clock Frequency Error < 3%
30.9
54.9
54.9
200
kꢀ
kꢀ
Pin Voltage
30.9k < R
< 200k
1.17
40
V
BIAS
Clock Frequency Drift
Over Temperature
R
= 30.9k
ppm/ºC
BIAS
CLKCNTL Pin Open
l
l
l
l
Clock Frequency Drift V+ , V+ from 2.7V to 3.6V, R = 30.9k
BIAS
0.2
50
0.5
55
%/V
%
V
A
D
Over Supply
CLKCNTL Pin Open
Output Clock Duty
Cycle
R
BIAS
= 30.9k
45
CLKIO Pin High Level CLKCNTL = 0V (Note 5)
Input Voltage
V+ – 0.3
D
CLKIO Pin Low Level CLKCNTL = 0V (Note 5)
Input Voltage
0.3
10
V
CLKIO Pin Input
Current
CLKCNTL = 0V
l
l
CLKIO = 0V (Note 6)
–1
μA
μA
CLKIO = V+
D
CLKIO Pin High Level V+ = V+ = 3V, CLKCNTL = 3V
A
D
Output Voltage
I
I
= –1mA
2.95
2.9
V
V
OH
OH
= –4mA
6603f
4
LTC6603
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =
2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CLKIO Pin Low Level V+ = V+ = 3V, CLKCNTL = 3V
A
D
Output Voltage
I
I
= 1mA
0.05
0.1
V
V
OL
OL
= 4mA
CLKIO Pin Rise Time V+ = V+ = CLKCNTL = 3V, C
= 5pF
= 5pF
0.3
0.3
ns
ns
V
A
D
LOAD
LOAD
CLKIO Pin Fall Time
V+ = V+ = CLKCNTL = 3V, C
A
D
l
l
SER High Level
Input Voltage
Pin 17
V+ – 0.3
D
SER Low Level
Input Voltage
Pin 17
0.3
2
V
l
l
SER Input Current
Pin 17 = 0V (Note 6)
Pin 17 = V+
–10
μA
μA
D
l
CLKCNTL High Level Pin 5
Input Voltage
V+ – 0.5
D
V
CLKCNTL Low Level Pin 5
Input Voltage
0.5
25
V
l
l
CLKCNTL Input
Current
CLKCNTL = 0V (Note 6)
CLKCNTL = V+
–25
–15
15
μA
μA
D
Pin Programmable Control Mode Specifications. Specifications apply to pins 6, 9, 21 and 22 in pin programmable control mode.
SYMBOL
V+ = 2.7V to 3.6V
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
D
l
l
l
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
Pins 6, 9, 21, 22
2
V
V
IH
IL
Pins 6, 9, 21, 22
0.8
1
I
IN
Pins 6, 9, 21, 22 (Note 6)
–1
μA
Serial Port DC and Timing Specifications. Specifications apply to pins 6, 9-11, and 21 in serial programming mode.
SYMBOL
V+ = 2.7V to 3.6V
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
D
l
l
l
l
l
l
l
l
l
l
l
l
l
l
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
Digital Output High Voltage
Digital Output Low Voltage
SDI Valid to SCLK Setup
SDI Valid to SCLK Hold
SCLK Low
Pins 6, 9, 10
2
V
V
IH
IL
V
Pins 6, 9, 10
0.8
1
I
IN
Pins 6, 9, 10 (Note 6)
Pins 11, 21 Sourcing 500μA
Pins 11, 21 Sinking 500μA
–1
μA
V
V
V
– 0.3
OH
OL
SUPPLY
V
0.3
V
t (Note 5)
1
60
0
ns
ns
ns
ns
ns
ns
ns
ns
t (Note 5)
2
t
3
t
4
t
5
100
100
60
SCLK High
CS Pulse Width
t (Note 5)
6
LSB SCLK to CS
60
t (Note 5)
7
CS Low to SCLK
30
t
8
SDO Output Delay
C = 15pF
L
125
t (Note 5)
9
SCLK Low to CS Low
0
ns
6603f
5
LTC6603
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: This test measures the internal oscillator accuracy (deviation from
the f equation). Variations in the internal oscillator cause variations in
the filter cutoff frequency. See the “Applications Information” section.
CLK
Note 5: Guaranteed by design, not subject to test.
Note 2: LTC6603C and LTC6603I are guaranteed functional over the
operating temperature range of –40°C to 85°C.
Note 6: To conform to the logic IC standard, current out of a pin is
arbitrarily given a negative value.
Note 3: LTC6603C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6603C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LTC6603I is guaranteed to meet the
specified performance limits from –40°C to 85°C.
TYPICAL PERFORMANCE CHARACTERISTICS
DC Gain Matching
DC Gain Matching
Phase Matching
70
60
50
40
30
20
10
0
30
25
20
15
10
5
70
60
50
40
30
20
10
0
V
= 3V, BW = 156.25kHz
V = 3V, BW = 2.5MHz
S
V
= 3V, BW = 2.5MHz
S
S
GAIN SETTING = 0dB, T = 25°C
A
f = 2MHz, T = 25°C
A
GAIN SETTING = 0dB, T = 25°C
A
1000 UNITS
1000 UNITS
1000 UNITS
0
–0.06–0.04–0.02
0
0.02 0.04 0.06 0.08 0.1
–2.5–2–1.5–1–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
–0.2 –0.15 –0.1 –0.05
0
0.05 0.1 0.15 0.2
MISMATCH (dB)
MISMATCH (DEG)
MISMATCH (dB)
6603 G02
6603 G03
6603 G01
Gain and Group Delay
vs Frequency
Phase Matching
60
50
40
35
30
20
10
0
30
20
800
760
720
680
640
600
560
520
480
440
400
V
= 3V, BW = 156.25kHz
S
GAIN = 24dB
f = 125kHz, T = 25°C
A
1000 UNITS
10
0
GAIN = 0dB
–10
–20
–30
–40
–50
–60
–70
GAIN = 12dB
GAIN = 6dB
GROUP DELAY
R
= 30.9k, V = 3V
S
BIAS
LPF1 = 1, BW = 2.5MHz
= 25°C
T
A
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
10k
100k
1M
10M
MISMATCH (DEG)
FREQUENCY (Hz)
6603 G04
6603 G05
6603f
6
LTC6603
TYPICAL PERFORMANCE CHARACTERISTICS
Gain and Group Delay
vs Frequency
Gain and Group Delay
vs Frequency
Distortion vs Input Frequency
30
20
12.0
11.5
11.0
10.5
10.0
9.5
30
20
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
–50
–60
–70
–80
–90
R
= 30.9k, V = 3V
S
BIAS
GAIN = 12dB
GAIN = 6dB
GAIN = 24dB
GAIN = 24dB
LPF1 = 1, BW = 2.5MHz
= 2V , T = 25°C
V
OUT
P-P
A
10
10
HD3, GAIN = 24dB
HD3, GAIN = 0dB
0
0
GAIN = 0dB
GAIN = 12dB
GAIN = 6dB
GAIN = 0dB
GROUP DELAY
–10
–20
–30
–40
–50
–60
–70
–10
–20
–30
–40
–50
–60
–70
GROUP DELAY
9.0
HD2, GAIN = 0dB
8.5
HD2, GAIN = 24dB
R
= 30.9k, V = 3V
S
R
= 30.9k, V = 3V
S
BIAS
BIAS
8.0
LPF1 = LPF0 = 0,
BW = 156.25kHz
LPF1 = 0, LPF0 = 1,
BW = 625kHz
7.5
T
A
= 25°C
T
A
= 25°C
7.0
1k
10k
100k
1M
10k
100k
1M
10M
100
500
900
1300
1700
FREQUENCY (Hz)
FREQUENCY (Hz)
INPUT FREQUENCY (kHz)
6603 G07
6603 G06
6603 G08
Distortion vs Input Frequency
Distortion vs Input Frequency
Distortion vs Input Frequency
–60
–65
–70
–75
–80
–85
–90
–70
–75
–80
–85
–90
–95
–100
–60
–65
–70
–75
–80
–85
–90
R
= 30.9k, V = 3V
S
R
= 54.9k, V = 3V
S
BIAS
BIAS
HD3, GAIN = 0dB
LPF1 = 0, LPF0 = 1, BW = 625kHz
= 2V , T = 25°C
LPF1 = 1, BW = 1.41MHz
= 25°C
V
OUT
HD3, GAIN = 24dB
T
P-P
A
A
HD3, GAIN = 0dB
HD3, GAIN = 0dB
HD2, GAIN = 24dB
HD2, GAIN = 0dB
HD3, GAIN = 24dB
HD2, GAIN = 0dB
HD2, GAIN = 24dB
HD2, GAIN = 24dB
HD2, GAIN = 0dB
R
= 30.9k, V = 3V
S
BIAS
LPF1 = LPF0 = 0, BW = 156.25kHz
= 2V , T = 25°C
HD3, GAIN = 24dB
V
OUT
P-P
A
100
300
500
700
900
1100
10
30
50
70
90 110 130 150
20
120
220
320
420
520
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
6603 G09
6603 G11
6603 G10
Filter Cutoff Accuracy
vs Supply Voltage
Filter Cutoff Accuracy
vs Temperature
Distortion vs Output Voltage
–60
–70
1.0
0.8
0.2
0.1
LPF1 = LPF0 = 0, BW = 156.25kHz
R
= 30.9k, V = 3V, LPF1 = 0, LPF0 = 1,
V = 3V
S
BIAS
S
BW = 2.5MHz, GAIN = 24dB, T = 25°C
A
R
= 30.9k
BIAS
0.0
0.6
HD3, f = 1MHz
HD2, f = 1MHz
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
LPF1 = 0, LPF0 = 1,
BW = 625kHz
0.4
BW = 156.25kHz
BW = 625kHz
0.2
–80
0.0
LPF1 = 1, BW = 2.5MHz
–0.2
–0.4
–0.6
–0.8
HD3, f = 200kHz
–90
BW = 2.5MHz
R
A
= 30.9k
BIAS
HD2, f = 200kHz
T
= 25°C
–100
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
OUTPUT VOLTAGE (V
–50 –30 –10 10
30
50
70
90
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
P-P
6603 G11
6603 G14
6603 G13
6603f
7
LTC6603
TYPICAL PERFORMANCE CHARACTERISTICS
Common Mode Rejection Ratio
Common Mode Rejection Ratio
Common Mode Rejection Ratio
110
100
90
80
70
60
50
40
30
20
120
110
100
90
100
90
80
70
60
50
40
30
20
V
= 3V, R
= 30.9k
BIAS
GAIN = 0dB
GAIN = 6dB
GAIN = 24dB
GAIN = 12dB
S
LPF1 = 0, LPF0 = 1,
BW = 625kHz, T = 25°C
A
GAIN = 24dB
GAIN = 6dB
GAIN = 0dB
GAIN = 12dB
GAIN = 12dB
GAIN = 24dB
80
GAIN = 0dB
GAIN = 6dB
70
60
50
V
= 3V, R
= 30.9k
BIAS
V
= 3V, R
= 30.9k
BIAS
S
S
40
LPF1 = 1, BW = 2.5MHz
= 25°C
LPF1 = LPF0 = 0, BW = 156.25kHz,
= 25°C
T
A
T
A
30
10k
100k
1M
10M
1k
10k
100k
1M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6603 G16
6603 G17
6603 G15
Common Mode Rejection
Common Mode Rejection
Common Mode Rejection
100
90
80
70
60
50
40
30
100
90
80
70
60
50
110
100
90
CMR = ΔV
/ΔV
OUT-DIFF
V
= 3V, R
= 30.9k
IN-CM
BIAS
GAIN = 12dB
S
LPF1 = 0, LPF1 = 1, BW = 625kHz,
T
= 25°C
GAIN = 0dB
A
GAIN = 0dB
GAIN = 6dB
GAIN = 6dB
GAIN = 24dB
GAIN = 0dB
GAIN = 6dB
GAIN = 12dB
GAIN = 24dB
80
GAIN = 12dB
GAIN = 24dB
70
CMR = ΔV
S
LPF1 = LPF0 = 0, BW = 156.25kHz,
T = 25°C
A
/ΔV
OUT-DIFF
IN-CM
V
= 3V, R
= 30.9k
V
= 3V, R
= 30.9k
BIAS
60
BIAS
S
LPF1 = 1, BW = 2.5MHz,
= 25°C
T
A
CMR = ΔV
/ΔV
IN-CM
OUT-DIFF
50
10k
100k
1M
10M
1k
10k
100k
1M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6603 G18
6603 G20
6603 G19
OIP3 vs Average Signal
Frequency
OIP3 vs Average Signal
Frequency
OIP3 vs Average Signal
Frequency
41
40
39
38
37
36
35
34
46
44
42
40
38
36
43
42
41
40
39
38
37
36
35
GAIN = 0dB
GAIN = 12dB
GAIN = 0dB
GAIN = 6dB
GAIN = 6dB
GAIN = 12dB
GAIN = 12dB
GAIN = 6dB
GAIN = 24dB
GAIN = 24dB
GAIN = 24dB
GAIN = 0dB
V
= 3V, R
= 30.9k, T = 25°C
V
= 3V, R
= 30.9k, T = 25°C
V
= 3V, R
= 30.9k, T = 25°C
BIAS A
BIAS
A
BIAS A
S
S
S
LPF1 = 0, LPF0 = 1, BW = 625kHz
= 6dBm PER TONE FOR 2-TONE TEST
LPF1 = 0, LPF0 = 1, BW = 625kHz
V = 6dBm PER TONE FOR 2-TONE TEST
OUT
LPF1 = 0, LPF0 = 1, BW = 156.25kHz
= 6dBm PER TONE FOR 2-TONE TEST
V
V
OUT
OUT
Δf = 10kHz
100 500
AVERAGE FREQUENCY OF TWO TONES (kHz)
Δf = 10kHz
100
AVERAGE FREQUENCY OF TWO TONES (kHz)
Δf = 10kHz
20 40
AVERAGE FREQUENCY OF TWO TONES (kHz)
900 1300 1700 2100 2500
0
200
300
400
500
600
60
80 100 120 140 160
6603 G21
6603 G22
6603 G23
6603f
8
LTC6603
TYPICAL PERFORMANCE CHARACTERISTICS
OIP3 vs Temperature
Output Impedance vs Frequency
Supply Current vs Supply Voltage
10
1
42
41
40
39
38
37
36
35
200
180
160
140
120
100
80
V
= 3V, R
= 30.9k
BIAS
V
S
= 3V, R
= 30.9k, T = 25°C
BIAS A
T
= 25°C
BIAS
S
A
PASSBAND GAIN = 24dB
= 6dBm PER TONE FOR 2-TONE TEST
Δf = 10kHz
R
= 30.9k
V
OUT
LPF1 = 0, LPF0 = 1,
BW = 625kHz
BW = 2.5MHz
LPF1 = LPF0 = 0,
BW = 156.25kHz
BW = 625kHz,
FREQUENCY = 200kHz
0.1
BW = 625kHz
BW = 156.25kHz,
FREQUENCY = 60kHz
BW = 156.25kHz
LPF1 = 1, BW = 2.5MHz
0.01
0.001
BW = 2.5MHz, FREQUENCY = 1MHz
60
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–50 –30 –10 10
30
50
70
90
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
6603 G25
6603 G23
6603 G26
Supply Current vs Temperature
Clock Output Operating at 80MHz
RBIAS Pin Voltage vs IRBIAS
1.25
1.20
1.15
1.10
180
160
140
120
100
80
5
4
T
= 25°C
= 3V
T
= 25°C
BIAS
R
T
= 30.9k, V = 3V
S
A
S
A
BIAS
A
V
R
= 30.9k
= 25°C
BW = 2.5MHz
3
2
BW = 625kHz
1
0
BW = 156.25kHz
–1
–2
60
0
5
10
I
15
(μA)
20
25
–50 –30 –10 10
30
50
70
90
–14 –12 –10 –8 –6 –4 –2
TIME (ns)
0
2
TEMPERATURE (°C)
RBIAS
6603 G29
6603 G27
6603 G28
Input Referred Noise Density
Input Referred Noise Density
Input Referred Noise Density
1000
100
10
1000
100
10
1000
GAIN = 0dB
GAIN = 0dB
GAIN = 6dB
GAIN = 6dB
GAIN = 0dB
GAIN = 6dB
GAIN = 12dB
GAIN = 12dB
100
10
1
GAIN = 12dB
GAIN = 24dB
GAIN = 24dB
GAIN = 24dB
1
V
= 3V, R
= 30.9k
BIAS
V
= 3V, R
= 30.9k
BIAS
S
S
V
= 3V, R
= 30.9k
BIAS
S
LPF1 = 0, LPF0 = 0,
BW = 156.25kHz
LPF1 = 0, LPF0 = 1,
BW = 625kHz
LPF1 = 1, BW = 2.5MHz
= 25°C
T
A
T
= 25°C
T
= 25°C
A
A
0.1
1
10k
100k
1M
10M
1k
10k
100k
1M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6603 G30
6603 G32
6603 G31
6603f
9
LTC6603
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Input Referred Noise
Integral Input Referred Noise
Integral Input Referred Noise
1000
100
10
1000
100
10
1000
100
10
V
= 3V, R
= 30.9k
BIAS
V
= 3V, R
= 30.9k
V
= 3V, R
= 30.9k
BIAS
BIAS
S
S
S
LPF1 = 1,BW = 2.5MHz
= 25°C
LPF1 = 0, LPF0 = 1, BW = 625kHz
= 25°C
LPF1 = LPF0 = 0, BW = 156.25kHz
T = 25°C
A
T
A
T
A
GAIN = 0dB
GAIN = 6dB
GAIN = 12dB
GAIN = 0dB
GAIN = 6dB
GAIN = 12dB
GAIN = 6dB
GAIN = 0dB
GAIN = 24dB
GAIN = 24dB
GAIN = 12dB
GAIN = 24dB
1
1
1
10k
100k
1M
10M
10k
100k
1M
10M
10k
100k
INTEGRATION BW (Hz)
1M
INTEGRATION BW (Hz)
INTEGRATION BW (Hz)
6603 G33
6603 G34
6603 G35
PIN FUNCTIONS
V+ (Pin 1): Input Voltage Supply (2.7V ≤ V ≤ 5.5V). This
For best performance, use a precision metal film resis-
tor with a value between 30.9k and 200k and limit the
capacitance on this pin to less than 10pF. This resistor is
necessary even if an external clock is used.
IN
supply must be kept free from noise and ripple. It should
be bypassed directly to a ground plane with a 0.1μF ca-
pacitor unless it is tied to V+ (Pin 2). The bypass should
A
be as close as possible to the IC, but is not as critical as
CLKCNTL (Pin 5): Clock Control Input. This three-state
input selects the function of CLKIO (Pin 15). Tying the
CLKCNTL pin to ground allows the CLKIO pin to be driven
by an external clock (CLKIO is the master clock input).
If the CLKCNTL pin is floated, the internal oscillator is
enabled, but the master clock is not present at the CLKIO
pin (CLKIO is a no-connect). If the CLKCNTL pin is tied
the bypassing of V+ and V+ (Pin16).
A
D
V+ (Pin 2): Analog Voltage Supply (2.7V ≤ V ≤ 3.6V). This
A
supplymustbekeptfreefromnoiseandripple.Itshouldbe
bypassed directly to a ground plane with a 0.1μF capacitor.
The bypass should be as close as possible to the IC.
V
(Pin 3): Output common mode voltage reference. If
OCM
to V+ (Pin 16), the internal oscillator is enabled and the
D
floated, aninternalresistivedividersetsthevoltageonthis
pin to half the supply voltage (typically 1.5V), maximiz-
ing the dynamic range of the filter. If this pin is floated, it
must be bypassed with a quality 1μF capacitor to ground.
This pin has a typical input impedance of 3.4k and may
be overdriven. Driving this pin to a voltage other than the
default value will reduce the signal range the filter can
handle before clipping.
master clock is present at the CLKIO pin (CLKIO is the
master clock output). To detect a floating CLKCNTL pin,
the LTC6603 attempts to pull the pin toward mid-supply.
Thisisrealizedwithtwointernal15μAcurrentsources,one
tied to V+ and CLKCNTL and the other one tied to ground
D
and CLKCNTL. Therefore, driving the CLKCNTL pin high
requires sourcing approximately 15μA. Likewise, driving
the CLKCNTL pin low requires sinking 15μA. When the
CLKCNTL pin is floated, it should be bypassed by a 1nF
capacitor to ground or be surrounded by a ground shield
to prevent excessive coupling from other PCB traces.
R
(Pin4):OscillatorFrequency-SettingResistorInput.
BIAS
The value of the resistor connected between this pin and
ground determines the frequency of the master oscillator,
andsetsthebiascurrentsforthefilternetworks.Thevoltage
on this pin is held by the LTC6603 to approximately 1.17V.
6603f
10
LTC6603
PIN FUNCTIONS
V+ (Pin 16): Digital Voltage Supply (2.7V ≤ V ≤ 3.6V).
LPF1(CS) (Pin 6): TTL Level Input. When in pin program-
mable control mode, this pin is the MSB of the lowpass
cutoff frequency control code; in serial control mode, this
pin is the chip select input (active low).
D
This supply must be kept free from noise and ripple. It
shouldbebypasseddirectlytoagroundplanewitha0.1μF
capacitor. The bypass should be as close as possible to
the IC.
+INB, –INB (Pins 7, 8): Channel B differential inputs.
The input range and input resistance are described in the
Applications Information section. Input voltages which
SER (Pin 17): Interface Selection Input. When tied to V+
D
(Pin 16) or floated, the interface is in pin programmable
control mode, i.e. the filter gain and cutoff frequencies
are programmed by the GAIN1, GAIN0, LPF1 and LPF0
pins. When SER is tied to ground, the filter gain, the filter
cutoff frequency and shutdown mode are programmed
by the serial interface.
exceed V+ (Pin 1) should be avoided.
IN
LPF0(SCLK)(Pin9):TTLLevelInput.Wheninpinprogram-
mable control mode, this pin is the LSB of the lowpass
cutoff frequency control code; in serial control mode, this
pin is the clock of the serial interface.
–OUTA, +OUTA (Pins 18, 19): Channel A differential filter
outputs. These pins can drive 1k and/or 50pF loads. For
larger capacitive loads, an external 100ꢀ series resistor
is recommended for each output. The common mode
voltage of the filter outputs is the same as the voltage at
SDI (Pin 10): TTL Level Input. When in pin programmable
control mode, this pin is left floating; in serial control
mode, this pin is the serial data input.
SDO(Pin11):TTLLevelInput. Wheninpinprogrammable
control mode, this pin is left floating; in serial control
mode, this pin is the serial data output.
V
(Pin 3).
OCM
CAP (Pin 20): Connect a 0.1μF bypass capacitor to this
pin. Pin 20 is a buffered version of Pin 3.
–OUTB, +OUTB (Pins 12, 13): Channel B differential filter
outputs. These pins can drive 1k and/or 50pF loads. For
larger capacitive loads, an external 100ꢀ series resistor
is recommended for each output. The common mode
voltage of the filter outputs is the same as the voltage at
GAIN0(D0) (Pin 21): TTL Level Input. When in pin pro-
grammable control mode, this pin is the LSB of the gain
control code; in serial control mode, this pin is the LSB
of the serial control register, an output.
V
OCM
(Pin 3).
GAIN1(Pin22):TTLLevelInput.Wheninpinprogrammable
control mode, this pin is the MSB of the gain control code;
in serial control mode, this pin is a no-connect.
GND (Pin 14): Ground. Should be tied to a ground plane
for best performance.
CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground,
CLKIOisthemasterclockinput.WhenCLKCNTLisfloated,
CLKIO is pulled to ground by a weak pulldown. When
–INA, +INA (Pins 23, 24): Channel A differential inputs.
The input range and input resistance are described in the
Applications Information section. Input voltages which
CLKCNTL is tied to V+ (Pin 16), CLKIO is the master
D
exceed V+ (Pin 1) should be avoided.
IN
clock output. When configured as a clock output, this pin
can drive 1k and/or 5pF loads (heavier loads will cause
inaccuracies).
Exposed Pad (Pin 25): Ground. The Exposed Pad must
be soldered to PCB.
6603f
11
LTC6603
BLOCK DIAGRAM
+INA
–INA
23
GAIN1
22
GAIN0(D0)
21
CAP
20
+OUTA
19
24
V+
1
18
17
–OUTA
IN
CHANNEL A
GAIN
LPF
V+
SER
2
3
A
CONTROL
BIAS
CLK
V+
A
TO PIN 20
V
OCM
16 V+
D
CLOCK
GENERATOR
CONTROL
LOGIC
BIAS/OSC
GND
R
4
5
6
15
CLKIO
BIAS
BIAS
GAIN
CONTROL
CLK
CLKCNTL
14 GND
LPF
CHANNEL B
+OUTB
LPF1(CS)
13
7
8
9
10
11
12
+INB
–INB
LPF0(SCLK)
SDI
SDO
–OUTB
6603 BD
TIMING DIAGRAM
Timing Diagram of the Serial Interface
t
4
t
1
t
6
t
2
t
t
7
3
SCLK
t
9
D3
D2
D1
D0
D7 • • • • D4
D3
SDI
t
5
CS
t
8
D4
D3
D2
D1
D0
D7 • • • • D4
D3
SDO
PREVIOUS BYTE
CURRENT BYTE
6603 TD
6603f
12
LTC6603
APPLICATIONS INFORMATION
Theory of Operation (Refer to Block Diagram)
pull-up to V+ . None of the logic inputs have an internal
D
pull-up or pull-down.
The LTC6603 features two matched filter channels, each
containing gain control and lowpass filter networks that
are controlled by a single control block and clocked by
a single clock generator. The gain and cutoff frequency
can be separately programmed. The two channels are
not independent, i.e. if the gain is set to 24dB then both
channels have a gain of 24dB. The filter can be clocked
with an external clock source, or using the internal oscil-
Serial Interface
ConnectingSERtogroundallowsthefiltertobecontrolled
through the SPI serial interface. When CS is low, the serial
data on SDI is shifted into an 8-bit shift-register on the
rising edge of the clock (SCLK), with the MSB transferred
first (see Figure 3). Serial data on SDO is shifted out on
the clock’s falling edge. A high CS will load the 8 bits of
the shift-register into an 8-bit D-latch, which is the serial
control register. The clock is disabled internally when
CS is pulled high. Note: SCLK must be low before CS is
pulled low to avoid an extra internal clock pulse. SDO is
always active in serial mode (never tri-stated) and cannot
be “wire-or’ed” to other SPI outputs. In addition, SDO is
not forced to zero when CS is pulled high.
lator. A resistor connected to the R
pin sets the bias
BIAS
currents for the filter networks and the internal oscillator
frequency(unlessdrivenbyanexternalclock).Alteringthe
clock frequency changes the filter bandwidth. This allows
the filters to be “tuned” to many different bandwidths.
Pin Programmable Interface
As shown in Figure 1, connecting SER to V+ allows the
D
filter to be directly controlled through the pin program-
mable control lines GAIN1, GAIN0, LPF1 and LPF0. The
GAIN0(D0)pinisbidirectional(inputinpinprogrammable
controlmode,outputinserialmode).Inpinprogrammable
An LTC6603 may be daisy chained with other LTC6603s
or other devices having serial interfaces. Daisy chain-
ing is accomplished by connecting the SDO of the lead
chip to the SDI of the next chip, while SCLK and CS
remain common to all chips in the daisy chain. The se-
rial data is clocked to all the chips then the CS signal
is pulled high to update all of them simultaneously.
Figure 4 shows an example of two LTC6603s in a daisy
chained SPI configuration.
controlmode,thevoltageatGAIN0(D0)cannotexceedV+ ;
D
otherwise,largecurrentscanbeinjectedtoV+ throughthe
D
parasitic diodes (see Figure 2). Connecting a 10k resistor
at the GAIN0(D0) pin (see Figure 1) is recommended for
current limiting, to less than 10mA. SER has an internal
3.3V
3.3V
LTC6603
0.1μF
LTC6603
0.1μF
V+
V+
V+
V+
V+
V+
IN
IN
A
A
D
D
+
V
–
+
V
–
+
+
+INA
+OUTA
–OUTA
+INA
+OUTA
–OUTA
V
V
OUT
OUT
IN
IN
–INA
–INA
–
–
SER
SER
LPF1
LPF0
LPF1(CS)
LPF0(SCLK)
LPF1(CS)
LPF0(SCLK)
μP
GAIN1
GAIN0
GAIN1
GAIN1
GAIN0(D0)
GND
GAIN0(D0)
GND
10k
LOWPASS CUTOFF = 2.5MHz (f
GAIN = 4
= 80MHz)
GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR.
10k RESISTORS ON GAIN0(OUT) PROTECTS THE
CLK
DEVICE WHEN V
> V+
GAIN0
D
6603 F01
Figure 1. Filter in Pin Programmable Control Mode
6603f
13
LTC6603
APPLICATIONS INFORMATION
SHUTDOWN
NO
FUNCTION
4-BIT GAIN, BW
CONTROL CODE
OUT
V+
D
8-BIT LATCH
CS
GAIN0(D0)
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8-BIT
SDI
SHIFT-REGISTER
(INTERNAL
NODE)
SDO
6603 F02
SCLK
6603 F03
Figure 2. Bidirectional Design of GAIN0(OUT) Pin
Figure 3. Diagram of Serial Interface (MSB First Out)
3.3V
3.3V
LTC6603
0.1μF
LTC6603
#2
0.1μF
V+
V+
V+
#1
V+
V+
V+
IN
IN
A
A
D
D
+
+OUTA
–OUTA
+
+OUTA
–OUTA
+
V
–
+
V
–
+INA
+INA
V
V
IN1
OUT1
IN2
OUT2
–
–INA
–
–INA
SER
SER
CSX
SCLK
SDI
LPF1(CS)
LPF0(SCLK)
SDI
LPF1(CS)
LPF0(SCLK)
SDI
μP
GAIN0(D0)
SDO
GAIN0(D0)
SDO
OUT1
OUT2
SDO
GND
GND
SCLK
SDI
CS
D15
D11
D10
D9
D8
D7
D3
D2
D1
D0
SHUTDOWN FOR #2
SHUTDOWN FOR #1
GAIN, BW CONTROL WORD FOR #1
GAIN, BW CONTROL WORD FOR #2
6603 F04
Figure 4. Two Devices in a Daisy Chain
Serial Control Register Definition
D7
D6
D5
D4
D3
D2
D1
D0
OUT
GAIN0
GAIN1
LPF0
LPF1
NO FUNCTION NO FUNCTION
SHDN
6603f
14
LTC6603
APPLICATIONS INFORMATION
GAIN1 and GAIN0 are the gain control bits (register bits
D6 and D7 when in serial mode). Their function is shown
in Table 1. In serial mode, register bit D1 can be set to
“1” to put the device into a low power shutdown mode.
Register bit D0 is a general purpose output (Pin 21) when
in serial mode.
be accurately varied from 24.14kHz to 2.5MHz. Table 2
summarizes the cutoff frequencies that can be obtained
with an external resistor (R
) value of 30.9k. Note that
BIAS
the cutoff frequencies scale with the clock frequency. For
example, if LPF1 and LPF0 are both equal to zero, and
R
is increased from 30.9k to 200k, f
will decrease
BIAS
CLK
from 80MHz to 12.36MHz and the cutoff frequency will
be reduced from 156.25kHz to 24.14kHz. The cutoff
frequencies that can be obtained with external resistor
values of 54.9k and 200k are shown in Table 3 and Table 4,
respectively. When the LTC6603 is programmed for the
cutoff frequencies lower than the maximum, the power is
automatically reduced. The power savings at the middle
bandwidth setting (LPF1 = ‘0’, LPF0 = ‘1’), is about 23%,
while the power savings at the lowest bandwidth setting
(LPF1 = ‘0’, LPF0 = ‘0’) is about 60%.
Table 1. Gain Control
PASSBAND GAIN
GAIN 1
GAIN 0
(dB)
0
0
1
1
0
1
0
1
0
6
12
24
Self-Clocking Operation
Table 2. Cutoff Frequency Control, RBIAS = 30.9k, fCLK = 80MHz
TheLTC6603featuresauniqueinternaloscillatorwhichsets
the filter cutoff frequency using a single external resistor
LPF1
LPF0
LOWPASS BW(kHz)
0
0
1
1
0
1
0
1
156.25
625
connected to the R
pin. The clock frequency is deter-
BIAS
mined by the following simple formula (see Figure 5):
2500
2500
f
= 247.2MHz • 10k/R
CLK
BIAS
Note: R
≤ 200k
BIAS
Table 3. Cutoff Frequency Control, RBIAS = 54.9k, fCLK = 45MHz
The design is optimized for V+ , V+ = 3V, f = 45MHz,
A
D
CLK
LPF1
LPF0
LOWPASS BW(kHz)
where the filter cutoff frequency error is typically <3%
0
0
1
1
0
1
0
1
87.94
351.78
1407
when a 0.1% external 54.9k resistor is used (any resis-
tor (R
) tolerance, will shift the clock frequency). With
BIAS
different resistor values and cutoff frequency control set-
tings (LPF1 and LPF0), the lowpass cutoff frequency can
1407
Table 4. Cutoff Frequency Control, RBIAS = 200k, fCLK = 12.36MHz
200
175
150
125
100
75
LPF1
LPF0
LOWPASS BW(kHz)
24.14
0
0
1
1
0
1
0
1
96.56
386.25
386.25
50
25
10
20
30
40
50
60
70
80
DESIRED CLOCK FREQUENCY (MHz)
6603 F05
Figure 5. RBIAS vs Desired Clock Frequency
6603f
15
LTC6603
APPLICATIONS INFORMATION
The following graphs show a few of the possible lowpass
filters.
Alternative Methods of Setting the Clock Frequency of
the LTC6603
The oscillator may be programmed by any method that
Gain and Group Delay vs Frequency
(2.5MHz Lowpass Response)
sinks a current out of the R
pin. The circuit in Figure 6
BIAS
setstheclockfrequencybyusingaprogrammablecurrent
source and in the expression for f , the resistor R
1.2
CLK
BIAS
. Because the
0
GAIN
is replaced by the ratio of 1.17V/I
CONTROL
1.0
0.8
0.6
0.4
0.2
0
–20
–40
voltage of the R
pin is approximately 1.17V 5%, the
BIAS
Figure 6 circuit is less accurate than if a resistor controls
the clock frequency.
–60
GROUP DELAY
In this circuit, the LTC2621 (a 12-bit DAC) is daisy chained
with the LTC6603. Because the sinking current from the
–80
R
BIAS
pin is
–100
–120
VRBIAS •k
2N •R1
100k
1M
FREQUENCY (Hz)
10M
6603 G17
the equivalent R
is
BIAS
2N •R1
Gain and Group Delay vs Frequency
(650kHz Lowpass Response)
k
,
4
0
–20
–40
–60
–80
where k is the binary DAC input code and N is the resolu-
tion. Figure 7 shows some of the frequency responses
that can be obtained using this circuit.
GAIN
3
2
Figure 8 shows the LTC6603’s oscillator configured as
a VCO. A voltage source is connected in series with the
GROUP DELAY
R
resistor. The clock frequency, f , will vary with
BIAS
CLK
1
V
. Again, this circuit decouples the relationship
CONTROL
between the current out of the R
of the R
The clock frequency, however, will increase monotonically
with decreasing V
pin and the voltage
BIAS
0
pin; the frequency accuracy will be degraded.
BIAS
100k
1M
FREQUENCY (Hz)
6603 G18
.
CONTROL
The oscillator is sensitive to transients on the positive
supply. The IC should be soldered to the PC board and
the PCB layout should include a 0.1μF ceramic capacitor
Operation Using an External Clock
The LTC6603 may be clocked by an external oscillator
for tighter bandwidth control by pulling CLKCNTL (Pin 5)
to ground and driving a clock into CLKIO (Pin 15). If an
between V+ (Pin 2) and ground, as close as possible to
A
the IC to minimize inductance. The PCB layout should also
external clock is used, the R
resistor is still necessary.
include an additional 0.1μF ceramic capacitor between
BIAS
The value of R
must be no larger than the value that
V+ (Pin 16) and ground. Avoid parasitic capacitance on
BIAS
D
BIAS
would be required for using the internal oscillator. For
example,a100kresistorwouldprogramtheinternaloscil-
latorfor24.705MHz, soanexternaloscillatorfrequencyof
R
(Pin 4) and avoid routing noisy signals near R
.
BIAS
Use a ground plane connected to Pin 14 and the Exposed
Pad (Pin 25).
24.705MHz would require an R
resistance of no more
BIAS
6603f
16
LTC6603
APPLICATIONS INFORMATION
5V
3V
–INB
+INB
+INA
–INA
V+
5V
V+
IN
I RANGE = 6μA TO 38.4μA
R23
50k
R24
50k
R25
50k
R26
50k
USE NARROW SHORT
TRACES FOR MINIMUM
CAPACITANCE.
C7
100nF
C2
2.2μF
C3
2.2μF
C4
100nF
C1
100nF
LTC6078
2
V+
–IN
1
2
Q1
OUT
V–
3
RK7002AT116CT
V
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
OCM
+IN
V+
V+
+INA
–INA
GAIN1
IN
A
C18
50pF
C19
50pF
V
OCM
R
GAIN0(D0)
BIAS
R1
CLKCNTL
LPF1(CS)
+INB
–INB
LPF0(SCLK)
SDI
V
CAP
OCM
30.5k
+OUTA
–OUTA
+OUTA
–OUTA
SER
V+
D
CLK IO
GND
5V
LTC6603
LTC6078
V+
C16
50pF
C15
10nF
7
10
11
12
–IN
+IN
OUT
C17
50pF
SDO
–OUTB
V–
+OUTB
–OUTB
+OUTB
5V
R4
100k
6603 F06
C8
100nF
SPI INTERFACE
SDI
1
2
3
4
5
10
V
REF
V
SDO
SDI
SCK
CLR
CS/LD
LDAC
CC
7
SCLK
LTC2621-1
GND
V
OUT
CS
5V
C9
1μF
CLR LOW WILL SET DAC TO MID-SCALE (WITH A –1 VERSION).
HAS ~100ms TC AT START-UP TO RESET TO ZERO SCALE.
DATA FORMAT
DATA IS SHIFTED FROM MOSI (MASTER OUT, SLAVE IN) THRU LTC6603 INTO THE LTC2621.
THE TOTAL PACKET IS 32 BITS. IT STARTS WITH A CONTROL BYTE (0011 XXXX) THEN MSB OF THE DAC,
WITH DUMMY BITS AT THE END, 16 BITS (24 BITS TOTAL). THEN 8 BITS TO THE FILTER.
D6 & D7 = GAIN, D4 & D5 = LPF, D1 = SHDN. D0 = GEN. PURPOSE OUTPUT.
Figure 6. Current Controlled Clock Frequency
10
0
–10
–20
–30
–40
–50
–60
–70
–80
R
BIAS
R
BIAS
+
–
V
CONTROL
V
= 3V
S
A
T
= 25°C
f
= 247.2MHz • (10k/R
) • (1 – V /1.17V)
CONTROL
1k
10k
100k
1M
10M
CLK
BIAS
FREQUENCY (Hz)
6603 F08
6603 F07
Figure 7. Frequency Response Controlled by LTC2621-1
Figure 8. Voltage Controlled Clock Frequency
6603f
17
LTC6603
APPLICATIONS INFORMATION
than 100k. If the value of R
is too large, the filters will
control bits LPF1 and LPF0. The differential input imped-
ance is a function of the clock frequency and the control
bits LPF1, LPF0, GAIN1 and GAIN0. Table 5 shows the
typical input impedances for a clock frequency of 80MHz.
BIAS
not receive a large enough bias current, possibly causing
errors due to insufficient settling. Be sure to obey the
absolute maximum specifications when driving a clock
into CLKIO (Pin 15).
These input impedances are all proportional to 1/f , so
CLK
if the clock frequency were reduced by half to 40MHz,
the impedances would be doubled. The typical variation
in dynamic input impedance for a given clock frequency
is –20% to +35%.
Input Common Mode and Differential Voltage Range
The input signal range extends from zero to the V+
IN
supply voltage. This input supply can be tied to V+ and
A
V+ , or driven up to 5.5V for increased input signal range.
D
Table 5. Differential, Common Mode Input Impedances,
Figure 9 shows the distortion of the filter versus common
fCLK = 80MHz
mode input voltage with a 2V differential input signal
Differential
Common Mode
P-P
Input Impedance Input Impedance
(V+ = 5V).
IN
GAIN1 GAIN0 LPF1 LPF0
(kꢀ)
38
(kꢀ)
40
20
5
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–60
16
HD3, f = 1MHz
2.5
2.5
20
5
–70
–80
–90
40
20
5
9.5
2.5
2.5
10
HD3, f = 200kHz
5
R
= 30.9k, V = 3V, V+ = 5.5V
S IN
BIAS
LPF1 = 1, BW = 2.5MHz, GAIN = 24dB
= V , T = 25°C
40
20
5
V
OUT
P-P
A
5.4
1.9
1.9
5.2
2.8
1.6
1.6
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COMMON MODE INPUT VOLTAGE (V)
6603 F09
5
Figure 9. Distortion vs Common Mode Input Voltage (5V)
40
20
5
For best performance, the inputs should be driven dif-
ferentially. For single ended signals, connect the unused
5
input to V
(Pin 3) or to a quiet DC reference voltage.
OCM
To achieve the best distortion performance, the input
signal should be centered around the DC voltage of the
unused input.
Output Common Mode and Differential Voltage Range
The output voltage is a fully differential signal with a
common mode level equal to the voltage at V . Any of
OCM
Refer to the Typical Performance Characteristics section
to estimate the distortion for a given input level.
the filter outputs may be used as single-ended outputs,
although this will degrade the performance. The output
Dynamic Input Impedance
voltage range is typically 0.5V to V+ – 0.5V (V+ = 2.7V
A
A
to 3.6V).
The common mode output voltage can be adjusted by
overdriving the voltage present on V . To maximize
The unique input sampling structure of the LTC6603
has a dynamic input impedance which depends on the
configuration and the clock frequency. This dynamic
input impedance has both a differential component and
a common mode component. The common mode input
impedance is a function of the clock frequency and the
OCM
the undistorted peak-to-peak signal swing of the filter,
the V
voltage should be set to V+ /2. Note that the
OCM
A
output common mode voltages of the two channels are
6603f
18
LTC6603
APPLICATIONS INFORMATION
not independent as they are both set by the V
pin.
Connecting resistors between each input and V+ will
OCM
IN
Figure 10 illustrates the distortion versus output common
pull the input common mode voltage up, increasing the
mode voltage for a 2V differential input voltage and a
inputsignalswing. Theresistance, R
, necessaryto
P-P
PULL-UP
common mode input voltage that is equal to mid-supply.
set the input common mode voltage, V , to any desired
ICM
level can be calculated by
–60
R
= 30.9k, V = 3V,
S
BIAS
GAIN = 24dB, T = 25°C
A
ꢁ
ꢄ
VSUPPLY
SIGNAL FREQUENCY = 200kHz
RPULLꢀUP =RCM
ꢀ1
ꢆ
ꢃ
–65
–70
–75
–80
HD3, LPF1 = 0, LPF0 = 1
V
ꢂ
ꢅ
ICM
where
HD2, LPF1 = 0,
LPF0 = 1
R
R
R
= 40k•80MHz/f
= 20k•80MHz/f
for LPF1=0, LPF0=0
for LPF1=0, LPF0=1
CM
CM
CM
CLK
HD2, LPF1 = 1
HD3, LPF1 = 1
CLK
= 5k•80MHz/f
for LPF1=1
CLK
For example, if the lowpass cutoff frequency is set to
2.5MHz, 5k resistors connected between each input and
0.8
1.0
1.2
1.4
1.6
1.8
COMMON MODE OUTPUT VOLTAGE (V)
6603 F10
V+ will set the input common mode voltage to mid-
IN
supply.
Figure 10. Distortion vs Common Mode Output Voltage
Circuit A of Figure 12 is for a fixed CLK and LPF0, LPF1
setting.IftheclockvariesortheLPF0,LPF1settingchanges
then Circuit B of Figure 12 should be used.
Interfacing to the LTC6603
TheinputandoutputcommonmodevoltagesoftheLTC6603
are independent. The input common mode voltage is set
by the signal source if DC coupled, as shown in Figure 11.
If the inputs are AC coupled, as shown in Figure 12
(CircuitA),theinputcommonmodevoltagewillbepulledto
Duetothesampleddatanatureofthefilter, ananti-aliasing
filter at the inputs is recommended.
The output common mode voltage is equal to the voltage
of the V
pin. The V
pin is biased to one half of the
OCM
OCM
groundbyanequivalentresistanceofR ,showninTable5.
CM
supply voltage by an internal resistive divider (see Block
Diagram).Toalterthecommonmodeoutputvoltage,V
This does not affect the filter’s performance as long as
OCM
the input amplitude is less than 0.5V . At low filter gain
P-P
can be driven with an external voltage source or resistor
network. If external resistors are used, it is important to
note that the internal 2k resistors can vary 30% (their
ratio varies only 1%). The filter outputs can also be AC
coupled.
settings, a larger input voltage swing may be desired.
V
SUPPLY
LTC6603
0.1μF
V+
V+
V+
IN
A
TheLTC6603canbeinterfacedtoanA/Dconverterbypull-
ingCLKCNTL(Pin5)toV+ .ThisconfiguresCLKIO(Pin15)
D
D
+OUTA
–OUTA
V
V
+
–
+INA
–INA
as a clock output, which can be used to drive the clock
input of the A/D converter. This allows the A/D converter
to be synchronized with the filter sampling clock, avoiding
“beat frequencies” and simplifying the board layout. Any
routing attached to the CLKIO pin should be as short as
possible, in order to minimize reflections.
OUT
OUT
V
OCM
+
+
–
V
+
IN
1μF
V
IN
–
–
GND
DC COUPLED INPUT
V
V
(COMMON MODE) = (V + + V –)/2
IN
IN IN
(COMMON MODE) = (V + + V –)/2 = V
/2
OUT
OUT
OUT
SUPPLY
Similarly,theLTC6603canbeinterfacedtoanotherLTC6603
inamaster/slaveconfigurationasshowninFigure13.This
6603 F11
Figure 11. DC Coupled Inputs
6603f
19
LTC6603
APPLICATIONS INFORMATION
CIRCUIT A
V
V
SUPPLY
SUPPLY
LTC6603
0.1μF
V+
V+
V+
IN
A
R
R
PULL-UP
PULL-UP
D
+OUTA
–OUTA
+INA
–INA
V
V
+
–
OUT
OUT
0.1μF
+
+
+
–
V
V
IN
0.1μF
OCM
V
IN
–
–
1μF
GND
AC COUPLED INPUT
V
IN
(COMMON MODE) = V
(COMMON MODE) = V
/2
OUT
SUPPLY
CIRCUIT B
V+
IN
0.1μF
V+
A
V
SUPPLY
LTC6603
0.1μF
1.87k
V+
1.87k
IN
A
V+
V+
0.1μF
D
+OUTA
–OUTA
+INA
–INA
V
V
+
–
OUT
OUT
0.1μF
V
OCM
+
–
+
V
–
V
IN
+
1.87k
1.87k
IN
1μF
–
GND
AC COUPLED INPUT
(COMMON MODE) =
RCM • V +IN
2 •RCM +1.87k
V
IN
6603 F12
Figure 12. AC Coupled Inputs
3.3V
3.3V
LTC6603
MASTER
LTC6603
SLAVE
0.1μF
0.1μF
V+
V+
V+
V+
V+
V+
IN
A
IN
A
D
D
+
+
+
+
+INA
–INA
+OUTA
–OUTA
+INA
–INA
+OUTA
–OUTA
V
V
OUT2
V
V
OUT1
IN1
IN2
–
–
–
–
CLKCNTL
CLKIO
GND
CLKCNTL
CLKIO
GND
6603 F13
Figure 13. Two Devices in a Master/Slave Clocking Configuration
6603f
20
LTC6603
APPLICATIONS INFORMATION
results in four matched filter channels, all synchronized to
the same clock. The master has its CLKCNTL pin pulled
tiples of the sampling frequency. The ratio of the LTC6603
input sampling frequency to the clock frequency, f , is
CLK
to V+ , configuring its CLKIO pin as an output, while the
determined by the state of control bits LPF1 and LPF0.
Table 6 shows the possible input sampling frequencies for
aclockfrequencyof80MHz.Theinputsamplingfrequency
is proportional to the clock frequency. For example, if the
clock frequency is lowered from 80MHz to 40MHz, the
input sampling frequency will be lowered by half. Input
signalswithfrequenciesneartheinputsamplingfrequency
will be aliased to the passband of the filter and appear at
the output unattenuated.
D
slavehasitsCLKCNTLpinpulledtoground,configuringits
CLKIOpinasaninput.Notethatinordertosynchronizethe
two filters, the clock frequency must not be buffered. This
requires that the filters be close together on the PC board.
If the clock is buffered, the filters would have matching
bandwidths, but would not be synchronized.
Output Drive
Thefilteroutputscandrive1kand/or50pFloadsconnected
to AC ground with a 0.5V to 2.5V signal (corresponding
Table 6. Input Sampling Frequency (fCLK = 80MHz)
LPF1
LPF0
Input Sampling Frequency (MHz)
to a 4V differential signal). For differential loads (loads
P-P
0
0
1
1
0
1
0
1
20
40
connected between +OUTA and –OUTA or +OUTB and
–OUTB) the outputs can produce a 4V signal across 2k
P-P
160
160
and/or25pF.Forsmallersignalamplitudes,theoutputscan
drive correspondingly larger loads. For larger capacitive
loads, an external 50ꢀ series resistor is recommended
for each output.
A simple LC anti-aliasing filter is recommended at the
filter inputs to attenuate frequencies near the input sam-
pling frequency that will be aliased to the passband. For
example, if the clock frequency is set to 80MHz and the
cutoff frequency of the filter is set to its maximum (LPF1
= ‘1’), the lowest frequency that would be aliased to the
Clock Feedthrough
ClockfeedthroughisdefinedastheRMSvalueoftheclock
frequency and its harmonics that are present at the filter’s
output. The clock feedthrough is measured with +INA and
passband would be f – f
, i.e. 160MHz – 2.5MHz
CLK CUTOFF
= 157.5MHz. The LTC6603 filter inputs should be driven
by a low impedance output (<100ꢀ).
–INA (or +INB, –INB) tied to V
and depends on the PC
OCM
board layout and the power supply decoupling. The clock
feedthrough can be reduced with a simple RC post filter.
Wideband Noise
Decoupling Capacitors
The wideband noise of the filter is the RMS value of the
device’soutputnoisespectraldensity.Thewidebandnoise
is nearly independent of the value of the clock frequency
andexcludestheclockfeedthrough. Mostofthewideband
noise is concentrated in the filter passband and cannot be
removed with post filtering.
The LTC6603 uses sampling techniques, therefore its
performance is sensitive to supply noise. 0.1μF ceramic
decouplingcapacitorsmustbeconnectedfromV+ (Pin2)
A
andV+ (Pin16)togroundwithleadsasshortaspossible.
D
A ground plane should be used. Noisy signals should be
isolated from the filter’s input pins. In addition, a 0.1μF
decoupling capacitor at Pin 20 is recommended since this
pin receives clocked current injection.
Power Supply Current
The power supply current depends on the state of the
lowpass cutoff frequency controls (LPF1, LPF0) and the
Aliasing
value of R
. When the LTC6603 is programmed for
BIAS
the middle cutoff frequency (LPF1 = ‘0’, LPF0 = ‘1’), the
supply current is reduced by about 23% relative to the
supply current for the higher bandwidth setting. Pro-
Aliasingisaninherentphenomenonofsampleddatafilters.
Significant aliasing only occurs when the frequency of the
input signal approaches the sampling frequency or mul-
6603f
21
LTC6603
APPLICATIONS INFORMATION
gramming the LTC6603 for the lowest cutoff frequency
(LPF1 = ‘0’, LFP0 = ‘0’) reduces the supply current by
about 60%. Power supply current vs. cutoff frequency
for various bandwidth settings is shown in the “Typical
Performance Characteristics” section. The LTC6603 can
be programmed through the serial interface to enter into
a low power shutdown mode. The power supply current
during shutdown is less than 235μA.
To extend the filter’s operational frequency range, the
master clock is divided down before reaching the filter.
LPF1 and LPF0 set the division ratio of the lowpass clock.
Figure 14 shows the possible cutoff frequencies versus
f
, LPF1 and LPF0. Overlapping frequency ranges allow
CLK
more than one possible choice of bandwidth settings for
some cutoff frequencies. Figure 15 shows supply current
as a function of the filter cutoff frequency, LPF1 and LPF0.
Note that the higher bandwidth setting always gives the
minimum supply current for a given cutoff frequency. The
input referred integrated noise voltage for a passband
gain of 24dB is shown in Table 7. Note that the noise is
higher for the higher bandwidth settings. This creates a
tradeoff between supply current and noise. For a given
cutoff frequency, using the highest possible bandwidth
setting gives the minimum supply current at the expense
of higher noise.
Supply Current vs. Noise Tradeoff
The passband of the LTC6603 is determined by the master
clock frequency (which is set by R
when the internal
BIAS
oscillator is used), LPF1 and LPF0. The LTC6603 is op-
timized for use with R having a value between 200k
BIAS
and 30.9k to set the internal oscillation frequency from
12.36MHz to 80MHz. The lowpass corner frequency is
proportional to the clock frequency (internal or external).
180
100
T
= 25°C
V = 3V
S
A
160
140
120
100
80
CLKCNTL PIN FLOATING
GAIN = 0dB
LPF1 = 0
LPF0 = 0
LPF1 = 0
LPF0 = 1
LPF1 = 1
LPF1 = 1
LPF1 = 0
LPF0 = 0
60
40
LPF1 = 0
LPF0 = 1
20
0
10
10k
100k
1M
10M
10k
100k
1M
10M
FILTER CUTOFF FREQUENCY (Hz)
FILTER CUTOFF FREQUENCY (Hz)
6603 F15
6603 F14
Figure 14. fCLK vs Filter Cutoff Frequencies
Figure 15. Supply Current vs Filter Cutoff Frequency
Table 7. Total Input Referred Integrated Noise Voltage (Passband Gain = 24dB)
LPF1
LPF0
Noise Voltage
–81dBm
0
0
1
0
1
X
–80dBm
–76dBm
6603f
22
LTC6603
TYPICAL APPLICATIONS
LTC6603 SPI Clock Control
LTC6603 Parallel Clock Control
3V
3V
1
2
16
V+
1
2
16
V+
0.1
0.1μF
V+
V+
A
V+
V+
IN
D
IN
A
D
24
23
7
19
18
13
12
15
24
23
7
19
18
13
12
15
+INA
–INA
+INB
–INB
+OUTA
–OUTA
+OUTB
–OUTB
CLKIO
+INA
–INA
+INB
–INB
+OUTA
–OUTA
+OUTB
–OUTB
CLKIO
DAC V
RANGE 0V TO 2.5V
OUT
(USING THE LTC2630 INTERNAL REFERENCE)
8
8
LTC6603
LTC6603
V
C
V
B
R2
1
6
4
4
R
R
CS
V
BIAS
BIAS
OUT
0.1μF
0.1μF
0.1μF
0.1μF
2
3
5
4
R3
R2
R1
3
17
3
17
5
SCLK
SDI
GND
V+
0.1μF
R1
3V
V
SER
V
SER
OCM
OCM
DIODES INC
DMN2004DWK
20
5
20
LTC2630
8-BIT DAC
CAP
CLKCNTL
CAP
CLKCNTL
3V
3V
22
21
11
10
V
OCM
GAIN1
SDO
SDI
22
21
11
10
GAIN1
SDO
SDI
GAIN0(D0)
GAIN0(D0)
14
25
9
6
GND
GND
LPF0(SCLK)
14
25
9
6
GND
GND
LPF0(SCLK)
LPF1(CS)
CLK1
CLK0
LPF1
LPF1(CS)
LPF0
CS1
SCK
SDI
CS2
GAIN1
GAIN0
6603 TA03
6603 TA02
IF R1 = 51.1k and R2 = 78.7k THEN
ꢁ
ꢄ
VC
R1+R2
R1•R2 VB •R2
fCLK = 2.472 •1012
ꢀ
ꢃ
ꢆ
THE f
RANGE IS 12.36MHz to 80MHz
CLK
ꢂ
ꢅ
CLK1
CLK0
12
12
0
0
1
1
0
1
0
1
R
BIAS1
R
BIAS2
R
BIAS3
R
BIAS4
f
f
f
f
CLK1
CLK2
CLK3
CLK4
5.282 • 10
5.282 • 10
f – f
CLKHI CLKLO
V
RANGE 0V to 2.5V, V = 1.17V
B
C
R1 =
, R2 =
1.137f
+ f
CLKHI CLKLO
IF V = 0V THEN f = f
C
C
CLK CLKHI
CLK CLKLO
IF V = 2.5V THEN f = f
R
R
> R
OR R
BIAS2 BIAS3
BIAS1
DESIGN PROCEDURE
1. CHOOSE f , f
BIAS1 BIAS2
3. CALCULATE R2, R3 AND R
2472
=
AND f
BIAS
CLK1 CLK2
2. CALCULATE R , R
CLK3
f
CLK
AND R
BIAS3
R
IN k
BIAS4
BIAS
f
in MHz
CLK
R
R
• R
BIAS2
R
R
• R
BIAS3
R1 • R2 • R3
R1 • (R2 + R3) + R2 • R3
BIAS1
BIAS1
BIAS1
BIAS1
R1 = R
R2 =
R3 =
R
=
BIAS4
BIAS1
– R
BIAS2
– R
BIAS3
PACKAGE DESCRIPTION
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
PIN 1 NOTCH
R = 0.20 TYP OR
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
0.35 × 45° CHAMFER
TYP
23 24
0.70 ±0.05
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
4.50 ± 0.05
3.10 ± 0.05
2.45 ± 0.05
(4 SIDES)
2.45 ± 0.10
(4-SIDES)
PACKAGE
OUTLINE
(UF24) QFN 0105
0.200 REF
0.25 ± 0.05
0.25 ±0.05
0.50 BSC
0.00 – 0.05
0.50 BSC
NOTE:
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6603f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC6603
TYPICAL APPLICATION
Direct Conversion Demodulator and I and Q Baseband Filter, fCUTOFF =1.92MHz (UTMS WCDMA)
5V
3V
56nH*
49.9Ω
3.9pF
RF IN
0.1μF
0.1μF
56nH*
10pF
1
2
16
V+
100pF
I
10pF
10pF
OUT
V+
IN
V+
A
D
4
3
2
1
10pF
100pF
10pF
56nH*
56nH*
49.9Ω
49.9Ω
24
23
7
19
18
13
12
15
GND GND RF GND
+INA
–INA
+INB
–INB
+OUTA
–OUTA
+OUTB
–OUTB
CLKIO
56nH*
16
15
5
6
EN
I
I
+
–
+
–
OUT
OUT
OUT
OUT
V
V
V
CC
CC
CC
LTC5575
14
13
8
7
8
5V
Q
Q
LTC6603
56nH*
4
R
10pF
BIAS
100pF
0.1μF
0.1μF
1μF
0.1μF
1000pF
40.2k
10pF
10pF
Q
OUT
GND LO GND V
3
17
CC
10 11 12
V
SER
OCM
10pF
56nH*
9
100pF
10pF
56nH*
49.9Ω
20
5
3V
CAP
CLKCNTL
5.6pF
1000pF
22
21
11
10
LO IN
GAIN1
SDO
SDI
GAIN0(D0)
14
25
9
6
GND
GND
LPFO(SCLK)
3V
LPF1(CS)
GAIN1 GAIN0
BASEBAND
GAIN CONTROL
*COILCRAFT 0603HP
6603 TA04
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC®1565-31
LTC1566-1
LTC1567
650kHz Linear Phase Lowpass Filter
Low Noise, 2.3MHz Lowpass Filter
Continuous Time, SO8 Package, Fully Differential
Continuous Time, SO8 Package
Very Low Noise, High Frequency Filter Building Block
Very Low Noise, 4th Order Building Block
1.4nV/√Hz Op Amp, MSOP Package, Differential Outputs
Lowpass and Bandpass Filter Designs Up to 10MHz, Differential Outputs
f ≤ 64kHz, One Resistor Sets f , SO-8 Differential Inputs
LTC1568
LTC1569-6
LTC1569-7
LT1994
Low Power 10-Pole Delay Equalized Elliptic Lowpass
10-Pole Delay Equalized Elliptic Lowpass
C
C
f ≤ 256kHz, One Resistor Sets f , SO-8 Differential Inputs
C
C
Low Distortion, Low Noise Differential Amplifier/ADC Driver
3GHz Low Noise, Rail-to-Rail Input Differential ADC Driver
Adjustable, Low Power, V = 2.375V to 12.6V
S
LTC6406
Low Noise: 1.6nV/√Hz, Low Power: 18μA
LT6600-2.5
LT6600-5
Very Low Noise, Fully Differential Amplifier and 2.5MHz Filter 86dB S/N with 3V Supply, SO-8 Package
Very Low Noise, Fully Differential Amplifier and 5MHz Filter 82dB S/N with 3V Supply, SO-8 Package
LT6600-10
LT6600-15
LT6600-20
LTC6601
Very Low Noise, Fully Differential Amplifier and 10MHz Filter 82dB S/N with 3V Supply, SO-8 Package
Very Low Noise, Fully Differential Amplifier and 15MHz Filter 76dB S/N with 3V Supply, SO-8 Package
Very Low Noise, Fully Differential Amplifier and 20MHz Filter 76dB S/N with 3V Supply, SO-8 Package
Pin-Configurable Second Order Filter/Driver
f 7MHz to 27MHz Fully Differential 4mm × 4mm QFN Package
C
LTC6602
Dual Baseband Bandpass Filter for UHF RFID
Fully Differential 4mm × 4mm QFN Package
LTC6604-2.5
LTC6604-5
LTC6604-10
LTC6604-15
Dual Very Low Noise, Differential Amp and 2.5MHz Filter
Dual Very Low Noise, Differential Amp and 5MHz Filter
Dual Very Low Noise, Differential Amp and 10MHz Filter
Dual Very Low Noise, Differential Amp and 15MHz Filter
86dB S/N with 3V Supply, 4mm × 7mm QFN Package
82dB S/N with 3V Supply, 4mm × 7mm QFN Package
82dB S/N with 3V Supply, 4mm × 7mm QFN Package
76dB S/N with 3V Supply, 4mm × 7mm QFN Package
6603f
LT 0908 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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