LTC6605IDJC-14-TRPBF [Linear]
Dual Matched 14MHz Filter with Low Noise, Low Distortion Differential Amplifi er; 与低噪声双路匹配14MHz滤波器，低失真差分功率放大器儿
| 型号： | LTC6605IDJC-14-TRPBF |
| 厂家： | 
Linear |
| 描述： | Dual Matched 14MHz Filter with Low Noise, Low Distortion Differential Amplifi er |
| 文件： | 总20页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6605-14
Dual Matched 14MHz Filter
with Low Noise, Low Distortion
Differential Amplifier
FEATURES
DESCRIPTION
The LTC®6605-14 contains two independent, fully differ-
ential amplifiers configured as matched 2nd order 14MHz
n
Two Matched 14MHz 2nd Order Lowpass Filters
with Differential Amplifiers
Gain Match: ±±.2ꢀdꢁ Maꢂ, ꢃassꢄand
ꢃhase Match: ±1.1ꢅ Maꢂ, ꢃassꢄand
Single-Ended or Differential Inputs
lowpass filters. The f
of the filters is adjustable in the
–3dB
range of 12.4MHz to 20MHz and 25MHz.
The internal op amps are fully differential, feature very
low noise and distortion, and are compatible with 16-bit
dynamic range systems. The inputs can accept single-
ended or differential signals. An input pin is provided
for each amplifier to set the common mode level of the
differential outputs.
n
< –84dꢁc Distortion in ꢃassꢄand
n
2.1nV/√Hz Op Amp Noise Density
Pin-Selectable Gain (0dB/6dB/9.5dB)
Pin-Selectable Power Consumption (0.35mA/
16.2mA/33.1mA)
Rail-to-Rail Output Swing
n
n
n
Internallaser-trimmedresistorsandcapacitorsdetermine
a precise, very well matched (in gain and phase) 14MHz
2nd order filter response. A single optional external re-
sistor per channel can tailor the frequency response for
each amplifier.
Adjustable Output Common Mode Voltage Control
Buffered, Low Impedance Outputs
n
2.7V to 5.25V Supply Voltage
n
Small 22-Pin 6mm × 3mm × 0.75mm DFN Package
Three-state BIAS pins determine each amplifier’s power
consumption, allowing a choice between shutdown, me-
dium power or full power.
APPLICATIONS
n
Broadband Wireless ADC Driver/Filter
n
Antialiasing Filter
The LTC6605-14 is available in a compact 6mm × 3mm
22-pin leadless DFN package and operates over a –40°C
to 85°C temperature range.
n
Single-Ended to Differential Conversion
DAC Smoothing Filter
n
n
Zero-IF Direct Conversion Receivers
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Dual, Matched 12.4MHz Lowpass Filter
Channel to Channel ꢃhase Matching
160
354 TYPICAL UNITS
+
1
2
22
21
20
19
18
17
16
15
14
13
12
T
f
= 25°
A
140
120
100
80
3V
+
–
= 14MHz
–
IN
0.1μF
0.1μF
V
V
3V
3
OUTA
INA
+
4
5
–
+
LTC6605-14
6
60
7
40
8
3V
+
–
–
OUTB
+
0.1μF
0.1μF
20
V
V
3V
9
INB
10
11
0
–1.0
–0.6
–0.2
0
0.2
0.6
1.0
–
PHASE MATCH (DEG)
660514 TA01
66057 TA01b
660514f
1
LTC6605-14
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
+
–
TOP VIEW
Total Supply Voltage (V to V )................................5.5V
Input Current (Note 2).......................................... 10mA
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range (Note 4).... –40°C to 85°C
Specified Temperature Range (Note 5) .... –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
+IN2 A
+IN1 A
BIAS A
–IN1 A
–IN2 A
1
2
3
4
5
6
7
8
9
22 –OUT A
+
21
20
19
V
V
V
A
–
OCMA
18 +OUT A
–
–
23
V
17 V
+IN2 B
+IN1 B
BIAS B
16 –OUT B
+
15
14
13
V
V
V
B
–
–IN1 B 10
–IN2 B 11
OCMB
12 +OUT B
DJC PACKAGE
22-LEAD (6mm × 3mm) PLASTIC DFN
T
= 150°C, θ = 46.5°C/W
JMAX
JA
–
EXPOSED PAD (PIN 23) IS V , MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAꢃE AND REEL
ꢃART MARKING*
ꢃACKAGE DESCRIꢃTION
22-Lead (6mm × 3mm) Plastic DFN
22-Lead (6mm × 3mm) Plastic DFN
TEMꢃERATURE RANGE
0°C to 70°C
–40°C to 85°C
LTC6605CDJC-14#PBF
LTC6605IDJC-14#PBF
LTC6605CDJC-14#TRPBF 660514
LTC6605IDJC-14#TRPBF 660514
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 2ꢀꢅC. V+ = 3V, V– = ±V, VINCM = VOCM = mid-supply, ꢁIAS tied to V+, RL =
Open, RꢁAL = 1±k. The filter is configured for a gain of 1, unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as
(V+OUT + V–OUT)/2. VINCM is defined as (VINꢃ + VINM)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINꢃ – VINM).
See Figure 1.
SYMꢁOL
ꢃARAMETER
CONDITIONS
MIN
TYꢃ
MAX
UNITS
l
V
Differential Offset Voltage (at Op Amp V = 2.7V to 5V
0.25
1
mV
OS
S
Inputs) (Note 6)
+
l
l
ΔV /ΔT
OS
Differential Offset Voltage Drift (at Op BIAS = V
1
1
μV/°C
μV/°C
Amp Inputs)
BIAS = Floating
+
l
l
I
I
Input Bias Current (at Op Amp Inputs) BIAS = V
–60
–30
–25
0
0
μA
μA
B
(Note 7)
BIAS = Floating
–12.5
Input Offset Current
(at Op Amp Inputs) (Note 7)
1
μA
OS
660514f
2
LTC6605-14
DC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 2ꢀꢅC. V+ = 3V, V– = ±V, VINCM = VOCM = mid-supply, ꢁIAS tied to V+, RL =
Open, RꢁAL = 1±k. The filter is configured for a gain of 1, unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as
(V+OUT + V–OUT)/2. VINCM is defined as (VINꢃ + VINM)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINꢃ – VINM).
See Figure 1.
SYMꢁOL
ꢃARAMETER
CONDITIONS
V = 3V
MIN
TYꢃ
MAX
UNITS
l
l
V
Input Common Mode Voltage Range
(Note 8)
–0.2
–0.2
1.7
4.7
V
V
INCM
S
V = 5V
S
l
l
CMRR
PSRR
Common Mode Rejection Ratio
V = 3V; ΔV
= 1.5V
= 2.5V
46
46
74
74
dB
dB
S
INCM
INCM
(ΔV
/ΔV ) (Note 9)
V = 5V; ΔV
S
INCM
OS
l
Power Supply Rejection Ratio
(ΔV /ΔV ) (Note 10)
V = 2.7V to 5V
S
66
95
dB
S
OS
l
l
V
V
V
Common Mode Offset Voltage
(V – V
V = 3V
10
10
15
15
mV
mV
OSCM
OCM
MID
S
)
V = 5V
S
OUTCM
OCM
l
l
Output Common Mode Range
(Valid Range for V Pin) (Note 8)
V = 3V
1.1
1.1
2
4
V
V
S
V = 5V
OCM
S
l
l
Self-Biased Voltage at the V
Pin
V = 3V
S
1.475
12.5
1.5
1.525
23.5
V
OCM
R
Input Resistance of V
Pin
OCM
18.8
kΩ
VOCM
l
l
l
V
Output Voltage Swing, High
V = 3V; I = 0mA
245
285
415
450
525
750
mV
mV
mV
OUT
S
L
+
(Measured Relative to V )
V = 3V; I = 5mA
S L
V = 3V; I = 20mA
S
L
l
l
l
V = 5V; I = 0mA
350
390
550
625
700
1000
mV
mV
mV
S
L
V = 5V; I = 5mA
S
L
V = 5V; I = 20mA
S
L
l
l
l
Output Voltage Swing, Low
V = 3V; I = 0mA
120
135
195
225
250
350
mV
mV
mV
S
L
–
(Measured Relative to V )
V = 3V; I = –5mA
S L
V = 3V; I = –20mA
S
L
l
l
l
V = 5V; I = 0mA
175
200
270
325
360
475
mV
mV
mV
S
L
V = 5V; I = –5mA
S
L
V = 5V; I = –20mA
S
L
l
l
I
Output Short-Circuit Current (Note 3)
V = 3V
S
40
50
70
95
mA
mA
SC
S
V = 5V
l
V
Supply Voltage
2.7
5.25
V
S
+
l
l
l
I
Supply Current (per Channel)
V = 2.7V to 5V; BIAS = V
S
S
33.1
16.2
0.35
45
26.5
1.6
mA
mA
mA
S
S
V = 2.7V to 5V; BIAS = Floating
–
V = 2.7V to 5V; BIAS = V
–
l
l
l
l
l
BIAS Pin Range for Shutdown
BIAS Pin Range for Medium Power
BIAS Pin Range for Full Power
Referenced to V
0
1
0.4
1.5
V
V
–
Referenced to V
–
Referenced to V
2.3
1.05
100
V
V
S
–
BIAS Pin Self-Biased Voltage (Floating) Referenced to V
BIAS Pin Input Resistance
1.15
150
400
400
1.25
200
V
R
kΩ
ns
ns
BIAS
–
+
–
t
t
Turn-On Time
Turn-Off Time
V = 3V, V
= V to V
ON
OFF
S
BIAS
BIAS
+
V = 3V, V
S
= V to V
660514f
3
LTC6605-14
AC ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 2ꢀꢅC. V+ = 3V, V– = ±V, VINCM = VOCM = mid-supply, VꢁIAS = V+, unless
otherwise noted. Filter configured as in Figure 2, unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (V+OUT
V–OUT)/2. VINCM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (V+IN + V–IN).
+
SYMꢁOL
ꢃARAMETER
CONDITIONS
ΔV 0.125V, DC
= 0.5V , f = 7MHz
MIN
TYꢃ
MAX
UNITS
l
l
l
l
l
l
Gain
Filter Gain
=
–0.25
–1.25
–2.5
–4.15
–11.65
–28
0.05
–0.92
–2.12
–3.75
–11.1
–25.2
0.25
–0.6
–1.75
–3.35
–10.6
–24.3
dB
dB
dB
dB
dB
dB
IN
V
V
V
V
V
INDIFF
INDIFF
INDIFF
INDIFF
INDIFF
P-P
= 0.5V , f = 10.5MHz
P-P
= 0.5V , f = 14MHz
P-P
= 0.5V , f = 28MHz
P-P
= 0.5V , f = 70MHz
P-P
Phase
Filter Phase
ΔV
=
0.125V, DC
0
Deg
Deg
Deg
Deg
IN
V
V
V
= 0.5V , f = 7MHz
–43.3
–63.6
–81.2
INDIFF
INDIFF
INDIFF
P-P
= 0.5V , f = 10.5MHz
P-P
= 0.5V , f = 14MHz
P-P
l
l
l
l
ΔGain
Gain Match (Channel-to-Channel)
Phase Match (Channel-to-Channel)
ΔV
=
0.125V, DC
–0.175
–0.2
0.04
0.04
0.04
0.05
0.175
0.2
dB
dB
dB
dB
IN
V
V
V
= 0.5V , f = 7MHz
INDIFF
INDIFF
INDIFF
P-P
= 0.5V , f = 10.5MHz
–0.2
0.2
P-P
= 0.5V , f = 14MHz
–0.25
0.25
P-P
l
l
l
ΔPhase
V
V
V
= 0.5V , f = 7MHz
–0.9
–1.0
–1.1
0.2
0.2
0.2
0.9
1.0
1.1
Deg
Deg
Deg
INDIFF
INDIFF
INDIFF
P-P
= 0.5V , f = 10.5MHz
P-P
= 0.5V , f = 14MHz
P-P
l
2V/V Gain
Filter Gain in 2V/V Configuration
Inputs at IN1 Pins, IN2 Pins Floating
ΔV
=
0.125V, DC
5.8
6
6.25
dB
IN
Channel Separation
V
= 1V , f = 7MHz
–96
dB
INDIFF
P-P
+
f
TC
Filter Cut-Off Frequency Temperature
Coefficient (T = –45°C to 85°C)
BIAS = V
–95
–230
ppm/°C
ppm/°C
O
BIAS = Floating
Noise
Integrated Output Noise
(BW = 10kHz to 28MHz)
54
μV
RMS
+
Input Referred Noise Density
(f = 1MHz)
BIAS = V
Figure 4, Gain = 1
Figure 4, Gain = 2
Figure 4, Gain = 3
13.2
6.6
4.4
nV/√Hz
nV/√Hz
nV/√Hz
+
e
Voltage Noise Density Referred to
Op Amp Inputs (f = 1MHz)
BIAS = V
2.1
2.6
nV/√Hz
nV/√Hz
n
BIAS = Floating
+
i
Current Noise Density Referred to
Op Amp Inputs (f = 1MHz)
BIAS = V
3
2.1
pA/√Hz
pA/√Hz
n
BIAS = Floating
+
HD2
HD3
2nd Harmonic Distortion
BIAS = V
–81
–69
dBc
dBc
f
= 7MHz; V = 2V Single-Ended
BIAS = Floating, R
= 400Ω
= 400Ω
IN
IN
P-P
LOAD
LOAD
+
3rd Harmonic Distortion
= 7MHz; V = 2V Single-Ended
BIAS = V
–93
–76
dBc
dBc
f
BIAS = Floating, R
IN
IN
P-P
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All pins are protected by steering diodes to either supply. If any
pin is driven beyond the LTC6605-14’s supply voltage, the excess input
current (current in excess of what it takes to drive that pin to the supply
rail) should be limited to less than 10mA.
Note ꢀ: The LTC6605C is guaranteed to meet specified performance
from 0°C to 70°C. The LTC6605C is designed, characterized and
expected to meet specified performance from –40°C to 85°C, but is
not tested or QA sampled at these temperatures. The LTC6605I is
guaranteed to meet specified performance from –40°C to 85°C.
Note 6: Output referred voltage offset is a function of gain. To determine
output referred voltage offset, or output voltage offset drift, multiply V
by the noise gain (1 + GAIN). See Figure 3.
OS
Note 3: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefinitely. Long-term application of output currents in excess of the
Absolute Maximum Ratings may impair the life of the device.
Note 4: Both the LTC6605C and the LTC6605I are guaranteed functional
over the operating temperature range –40°C to 85°C.
Note 7: Input bias current is defined as the average of the currents
flowing into the noninverting and inverting inputs of the internal amplifier
and is calculated from measurements made at the pins of the IC. Input
offset current is defined as the difference of the currents flowing into
the noninverting and inverting inputs of the internal amplifier and is
calculated from measurements made at the pins of the IC.
660514f
4
LTC6605-14
ELECTRICAL CHARACTERISTICS
Note 8: See the Applications Information section for a detailed
discussion of input and output common mode range. Input common
mode range is tested by measuring the differential DC gain with V
table, verifying that the differential gain has not deviated from the
mid-supply common mode input case by more than 0.5%, and that the
common mode offset (V
) has not deviated by more than 10mV
OSCM
INCM
= mid-supply, and again with V
limits listed in the Electrical Characteristics table, with ΔV
verifying that the differential gain has not deviated from the mid-supply
common mode input case by more than 0.5%, and that the common
at the input common mode range
from the mid-supply case.
INCM
= 0.25,
IN
Note 9: CMRR is defined as the ratio of the change in the input common
mode voltage at the internal amplifier inputs to the change in differential
input referred voltage offset (V ).
OS
mode offset (V
) has not deviated from the mid-supply common
OSCM
Note 1±: Power supply rejection ratio (PSRR) is defined as the ratio of
the change in supply voltage to the change in differential input referred
mode offset by more than 10mV.
Output common mode range is tested by measuring the differential DC
voltage offset (V ).
OS
gain with V
= mid-supply, and again with voltage set on the V
pin
OCM
OCM
at the output common range limits listed in the Electrical Characteristics
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Temperature
Filter Gain vs Temperature
37.5
35.0
32.5
30.0
27.5
25.0
22.5
20.0
17.5
15.0
12.5
1.010
1.005
+
V
= V
= MID-SUPPLY
OCM
V
V
= 3V, BIAS = V
INCM
S
= V
= MID-SUPPLY
5 REPRESENTATIVE UNITS
INCM
OCM
V
V
V
V
V
V
= 2.7V, BIAS = FLOAT
= 3V, BIAS = FLOAT
= 5V, BIAS = FLOAT
S
S
S
S
S
S
+
1.000
0.995
0.990
= 2.7V, BIAS = V
+
= 3V, BIAS = V
+
= 5V, BIAS = V
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
80
–60
20
TEMPERATURE (°C)
60
–40 –20
0
40
100
660514 G01
660514 G02
–3dꢁ Frequency vs Temperature
Filter Frequency Response
10
2.0
1.5
+
BIAS = V
V
V
= 3V
INCM
S
BIAS PIN FLOATING
= V
= 1.5V
OCM
0
–10
–20
–30
–40
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
BIAS = FLOAT
V
V
= 3V
INCM
S
+
BIAS = V
= V
= MID SUPPLY
10
OCM
0.1
1.0
100
1000
–60
60 80
–40 –20
20
TEMPERATURE (°C)
0
40
100
FREQUENCY (MHz)
660514 G04
660514 G03
660514f
5
LTC6605-14
TYPICAL PERFORMANCE CHARACTERISTICS
Harmonic Distortion
Harmonic Distortion
Harmonic Distortion
vs Input Amplitude
vs Frequency, ꢁIAS High
vs Frequency, ꢁIAS Floating
–40
–50
–40
–50
–40
–50
DIFFERENTIAL INPUT, HD2
DIFFERENTIAL INPUT, HD3
SINGLE-ENDED
DIFFERENTIAL INPUT, HD2
DIFFERENTIAL INPUT, HD3
SINGLE-ENDED INPUT, HD2
SINGLE-ENDED INPUT, HD3
DIFFERENTIAL INPUT, HD2
DIFFERENTIAL INPUT, HD3
SINGLE-ENDED
INPUT, HD2
INPUT, HD2
–60
–60
–60
SINGLE-ENDED
SINGLE-ENDED
INPUT, HD3
INPUT, HD3
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0.1
V
1
10
FREQUENCY (MHz)
= 2V , V = 3V
100
0
4
6
1
2
3
5
0.1
V
1
10
FREQUENCY (MHz)
= 2V , V = 3V
100
V
(V
)
IN P-P
660514 G05
660514 G07
660514 G06
+
IN
P-P
S
V
R
= 3V, BIAS TIED TO V , V
= V
= 1.5V,
IN
P-P
S
S
INCM
OCM
R
= 400Ω DIFFERENTIAL, GAIN = 1V/V
R
= 400Ω DIFFERENTIAL, GAIN = 1V/V
L
= 400Ω, f = 3MHz, GAIN = 1V/V
IN
L
LOAD
Harmonic Distortion vs Input
Harmonic Distortion vs Input
Differential Output Noise
vs Frequency
Common Mode Voltage (VS = 3V)
Common Mode Voltage (VS = ꢀV)
1000
100
10
–40
–50
100
10
1
–40
–50
DIFFERENTIAL
INPUT, HD2
DIFFERENTIAL
INPUT, HD3
SINGLE-ENDED
INPUT, HD2
SINGLE-ENDED
INPUT, HD3
DIFFERENTIAL INPUT, HD2
DIFFERENTIAL INPUT, HD3
SINGLE-ENDED INPUT, HD2
SINGLE-ENDED INPUT, HD3
V
= 3V
S
+
BIAS TIED TO V
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
OUTPUT NOISE
SPECTRAL DENSITY
INTEGRATED OUTPUT
NOISE
0.1
1
–0.5
1.5
INPUT COMMON MODE VOLTAGE (V)
= 2V , V = 1.5V
3
0
0.5
1
2
2.5
–0.5 0
3 3.5
4
0.5
INPUT COMMON MODE VOLTAGE (V)
= 2V , V = 2.5V
1
1.5
2
2.5
4.5 5
0.001
0.01
0.1
1
10
100
FREQUENCY (MHz)
660514 G10
V
660514 G08
V
660514 G09
IN
P-P OCM
IN
P-P OCM
BIAS = 3V, f = 3MHz
= 400Ω DIFFERENTIAL, GAIN = 1V/V
BIAS = 5V, f = 3MHz
= 400Ω DIFFERENTIAL, GAIN = 1V/V
R
L
R
L
Channel Separation vs Frequency
Overdrive Transient Response
2.0
1.5
–20
–30
+
+OUT
BIAS = V
–OUT
–IN2
+IN2
BIAS = FLOAT
–40
1.0
–50
0.5
–60
–70
0
–80
–0.5
–1.0
–1.5
–2.0
–90
–100
–110
–120
0.1
1
10
100
1000
50ns/DIV
= 1.5V
FREQUENCY (MHz)
V
= 3V, V
OCM
660514 G11
S
660514 G12
V
= 1V , V = 3V
P-P S
= 400Ω DIFFERENTIAL
IN
L
BIAS = 3V, R
= 400Ω
LOAD
R
660514f
6
LTC6605-14
TEST CIRCUITS
I
LTC6605-14
200Ω
L
81.5pF
48.2pF
+
25Ω
V
–OUT
22
200Ω
125Ω
1
2
100Ω
+
+
21
20
19
V
V
INP
R
0.1μF
BAL
–
0.1μF
–
+
–
BIAS
3
BIAS
V
OUTCM
V
0.1μF
–
+
–
V
V
–
+
R
V
BAL
INM
48.2pF
36k
36k
100Ω
200Ω
125Ω
200Ω
V
4
5
OCM
0.01μF
I
L
81.5pF
25Ω
V
+OUT
18
660514 TC01
Figure 1. DC Test Circuit (Channel A Shown)
LTC6605-14
200Ω
1μF
81.5pF
100Ω
V
–OUT
22
1μF
200Ω
V
+IN
1
48.2pF
125Ω
100Ω
COILCRAFT
TTWB-4-B
+
2
3
21
20
19
V
0.1μF
0.1μF
+
–
–
+
+
–
50Ω
–
V
BIAS
BIAS
V
IN
0.1μF
+
V
V
48.2pF
36k
100Ω
200Ω
125Ω
200Ω
V
4
5
OCM
36k
0.01μF
1μF
–
V
–IN
1μF
81.5pF
V
100Ω
+OUT
18
660514 TC02
Figure 2. AC Test Circuit (Channel A Shown)
660514f
7
LTC6605-14
PIN FUNCTIONS
+IN2 A, –IN2 A, +IN2 ꢁ, –IN2 ꢁ (ꢃins 1, ꢀ, 7, 11): Inputs
to Trimmed 200Ω Resistors. Can accept an input signal,
be floated, tied to an output pin, or connected to external
components.
V
, V
(ꢃins 19, 13): The voltage applied to these
OCMA OCMꢁ
pins sets the output common mode voltage of each filter
channel. If left floating, V self-biases to a voltage
OCM
+
–
midway between V and V .
+
+
+IN1 A, –IN1 A, +IN1 ꢁ, –IN1 ꢁ (ꢃins 2, 4, 8, 1±): Inputs
to Trimmed 100Ω Resistors. Can accept an input signal,
be floated, tied to an output pin, or connected to external
components.
V A,V ꢁ(ꢃins 21,1ꢀ):PositiveSupplyforFilterChannel
A and B, Respectively. These are not connected to each
other internally.
–OUT A, +OUT A, –OUT ꢁ, +OUT ꢁ (ꢃins 22, 18, 16, 12):
Differential Output Pins.
ꢁIAS A, ꢁIAS ꢁ (ꢃins 3, 9): Three-State Input to Select
Amplifier Power Consumption. Drive low for shutdown,
drive high for full power, leave floating for medium power.
BIAS presents an input resistance of approximately 150k
Eꢂposed ꢃad (ꢃin 23): Always tie the underlying Exposed
–
Pad to V . If split supplies are used, do not tie the pad
to ground.
–
to a voltage 1.15V above V .
–
–
V (ꢃins 6, 14, 17, 2±): Negative Supply. All V pins
should be connected to the same voltage, either a ground
plane or a negative supply rail.
660514f
8
LTC6605-14
BLOCK DIAGRAM
81.5pF
48.2pF
–OUT A
22
21
200Ω
100Ω
200Ω
125Ω
+IN2 A
+IN1 A
1
2
+
V
A
+
–
+
–
V
V
BIAS A
3
BIAS
20
19
–
+
V
A
48.2pF
36k
100Ω
200Ω
125Ω
200Ω
–IN1 A
–IN2 A
4
5
OCMA
36k
–
V
81.5pF
18 +OUT A
–
–
V
6
V
17
81.5pF
48.2pF
–OUT B
16
15
200Ω
100Ω
200Ω
125Ω
+IN2 B
+IN1 B
7
8
+
V
B
+
–
+
–
9
BIAS B
BIAS
V
V
14
13
–
+
V
B
48.2pF
36k
100Ω
200Ω
125Ω
200Ω
OCMB
–IN1 B
–IN2 B
10
11
36k
–
V
81.5pF
+OUT B
12
660514 BD
660514f
9
LTC6605-14
APPLICATIONS INFORMATION
Functional Description
capacitances should be decoupled with at least 25Ω of
series resistance from each output.
The LTC6605-14 is designed to make the implementation
of high frequency fully differential filtering functions very
easy. Two very low noise amplifiers are surrounded by
precisionmatchedresistorsandprecisionmatchedcapaci-
torsenablingvariousfilterfunctionstobeimplementedby
hard wiring pins. The amplifiers are wide band, low noise
andlowdistortionfullydifferentialamplifierswithaccurate
output phase balancing. They are optimized for driving
low voltage, single-supply, differential input analog-to-
digital converters (ADCs). The LTC6605-14 operates with
a supply voltage as low as 2.7V and accepts inputs up to
Filter Frequency Response and Gain Adjustment
Figure 3 shows the filter architecture. The Laplace transfer
function can be expressed in the form of the following
generalized equation for a 2nd order lowpass filter:
VOUT(DIFF)
GAIN
=
,
s2
V
s
IN(DIFF)
1+
+
2
2πfO • Q
2πf
(
)
O
with GAIN, f and Q as given in Figure 3.
O
–
325mV below the V power rail, which makes it ideal for
Note that GAIN and Q of the filter are based on component
ratios, which both match and track extremely well over
converting ground referenced, single-ended signals into
differentialsignalsthatarereferencedtotheuser-supplied
common mode voltage. This is ideal for driving low volt-
age, single-supply, differential input ADCs. The balanced
differential nature of the amplifier and matched surround-
ing components provide even-order harmonic distortion
cancellation, and low susceptibility to common mode
noise (like power supply noise). The LTC6605-14 can be
operated with a single-ended input and differential output,
or with a differential input and differential output.
temperature. The corner frequency f of the filter is a
O
function of an RC product. This RC product is trimmed to
1% and is not expected to drift by more than 1% from
nominal over the entire temperature range –40°C to 85°C.
As a result, fully differential filters with tight magnitude,
phase tolerance and repeatability are achieved.
Various values for resistors R1 and R4 can be formed
by pin-strapping the internal 100Ω and 200Ω resis-
tors, and optionally by including one or more external
resistors. Note that non-zero source resistance should be
combined with, and included in, R1.
The outputs of the LTC6605-14 can swing rail-to-rail.
They can source or sink a transient 70mA of current. Load
R2
200Ω
C2
81.5pF
R3
125Ω
C1
48.2pF
R1
+
–
R4A
+
–
–
–
+
V
R
V
IN(DIFF)
EXT
OUT(DIFF)
+
R4B
R3
125Ω
C1
48.2pF
R1
C2
81.5pF
R2
200Ω
R4 = R4A + R4B + R
EXT
660514 F03
Figure 3. Filter Architecture and Equations
660514f
10
LTC6605-14
APPLICATIONS INFORMATION
Setting the passband gain (GAIN = R2/R1) only requires
choosing a value for R1, since R2 is a fixed internal 200Ω.
Therefore,thefollowingthreegainscanbeeasilyconfigured
without external components:
Figure 4 shows three filter configurations with an
–3dB
filters have a Q = 0.57, which is an almost ideal Bessel
characteristic with linear phase.
f
= 12.3MHz,withoutanyexternalcomponents.These
Figure5showsfilterconfigurationsthatusesomeexternal
resistors, and are tailored for a very flat passband.
Taꢄle 1. Configuring the ꢃassꢄand Gain Without Eꢂternal
Components
GAIN
(V/V)
Manyotherconfigurationsarepossiblebyusingtheequa-
tions in Figure 3. For example, external resistors can be
added to modify the value of R1 to configure GAIN ≠ 1. For
an even more flexible filter IC with similar performance,
consider the LTC6601.
GAIN (dꢁ)
R1 (Ω)
INꢃUT ꢃINS TO USE
1
0
200
Drive the 200Ω Resistors. Tie
the 100Ω Resisters Together.
2
3
6
100
Drive the 100Ω Resistors.
9.5
66.7
Drive the 200Ω and 100Ω
Resistors in Parallel.
ꢁIAS ꢃin
The resonant frequency, f , is independent of R1, and
O
Each channel of the LTC6605-14 has a BIAS pin whose
functionistotailorbothperformanceandpower. TheBIAS
pin can be modeled as a voltage source whose potential
thereforeindependentofthegain.ForanyLTC6605-14filter
configuration that conforms to Figure 3, the f is fixed at
O
16.1MHz. The f
frequency depends on the combina-
tion of f and Q. For any specific gain, Q is adjusted by
–3dB
–
is 1.15V above the V supply and that has a Thevenin
O
equivalentresistanceof150k.Thisthree-statepinhasfixed
the selection of R4.
–
logiclevelsrelativetoV (seetheElectricalCharacteristics
table), and can be driven by any external source that can
drive the BIAS pin’s equivalent input impedance.
Setting the f
Frequency
–3dꢁ
Using an external resistor (R ), the f
frequency is ad-
EXT
–3dB
If the BIAS pin is tied to the positive supply, the part is
in a fully active state configured for highest performance
(lowest noise and lowest distortion).
justable in the range of 12.4MHz to 20.0MHz (see Figure 3).
The minimum f is set for R equal to 0Ω and the
–3dB
EXT
maximum f
is arbitrarily set for a maximum passband
–3dB
gain peak less than 1dB.
If the BIAS pin is floated (left unconnected), the part is in
afullyactivestate, butwithamplifiercurrentsreducedand
performancescaledbacktopreservepowerconsumption.
Care should be taken to limit external leakage currents
to this pin to under 1μA to avoid putting the part in an
unexpected state.
Taꢄle 2. REXT Selection GAIN = 1,
R1 = 2±±ꢆ, R4A = R4ꢁ = 1±±ꢆ
f
(MHz)
12.4
14
R
Ω
EXT
–3dꢁ
0
30.9
41.2
52.3
64.9
78.7
80.6
110
–
14.5
15
If the BIAS pin is tied to the most negative supply (V ),
the part is in a low power shutdown mode with amplifier
outputs disabled. In shutdown, all internal biasing current
sources are shut off, and the output pins each appear as
open collectors with a non-linear capacitor in parallel and
steering diodes to either supply. Because of the non-linear
capacitance, the outputs can still sink and source small
amounts of transient current if exposed to significant
voltage transients. Using this function to wire-OR outputs
together is not recommended.
15.5
16
16.5
17
17.5
18
127
150
174
18.5
19
205
241
287
19.5
20
660514f
11
LTC6605-14
APPLICATIONS INFORMATION
1
2
4
5
22
1
2
4
5
22
1
2
4
5
22
+
–
+
–
+
–
18
16
18
16
18
16
7
8
7
8
7
8
+
–
+
–
+
–
10
11
10
11
10
11
12
12
12
660514 F04a
660514 F04b
660514 F04c
f
= 12.3MHz
f
= 12.3MHz
f = 12.3MHz
–3dB
GAIN = 3V/V (9.5dB)
Z = 133Ω
IN
–3dB
–3dB
GAIN = 1V/V (0dB)
= 400Ω
GAIN = 2V/V (6dB)
= 200Ω
Z
Z
IN
IN
Gain Response
Gain Response
Gain Response
20
10
20
10
20
10
0
0
0
–10
–20
–10
–20
–10
–20
–30
–40
–30
–40
–30
–40
0.1
1
10
100
1000
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
660514 G04e
660514 G04f
660514 G04d
ꢃhase and Group Delay Response
Small Signal Step Response
0
–20
20
GAIN = 1V/V
18
16
14
12
10
8
–40
GROUP DELAY
PHASE
–60
–80
–100
–120
–140
–160
–180
–200
100mV/DIV
6
4
2
0
0.1
1
10
100
1000
20ns/DIV
FREQUENCY (MHz)
660514 G04i
660514 G04j
Figure 4. f–3dꢁ = 12.3MHz Filter Configurations without Eꢂternal Components
660514f
12
LTC6605-14
APPLICATIONS INFORMATION
1
2
4
5
22
1
2
4
5
22
+
–
+
–
200Ω
18
16
18
16
7
8
7
8
+
–
+
–
200Ω
10
11
10
11
12
12
660514 F05a
660514 F05c
0.4dB 14MHz PASSBAND
GAIN = 1V/V (0dB)
0.4dB 14MHz PASSBAND
GAIN = 2V/V (6dB)
Z
= 400Ω
Z
= 200Ω
IN
IN
Gain Response
Gain Response
10
0
10
0
–10
–20
–30
–40
–10
–20
–30
–40
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
660514 G05d
660514 G05e
ꢃassꢄand ꢃhase and Group Delay
Small Signal Step Response
30
0
55
50
45
40
35
30
25
20
15
10
5
GAIN = 1V/V
PHASE
–30
–60
–90
–120
100mV/DIV
GROUP DELAY
20ns/DIV
0.1
1
10
100
FREQUENCY (MHz)
660514 G05i
660514 G05j
Figure ꢀ. Flat ꢃassꢄand Filter Configurations with Some Eꢂternal Resistors
660514f
13
LTC6605-14
APPLICATIONS INFORMATION
Input Impedance
the ESD protection diodes on the input pins, neither input
–
should swing further than 325mV below the V power
Calculating the low frequency input impedance depends
on how the inputs are driven.
rail. Therefore, the input common mode voltage should
be constrained to:
Figure 6 shows a simplified low frequency equivalent cir-
cuit. For balanced input sources (V = –V ), the low
ꢂ
ꢅ
V
R1
INDIFF
2
Vꢀ ꢀ 325mV +
• V+ ꢀ1.4V ꢀ
ꢁ V
ꢁ 1+
INP
INM
ꢄ
ꢇ
INCM
frequency input impedance is given by the equation:
ꢃ
R2ꢆ
ꢂ
ꢅ
R
= R = R1
R1
INP
INM
V
ꢇ
OCM
ꢄ
(
)
ꢃR2ꢆ
Therefore, the differential input impedance is simply:
= 2 • R1
R
ThespecificationsintheElectricalCharacteristicstableare
a special case of the general equation above. For a single
IN(DIFF)
R2
+
–
R
INP
3V power supply, (V = 3V, V = 0V) with V
= 1.5V,
OCM
R1
–
V
+
OUT
ΔV
= 0.25V and R1 = R2, the valid input common
–
INDIFF
R3
R3
V
INP
+
–
mode range is:
–
–
V
OUTDIFF
–200mV ≤ V
≤ 1.7V
INCM
V
INM
R1
+
+
+
–
+
V
Likewise, for a single 5V power supply, (V = 5V, V = 0V)
OUT
R2
R
INM
V
with V
= 2.5V, ΔV
= 0.25V and R1 = R2, the valid
OCM
OCM
INDIFF
0.1μF
input common mode range is:
660514 F06
–200mV ≤ V ≤ 4.7V
INCM
Figure 6. Input Impedance
For single-ended inputs (V
increases over the balanced differential case due to the
fact that the summing node (at the junction of R1, R2
and R3) moves in phase with V to bootstrap the input
impedance. Referring to Figure 6 with V
impedance looking into either input is:
= 0), the input impedance
Output Common Mode and V
ꢃin
INM
OCM
The output common mode voltage is defined as the aver-
age of the two outputs:
INP
−
= 0, the input
VOUT+ + VOUT
INM
VOUTCM = VOCM
=
2
R1
RINP = RINM
As the equation shows, the output common mode voltage
is independent of the input common mode voltage, and
is instead determined by the voltage on the V
means of an internal feedback loop.
ꢇ
ꢊ
ꢄ
ꢁ
1
R2
1ꢀ •
ꢃ
ꢆ
ꢌ
ꢉ
2 ꢂR1+R2ꢅ
ꢈ
ꢋ
pin, by
OCM
Input Common Mode Voltage Range
If the V
pin is left open, an internal resistor divider
OCM
The input common mode voltage is defined as the average
of the two inputs into resistor R1:
+
–
develops a potential halfway between the V and V volt-
ages. The V pin can be overdriven to another voltage
if desired. For example, when driving an ADC, if the ADC
OCM
V
INP + V
INM
V
=
INCM
2
makes a reference available for setting the common mode
voltage,itcanbedirectlytiedtotheV
pin,aslongasthe
OCM
The input common mode range is a function of the filter
configuration (GAIN), V and the V potential.
ADCiscapableofdrivingtheinputimpedancepresentedby
the V pin as listed in the Electrical Characteristics table
INDIFF
OCM
OCM
Referring to Figure 6, the summing junction where R1, R2
(R
). The Electrical Characteristics table also specifies
VOCM
and R3 merge together should not swing within 1.4V of
the valid range that can be applied to the V
pin.
+
OCM
theV powersupply.Additionally,toavoidforwardbiasing
660514f
14
LTC6605-14
APPLICATIONS INFORMATION
Noise
the amplifier, the surrounding feedback resistors also
contribute noise. A noise model is shown in Figure 7a.
The output spot noise generated by both the amplifier
and the feedback components is given in Figure 7b.
When comparing the LTC6605-14’s noise to that of
other amplifiers, be sure to compare similar specifi-
cations. Standalone op amps often specify noise re-
ferred to the inputs of the op amp. The LTC6605-14’s
internal op amp has input referred voltage noise of
only 2.1nV/√Hz. In addition to the noise generated by
Substituting the equation for Johnson noise of a resistor
2
(e = 4kTR) into the equation in Figure 7b and simplify-
nR
ing gives the result shown in Figure 7c.
2
e
nR2
R2
2
e
e
nR1
nR1
R1
R1
+
2
I
n
2
2
2
e
e
e
ni
nR3
nR3
R3
+
–
2
e
no
R3
2
–
2
I
n
2
e
nR2
R2
660514 F07a
Figure 7a. Differential Noise Model
ꢆ
ꢇ n
ꢉ2
ꢆ
ꢉ2
ꢀ
ꢃ
ꢆ
ꢉ2
ꢆ
ꢉ2
ꢃ
ꢀ
ꢃ
ꢆ
ꢉ
ꢀ
ꢃ
ꢀ
R2
R2
R1
R2
R1
R2
R1
2
eno
=
e • 1+
+ 2 • I • R2+R3 • 1+
+ 2 • e
•
+ 2 • e
• 1+
+ 2 • enR2
ꢅꢋ
ꢈ
ꢋ
ꢂ
ꢅ
ꢈ
ꢂ
ꢅꢋ
ꢈ
ꢂ
ꢅꢋ
ꢈ
ꢂ
ni
ꢈ
ꢋ
nR1
nR3
R1ꢄ
ꢇ
ꢊ
ꢁ
ꢄ
ꢊ
ꢁ
ꢄ
ꢊ
ꢁ
ꢇ
ꢊ
ꢇ
ꢇ
ꢁ
ꢄ
ꢊ
Figure 7ꢄ
ꢉ2
ꢀ
ꢃ2
ꢆ
ꢈ
ꢉ
ꢆ
ꢇ n
ꢉ2
ꢃ
ꢆ
ꢀ
ꢃ
ꢆ
ꢉ
ꢀ
ꢃ
ꢀ
R2
R2
R1
R2
R1
R2
R1
ꢋ
eno
=
e • 1+
+ 2 • I • R2+R3 • 1+
+ 8 • k • T • R2 • 1+
+ R3 • 1+
ꢈ
ꢋ
ꢅ
ꢂ
ꢈ
ꢂ
ꢅꢋ
ꢂ
ꢅ
ꢂ
ꢅ
ni
ꢈ
ꢋ
ꢈ
ꢁ
ꢋ
R1ꢄ
ꢇ
ꢊ
ꢄ
ꢁ
ꢄ
ꢁ
ꢇ
ꢊ
ꢁ
ꢄ
ꢊ
ꢇ
ꢊ
Figure 7c
660514f
15
LTC6605-14
APPLICATIONS INFORMATION
ꢁoard Layout and ꢁypass Capacitors
away any ground plane underneath. Floating unused pins
does not reduce the reliability of the part.
For single-supply applications it is recommended that a
highqualityX5RorX7R,0.1μFbypasscapacitorbeplaced
At the output, always keep in mind the differential nature
of the LTC6605-14, because it is important that the load
impedances seen by both outputs (stray or intended) be
as balanced and symmetric as possible. This will help pre-
servethebalancedoperationthatminimizesthegeneration
of even-order harmonics and maximizes the rejection of
common mode signals and noise.
+
–
–
directly between V and the adjacent V pin. The V pins,
including the Exposed Pad, should be tied directly to a
low impedance ground plane with minimal routing.
For split power supplies, it is recommended that addi-
tional high quality X5R or X7R, 0.1μF capacitors be used
+
–
to bypass pin V to ground and V to ground, again with
minimal routing.
Driving ADCs
For driving heavy differential loads (< 200Ω), additional
The LTC6605-14’s rail-to-rail differential output and ad-
justable output common mode voltage make it ideal for
interfacing to differential input ADCs. These ADCs are
typically supplied from a single-supply voltage which can
beaslowas3V(2.7Vminimum),andhaveanoptimalcom-
mon mode input range near mid-supply. The LTC6605-14
makes interfacing to these ADCs easy, by providing
antialiasing, single-ended to differential conversion and
common mode level shifting.
+
–
bypass capacitance may be needed between V and V for
optimal performance. Keep in mind that small geometry
(e.g.,0603)surfacemountceramiccapacitorshaveamuch
higher self-resonant frequency than do leaded capacitors,
and perform best in high speed applications.
The V
pins should be bypassed to ground with a high
OCM
quality ceramic capacitor (at least 0.01μF). In split-sup-
ply applications, the V
ground or directly hard wired to ground.
pin can be either bypassed to
OCM
The sampling process of ADCs creates a transient that is
caused by the switching in of the ADC sampling capaci-
tor. This momentarily “shorts” the output of the amplifier
as charge is transferred between amplifier and sampling
capacitor. The amplifier must recover and settle from this
Stray parasitic capacitances to any unused input pins
shouldbekepttoaminimumtopreventdeviationsfromthe
ideal frequency response. The best approach is to remove
the solder pads for the unused component pins and strip
660514f
16
LTC6605-14
APPLICATIONS INFORMATION
load transient before the acquisition period has ended, for
a valid representation of the input signal. The LTC6605-14
will settle quickly from these periodic load impulses. The
RC network between the outputs of the driver decouples
the sampling transient of the ADC (see Figure 8). The
capacitance serves to provide the bulk of the charge
during the sampling process, while the two resistors at
the outputs of the LTC6605-14 are used to dampen and
attenuate any charge injected by the ADC. The RC filter
gives the additional benefit of band limiting broadband
output noise. The selection of the RC time constant is trial
and error for a given ADC, but the following guidelines are
recommended.ChooseanRCtimeconstantthatissmaller
than the reciprocal of the filter cutoff frequency configured
by the LTC6605-14. Time constants on the order of 2ns
do a good job of filtering broadband noise. Longer time
constants improve SNR at the expense of settling time.
The resistors in the decoupling network should be at least
25Ω. Too large of a resistor will leave insufficient settling
time. Too small of a resistor will not properly dampen the
load transient of the sampling process, prolonging the
time required for settling. In 16-bit applications, this will
typically require a minimum of eleven RC time constants.
The 10Ω resistors at the inputs to the ADC minimize the
sampling transients that charge the RC filter capacitors.
Forlowestdistortion,choosecapacitorswithlowdielectric
absorption, such as a C0G multilayer ceramic capacitor.
1/2 LTC6605-14
CONTROL
R
C1
1
2
3
4
5
22
21
20
19
18
+
V
D15
•
IN
•
–
3V
10Ω
+
D0
A
0.1μF
10nF
+
–
IN
1μF
C2
C1
10Ω
ADC
–
BIAS
A
IN
3.3V
V
GND
CM
V
1μF
OCM
2.2μF
R
CHANNEL A
660514 F08
τ = R • (C1 + 2 • C2)
Figure 8. Driving an ADC
660514f
17
LTC6605-14
TYPICAL APPLICATIONS
Dual, Matched, 4th Order 14MHz Lowpass Filter
LTC6605-14
LTC6605-14
1
2
22
1
2
4
5
22
+
–
+
–
V
1.4k
V
INA
OUTA
4
5
18
16
18
16
7
8
7
8
+
–
+
–
1.4k
V
V
INB
OUTB
10
11
10
11
12
12
660514 TA02
THREE GAINS ARE POSSIBLE,
AS SHOWN IN FIGURE 4
Gain Magnitude vs Frequency
10
0
–10
–20
–30
–40
–50
–60
0.1
1
10
100
FREQUENCY (MHz)
660514 TA03
660514f
18
LTC6605-14
PACKAGE DESCRIPTION
DJC ꢃackage
22-Lead ꢃlastic DFN (6mm × 3mm)
(Reference LTC DWG # 05-08-1714)
0.889
NOTE:
0.70 0.05
1. DIMENSIONS ARE IN MILLIMETERS
2. APPLY SOLDER MASK TO AREAS THAT
ARE NOT SOLDERED
3. DRAWING IS NOT TO SCALE
R = 0.10
0.889
3.60 0.05
1.65 0.05
2.20 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
5.35 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.40 0.05
22
6.00 0.10
(2 SIDES)
TYP
0.889
12
R = 0.10
TYP
0.889
3.00 0.10
(2 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PIN #1 NOTCH
R0.30 TYP OR
11
1
0.25mm × 45°
0.25 0.05
CHAMFER
0.75 0.05
0.200 REF
0.50 BSC
5.35 0.10
(2 SIDES)
(DJC) DFN 0605
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
660514f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC6605-14
TYPICAL APPLICATION
Gain Magnitude vs Frequency
Dual, Matched, 2nd Order 2ꢀMHz Lowpass Filter
3
0
LTC6605-14
1
2
4
5
22
–3
–6
–9
–12
+
–
V
V
INA
OUTA
18
16
–15
–18
–21
–24
7
8
+
–
0.1
1
10
100
V
FREQUENCY (MHz)
V
INB
OUTB
10
11
660514 TA05
12
660514 TA04
RELATED PARTS
ꢃART NUMꢁER
LT1568
DESCRIꢃTION
4th Order Filter Building Block
COMMENTS
Lowpass and Bandpass Responses Up to 10MHz
1.5nV/√Hz Noise, –95dBc Distortion at 10MHz
1.6nV/√Hz Noise, –72dBc Distortion at 50MHz, 18mA
LTC6404
Rail-to-Rail Output Differential Op Amp
LTC6406
3GHz Rail-to-Rail Input Differential Op Amp
LT6600-2.5/LT6600-5/ Differential 4th Order Lowpass Filters
LT6600-10/LT6600-15/
LT6600-20
Cut-Off Frequencies of 2.5MHz/5MHz/10MHz/15MHz/20MHz
LTC6601
Differential Pin-Configurable 2nd Order Filter
Building Block
7MHz to 25MHz Pin-Configurable
LT6604-2.5/LT6604-5 Dual Differential 4th Order Lowpass Filters
Cut-Off Frequencies of 2.5MHz or 5MHz
660514f
LT 1208 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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