LTC6801_技术文档

Electrical Specifications Subject to Change

LTC6801

Independent Multicell

Battery Stack Fault Monitor

FEATURES

DESCRIPTION

The LTC^®6801 is a multicell battery monitoring IC incor-

porating a 12-bit ADC, a precision independent voltage

reference, sampled comparator, and a high voltage input

multiplexer.TheLTC6801canmonitorasmanyas12series

connectedbatterycellsforovervoltage,undervoltage,and

overtemperature conditions, indicating whether the cells

are within speciﬁed parameters. The LTC6801 generates

a clock output when no fault conditions exist. Differential

clocking provides high noise immunity and ensures that

battery stack fault conditions cannot be hidden by frozen

bits or short circuit conditions.

n

Monitors Up to 12 Li-Ion Cells in Series (60V Max)

n

Stackable Architecture Enables >1000V Systems

n

Adjustable Overvoltage and Undervoltage

Detection

n

Self Test Features Guarantee Accuracy

n

Robust Fault Detection Using Differential Signals

n

Simple Pin-Strapped Conﬁguration Allows Battery

Monitoring without a Microcontroller

n

15ms to Monitor All Cells in a System

n

Programmable Response Time

n

Two Temperature Monitor Inputs

n

Low Power Idle Mode

36-Lead SSOP Package

Each LTC6801 can operate with a battery stack voltage up

to 60V and multiple LTC6801 devices can be stacked to

monitor each individual cell in a long battery string. When

multiple devices are stacked, the status signal of each

LTC6801 can be daisy-chained, without opto-couplers or

isolators, providing a single status output for the entire

battery string.

n

APPLICATIONS

n

Redundant Battery Monitor

n

Hybrid Electric Vehicles

n

Battery Backup Systems

Power Systems Using Multiple Battery Cells

n

The LTC6801 is conﬁgurable by external pin strapping.

Adjustable overvoltage and undervoltage thresholds sup-

port various Li-Ion chemistries. Selectable measurement

times allow users to save power.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

BLOCK DIAGRAM

0V Detection Level Error

NEXT HIGHER

CELL PACK

LTC6801

+

1

2

3

V

1.0

+

V

= 43.2V

0.8 OV = 4.120V

C12

C11

0.6

0.4

0.2

0

5 TYPICAL UNITS

CONTROL

LOGIC

12

ADC

MUX

C2

C1

–0.2

ENABLE

INPUT

12

13

14

ISOLATION

–0.4

–0.6

–0.8

–1.0

20

“CELLS GOOD”

CLOCK SIGNAL

INPUT ENABLES

THE LTC6801

–

V

–40 –25 –10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

22

NEXT LOWER

CELL PACK

6801 TA01b

REFERENCE

STATUS

OUTPUT

CLOCK SIGNAL

OUTPUT INDICATES

SYSTEM “OK”

V

TEMP1

15

TEMP2

16

REF

17

6801 TA01a

NTC

6801p

1

LTC6801

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

+

–

Total Supply Voltage (V to V ).................................60V

+

1

2

OV1

OV0

UV1

UV0

HYST

CC1

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

V

C12

C11

C10

C9

–

Input Voltage (Relative to V )

C1............................................................ –0.3V to 9V

3

+

C12...........................................V –0.3V to V + 0.3V

All Other Pins (Not C Inputs) ................... –0.3V to 7V

Voltage Between Inputs

4

5

6

C8

Cn to Cn-1* ............................................. –0.3V to 9V

C12 to C8............................................... –0.3V to 25V

C8 to C4................................................. –0.3V to 25V

7

CC0

C7

8

SLT

C6

9

SLTOK

DC

C5

–

10

11

12

13

14

15

16

17

18

C4

C4 to V ................................................. –0.3V to 25V

EOUT

SIN

C3

Operating Temperature Range.................. –40°C to 85°C

Speciﬁed Temperature Range .................. –40°C to 85°C

Junction Temperature ........................................... 150°C

Storage Temperature Range................... –65°C to 150°C

C2

C1

–

SIN

V

SOUT

EIN

V

TEMP1

TEMP2

*n = 2 to 12

V

REF

EIN

V

REG

G PACKAGE

36-LEAD PLASTIC SSOP

= 150°C, θ = 70°C/W

T

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

SPECIFIED TEMPERATURE RANGE

LTC6801IG#PBF

LTC6801IG#TRPBF

LTC6801IG

36-Lead Plastic SSOP

–40°C to 85°C

Consult LTC Marketing for information on lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

6801p

2

LTC6801

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C, V⁺= 43.2V, V^–= 0V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC Speciﬁcations

+

V

Measurement Error

V

CELL

V

CELL

V

CELL

V

CELL

> 0.8V, 10V < V < 50V

–0.5

–1

–1.5

–2

0.5

1

1.5

2

%

ERR

l

> 0.8V, 10V < V < 50V

≤ 0.8V, 10V < V < 50V

V

Cell Voltage Range

Full Scale Voltage Range

5

V

CELL

Common Mode Voltage Range Measured

V

Speciﬁcations Met

ERR

CM

–

l

Relative to V

Range of Inputs Cn, n = 3 to 11

Range of Input C2

1.8

1.2

0

5 • n

10

5

V

Range of Input C1

l

V

Overvoltage (OV) Detection Level

Undervoltage (UV) Detection Level

Temperature Input Detection Level Error

Programmed for 4.128V, Increasing V

,

4.079

2.087

–18

4.120

2.108

4.161

2.129

12

V

OV

CELL

+

10V < V < 50V

Programmed for 2.112V, Decreasing V

,

V

UV

CELL

+

10V < V < 50V

+

V

TV

10V < V < 50V

mV

%

(Relative to V /2)

REF

+

HYS

UV/OV Detection Hysteresis Error

(Relative to Selected Value)

10V < V < 50V

–25

25

–

V

Reference Pin Voltage

V

REF

Pin Loaded With 100k to V

3.043

3.038

3.058

3.073

3.078

V

REF

l

Reference Voltage Temperature Coefﬁcient

Reference Voltage Hysteresis

Reference Voltage Long Term Drift

Regulator Pin Voltage

5

ppm/˚C

ppm

50

60

ppm/√khr

l

V

10 < V < 50, No Load

4.5

4.1

5

4.8

5.5

V

REG

S

10 < V < 50, I

= 4mA

LOAD

S

l

Regulator Pin Short Circuit Current Limit

5

9

mA

V

+

–

Supply Voltage, V Relative to V

V

Speciﬁcations Met

10

50

10

S

ERR

I

B

Input Bias Current

In/Out of Pins C1 Thru C12

When Measuring Cells During Self Test

When Measuring Cells

When Idle

100

1

μA

nA

l

–10

+

I

M

Supply Current, Monitor Mode

Current Into the V Pin While Monitoring

for UV and OV Conditions, F

Continuous Monitoring

Monitor Every 130ms

Monitor Every 500ms

= 10kHz

ENA

l

500

20

700

200

90

1000

40

μA

+

I

Supply Current, Idle

Current into the V Pin When Idle, F

= 0

30

μA

QS

ENA

LTC6801 Timing Speciﬁcations

l

T

Measurement Cycle Time

Valid EIN/EIN Frequency

Valid EIN/EIN Period = 1/ F

Valid EIN/EIN Duty Cycle

DC = CC1 = CC0 = V

13.5

2

15.5

17.5

50

ms

kHz

μs

CYCLE

ENA

REG

F

T

20

40

500

60

ENA

DC

F

= 50kHz

ENA

%

ENA

LTC6801 Single Ended Digital I/O Speciﬁcations (SLT, SLTOK Pins)

l

V

Digital Input Voltage High

SLT Pin

2

V

IH

Digital Input Voltage Low

SLT Pin

0.5

0.3

IL

Digital Output Voltage Low, Open Drain

Digital Output Voltage High

Digital Output Voltage Low

SLT Pin, 10k to V

SLTOK Pin, 10k to V

ODL

OH

OL

REG

–

V

– 0.3

REG

0.3

V

REG

6801p

3

LTC6801

The l denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C, V⁺= 43.2V, V^–= 0V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

I

Pull-Up Current

SLT Pin

2.5

5

10

μA

PU-ST

LTC6801 Differential Digital Input Speciﬁcations (SIN/SIN, EIN/EIN Pins) (See Figure 1)

l

V

Minimum Differential Input Voltage High

Minimum Differential Input Voltage Low

Valid Input Voltage Low

Differential Voltage Applied Between SIN

1.7

V

IDH

IDL

and SIN or EIN and EIN

–1.7

1.2

6

–

Low Side of Differential Signal, Ref. to V

High Side of Differential Signal, Ref. to V

0

V

IL

–

Valid Input Voltage High

2.5

V

IH

Differential Input Hysteresis

Open Circuit Voltage

1

V

DHYS

OPEN

l

2

2.5

150

300

3

V

R

Input Resistance, Common Mode

Input Resistance, Differential

100

200

kΩ

INCM

Between SIN to SIN, EIN to EIN

INDIFF

LTC6801 Differential Digital Output Speciﬁcations (SOUT/SOUT, EOUT/EOUT Pins)

–

l

V

Digital Output Voltage High

Digital Output Voltage Low

Output Pins Loaded With 100k to V

V

REG

– 0.3

V

ODH

ODL

0.3

REG

LTC6801 Three-Level Digital Input Speciﬁcations (OV0, OV1, UV0, UV1, HYST, DC, CC0 and CC1 Pins)

l

V

Three-Level Digital Input Voltage High

Three-Level Digital Input Voltage Mid

Three-Level Digital Input Voltage Low

Pull-Up Current

V

– 0.3

V

3IH

3IM

3IL

REG

V

REF

+ 0.3

REF

0.3

2

V

I

PU

I

PD

Pins DC, CC0, CC1, UV0 and UV1

Pins HYST, OV0 and OV1

0.5

1

μA

Pull-Down Current

2

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

EIN

V

IDH

MAX, V

MIN, V

(VALID HIGH WHEN

EIN – EIN ≥ V

IH

T

ENA

)

IDH

EIN

MAX, V

IL

V

IDL

(VALID LOW WHEN EIN – EIN ≤ V

)

IDL

–

V

= 0V

6801 F01

Figure 1. Differential Input Speciﬁcations

6801p

4

LTC6801

TYPICAL PERFORMANCE CHARACTERISTICS

Supply Current, Monitor Mode

Supply Current, Idle Mode

250

200

150

100

50

800

780

760

740

720

700

680

660

640

620

600

40

35

30

25

20

15

10

5

CC1 = CC0 = V

REG

DC PIN TIED TO V

REG

f

= 10kHz

f

= 10kHz

ENA

85°C

25°C

85°C

DC PIN = V

REF

–40°C

–

DC PIN = V

85°C

25°C

–40°C

0

10

20

30

40

50

60

10

20

30

40

50

60

10

20

30

40

50

60

+

V

(V)

V

(V)

V

(V)

6801 G02

6801 G01

6801 G03

Supply Current, Monitor Mode

Supply Current, Idle Mode

800

780

760

740

720

700

680

660

640

620

600

250

200

150

100

50

40

35

30

25

20

15

10

5

DC PIN TIED TO V

ENA

CC1 = CC0 = V

REG

f

= 10kHz

f

= 10kHz

ENA

+

V

= 60V

+

V

= 60V

+

V

= 35V

+

DC PIN = V

REF

V

= 10V

+

V

= 35V

+

–

V

= 10V

DC PIN = V

+

V

= 60V

= 35V

= 10V

0

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

6801 G04

6801 G05

6801 G06

UV Detection Level Error

0V Detection Level Error

Supply Current

1.0

0.8

1.0

0.8

800

780

760

740

720

700

680

660

640

620

600

+

V

= 43.2V

V

= 43.2V

V

= 43.2V

UV = 2.108V

OV = 4.120V

CONTINUOUS MEAS MODE

0.6

5 TYPICAL UNITS

85°C

0.4

0.2

25°C

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–40°C

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

1

10

(kHz)

100

TEMPERATURE (°C)

f

ENA

6801 G07

6801 G08

6801 G09

6801p

5

LTC6801

TYPICAL PERFORMANCE CHARACTERISTICS

Cell Input Bias Current when

Measuring

UV/OV Detection Level Error

Measurement Cycle Time

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

17.0

16.5

16.0

15.5

15.0

14.5

14.0

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

R

IN SERIES WITH Cn AND Cn-1

CONTINUOUS MEAS MODE

CELL INPUT = 3.6V

S

–

10nF FROM Cn, Cn-1 TO V

CC1 = CC0 = V

REG

85°C

25°C

+

–40°C

V

= 10V

+

V

= 60V

0

2

4

6

8

10

–40 –25 –10

5

20 35 50 65 80 95 110 125

–40 –25 –10

5

20 35 50 65 80 95 110 125

EXTERNAL SERIES RESISTANCE, R (kΩ)

TEMPERATURE (°C)

S

6801 G11

6801 G12

6801 G10

Cell Voltage Measurement

Hysteresis

Cell Input Bias Current, Idle Mode

V_REFLine Regulation

50

40

30

20

10

0

12

10

8

3.070

3.065

3.060

3.055

3.050

CELL INPUT = 3.6V

UV THRESHOLD = 2.108V

OV THRESHOLD = 4.120V

NO LOAD

HYST = V

REG

25°C

6

–40°C

85°C

4

UNDERVOLTAGE

DETECTED

C12

C1

2

0

C2 TO C11

V

, V

TEMP1 TEMP2

OVERVOLTAGE DETECTED

–10

–2

–40 –25 –10

5

20 35 50 65 80 95 110 125

0

1

2

3

4

5

10

20

30

40

50

60

+

TEMPERATURE (°C)

CELL VOLTAGE (V)

V (V)

6801 G13

6801 G14

6801 G15

V_REFOutput Voltage

V_REGLine Regulation

V_REFLoad Regulation

3.070

3.065

3.060

3.055

3.050

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

NO LOAD

IDLE MODE

NO LOAD

3.070

3.065

3.060

3.055

3.050

85°C

25°C

5 TYPICAL UNITS

–40°C

25°C

85°C

–40 –25 –10

5

20 35 50 65 80 95 110 125

10

20

30

40

50

60

0

50

100

150

(μA)

200

250

300

+

TEMPERATURE (°C)

V (V)

6801 G16

6801 G17

I

LOAD

6801 G20

6801p

6

LTC6801

TYPICAL PERFORMANCE CHARACTERISTICS

V_REGLoad Regulation

V_REGOutput Voltage

V_REGLine Regulation

5.5

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

IDLE MODE

5.5

IDLE MODE

–

5.4

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

4mA LOAD TO V

5.0

4.5

4.0

NO LOAD

4mA LOAD

85°C

25°C

–40°C

25°C

+

V

= 60V

= 35V

= 10V

–40°C

+

V

= 60V

= 10V

0

2

4

6

8

10

–40 –25 –10

5

20 35 50 65 80 95 110 125

10

20

30

40

50

60

I

(mA)

TEMPERATURE (°C)

LOAD

+

6801 G19

6801 G21

V

(V)

6801 G18

UV/OV Detection Level Thermal

Hysteresis

UV/OV Detection Level Thermal

Hysteresis

Status Output Operating at 10kHz

16

14

12

10

8

20

18

16

14

12

10

8

–

100k LOAD TO V

T

= 85°C TO 25°C

T = –40°C TO 25°C

A

SOUT

2V/DIV

SOUT

6

4

6801 G22

2

20μs/DIV

2

0

–100 –50

0

50

100

150

200

–100 –50

0

50

100

150

200

CHANGE IN DETECTION LEVEL (ppm)

6801 G23

6801 G24

6801p

7

LTC6801

PIN FUNCTIONS

V (Pin 1): Tied to the most positive potential in the bat-

tery stack. For example, the same potential as C12 when

measuring a stack of 12 cells, or the same potential as

C7 when measuring a stack of 7 cells.

+

SOUT, SOUT (Pin 21, Pin 22): Differential Status Output.

–

Swings V to V . This output will toggle at the same fre-

REG

quencyasEIN/EINwhenavalidsignalisdetectedatSIN/SIN

and the battery stack being monitored is within speciﬁed

parameters, otherwise SOUT is low and SOUT high.

C12, C11, … C1 (Pin 2 to Pin 13): Cell Voltage Inputs.

Up to 12 cells can be monitored. The lowest potential is

SIN, SIN (Pin 23, Pin 24): Differential status input from

the IC above. To indicate that the stack is good, SIN must

be the same frequency and phase as EIN. See applications

circuits for interfacing SIN to the SOUT above.

–

tied to V . The next lowest potential is tied to C1 and so

forth. Due to internal overvoltage protection, each C input

must be tied to a potential equal to or greater than the next

lowernumberedCinput.SeetheﬁguresintheApplications

Informationsectionformoredetailsonconnectingbatteries

to the LTC6801. See Electrical Characteristics table for

voltage range and input bias current requirements.

EOUT, EOUT (Pin 25, Pin 26): A Buffered Version of

–

EIN/EIN. Swings V to V . Must be capacitively coupled

REG

to the EIN/EIN inputs of the next higher voltage LTC6801

in a stack, or looped to SIN/SIN of the same chip (pins

23, 24).

–

V (Pin 14): Tied to the most negative cell potential (bot-

tom of monitored cell stack).

DC (Pin 27): Duty Cycle Three-Level Input. This pin may

–

V

, V

(Pin 15, Pin 16): Temperature Sensor

be tied to V , V

or V . The DC pin selects the duty

TEMP1

TEMP2

REG REF

Inputs. The ADC will measure the voltages on V

cycle of the monitoring function and has an internal pull-

TEMP1

–

and V

referenced to the V

relative to V . The ADC measurements are

up to V . See Table 3.

TEMP2

REG

pin voltage. Therefore a simple

REF

SLTOK(Pin28):SelfTestLogicOutput.SLTOKisheldHIGH

thermistorandresistorcombinationconnectedtotheV

REF

(V

voltage) upon reset or successful completion of a

REG

pin can be used to monitor temperature. These pins have

–

self test cycle. A LOW output level (V voltage) indicates

a ﬁxed undervoltage threshold equal to one half V . A

REF

the last self test cycle failed.

–

ﬁltering capacitor to V is recommended. Temperature

SLT (Pin 29): Self Test Open Collector Input/Output. SLT

initiates a self test cycle when it is pulled low externally.

Whenahightolowtransitionisdetected,thenextscheduled

measurement cycle will be a self test cycle. SLT indicates a

self test cycle is in progress when pulled low internally. A

self test is automatically initiated after 1024 measurement

sensor input pins may be tied to V to disable.

REF

V

(Pin 17): Reference Output, Nominally 3.072V. Re-

REF

–

quires a 1μF bypass capacitor to V . The V

pin can

REF

–

drive a 100k resistive load connected to V . V

must

REF

be buffered with an LT6003 ampliﬁer, or similar device to

drive heavier loads. V becomes high impedance when

REF

cycles. This pin has an internal pull-up to V

.

REG

the IC is disabled or idle between monitoring events.

CC0, CC1 (Pin 30, Pin 31): Cell Count Three-Level Inputs.

V

(Pin 18): Regulator Output, Nominally 5V. Requires

–

REG

These pins may be tied to V , V or V . CC1 and CC0

REG REF

–

a 1μF bypass capacitor to V . The V

pin is capable of

REG

select the number of cells attached to the device and each

pin has an internal pull-up to V . See Table 5.

supplying up to 4mA to an external load and is continu-

ally enabled.

REG

HYST(Pin32):HysteresisThree-LevelInput.Thispinmay

EIN, EIN (Pin 19, Pin 20): Differential Enable Input. A

clocksignalgreaterthan2kHzwillenabletheLTC6801.For

operationwithasingle-endedenablesignal(upto10kHz),

–

be tied to V , V

or V . HYST selects the amount of

REG REF

hysteresis applied to the undervoltage and overvoltage

threshold settings and has an internal pull-down to V .

–

drive EIN and connect a 1nF capacitor from EIN to V .

See Table 4.

6801p

8

LTC6801

PIN FUNCTIONS

UV0, UV1 (Pin 33, Pin 34): Undervoltage Three-Level

Table 3. Duty Cycle Select

DC

–

Inputs. These pins may be tied to V , V

or V . UV1

REG REF

NOMINAL CYCLE TIME*

and UV0 select the undervoltage threshold and each pin

V

REG

15ms

has an internal pull-up to V . See Table 2.

REG

V

Approximately 130ms

Approximately 500ms

REF

–

OV0, OV1 (Pin 35, Pin 36): Overvoltage Three-Level

V

–

Inputs. These pins may be tied to V , V

or V . OV1

*Cycle time based on LTC6801 measuring 12 cells and 2 temperatures.

REG REF

and OV0 select the overvoltage threshold and each pin

–

has an internal pull-down to V . See Table 1.

Table 4. Hysteresis Select

HYST

UV HYSTERESIS*

500mV

OV HYSTERESIS

200mV

Table 1. Overvoltage Inputs

V

REG

OV1

OV0

OVERVOLTAGE THRESHOLD (V)

V

250mV

100mV

V

4.503

4.407

4.311

4.216

4.120

4.024

3.928

3.832

3.737

REF

–

REG

V

0mV

V

REG

REF

–

*UV hysteresis is disabled when the undervoltage threshold is set to 0.766V.

V

REG

REF

V

Table 5. Cell Count Select

REF

–

V

CC1

CC0

CELL COUNT

REF

–

V

12

11

10

9

V

REG

–

V

REF

V

REF

–

V

REG

REF

V

8

REF

Table 2. Undervoltage Inputs

UV1 UV0

–

V

7

REF

–

UNDERVOLTAGE THRESHOLD (V)

V

REG

6

V

REG

V

REG

V

REG

V

2.874

2.683

2.491

2.299

2.108

1.916

1.725

1.533

0.766

REG

–

V

5

V

REF

–

V

4

V

REG

REF

V

REF

–

V

REF

–

V

REG

–

V

REF

–

V

6801p

9

LTC6801

BLOCK DIAGRAM

TheLTC6801measuresbetween4and12cellvoltagesand

2 temperature inputs. If all measurements are within an

acceptablewindow,theLTC6801willproduceadifferential

clock output signal (SOUT, SOUT). If any of the channels

exceed user set upper and lower thresholds, a logic low

signal is produced at SOUT.

+

V

REG

REGULATOR

C12

C11

HYST

CC1

C10

12

CC0

+

ADC

C9

C8

C7

C6

C5

C4

C3

C2

C1

DC

–

DIGITAL

COMPARATORS

UV/OV

FLAGS AND

CONTROL

LOGIC

SLT

–

REFERENCE

SLTOK

MUX

EIN

+

–

+

SELF TEST

REFERENCE

(REF2)

EIN

EOUT

SIN

+

–

“GOOD”

–

SIN

V

SOUT

DECODER

UV0

SOUT

V

REF

TEMP1

TEMP2

OV0

OV1

UV1

6801 BD

6801p

10

LTC6801

BLOCK DIAGRAM OF ENABLE IN/OUT AND STATUS IN/OUT

EOUT

V

REG

300k

SIN

+

–

V

THE FREQUENCY MATCH

DETECT OUTPUT GOES

HIGH WHEN SIN AND EIN

ARE THE SAME FREQUENCY

300k

REG

FREQUENCY

MATCH

DETECT

300k

SIN

300k

THE SIGNAL IS

HIGH WHEN

ALL READINGS

ARE “GOOD”

SOUT

SOUT IS ACTIVE WHEN

1) EIN IS ACTIVE

2) SIN AND EIN ARE THE SAME FREQUENCY

3) ALL READINGS ARE “GOOD”

SOUT

V

REG

300k

EIN

–

+

THE CLK DETECT

OUTPUT GOES

HIGH WHEN EIN IS

2kHz TO 50kHz

V

REG

CLK

DETECT

300k

EIN

6801 BDa

6801p

11

LTC6801

APPLICATIONS INFORMATION

OVERVIEW

INDEPENDENT OPERATION

The LTC6801 is designed as an easy to implement, low-

cost battery stack monitor that provides a simple indica-

tion of correct battery stack operation without requiring

a microcontroller interface. For battery stack monitoring

with cell voltage read back and discharge circuitry, refer

to the LTC6802 battery stack monitor data sheet.

Figure 3 shows how three groups of 12 cells can be

monitored independently.

REGULATED OUTPUTS

AregulatedvoltageisprovidedattheV pin,biasedfrom

REG

the battery stack. The V

pin can supply up to 4mA at

REG

The LTC6801 contains a 12-bit ADC, a precision voltage

reference, sampled comparator, high voltage multiplexer

and timer/sequencer. During normal operation, the se-

quencer multiplexes the ADC inputs between each of the

channel input pins in turn, performing a single compari-

son to the undervoltage and overvoltage thresholds. The

5V and may be used to power small external circuits. The

regulated output remains at 5V continually, as long as the

total stack voltage is between 10V and 50V.

A low current, precision reference voltage is provided at

the V pin, which can drive loads of greater than 100k.

REF

The V

output is high impedance when the LTC6801

REF

V

inputs are also monitored for an undervoltage at a

TEMP

is idle.

ﬁxed threshold of V /2.

REF

–

Both the V

and V pins must be bypassed to V with

REG

REF

Thepresenceofastatusoutputclockindicatesthesystem

is “OK”. Becase the status output is dynamic, it cannot

get stuck in the “OK” state.

a 1μF capacitor.

CONTROL INPUTS

STACKED OPERATION

The LTC6801 thresholds are controlled by the UV1, UV0,

OV1 and OV0 pins. These pins are designed to be tied

Each LTC6801 monitors a group of up to 12 series con-

nected cells. Groups of cells can be connected in series

or parallel to form a large battery pack. The LTC6801s can

be daisychained with simple capacitive or transformer

coupling. This allows every cell in a large battery pack

to be monitored with a single signal. Figure 2 illustrates

monitoring of 36 series connected cells.

–

directly to V , V or V in order to set the comparison

REG REF

thresholds for all channels simultaneously. The pins are

not designed to be variable. In particular, changes made

to the pins while the chip is not in idle mode may result

in unpredictable behavior. See Tables 1 and 2 for setting

and threshold information.

To cancel systematic duty cycle distortion through the

clock buffers, it is recommended that the clock lines are

cross-coupled (EOUT goes to EIN etc.) as they route up

and down the stack as shown in Figure 2.

6801p

12

LTC6801

APPLICATIONS INFORMATION

ENABLE INPUTS

The maximum delay between when a bad cell voltage

occurs and when it is detected depends on the measure-

ment duty cycle setting. The SOUT clock turns on or off

at the end of each measurement cycle. Figure 4 shows

themaximumdetectiondelayincontinuousmonitormode

In order to support stacked operation, the LTC6801 is

enabled through a differential signal chain encompassing

the EIN/EIN, EOUT/EOUT, and SIN/SIN pins.

The LTC6801 will be enabled if a differential square wave

with a frequency between 2kHz and 50kHz is applied at

EIN/EIN. Otherwise, the LTC6801 will default to a low

power idle mode.

(DC pin tied to V ).

REG

FAULT PROTECTION

Overview

IfthedifferentialsignalatSIN/SINisnotequalinfrequency

tothedifferentialsignaloutputatEOUT/EOUT,theLTC6801

will be enabled but SOUT will be held at 0V and SOUT will

Care should always be taken when using high energy

sources such as batteries. There are countless ways that

systems can be [mis-]conﬁgured during the assembly

and service procedures that can impact a battery’s long

term performance. Table 6 shows various situations to

consider when planning protection circuitry.

be held at V

.

REG

For the simplest operation in a single chip conﬁguration,

EOUTshouldbeconnecteddirectlytoSINandEOUTshould

be connected directly to SIN, and a square wave with a

frequency between 2kHz and 50kHz should be applied

differentially to EIN and EIN. For enable clock frequencies

up to 10kHz, a single-ended square wave with a 5V swing

may be used at EIN while a 1nF capacitor is connected

Battery Interconnection Integrity

Please note: The last condition shown in the FMEA table

couldcausecatastrophicICfailures.Inthiscase,thebattery

string integrity is lost within a cell group monitored by an

LTC6801. This condition could place excessive stress on

certaincellinputsignalclamp-diodesandprobablyleadto

IC failure. If this scenario seems at all likely in a particular

application, Schottky diodes should be added in parallel

with the cells as shown in Figure 5 to form a redundant

load current path and a means of limiting stress on the

IC inputs. The diodes used in this situation need current

ratings sufﬁcient to open a protective fuse in the battery

tap signal (otherwise they would have to carry the normal

range of cell currents).

–

from EIN to V .

STATUS OUTPUT

If the chip is properly enabled (EIN/EIN, SIN/SIN are the

same frequency), all cells are within the undervoltage

and overvoltage thresholds, and the voltage at V

TEMP1

and V

is over one half V , the differential output

TEMP2

REF

at SOUT/SOUT will toggle at the same frequency and in

phase with the signal at EIN/EIN. Otherwise, SOUT will be

low and SOUT will be high.

6801p

13

LTC6801

APPLICATIONS INFORMATION

TOP OF

STACK

TOP OF

STACK

PROGRAMMED CONDITIONS:

CONTINUOUS MONITOR MODE

OV = 4.120V

+

V

OV1

V

OV1

LTC6801

UV = 2.108V

C12

C11

C10

C9

C8

C7

C12

C11

C10

C9

C8

C7

OV0

UV1

UV0

HYST

CC1

OV0

UV1

UV0

HYST

CC1

HYST = 250mV (UV), 100mV (OV)

CC = 12

CC0

SLT

CC0

SLT

C6

C5

C4

SLTOK

DC

C5

C4

SLTOK

DC

C3

C2

C1

EOUT

SIN

C3

C2

C1

EOUT

SIN

–

SIN

V

SIN

V

SOUT

V

SOUT

TEMP1

V

SOUT

V

SOUT

TEMP2

V

EIN

V

EIN

REF

REG

+

V

OV1

V

OV1

LTC6801

C12

C11

C10

C9

C8

C7

C12

C11

C10

C9

C8

C7

OV0

UV1

UV0

HYST

CC1

CC0

OV0

UV1

UV0

HYST

CC1

CC0

C6

SLT

C6

SLT

C5

C4

SLTOK

DC

C5

C4

SLTOK

DC

C3

C2

C1

EOUT

SIN

C3

C2

C1

EOUT

SIN

–

SIN

V

SIN

V

SOUT

V

SOUT

TEMP1

V

SOUT

V

SOUT

TEMP2

V

EIN

V

EIN

REF

REG

+

V

OV1

V

OV1

LTC6801

C12

C11

C10

C9

C8

C7

C12

C11

C10

C9

C8

C7

OV0

UV1

UV0

HYST

CC1

CC0

OV0

UV1

UV0

HYST

CC1

CC0

C6

SLT

C6

SLT

C5

C4

SLTOK

DC

C5

C4

SLTOK

DC

C3

C2

C1

EOUT

SIN

C3

C2

C1

EOUT

SIN

ALL CLOCKS

OUT WHEN ALL

CELLS GOOD

–

SIN

SOUT

V

SIN

SOUT

V

CLOCK OUT

WHEN ALL

CELLS GOOD

TEMP1

V

TEMP2

V

EIN

USER SUPPLIED

CLOCK IN

V

EIN

USER SUPPLIED

CLOCK IN

REF

REG

6801 F02

6801 F03

BOTTOM

OF STACK

BOTTOM

OF STACK

Figure 2. Serial Connection of Status Lines for Multiple 6801s

on the Same PCB (Simpliﬁed Schematic, Not All Components

Shown)

Figure 3. Independent Status Lines for Multiple 6801s on the

Same PCB (Simpliﬁed Schematic, Not All Components Shown)

6801p

14

LTC6801

APPLICATIONS INFORMATION

6801p

15

LTC6801

APPLICATIONS INFORMATION

Table 6. Failure Mechanism Effect Analysis (FMEA)

SCENARIO

EFFECT

DESIGN MITIGATION

+

–

Cell input open-circuit (random)

Power-up sequence at IC inputs

Clamp diodes at each pin to V & V (within IC)

provide alternate PowerPath.

Cell input open-circuit (random)

Differential input voltage overstress

Zener diodes across each cell voltage input pair

(within IC) limit stress.

+

–

Top cell input connection loss (V )

Power will come from highest connected cell

input

Clamp diodes at each pin to V and V (within

IC) provide alternate PowerPath. Error condition

will be indicated by all upstream and downstream

units (no clock on SOUT/ SOUT).

–

+

–

Bottom cell input connection loss (V )

Power will come from lowest connected cell input Clamp diodes at each pin to V and V (within

IC) provide alternate PowerPath. Error condition

will be indicated by all upstream and downstream

units (no clock on SOUT/ SOUT).

+

–

Power input disconnection

(amongst stacked units)

Loss of supply connections

Clamp diodes at each pin to V and V (within

IC) provide alternate PowerPath. Error condition

will be indicated by all upstream and downstream

units (no clock on SOUT/ SOUT).

Status link disconnection

(between stacked units)

Break of “daisy chain” communication

(no stress to ICs)

Daisy chain will be broken and error condition

will be indicated by all upstream and downstream

units (no clock on SOUT/ SOUT).

–

Short between any two conﬁguration inputs

Power supplies connected to pins will be shorted If V or V

is shorted to V , supply will

REF

REG

be removed from internal circuitry and error

condition will be indicated by all upstream and

downstream units (no clock on SOUT/ SOUT). If

V

is shorted to V , a self test error will be

REG

REF

ﬂagged.

Open connection on conﬁguration input

Control input will be pulled towards positive or

negative potential depending on pin

Control input will be pulled to a more stringent

condition (larger number of channels, higher UV

threshold, lower OV threshold, shorter duty cycle,

etc. ensuring either more stringent monitoring or

error condition will be indicated by all upstream

and downstream units (no clock on SOUT/

SOUT).

Cell-pack integrity, break between stacked units

Cell-pack integrity, break within stacked unit

Daisy-chain voltage reversal up to full stack

potential

Full stack potential may appear across status/

enable isolation devices, but will not be seen by

the IC. isolation capacitors should therefore be

rated to withstand the full stack potential.

Cell input reverse overstress

Add parallel schottky diodes across each cell for

current path redundancy. Diode and connections

must handle full operating current of stack, will

limit stress on IC

6801p

16

LTC6801

APPLICATIONS INFORMATION

+

LTC6801

V

PROTECT

AGAINST

BREAKS

HERE

C12

C11

C10

C9

EOUT

SIN

6801 F05

Figure 5. Using Diodes to Form a Redundant

Load Path (One Cell Connection Shown)

SIN

ZCLAMP

SOUT

EIN

Internal Protection Structure

The LTC6801 incorporates a number of protective struc-

tures, including parasitic diodes, Zener-like overvoltage

suppressors, and other internal features that provide

protection against ESD and certain overstress conditions

that could arise in practice. Figure 6 shows a simpliﬁed

internal schematic that indicates the signiﬁcant protective

structures and their connectivity. The various diodes indi-

catetheapproximatecurrentversusvoltagecharacteristics

that are intrinsic to the part, which is useful in analyzing

responses to certain external stresses, such as during a

hot-start scenario.

C8

EIN

V

TEMP1

C7

TEMP2

V

REF

C6

ZCLAMP

V

REG

C5

OV1

OV0

UV1

UV0

HYST

CC1

CC0

SLT

C4

C3

SELF TEST CIRCUITRY

TheLTC6801hasinternalcircuitrythatperformsaperiodic

self test of all measurement functions. The LTC6801 self

test circuitry is intended to prevent undetectable failure

modes. Accuracy and functionality of the voltage refer-

ence and comparator are veriﬁed, as well as functionality

of the high voltage multiplexer and ADC decimation ﬁlter.

Additionally, open connections on the cell input pins C1

to C11 are detected (Open connections on V or C12/V

will cause an undervoltage failure during the normal

measurement cycle).

C2

ZCLAMP

C1

SLTOK

DC

–

V

6801 F06

–

+

Figure 6. Internal Protection Structures

6801p

17

LTC6801

APPLICATIONS INFORMATION

Self Test Pins

The self test guarantees that V

is within 5% of the

REF

speciﬁed nominal value. Also, this test guarantees the

analog portion of the ADC is working.

The SLT pin is used to initiate a self test. It is conﬁgured

as an open collector input/output. The pin should be nor-

mally tied to V

with a resistor greater than or equal to

REG

High Voltage Multiplexer Veriﬁcation

100k or ﬂoated. The pin may be pulled low at any time to

initiate a self test cycle.

The most dangerous failure mode of the high voltage

multiplexer would be a stuck bit condition in the address

decoder. Such a fault would cause some channels to be

measured repeatedly while other channels are skipped.

A skipped channel could mean a bad cell reading is not

detectable. Othermultiplexerfailures,likethesimultaneous

selectionofmultiplechannels, orshortsinthesignalpath,

would result in an undervoltage or overvoltage condition

on at least one of the channels.

The device will automatically initiate a self test if SLT has

notbeenexternallyactivatedfor1024measurementcycles,

and pull down the SLT pin internally to indicate that it is

in self test mode.

The SLTOK pin is a simple logic output. If the previous self

test failed the output is held low, otherwise the output will

be high. The SLTOK pin is high upon power-up. The SLTOK

output can be connected to a microcontroller through an

isolation path.

The LTC6801 incorporates circuitry to ensure that

all requested channels are measured during each

measurement cycle and none are skipped. If a channel is

skipped, an error is ﬂagged during the self test cycle.

The LTC6801 status output will remain active while the

SLTOK pin is low. The LTC6801 will continue to monitor

cells if the self test fails. If the next self test passes, the

SLTOK output returns high.

ADC Decimation Filter Veriﬁcation

The ADC decimation ﬁlter test veriﬁes that the digital cir-

cuits in the ADC are working, i.e. there are no stuck bits

in the ADC output register. During each self test cycle,

the LTC6801 feeds two test waveforms into the ADC. The

internallygeneratedwaveformsweredesignedtogenerate

complementary zebra patterns (alternating 0’s and 1’s) at

the ADC output. If either of the waveforms generates an

incorrect output value, an error is ﬂagged during the self

test cycle.

Reference and Comparator Veriﬁcation

A secondary internal bandgap voltage reference (REF2)

is included in the LTC6801 to aid in veriﬁcation of the

reference and comparator. During the self test cycle, the

comparator and main reference are used to measure the

REF2 voltage.

To verify the comparator functionality, the upper and

lower thresholds are ﬁrst set in a close window around

the expected REF2 voltage and the comparator output is

veriﬁed. Then the upper threshold is set below the REF2

voltageandthecomparatoroutputisveriﬁedagain.Lastly,

the lower threshold is set above the REF2 voltage and the

comparator output is veriﬁed a third time.

Open Cell Connection Detection

The open connection detection algorithm ensures that an

open circuit is not misinterpreted as a valid cell reading.

6801p

18

LTC6801

APPLICATIONS INFORMATION

self test, this current will cause the cell input to settle to

a voltage low enough to trigger an undervoltage condition

during the normal measurement cycle.

In the absence of external noise ﬁltering, the input resis-

tance of the ADC will cause open wires to produce a near

zero reading. This reading will cause an undervoltage

failure during the normal measurement cycle.

Note, an open cell connection may not be detected when

the UV = 0.766V setting is used. For all other UV settings,

an open cell connection will result in either a self test error

or no SOUT clock.

Some applications may include external noise ﬁltering to

improve the quality of the voltage comparisons. When

an RC network is used to ﬁlter noise, an open wire may

not produce a zero reading because the comparator input

resistance is too large to discharge the capacitors on the

input pin. Charge may build up on the open pin during

successive measurement cycles to the extent that it could

indicate a valid cell voltage reading.

Using The LTC6801 with Other Battery Monitors

WhenusedincombinationwithanLTC6802-1,itispossible

tochecktheLTC6801selftestresultviatheLTC6802-1and

its isolated SPI. As shown in Figure 7, the SLTOK output

is tied to the GPIO2 pin on the LTC6802-1. SLTOK will

remain high as long as it is passing the self test. A self test

will occur automatically every 1024 measurement cycles

(17 seconds to 9 minutes, depending on measurement

duty cycle). A self test can be initiated by a falling edge

on SLT, via the LTC6802-1 GPIO1 line. A self test will start

after the current measurement cycle is complete, and the

SLTOK status will be valid when the self test completes.

The worst case delay before SLTOK is valid in continuous

monitormodeisapproximately15msforthecurrentcycle

to complete plus 17ms for the self test to complete.

During each self test cycle, the LTC6801 will sink 100μA

–

to V from each side of the cell being measured. The

undervoltage threshold is not checked during the self test

because the 100μA pull-down current would cause false

failures in some cases. If an input is open, this current will

discharge any ﬁltering capacitors and cause the input to

ﬂoat down to approximately 0.7V below the next lower cell

input. In most cases, the cell voltage of the cell above the

open input will exceed the overvoltage threshold and ﬂag

a self test error. During the normal measurement cycle,

–

the LTC6801 will sink 1μA to V from each side of the cell

being measured. If the cell voltages are low enough that

an open wire is not detected as an overvoltage during

The6802-1canmeasuretheLTC6801reference,whichwill

independently test the analog circuitry of the LTC6802.

CSBO

SDOI

SCKO

CSBI

SDO

SDI

+

V

SCKI

+

V

OV1

OV0

UV1

UV0

HYST

CC1

CC0

SLT

SLTOK

DC

C12

S12

C11

S11

C10

S10

C9

V

C12

C11

C10

C9

MODE

IN

CMPD6263

C12

C11

C10

C9

C8

C7

C6

C5

C4

C12

C11

C10

C9

C8

C7

C6

C5

C4

GPIO2

GPIO1

WDTB

MMB

TOS

OUT

1M

LTC6802-1

LTC6801

V

REG

S9

V

REF

1μF

C8

V

C8

TEMP2

TEMP1

NC

S8

C3

C2

C1

C3

C2

C1

EOUT

SIN

C7

–

V

S7

C6

S1

C1

S2

C2

S3

C3

C6

–

V

SIN

S6

SOUT

EIN

6801 F07

TEMP1

TEMP2

REF

C5

S5

V

REF

C4

S4

REG

1μF

C3

C2

C1

Figure 7. Interconnection of an LTC6802-1 and LTC6801 for Self Test.

6801p

19

LTC6801

APPLICATIONS INFORMATION

CELL-VOLTAGE FILTERING

tying both CC1 and CC0 to the V

pin, the highest cell

REF

+

potential (in this case C8) must be connected to the V

pin for proper operation. Unused cell connection pins (in

this case C9 to C12) may be left ﬂoating or may also be

tied to the highest cell potential.

The LTC6801 employs a sampling system to perform its

analog-to-digital conversions and provides a conversion

resultthatisessentiallyanaverageoverthe0.5msconver-

sionwindow.Ifthereissigniﬁcantnoiseatfrequenciesnear

500kHztheremaybealiasinginthedelta-sigmamodulator.

A lowpass ﬁlter with 30dB attenuation at 500kHz may be

beneﬁcial. Since the delta-sigma integration bandwidth is

about 1kHz, the ﬁlter corner need not be lower than this

to assure accurate conversions.

+

V

OV1

OV0

C12

C11

C10

C9

UV1

UV0

HYST

CC1

CC0

SLT

SLTOK

DC

C8

LTC6801

C7

C6

C5

Series resistors of 1k may be inserted in the input paths

without introducing measurement error. Shunt capacitors

C4

C3

EOUT

SIN

1μF

500k

NTC

B = 4567

500k

C2

–

NTC

C1

may be added from the cell inputs to V , creating RC ﬁlter-

–

B = 4567

V

SIN

1μF

SOUT

EIN

ing as shown in Figure 8. The combination of 1k and 10nF

is recommended as a robust, cost effective noise ﬁlter.

TEMP1

TEMP2

REF

EIN

100k

REG

6801 F09

MEASURING VARIOUS CELL COUNTS

Figure 9. Driving Thermistors Directly from V_REF

.

The LTC6801 is designed to measure up to 12 cells de-

pending on the state of the CC pins (See Table 5). When

using an LTC6801 conﬁgured for measuring less than

12 cells, for instance choosing to measure 8 cells by

Two Independent Probes With a +60°C Trip Point

+

V

OV1

OV0

UV1

UV0

HYST

CC1

CC0

SLT

C12

C11

C10

C9

C8

LTC6801

1k

C7

C3

C6

C5

SLTOK

DC

C4

C3

EOUT

SIN

1k

10nF

0.5μF

C2

C1

10k

NTC

B = 3380

10k

C2

NTC

C1

–

B = 3380

0.5μF

V

SIN

V

SOUT

EIN

TEMP1

V

TEMP2

REF

EIN

2.2k

REG

6801 F10

10nF

–

+

–

V

6801 F08

LT6003

Figure 8. Adding RC Filtering to the Cell inputs

Figure 10. Buffering V_REFfor Higher-Current Sensors.

Two Independent Probes With a +70°C Trip Point

6801p

20

LTC6801

APPLICATIONS INFORMATION

READING EXTERNAL TEMPERATURE PROBES

The LTC6801 includes two channels of ADC input, V

+

V

OV1

OV0

UV1

UV0

HYST

CC1

CC0

SLT

SLTOK

DC

C12

C11

C10

C9

TEMP1

and V

, that are intended to monitor thermistors

TEMP2

C8

(tempco about –4%/°C generally) or diodes (–2.2mV/°C

typical) located within the cell array. Sensors can be

LTC6801

C7

C6

C5

C4

powered directly from V

30μA typical).

as shown in Figure 9 (up to

REF

C3

EOUT

SIN

500k

NTC

1μF

C2

1150k

C1

–

B = 4567

1μF

V

SIN

Thetemperaturemeasurementinputs(V

,V

)of

TEMP1 TEMP2

V

SOUT

EIN

TEMP1

TEMP2

REF

the LTC6801 are comparator input channels with a voltage

100k

NTC

B = 4250

EIN

6801 F11

100k

REG

threshold of one-half V . Input voltages above half V

REF

are considered good. Voltages below the one-half V

threshold are considered a fault condition. The inputs

may be used in combination with resistors, thermistors,

or diodes to sense both an upper and lower temperature

limit. Figure 9, Figure 10 and Figure 11 illustrate some

Figure 11. Sensing Both Upper and Lower Temperature

Thresholds. This Example Monitors a –20°C to +60°C Window

Detector. The Thermistors Should Be in Close Proximity

For circuits that include ﬁltering capacitance, note that

possibilities.ToignoretheseinputssimplyconnectV

TEMP1

–

only the fastest DC setting (V

connection) will keep

and V

to V . A ﬁltering capacitor to V is recom-

mendedtominimizetheerrorcausedbytheapproximately

REG

TEMP2

REF

V

steady and allow the V

voltages to settle. To use

REF

TEMP

the lower power DC settings, V must be buffered (see

700k input impedance of the ADC.

Figure 10), so that a low impedance is presented to the

For sensors that require higher drive currents, a buffer

ampliﬁer may be used as shown in Figure 10. Power for

ADC, with a time constant of no more than about 1ms.

the sensor is actually sourced indirectly from the V

REG

ADVANTAGES OF DELTA-SIGMA ADCs

in this case. Probe loads up to about 1mA maximum are

supported in this conﬁguration. Since V is shut down

REF

The LTC6801 employs a delta-sigma analog to digital

converter for voltage measurement. The architecture of

delta-sigma converters can vary considerably, but the

common characteristic is that the input is sampled many

times over the course of a conversion and then ﬁltered or

averaged to produce the digital output code.

while the LTC6801 is idle between measurement cycles,

the thermistor drive is also shut off and thus power dis-

sipation is minimized. Since V

remains always-on, the

REG

buffer op amp (LT6003 shown) is selected for its ultralow

current consumption (10μA).

6801p

21

LTC6801

APPLICATIONS INFORMATION

For a given sample rate, a delta-sigma converter can

achieve excellent noise rejection while settling completely

in a single conversion. This is particularly important for

noisyautomotivesystems.Otheradvantagesofdelta-sigma

converters are that they are inherently monotonic, mean-

ing they have no missing codes, and they have excellent

DC speciﬁcations.

USING TRANSFORMERS FOR GALVANIC ISOLATION

As shown in Figure 12, small gate-drive signal transform-

ers can be used to interconnect devices and transport the

enableandsensesignalssafelyacrossanisolationbarrier.

Drivingatransformerwithasquarewaverequirestransient

currentsofseveralmAandfrequencyofoperationat20kHz

or higher. Since the output pins of the LTC6801 are current

limitedat<1mA, asmallexternalgatepair(NC7WZ17dual

buffer) is used to provide the needed drive current. 330Ω

resistors are placed in series with each buffer output to

optimize current ﬂow into the transformer primary and a

coupling capacitor provides prevention of current ﬂow in

static conditions. The secondary side is wired in a cen-

ter-tapped conﬁguration to terminate the common mode

voltage and thus suppress noise pickup. The differential

signalisterminatedinto1500Ωtooptimizethepeaksignal

The LTC6801’s ADC has a second order delta-sigma

modulator followed by a SINC2, ﬁnite impulse response

(FIR) digital ﬁlter, with a lowpass bandwidth of 1kHz. The

front-end sample rate is 512ksps, which greatly reduces

input ﬁltering requirements. A simple 16kHz, 1 pole ﬁlter

composed of a 1k resistor and a 10nF capacitor at each

input will provide adequate ﬁltering for most applications.

ThesecomponentvalueswillnotdegradetheDCaccuracy

of the ADC.

swing for the IC input (to about 4V ). Internal biasing

P-P

Each conversion consists of two phases – an autozero

phase and a measurement phase. The ADC is autozeroed

at each conversion, greatly improving CMRR.

features of the IC inputs maintain an optimal DC common

mode level at the transformer secondary.

6801p

22

LTC6801

APPLICATIONS INFORMATION

TO NEXT

CIRCUIT

NC7WZ17

100nF

+

–

100k

ENC2

+

V

OV1

OV0

UV1

UV0

HYST

CC1

+

V

GND

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

LTC6801

ENC2

10nF

•

+

CC0

S2

SLT

•

1.5k

SLTOK

DC

–

S2

EOUT

SIN

P0544NL

NC7WZ17

100nF

100Ω

–

V

SIN

SOUT

EIN

TEMP1

TEMP2

REF

+

V

GND

1μF

EIN

REG

•

1.5k

10nF

P0544NL

+

V

OV1

NC7WZ17

100nF

C12

C11

C10

C9

OV0

UV1

UV0

HYST

CC1

LTC6801

+

100Ω

ENC1

+

V

GND

–

ENC1

C8

10nF

C7

CC0

C6

SLT

C5

SLTOK

DC

•

+

S1

C4

•

C3

EOUT

SIN

1.5k

–

S1

C2

C1

–

V

SIN

P0544NL

+

–

SOUT

EIN

S_HOST

TEMP1

TEMP2

REF

1μF

+

EN_HOST

–

EIN

REG

6801 F12

Figure 12. Using Transformers for Galvanic Isolation

6801p

23

LTC6801

APPLICATIONS INFORMATION

INTERCOMMUNICATION USING DATA ISOLATORS

DEMO BOARD CIRCUIT

As shown in Figure 13, an inexpensive and compact

2-channeldataisolatorisusedtocommunicatetheenable

andthesenseclockingsignalsbetweendevices.Thewiring

carries isolator power and return plus two single-ended

logicsignalsthatarecompletelyisolatedattheupperdevice

interface, so the signals are effectively differential from a

common mode ingress perspective. The isolator provides

excellent rejection of noise between battery groups, but

consumes a few mA when operating, so a conventional

opto-coupler and a few discretes provide a power-down

scheme for periods where no monitoring is needed. Since

An LTC6801 demonstration circuit is shown in Figure 14.

The circuit includes a 10kHz oscillator (U2) for the enable

excitation and an LED (D15, driven by Q1) to indicate the

stateofthestatusoutputs,plusanassortmentofimportant

protection components to ensure robust operation and

hot-plugging of cell connections.

Seriesresistors(R14toR21)provideacontrolledcoupling

capacitor (C14 to C17) current in the inter-IC connections

during startup or other abrupt potential changes, and as-

sociated clamp diodes (D13 and D14 quad array devices)

redirect charge/surge current around the IC.

therequiredcurrentwouldloaddownV

ifuseddirectly,

REG

Input ﬁlters to each cell (R1, C1 to R12, C12) also use

6.2V Zener diodes (D1 to D12) to prevent overstress to

the internal ESD clamps.

the NPN transistor is used to form a quasi-regulated 4.3V

supply drawing from the full battery group potential, also

moving signiﬁcant thermal loading outside the IC. The

PMOS FET is a low resistance switch controlled by the

opto-coupler output. Since the opto-coupler is used to

switch only a small current, the LED need only be driven

with~500μA.Poweringdownthebottom-of-stackisolator

on the host μP side automatically powers down the entire

isolator chain.

+

The V input ﬁlter (R13, C13) has the same time constant

+

as the ADC input ﬁlters so that the V and C12 pins tend

to track during start-up or transients, minimizing stress

and ADC error.

6801p

24

LTC6801

APPLICATIONS INFORMATION

+

V

OV1

OV0

UV1

UV0

HYST

CC1

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

LTC6801

CC0

TO NEXT

CIRCUIT

SLT

SLTOK

DC

COM2

100Ω

1μF

ENABLE2

SENSE2

VISO2

EOUT

SIN

1nF

–

Si8421

V

SIN

1μF

100Ω

V

SOUT

EIN

V

DD2

TEMP1

DD1

1μF

V

TEMP2

REF

A1

B1

B2

EIN

REG

A2

GND1

GND2

1nF

6.8k

SI2351DS

CZT5551

33k

MOC207-M

+

V

OV1

C12

C11

C10

C9

OV0

UV1

UV0

HYST

CC1

LTC6801

C8

C7

CC0

C6

SLT

C5

SLTOK

DC

COM1

C4

100Ω

1μF

ENABLE1

SENSE1

VISO1

C3

EOUT

SIN

C2

C1

1nF

–

Si8421

V

SIN

1μF

100Ω

V

SOUT

EIN

V

CCHOST

TEMP1

DD1

DD2

1μF

V

TEMP2

REF

SENSEHOST

A1

B1

ENABLEHOST

COMHOST

EIN

REG

A2

GND1

B2

GND2

1nF

6.8k

SI2351DS

CZT5551

33k

MOC207-M

6801 F13

Figure 13. IC to IC Communication Using Data Isolators

6801p

25

LTC6801

APPLICATIONS INFORMATION

1

3

2

6801p

26

LTC6801

PACKAGE DESCRIPTION

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

12.50 – 13.10*

(.492 – .516)

1.25 p 0.12

36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19

7.8 – 8.2

5.3 – 5.7

7.40 – 8.20

(.291 – .323)

0.42 p 0.03

0.65 BSC

5

7

8

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

6

9 10 11 12 13 14 15 16 17 18

2.0

(.079)

MAX

5.00 – 5.60**

(.197 – .221)

0o – 8o

0.65

(.0256)

BSC

0.09 – 0.25

(.0035 – .010)

0.55 – 0.95

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

TYP

(.002)

NOTE:

MIN

1. CONTROLLING DIMENSION: MILLIMETERS

G36 SSOP 0204

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

6801p

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC6801

TYPICAL APPLICATION

5V

FILTERED STATUS

V

REG

(LOW = OK)

1.5k

10k

LED_GREEN

CMHD457

SOUT

2N7002

1M

10nF

6801 F15

Figure 15. Alarm Qualiﬁcation Filter/Status Indicator

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC6802-1

Multi-Cell Battery Stack Monitor with a Stackable

Serial Interface

Complete Battery Monitoring IC with 0.25% Cell Measurement Accuracy.

Level-Shifting Serial Interface Allows Multiple LTC6802-1 Devices to be Daisy-

Chained without Opto-Couplers or Isolators

LTC6802-2

Multi-Cell Battery Stack Monitor with an Individually Functionally Equivalent to LTC6802-1: Parallel Connection Between

Addressable Serial Interface Microcontroller and Multiple LTC6802-2 Devices

6801p

LT 1209 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC6801
厂家：	Linear
描述：	Independent Multicell Battery Stack Fault Monitor 独立的多节电池组故障监视器电池监视器
文件：	总28页 (文件大小：258K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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