LTC6802IG-1-PBF [Linear]
Multicell Battery Stack Monitor; 多节电池组监视器型号: | LTC6802IG-1-PBF |
厂家: | Linear |
描述: | Multicell Battery Stack Monitor |
文件: | 总32页 (文件大小:262K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Electrical Specifications Subject to Change
LTC6802-1
Multicell
Battery Stack Monitor
FEATURES
DESCRIPTION
The LTC®6802-1 is a complete battery monitoring IC that
includes a 12-bit ADC, a precision voltage reference, a
high voltage input multiplexer and a serial interface. Each
LTC6802-1canmeasureupto12seriesconnectedbattery
cellswithaninputcommonmodevoltageupto60V. Using
auniquelevel-shiftingserialinterface,multipleLTC6802-1
devices can be connected in series, without optocouplers
or isolators, allowing for monitoring of every cell in a long
string of series-connected batteries.
n
Measures up to 12 Li-Ion Cells in Series (60V Max)
n
Stackable Architecture Enables >1000V Systems
n
0.25% Maximum Total Measurement Error
n
13ms to Measure All Cells in a System
n
Cell Balancing:
On-Chip Passive Cell Balancing Switches
Provision for Off-Chip Passive Balancing
n
Two Thermistor Inputs Plus On-board
Temperature Sensor
n
1MHz Serial Interface with Packet Error Checking
When multiple LTC6802-1 devices are connected in series
theycanoperatesimultaneously,permittingallcellvoltages
in the stack to be measured within 13ms.
n
High EMI Immunity
n
Delta Sigma Converter With Built In Noise Filter
n
Open Wire Connection Fault Detection
Low Power Modes
44-Lead SSOP Package
n
To minimize power, the LTC6802-1 offers a measure mode
to monitor each cell for overvoltage and undervoltage
conditions. A standby mode is also provided.
n
Each cell input has an associated MOSFET switch for
discharging overcharged cells.
APPLICATIONS
n
Electric and Hybrid Electric Vehicles
The related LTC6802-2 offers an individually addressable
serial interface.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
n
High Power Portable Equipment
n
Backup Battery Systems
n
High Voltage Data Acquisition Systems
TYPICAL APPLICATION
Typical Application
Measurement Error Over
Extended Temperature
NEXT 12-CELL
SERIAL DATA
0.30
PACK ABOVE
LTC6802-1
V+
TO LTC6802-1
0.25
0.20
ABOVE
DIE TEMP
0.15
REGISTERS
AND
CONTROL
0.10
0.05
0
12-CELL
BATTERY
STRING
MUX
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
12-BIT
Δ∑ ADC
10ppm VOLTAGE
REFERENCE
–50 –25
0
25
50
75 100 125
V–
SERIAL DATA
TO LTC6802-1
BELOW
EXTERNAL
TEMP
TEMPERATURE (°C)
NEXT 12-CELL
PACK BELOW
68021 TA01a
100k
100k NTC
68021p
1
LTC6802-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
+
–
Total Supply Voltage (V to V ).................................60V
1
2
CSBI
SDO
SDI
SCKI
V
44
43
42
41
40
39
38
37
36
25
34
33
32
31
30
29
28
27
26
25
24
23
CSBO
SDOI
SCKO
–
Input Voltage (Relative to V )
C1............................................................ –0.7V to 9V
3
+
+
C12..........................................V – 0.7V to V + 0.7V
Sn pins ............................... Cn-1 – 0.7V to Cn-1 + 9V
+
4
V
5
C12
S12
C11
S11
C10
S10
C9
MODE
+
+
CSBO, SCKO, SDOI..................V – 1.4V to V + 0.7V
All other pins ........................................... –0.7V to 7V
Voltage Between Inputs
6
GPIO2
GPIO1
WDTB
MMB
TOS
7
8
Cn to Cn-1 ............................................... –0.7V to 9V
Input Current
All Pins ............................................................ 10mA
Operating Temperature Range..................–40°C to 85°C
Specified Temperature Range ..................–40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range...................–65°C to 150°C
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
REG
V
S9
REF
V
C8
TEMP2
V
S8
TEMP1
NC
C7
–
V
S7
S1
C1
S2
C2
S3
C3
C6
*n = 2 to 11
S6
C5
S5
C4
S4
G PACKAGE
44-LEAD PLASTIC SSOP
= 150°C, θ = 70°C/W
T
JMAX
JA
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6802IG-1#PBF
LTC6802IG-1#TRPBF
LTC6802IG-1
44-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
68021p
2
LTC6802-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted.
SYMBOL PARAMETER
DC Specifications
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
ACC
Measurement Resolution
ADC Offset Voltage
ADC Gain Error
Quantization of the ADC
(Note 2)
1.5
mV/Bit
mV
–0.5
0.5
(Note 2)
–0.12
–0.22
0.12
0.22
%
%
l
V
Total Measurement Error
(Note 4)
ERR
V
CELL
V
CELL
V
CELL
V
CELL
V
CELL
V
CELL
V
CELL
V
CELL
= 0V
0.75
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
= 2.3V
= 2.3V
= 3.6V
= 3.6V
= 4.2V
= 4.2V
= 4.6V
= 2.3V
= 3.6V
= 4.2V
–2.76
–5.06
–4.32
–7.92
–5.04
–9.24
2.76
5.06
4.32
7.92
5.04
9.24
l
l
l
8
V
–2.76
–4.32
–5.04
2.76
4.32
5.04
TEMP
V
TEMP
V
TEMP
V
V
Cell Voltage Range
Full Scale Voltage Range
5.175
V
CELL
+
l
l
l
Common Mode Voltage Range Measured
Range of Inputs C4 thru C11
Range of Input C3
Range of Inputs C1, C2
3.7
1.8
0
V
V
V
V
CM
–
Relative to V
15
10
l
l
l
Overvoltage (OV) Detection Level
Undervoltage (UV) Detection Level
Die Temperature Measurement Error
Reference Pin Voltage
Programmed for 4.2V
Programmed for 2.3V
4.182
2.290
4.200
2.300
4.218
2.310
10
V
V
Error in Measurement at 125°C
°C
–
V
R
LOAD
= 100k to V
3.040
3.035
3.072
3.072
3.105
3.110
V
V
REF
l
Reference Voltage Temperature Coefficient
Reference Voltage Thermal Hysteresis
Reference Voltage Long Term Drift
Regulator Pin Voltage
5
ppm/°C
ppm
25°C to 85°C and 25°C to –40°C
100
60
ppm/√khr
+
l
l
V
V
10 < V < 50, No Load
4.5
4.1
5.0
5.0
5.5
V
V
REG
I
= 4mA
LOAD
l
Regulator Pin Short Circuit Current Limit
5
mA
+
–
l
l
Supply Voltage, V Relative to V
V
Specifications Met
10
4
50
50
V
V
S
ERR
Timing Specifications Met
I
Input Bias Current
In/Out of Pins C1 Thru C12
When Measuring Cells
B
–10
10
μA
pA
When Not Measuring Cells
100
1
+
I
I
Supply Current, Active
Current Into the V Pin when Measuring Voltages
1.1
1.2
mA
mA
S
l
with the ADC
+
Supply Current, Monitor Mode
Average Current Into the V Pin While Monitoring
M
for UV and OV Conditions
Continuous Monitoring
Monitor Every 130ms
Monitor Every 500ms
Monitor Every 2s
950
300
175
130
μA
μA
μA
μA
+
I
I
Supply Current, Idle
Current into the V Pin When Idle
50
55
60
μA
μA
QS
l
l
All Serial Port Pins at Logic ‘1’
+
Supply Current, Serial I/O
Current into the V Pin During Serial
3.1
3.0
3.6
4.3
4.5
mA
mA
CS
Communications. All Serial Port Pins at Logic ‘0’
V
MODE
= 0, This Current is Added to I or I
S QS
68021p
3
LTC6802-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted.
SYMBOL PARAMETER
Discharge Switch On-Resistance
CONDITIONS
> 3V (Note 3)
MIN
TYP
MAX
20
UNITS
Ω
l
l
V
10
CELL
Temperature Range
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Voltage Mode Timing Specifications
–40
85
°C
145
5
°C
°C
l
l
t
Measurement Cycle Time
Time Required to Measure 11 or 12 Cells
Time Required to Measure Up to 10 Cells
Time Required to Measure 1 Cell
13
11
ms
ms
ms
CYCLE
2
l
l
l
l
l
l
l
l
l
l
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
SDI Valid to SCKI Rising Setup
SDI Valid to SCKI Rising Hold
SCKI Low
10
ns
ns
200
400
400
400
100
100
ns
SCKI High
ns
CSBI Pulse Width
ns
SCKI Rising to CSBI Rising
CSBI Falling to SCKI Rising
SCKI Falling to SDO Valid
Clock Frequency
ns
ns
200
1
ns
MHz
s
Watchdog Timer Time Out Period
1
2
Timing Specifications
l
l
l
l
t
t
t
t
CSBI to CSBO
C
C
C
C
= 150pF
= 150pF
= 150pF
600
300
300
300
ns
ns
ns
ns
PD1
PD2
PD3
PD4
CSBO
SCKO
SDOI
SCKI to SCKO
SDI to SDOI Write Delay
SDOI to SDO Read Delay
= 150pF
SDO
Voltage Mode Digital I/O Specifications
l
l
l
V
V
V
Digital Input Voltage High
Digital Input Voltage Low
Digital Output Voltage Low
Pins V
Pins V
, SCKI, SDI, and CSBI
, SCKI, SDI, and CSBI
2
V
V
V
IH
IL
MODE
0.8
0.3
MODE
Pin SDO; Sinking 500μA
OL
Current Mode Digital I/O Specifications
l
l
l
l
l
l
l
l
I
I
I
I
I
I
I
I
Digital Input Current High
Digital Input Current Low
Digital Input Current High
Digital Input Current Low
Digital Output Current High
Digital Output Current Low
Digital Output Current High
Digital Output Current Low
Pins CSBI, SCKI, and SDI (Write)
Pins CSBI, SCKI, and SDI (Write)
Pin SDOI (Read)
3
5
μA
μA
μA
μA
μA
μA
μA
μA
IH1
IL1
1000
1200
1500
–1500 –1200 –1000
IH2
IL2
Pin SDOI (Read)
–5
–3
3
Pins CSBO, SCKO, and SDOI (Write)
Pins CSBO, SCKO, and SDOI (Write)
Pin SDI (Read)
5
OH1
OL1
OH2
OL2
1000
1200
1500
–1500 –1200 –1000
–5 –3
Pin SDI (Read)
0
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3. Due to the contact resistance of the production tester, this
specification is tested to relaxed limits. The 20Ω limit is guaranteed by
design.
Note 4. V
refers to the voltage applied across the following pin
CELL
+
–
Note 2. The ADC specifications are guaranteed by the Total Measurement
combinations: V to C11, Cn to Cn-1 for n = 2 to 11, C1 to V . V
to the voltage applied from V
refers
TEMP
–
Error (V ) specification.
or V
to V
ERR
TEMP1
TEMP2
68021p
4
LTC6802-1
PIN FUNCTIONS
–
–
CSBO (Pin 1): Chip Select Output (Active Low). CSBO is
a buffered version of the chip select input, CSBI. CSBO
drives the next IC in the daisy chain. See Serial Port in the
Applications Information section.
V (Pin 29): Connect V to the most negative potential in
the series of cells.
–
NC (Pin 30): Pin 30 is internally connected to V through
10Ω. Pin 30 can be left unconnected or connected to pin
29 on the PCB.
SDOI (Pin 2): Serial Data I/O Pin. SDOI transfers data to
and from the next IC in the daisy chain. See Serial Port in
the Applications Information section.
V
,V
(Pins31,32):TemperatureSensorInputs.
TEMP1 TEMP2
The ADC measures the voltage on V
with respect to
TEMPx
–
SCKO (Pin 3): Serial Clock Output. SCKO is a buffered ver-
sion of SCKI. SCKO drives the next IC in the daisy chain.
See Serial Port in the Applications Information section.
V and stores the result in the TMP registers. The ADC
measurementsarerelativetotheV pinvoltage.Therefore
REF
a simple thermistor and resistor combination connected
to the V pin can be used to monitor temperature. The
+
REF
V (Pin 4): Tie pin 4 to the most positive potential in the
V
TEMP
inputs can also be general purpose ADC inputs.
+
battery stack. Typically V is the same potential as C12.
–
Any voltage from 0V to 5.125V referenced to V can be
C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins
5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27): C1 through
C12 are the inputs for monitoring battery cell voltages.
Up to 12 cells can be monitored. The lowest potential is
measured.
V
REF
(Pin 33): 3.075V Voltage Reference Output. This pin
should be bypassed with a 1μF capacitor. The V pin can
REF
–
drive a 100k resistive load connected to V . Larger loads
–
tied to pin V . The next lowest potential is tied to C1 and
should be buffered with an LT6003 op amp, or similar
device.
so forth. See the figures in the Applications Information
section for more details on connecting batteries to the
LTC6802-1.
V
REG
(Pin 34): Linear Voltage Regulator Output. This pin
should be bypassed with a 1μF capacitor. The V
pin is
REG
The LTC6802-1 can monitor a series connection of up to
12cells. TheLTC6802-1cannotmonitorparallelcombina-
tions of series cells. For example, 3 parallel groups of 4
series cells are not allowed.
capable of supplying up to 4mA to an external load. The
pin does not sink current.
V
REG
TOS (Pin 35): Top of Stack Input. Tie TOS to V
when
REG
the LTC6802-1 is the top device in a daisy chain. Tie TOS
S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins
6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28): S1 though
S12 pins are used to balance battery cells. If one cell in a
series becomes over charged, an S output can be used to
dischargethecell.EachSoutputhasaninternalN-channel
MOSFETfordischarging.SeetheBlockDiagram.TheNMOS
has a maximum on resistance of 20Ω. An external resistor
should be connected in series with the NMOS to dissipate
heat outside of the LTC6802-1 package. When using the
internal MOSFETs to discharge cells, the die temperature
should be monitored. See Power Dissipation and Thermal
Shutdown in the Applications Information section.
–
to V when the LTC6802-1 is any other device in a daisy
chain. When TOS is tied to V , the LTC6802-1 ignores
REG
–
the SDOI input. When TOS is tied to V , the LTC6802-1
expects data to be passed to and from the SDOI pin.
MMB (Pin 36): Monitor Mode (Active Low) Input. When
MMB is low (same potential as V ), the LTC6802-1 goes
into monitor mode. See Modes of Operation in the Ap-
plications Information section.
–
WDTB (Pin 37): Watchdog Timer Output (Active Low).
If there is no activity on the SCKI pin for 2 seconds, the
WDTB output is asserted. The WDTB pin is an open drain
NMOS output. When asserted it pulls the output down to
TheSpinsalsofeatureaninternal10kpull-upresistor.This
allows the S pins to be used to drive the gates of external
MOSFETs for higher discharge capability.
–
V and resets the configuration register to its default state.
The watchdog timer function can be disabled by setting
WDTEN = 0 in the configuration register. See Watchdog
Timer Circuit in the Applications Information section.
68021p
5
LTC6802-1
PIN FUNCTIONS
GPIO1, GPIO2 (Pins 38, 39): General Purpose Input/Out-
put. The operation of these pins depends on the state of
the MMB pin.
standard TTL logic levels. Connect V
to V
when
MODE
REG
the LTC6802-1 is the bottom device in a daisy chain.
–
When V
is connected to V , the SCKI, SDI, and CSBI
MODE
When MMB is high, the pins behave as traditional GPIOs.
By writing a “0” to a GPIO configuration register bit, the
pinsareconfiguredascurrentinputsandoutputs,andSDO
–
is unused. Connect V
to V when the LTC6802-1 is
MODE
–
open drain output is activated and the pin is pulled to V .
being driven by another LTC6802-1 in a daisy chain.
By writing a logic “1” to the configuration register bit, the
corresponding GPIO pin is high impedance. An external
SCKI (Pin 41): Serial Clock Input. The SCKI pin interfaces
to any logic gate (TTL levels) if V
is tied to V . SCKI
MODE
REG
resistor is needed to pull the pin up to V
.
REG
must be driven by the SCKO pin of another LTC6802-1 if
–
By reading the configuration register locations GPIO1
and GPIO2, the state of the pins can be determined. For
example, if a “0” is written to register bit GPIO1, a “0” is
always read back because the output NMOSFET pulls pin
V
is tied to V . See Serial Port in the Applications
MODE
Information section.
SDI (Pin 42): Serial Data Input. The SDI pin interfaces to
any logic gate (TTL levels) if V
is tied to V . SDI
MODE
REG
–
38 to V . If a “1” is written to register bit GPIO1, the pin
must be driven by the SDOI pin of another LTC6802-1 if
becomes high impedance. Either a “1” or a “0” is read
back, depending on the voltage present at pin 38. The
GPIOs makes it possible to turn on/off circuitry around
the LTC6802-1, or read logic values from a circuit around
the LTC6802-1.
–
V
is tied to V . See Serial Port in the Applications
MODE
Information section.
SDO(Pin43):SerialDataOutput. TheSDOpinisanNMOS
open drain output if V
MODE
Information section.
is tied to V . SDO is not used
MODE
REG
–
if V
is tied to V . See Serial Port in the Applications
When the MMB pin is low, the GPIO pins and the WDTB
pin are treated as inputs that set the number of cells to
be monitored. See Monitor Mode in the Applications
Information section.
CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI
pin interfaces to any logic gate (TTL levels) if V
is tied
MODE
to V . CSBI must be driven by the CSBO pin of another
REG
V
REG
(Pin40):VoltageModeInput.WhenV
istiedto
–
MODE
MODE
LTC6802-1 if V
is tied to V . See Serial Port in the
MODE
V
, theSCKI, SDI, SDO, andCSBIpinsareconfiguredas
Applications Information section.
voltage inputs and outputs. This means these pins accept
68021p
6
LTC6802-1
BLOCK DIAGRAM
4
+
V
5
REGULATOR
34
C12
V
REG
10k
6
S12
WATCHDOG
TIMER
37
WDTB
7
C11
3
2
1
SCKO
SDOI
CSBO
10k
24
S3
12
RESULTS
REGISTER
Δ∑ A/D CONVERTER
MUX
AND
44
43
42
41
CSBI
SDO
SDI
COMMUNICATIONS
25
C2
10k
26
S2
SCKI
27
C1
40
39
38
36
35
REFERENCE
V
MODE
10k
GPIO2
28
S1
CONTROL
GPIO1
MMB
TOS
29
–
V
10Ω
30
EXTERNAL
TEMP
DIE
TEMP
NC
V
V
V
REF
TEMP1
TEMP2
31
32
33
68021 BD
68021p
7
LTC6802-1
TIMING DIAGRAM
Timing Diagram of the Serial Interface
t
t
t
6
4
1
t
t
3
t
7
2
SCKI
SDI
…
D3
D2
D1
D0
D7
D4
D3
t
5
CSBI
t
8
…
D4
D3
D2
D1
D0
D7
D4
D3
SDO
PREVIOUS COMMAND
CURRENT COMMAND
6915 TD
OPERATION
THEORY OF OPERATION
the internal MOSFETs. This is completely controlled by
the host processor. The host processor writes values to a
configuration register inside the LTC6802-1 to control the
switches. The watchdog timer on the LTC6802-1 can be
used to turn off the discharge switches if communication
with the host processor is interrupted.
The LTC6802-1 is a data acquisition IC capable of mea-
suring the voltage of 12 series connected battery cells.
An input multiplexer connects the batteries to a 12-bit
delta-sigma analog to digital converter (ADC). An internal
10ppm voltage reference combined with the ADC give the
LTC6802-1 its outstanding measurement accuracy. The
inherent benefits of the delta-sigma ADC vs other types
of ADCs (e.g. successive approximation) are explained
in Advantages of Delta-Sigma ADCs in the Applications
Information section.
OPEN CONNECTION DETECTION
The open connection detection algorithm assures that an
open circuit is not misinterpreted as a valid cell reading.
In the absence of external noise filtering, the input resis-
tance of the ADC will cause open wires to produce a near
zero reading. Internal current sources can be used to
determine if the wire is truly open. For example, an open
on input C3 will result in a near zero reading for both cells
connected to C3. For illustration these cells are labeled B3
and B4 in Figure 2. If a near zero reading is encountered
for B3 and B4, the MPU can command the LTC6802-1 to
Communication between the LTC6802-1 and a host pro-
cessor is handled by a SPI compatible serial interface. As
shown in Figure 1, the LTC6802-1’s can pass data up and
down a stack of devices using simple diodes for isolation.
This operation is described in Serial Port in the Applica-
tions Information section.
The LTC6802-1 also contains circuitry to balance cell volt-
ages. Internal MOSFETs can be used to discharge cells.
TheseinternalMOSFETscanalsobeusedtocontrolexternal
balancing circuits. Figure 1 illustrates cell balancing by
internal discharge. Figure 4 shows the S pin controlling
an external balancing circuit. It is important to note that
the LTC6802-1 makes no decisions about turning on/off
–
place 100μA current sources from the ADC inputs to V .
If input C3 is open, the new reading will show B3 to be
zero and B4 to be full-scale.
Some applications may include external noise filtering to
improve the quality of the ADC readings. When an RC net-
work is used to filter noise, an open wire may not produce
68021p
8
LTC6802-1
OPERATION
BATTERY
POSITIVE
350V
BATTERIES #25–#84
AND
LTC6802-1 ICs #3–#7
LTC6802-1
IC #8
LTC6802-1
IC #2
CSBO
SDOI
CSBI
SDO
SDI
CSBO
SDOI
SCKO
CSBI
SDO
SDI
SCKO
+
V
SCKI
+
V
SCKI
C12
S12
C11
S11
C10
S10
C9
V
MODE
C12
S12
C11
S11
C10
S10
C9
V
MODE
GPIO2
GPIO1
WDTB
MMB
TOS
GPIO2
GPIO1
WDTB
MMB
TOS
V
REG
V
S9
V
REF
REG
S9
C8
S8
C7
S7
C6
S6
C5
V
C8
S8
C7
S7
C6
S6
C5
S5
V
V
REF
TEMP2
V
TEMP2
TEMP1
NC
V
TEMP1
NC
−
V
−
V
S1
C1
S2
C2
S3
C3
S1
C1
S2
C2
S3
C3
S5
C4
S4
C4
S4
3V
–
–
V2
V1
LTC6802-1
IC #1
OE2
OE1
MPU
MODULE
IO
CSBO
SDOI
SCKO
CSBI
SDO
SDI
CS
MISO
MOSI
CLK
+
V
SCKI
+
–
C12
S12
C11
S11
C10
S10
C9
V
V2
V1
MODE
–
+
3V
GPIO2
GPIO1
WDTB
MMB
TOS
V2
V1
DIGITAL
ISOLATOR
V
REG
S9
V
REF
C8
S8
C7
S7
V
V
TEMP2
TEMP1
NC
−
V
C6
S6
C5
S5
C4
S4
S1
C1
S2
C2
S3
C3
68021 F01
Figure 1. 96-Cell Battery Stack, Daisy Chain Interface. This Application Schematic illustrates the Simplest Possible System
68021p
9
LTC6802-1
OPERATION
LTC6802-1
DISCHARGING DURING CELL MEASUREMENTS
The primary cell voltage A/D measurement commands
(STCVAD and STOWAD) automatically turn off a cell’s
discharge switch while its voltage is being measured. The
dischargeswitchesforthecellaboveandthecellbelowwill
also be turned off during the measurement. For example,
discharge switches S4, S5, and S6 will be disabled while
cell 5 is being measured.
C4
B4
C3
B3
MUX
C2
C1
V–
100μA
In some systems it may be desirable to allow discharging
to continue during cell voltage measurements. The cell
voltageA/DconversioncommandsSTCVDCandSTOWDC
allow any enabled discharge switches to remain on during
cellvoltagemeasurements.Thisfeatureallowsthesystem
to perform a self-test to verify the discharge functionality
and multiplexer operation.
68021 F02
Figure 2. Open Connection
a zero reading because the ADC input resistance is too
large to discharge the capacitors on the input pin.
When using the STCVDC for all cells (command 0x60),
for each cell (CN) that is discharging, the adjacent lower
cell (CN-1) will return a cell voltage value near 0V. To avoid
misinterpretation of the cell voltages read after using this
command, there are two recommendations:
Consider the example in Figure 3 where input C3 is open.
After several cycles of measuring battery cells B3 and B4,
the ADC input resistance charges capacitors C and C .
F3
F4
The resulting potential on input C3 will be approximately
midway between C2 and C4. The ADC readings of B3 and
B4 may indicate a valid cell voltage when in fact the exact
stateofB3andB4isunknown.Ifthe100μAcurrentsources
are engaged, the potential at C3 will be pulled down. The
ADC reading for B3 will approach zero and the reading
for B4 will approach full scale. The amount of change in
the cell voltage reading is a function of the external filter
capacitor and time that the 100μA current sources are
connected to the cell.
1. Use the STCVDC command for all cell voltages (com-
mand 0x60) with only one discharge switch on at a
time. The value returned for the cell directly below the
cell being discharged will be invalid and read close to
0V. The voltage reading of all other cells, including the
cell being discharged, will be valid.
2. Use the individual cell commands with discharge
permitted (STCVDC commands 0x61 thru 0x6c) and
only turn on the discharge switch for the cell being
measured. The voltage reading for the individual cell
being measured and discharged will be valid.
LTC6802-1
C4
All discharge switches are automatically disabled during
OV and UV comparison measurements.
B4
B3
C
C
F4
C3
C2
C1
V–
MUX
F3
A/D CONVERTER DIGITAL SELF TEST
Two self test commands can be used to verify the func-
tionality of the digital portions of the ADC. The self tests
also verify the cell voltage registers and temperature
monitoring registers. During these self tests a test signal
is applied to the ADC. If the circuitry is working properly
all cell voltage and temperature registers will contain
100μA
68021 F03
Figure 3. Open Connection with RC Filtering
68021p
10
LTC6802-1
OPERATION
identical codes. For Self Test 1 the registers will contain
0x555. For Self Test 2, the registers will contain 0xAAA.
The time required for the self test function is the same as
required to measure all cell voltages or all temperature
sensors. Perform the self test function with CDC[2:0] set
to 1 in the configuration register.
Excessive heat results in elevated die temperatures. The
electrical characteristics are guaranteed for die tempera-
tures up to 85°C. Little or no degradation will be observed
in the measurement accuracy for die temperatures up
to 105°C. Damage may occur near 150°C, therefore the
recommended maximum die temperature is 125°C.
ToprotecttheLTC6802-1fromdamageduetooverheating,
a thermal shutdown circuit is included. Overheating of the
devicecanoccurwhendissipatingsignificantpowerinthe
celldischargeswitchesorwhencommunicatingfrequently
to the device using the current-mode serial interface. The
problem is exacerbated when operating with a large volt-
USING THE S PINS AS DIGITAL OUTPUTS OR
GATE DRIVERS
The S outputs include an internal 10k pull-up resistor.
Therefore the S pins will behave as a digital output when
loaded with a high impedance, e.g. the gate of an external
MOSFET.Forapplicationsrequiringhighbatterydischarge
currents, connectadiscretePMOSswitchdeviceandsuit-
able discharge resistor to the cell, and the gate terminal
to the S output pin, as illustrated in Figure 4.
+
–
age between V and V or when the thermal conductivity
of the system is poor.
The thermal shutdown circuit is enabled whenever the
device is not in standby mode (see Modes of Operation).
For the LTC6802-1, the thermal shutdown circuit will also
be enabled when any current mode input or output is
sinking or sourcing current. If the temperature detected
on the device goes above approximately 145°C, the con-
figuration registers will be reset to default states, turning
off all discharge switches and disabling A/D conversions.
Also, for the LTC6802-1, the current mode interface will
notoperateuntiltheovertemperatureconditiongoesaway.
When a thermal shutdown has occurred, the THSD bit
in the temperature register group will go high. The bit is
cleared by performing a read of the temperature registers
(RDTMP command).
C(n)
SI2351DS
15Ω
S(n)
1W
VISHAY CRCW2512 SERIES
C(n – 1)
68021 F04
Figure 4. External Discharge FET Connection (One Cell Shown)
POWER DISSIPATION AND THERMAL SHUTDOWN
TheMOSFETsconnectedtothepinsS1throughS12canbe
usedtodischargebatterycells.Anexternalresistorshould
beusedtolimitthepowerdissipatedbytheMOSFETs. The
maximum power dissipation in the MOSFETs is limited by
theamountofheatthatcanbetoleratedbytheLTC6802-1.
Since thermal shutdown interrupts normal operation, the
internal temperature monitor should be used to determine
whenthedevicetemperatureisapproachingunacceptable
levels.
APPLICATIONS INFORMATION
USING THE LTC6802-1 WITH LESS THAN 12 CELLS
Figure 5 shows an example of the LTC6802-1 when used
to monitor seven cells. The lowest C inputs connect to the
The LTC6802-1 can be used with as few as four cells.
The minimum number of cells is governed by the supply
voltage requirements of the LTC6802-1. The sum of the
cell voltages must be 10V to guarantee that all electrical
specifications are met.
+
seven cells and the upper C inputs connect to V . Other
configurations, e.g. 9 cells, would be configured in the
same way: the lowest C inputs connected to the battery
+
cellsandtheunusedCinputsconnectedtoV . Theunused
inputs will result in a reading of 0V for those channels.
68021p
11
LTC6802-1
APPLICATIONS INFORMATION
The read back value of that bit will be the logic level that
appears at the GPIO pin.
NEXT HIGHER GROUP OF 7 CELLS
LTC6802-1
+
V
When the MMB pin is low, the GPIO pins and the WDTB
pin are treated as inputs that set the number of cells to
be monitored. See the Monitor Mode section.
C12
S12
C11
S11
C10
S10
C9
WATCHDOG TIMER CIRCUIT
S9
The LTC6802-1 includes a watchdog timer circuit. If no
activity is detected on the SCKI pin for 2 seconds, the
WDTB open drain output is asserted low. The WDTB pin
remains low until an edge is detected on the SCKI pin.
C8
S8
C7
S7
C6
S6
C5
S5
C4
When the watchdog timer circuit times out, the configura-
tion bits are reset to their default (power-up) state.
S4
C3
S3
C2
S2
C1
In the power-up state, the S outputs are off. Therefore, the
watchdogtimerprovidesameanstoturnoffcelldischarg-
ing should communications to the MPU be interrupted.
The IC is in the minimum power standby mode after a
time out. Note that externally pulling the WDTB pin low
will not reset the configuration bits.
S1
−
V
68021 F05
NEXT LOWER GROUP OF 7 CELLS
The configuration bit WDTEN (byte CNFG0, bit 7) allows
the user to disable the watchdog timer operation. The
default value is WDTEN = 1 (enabled).
Figure 5. Monitoring 7 Cells with the LTC6802-1
The ADC can also be commanded to measure a stack of
cells by making 10 or 12 measurements, depending on
the state of the CELL10 bit in the control register. Data
from all 10 or 12 measurements must be down loaded
when reading the conversion results. The ADC can be
commanded to measure any individual cell voltage.
The watchdog timer operation is disabled when MMB
is low.
When reading the configuration register, byte CNFG0 bit
7 will reflect the state of the WDTB pin, independent of
what value was written to the WDTEN bit. Consequently,
if the watchdog timer is disabled by writing the WDTEN
bit to 0, the WDTB pin can be used as a general purpose
input, with the read value of the WDTEN bit reflecting an
input applied to the WDTB pin.
USING THE GENERAL PURPOSE INPUTS/OUTPUTS
(GPIO1, GPIO2)
TheLTC6802-1hastwogeneralpurposedigitalinputs/out-
puts. By writing a GPIO configuration register bit to a logic
low, the open drain output can be activated. The GPIOs
give the user the ability to turn on/off circuitry around the
LTC6802-1. One example might be a circuit to verify the
operation of the system.
REVISION CODE
The temperature register group contains a 3-bit revision
code. If software detection of device revision is neces-
sary, then contact the factory for details. Otherwise, the
code can be ignored. In all cases, however, the values of
all bits must be used when calculating the packet error
code (PEC) CRC byte on data reads.
When a GPIO configuration bit is written to a logic high,
the corresponding GPIO pin may be used as an input.
68021p
12
LTC6802-1
APPLICATIONS INFORMATION
MODES OF OPERATION
If fewer than 12 cells are connected to the LTC6802-1
then it is necessary to mask the unused input channels.
The MCxI bits in the configuration registers are used to
mask channels. If the CELL10 bit is high, then the inputs
for cells 11 and 12 are automatically masked.
The LTC6802-1 has three modes of operation: standby,
measure, and monitor. Standby mode is a power saving
statewhereallcircuitsexcepttheserialinterfaceareturned
off. In measure mode, the LTC6802-1 is used to measure
cell voltages and store the results in memory. Measure
mode will also monitor each cell voltage for overvoltage
(OV) and undervoltage (UV) conditions. In monitor mode,
thedevicewillonlymonitorcellsforUVandOVconditions.
A signal is output on the SDO pin to indicate the UV/OV
status. The serial interface is disabled.
The LTC6802-1 can monitor UV and OV conditions con-
tinuously. Alternatively, the duty cycle of the UV and OV
comparisons can be reduced or turned off to lower the
overall power consumption. The CDC bits are used to
control the duty cycle.
To initiate cell voltage measurements while in measure
mode, a Start A/D Conversion and Poll Status command
must be sent. After the command has been sent, the
LTC6802-1 will send the A/D converter status using either
thetogglepollingorthelevelpollingmethod, asdescribed
in the Serial Port section. If the CELL10 bit is high, then
only the bottom 10 cell voltages will be measured, thereby
reducing power consumption and measurement time. By
default the CELL10 bit is low, enabling measurement of all
12 cell voltages. During cell voltage measurement com-
mands, UV and OV flag conditions, reflected in the flag
registergroup,arealsoupdated.Whenthemeasurements
are complete, the part will go back to monitoring UV and
OV conditions at the rate designated by the CDC bits.
Standby Mode
The LTC6802-1 defaults (powers up) to standby mode.
Standby mode is the lowest possible supply current state.
Allcircuitsareturnedoffexcepttheserialinterfaceandthe
voltage regulator. For the lowest possible standby current
consumption all SPI logic inputs should be set to a logic
1 level. The LTC6802-1 can be programmed for standby
mode by setting the comparator duty cycle configuration
bits, CDC[2:0], to 0. If the part is put into standby mode
while ADC measurements are in progress, the measure-
ments will be interrupted and the cell voltage registers will
be in an indeterminate state. To exit standby mode, the
CDC bits must be written to a value other than 0.
Monitor Mode
Measure Mode
The LTC6802-1 can be used as a simple monitoring circuit
with no serial interface by pulling the MMB pin low. When
in this mode, the interrupt status is indicated on the SDO
pin using the toggle polling mode described in the Serial
Port section. Unlike serial port polling commands, how-
ever, the toggling is independent of the state of the CSBI
pin. See Figure 6.
LTC6802-1 is in measure mode when the CDC bits are
programmed with a value from 1 to 7. The IC monitors
each cell voltage and produces an interrupt signal on the
SDO pin indicating all cell voltages are within the UV and
OV limits. There are two methods for indicating the UV/OV
interruptstatus:togglepolling(usinga1kHzoutputsignal)
and level polling (using a high or low output signal). The
polling methods are described in the Serial Port section.
When the MMB pin is low, all the device configuration
values are reset to the default states shown in Table 12.
When MMB is held low the VUV, VOV, and CDC register
values are ignored. Instead VUV and VOV use factory-
programmed setings. CDC is set to state 5. The number
of cells to be monitored is set by the logic levels on the
WDTB and GPIO pins, as shown in Table 1.
The UV/OV limits are set by the VUV and VOV values in
the configuration registers. When a cell voltage exceeds
the UV/OV limits a bit is set in the flag register. The UV
and OV flag status for each cell can be determined using
the Read Flag Register Group.
68021p
13
LTC6802-1
APPLICATIONS INFORMATION
BATTERY POSITIVE
350V
LTC6802-1
LTC6802-1
IC #8
CSBI
SDO
SDI
CSBO
SDOI
SCKO
CSBO
SDOI
SCKO
CSBI
SDO
SDI
+
+
SCKI
V
V
SCKI
V
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
V
MODE
MODE
GPIO2
GPIO1
WDTB
MMB
TOS
GPIO2
GPIO1
WDTB
MMB
TOS
V
V
V
V
V
REG
V
REF
REG
REF
V
V
TEMP2
TEMP2
TEMP1
TEMP1
NC
NC
−
−
V
S7
S7
V
S1
C1
S2
C2
S3
C3
C6
S6
C5
S5
C4
S4
C6
S6
C5
S5
C4
S4
S1
C1
S2
C2
S3
C3
IC #3 TO IC #7
LTC6802-1
LTC6802-1
IC #2
CSBI
SDO
SDI
CSBO
SDOI
SCKO
CSBO
SDOI
SCKO
CSBI
SDO
SDI
+
+
SCKI
V
V
SCKI
V
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
V
MODE
MODE
GPIO2
GPIO1
WDTB
MMB
TOS
GPIO2
GPIO1
WDTB
MMB
TOS
V
V
V
V
V
REG
V
REF
REG
REF
V
V
TEMP2
TEMP2
TEMP1
TEMP1
NC
NC
−
−
V
S7
S7
V
S1
C1
S2
C2
S3
C3
C6
S6
C5
S5
C4
S4
C6
S6
C5
S5
C4
S4
S1
C1
S2
C2
S3
C3
3V
−
−
V2
V1
MPU
MODULE
IO
LTC6802-1
LTC6802-1
IC #1
OE2
OE1
CSBI
SDO
SDI
CSBO
SDOI
SCKO
CSBO
SDOI
SCKO
CSBI
SDO
SDI
CS
MISO
MOSI
CLK
+
+
SCKI
V
V
SCKI
+
−
V
MODE
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
V
V2
V1
MODE
−
+
GPIO2
GPIO1
WDTB
MMB
TOS
GPIO2
GPIO1
WDTB
MMB
TOS
V2
V1
3V
DIGITAL
ISOLATOR
V
V
V
V
V
REG
V
REF
REG
REF
V
V
TEMP2
TEMP2
TEMP1
TEMP1
NC
NC
−
−
V
S7
S7
V
S1
C1
S2
C2
S3
C3
C6
S6
C5
S5
C4
S4
C6
S6
C5
S5
C4
S4
S1
C1
S2
C2
S3
C3
68021 F06
Figure 6. Redundant Monitoring Circuit
68021p
14
LTC6802-1
APPLICATIONS INFORMATION
Table 1. Monitor Mode Cell Selection
are always outputs that can drive the next higher device
in a stack. SDI is a data input when writing to a stack of
devices. For devices not at the bottom of a stack, SDI is a
data output when reading from the stack. SDOI is a data
outputwhenwritingtoandadatainputwhenreadingfrom
a stack of devices. SDO is an open drain output that is only
used on the bottom device of a stack, where it may be tied
with SDI, if desired, to form a single, bi-directional port.
The SDO pin on the bottom device of a stack requires a
pull-up resistor. For devices up in the stack, SDO should
WDTB
GPIO2
GPIO1
CELL INPUTS MONITORED
Cells 1 to 5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Cells 1 to 6
Cells 1 to 7
Cells 1 to 8
Cells 1 to 9
Cells 1 to 10
Cells 1 to 11
Cells 1 to 12
–
be tied to the local V or left floating.
To communicate between daisy-chained devices, the
high side port pins of a lower device (CSBO, SCKO, and
SDOI) must be connected through PN junction diodes to
the respective low side port pins of the next higher device
(CSBI, SCKI, and SDI). In this configuration, the devices
communicate using current rather than voltage. To signal
a logic high from the lower device to the higher device,
the lower device sinks a smaller current from the higher
device pin. To signal a logic low, the lower device sinks
a larger current. Likewise, to signal a logic high from
the higher device to the lower device, the higher device
sources a larger current to the lower device pin. To signal
a logic low, the higher device sources a smaller current.
See Figure 7.
If MMB is low then brought high, all device configuration
values are reset to the default states including the VUV,
VOV, and CDC configuration bits.
SERIAL PORT
Overview
The LTC6802-1 has an SPI bus compatible serial port.
Several devices can be daisy chained in series.
There are two sets of serial port pins, designated as low
sideandhighside. Thelowsideandhighsideportsenable
devices to be daisy chained even when they operate at dif-
ferent power supply potentials. In a typical configuration,
the positive power supply of the first, bottom device is
connected to the negative power supply of the second, top
device, as shown in Figure 1. When devices are stacked in
this manner, they can be daisy chained by connecting the
high side port of the bottom device to the low side port of
thetopdevice.Withthisarrangement,themasterwritesto
or reads from the cascaded devices as if they formed one
long shift register. The LTC6802-1 translates the voltage
level of the signals between the low side and high side
ports to pass data up and down the battery stack.
Standbycurrentconsumedinthecurrentmodeserialinter-
face is minimized when CSBI, SCKI, and SDI are all high.
V
SENSE
+
(WRITE)
–
LOW SIDE PORT
ON HIGHER DEVICE
READ 1
Physical Layer
WRITE
On the LTC6802-1, seven pins comprise the low side and
high side ports. The low side pins are CSBI, SCKI, SDI,
and SDO. The high side pins are CSBO, SCKO and SDOI.
CSBI and SCKI are always inputs, driven by the master
or by the next lower device in a stack. CSBO and SCKO
HIGH SIDE PORT
ON LOWER DEVICE
V
SENSE
+
(READ)
–
68021 F07
Figure 7. Current Mode Interface
68021p
15
LTC6802-1
APPLICATIONS INFORMATION
Thevoltagemodepin(V
)determineswhetherthelow
Data Transfers: Every byte consists of 8 bits. Bytes are
transferred with the most significant bit (MSB) first. On a
write, the data value on SDI is latched into the device on
the rising edge of SCKI (Figure 8). Similarly, on a read,
the data value output on SDO is valid during the rising
edge of SCKI and transitions on the falling edge of SCKI
(Figure 9).
MODE
side serial port is configured as voltage mode or current
mode. For the bottom device in a daisy-chain stack, this
pin must be pulled high (tied to V ). The other devices
REG
–
in the daisy chain must have this pin pulled low (tied to V
)
to designate current mode communication. To designate
the top-of-stack device for polling commands, the TOS
pin on the top device of a daisy chain must be tied high.
The other devices in the stack must have TOS tied low.
See Figure 1.
CSBI must remain low for the entire duration of a com-
mand sequence, including between a command byte and
subsequent data. On a write command, data is latched in
on the rising edge of CSBI.
Data Link Layer
Afterapollingcommandhasbeenentered,theSDOoutput
will immediately be driven by the polling state, with the
SCKI input ignored (Figure 10). See the Toggle Polling
and Level Polling sections.
Clock Phase And Polarity: The LTC6802-1 SPI-compat-
ible interface is configured to operate in a system using
CPHA=1 and CPOL=1. Consequently, data on SDI must
be stable during the rising edge of SCKI.
CSBI
SCKI
LSB (DATA)
MSB (CMD)
BIT6 (CMD)
LSB (CMD)
MSB (DATA)
SDI
68021 F08
Figure 8. Transmission Format (Write)
CSBI
SCKI
SDI
MSB (CMD)
BIT6 (CMD)
LSB (CMD)
SDO
LSB (DATA)
MSB (DATA)
68021 F09
Figure 9. Transmission Format (Read)
68021p
16
LTC6802-1
APPLICATIONS INFORMATION
CSBI
SCKI
SDI
MSB (CMD)
BIT6 (CMD)
LSB (CMD)
SDO
POLL STATE
68021 F10
Figure 10. Transmission Format (Poll)
Network Layer
device A and top device B), the data will be output in the
following order:
Broadcast Commands: A broadcast command is one to
which all devices on the bus will respond, regardless of
device address. See the Bus Protocols and Commands
sections.
FLGR0(A), FLGR1(A), FLGR2(A), PEC(A), FLGR0(B),
FLGR1(B), FLGR2(B), PEC(B)
Toggle Polling: Toggle polling allows a robust determina-
tion both of device states and of the integrity of the con-
nections between the devices in a stack. Toggle polling
is enabled when the LVLPL bit is low. After entering a
polling command, the data out line will be driven by the
slave devices based on their status. When polling for the
A/D converter status, data out will be low when any device
is busy performing an A/D conversion and will toggle at
1kHz when no device is busy. Similarly, when polling for
interrupt status, the output will be low when any device
has an interrupt condition and will toggle at 1kHz when
none has an interrupt condition.
In daisy chained configurations, all devices in the chain
receive the command bytes simultaneously. For example,
to initiate A/D conversions in a stack of devices, a single
STCVAD command byte is sent, and all devices will start
conversions at the same time. For read and write com-
mands,asinglecommandbyteissent,andthenthestacked
devices effectively turn into a cascaded shift register, in
whichdataisshiftedthrougheachdevicetothenexthigher
(on a write) or the next lower (on a read) device in the
stack. See the Serial Command Examples section.
PEC Byte: The Packet Error Code (PEC) byte is a CRC
value calculated for all of the bits in a register group in
the order they are read, using the following characteristic
polynomial:
Toggle Polling—Daisy-Chained Broadcast Polling: The
SDO pin (bottom device) or SDI pin (stacked devices) will
be low if a device is busy/in interrupt. If it is not busy/not
in interrupt, the device will pass the signal from the SDOI
input to data out (if not the top-of-stack device) or toggle
the data out line at 1kHz (if the top-of-stack device).
8
2
x + x + x + 1
Onareadcommand,aftersendingthelastbyteofaregister
group, the device will shift out the calculated PEC, MSB
first. For daisy-chained devices, after the PEC is read from
the first device, the data from any daisy-chained devices
will follow in the same order. For example, when read-
ing the flag registers from two stacked devices (bottom
The master pulls CSBI high to exit polling.
Level polling: Level polling is enabled when the LVLPL
bit is high. After entering a polling command, the data
out line will be driven by the slave devices based on their
status. When polling for the A/D converter status, data
68021p
17
LTC6802-1
APPLICATIONS INFORMATION
out will be low when any device is busy performing an
A/D conversion and will be high when no device is busy.
Similarly, when polling for interrupt status, the output will
be low when any device has an interrupt condition and will
be high when none has an interrupt condition.
conversion time to pass before reading the results. The
second method is to hold CSBI low after an A/D start
commandhasbeensent.TheA/Dconversionstatuswillbe
outputonSDO. Aproblemwiththesecondmethodisthat
thecontrollerisnotfreetodootherserialcommunication
while waiting for A/D conversions to complete. The third
methodovercomesthislimitation.Thecontrollercansend
an A/D start command, perform other tasks, and then
send a Poll A/D Converter Status (PLADC) command to
determine the status of the A/D conversions.
Levelpolling—Daisy-ChainedBroadcastPolling:TheSDO
pin (bottom device) or SDI pin (stacked devices) will be
low if a device is busy/in interrupt. If it is not busy/not in
interrupt, thedevicewillpassthelevelfromtheSDOIinput
to data out (if not the top-of-stack device) or hold the data
out line high (if the top-of-stack device). Therefore, if any
device in the chain is busy or in interrupt, the SDO signal
at the bottom of the stack will be low. If all devices are
not busy/not in interrupt, the SDO signal at the bottom of
the stack will be high.
ForOV/UVinterruptstatus,thePollInterruptStatus(PLINT)
command can be used to quickly determine whether
any cell in a stack is in an overvoltage or undervoltage
condition.
Bus Protocols
The master pulls CSBI high to exit polling.
There are 3 different protocol formats, depicted in Table 3
through Table 5. Table 2 is the key for reading the protocol
diagrams.
PollingMethods:ForA/Dconversions,threemethodscan
be used to determine A/D completion. First, a controller
can start an A/D conversion and wait for the specified
Table 2. Protocol Key
PEC
Packet error code (CRC-8)
Master-to-slave
N
Number of bits
Slave-to-master
…
Continuation of protocol
Complete byte of data
Table 3. Broadcast Poll Command
8
Command
Poll Data
Table 4. Broadcast Read
8
8
8
8
8
8
Command
Data Byte Low
…
…
Data Byte High
PEC
Shift Byte 1
…
Shift Byte N
Table 5. Broadcast Write
8
8
8
8
8
Command
Data Byte Low
Data Byte High
Shift Byte 1
…
Shift Byte N
68021p
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LTC6802-1
APPLICATIONS INFORMATION
Commands
Table 6. Command Codes
Write Configuration Register Group
Read Configuration Register Group
Read Cell Voltage Register Group
Read Flag Register Group
WRCFG
RDCFG
RDCV
0x01
0x02
0x04
0x06
0x08
RDFLG
RDTMP
STCVAD
Read Temperature Register Group
Start Cell Voltage A/D Conversions and Poll Status
0x10 (all cell voltage inputs)
0x11 (cell 1 only)
0x12 (cell 2 only)
…
0x1A (cell 10 only)
0x1B (cell 11 only, if CELL10 bit=0)
0x1C (cell 12 only, if CELL10 bit=0)
0x1D (unused)
0x1E (cell self test 1; all CV=0x555)
0x1F (cell self test 2; all CV=0xAAA)
Start Open Wire A/D Conversions and Poll Status
STOWAD
0x20 (all cell voltage inputs)
0x21 (cell 1 only)
0x22 (cell 2 only)
…
0x2A (cell 10 only)
0x2B (cell 11 only, if CELL10 bit=0)
0x2C (cell 12 only, if CELL10 bit=0)
0x2D (unused)
0x2E (cell self test 1; all CV=0x555)
0x2F (cell self test 2; all CV=0xAAA)
Start Temperature A/D Conversions and Poll Status
STTMPAD
0x30 (all temperature inputs)
0x31 (external temp 1 only)
0x32 (external temp 1 only)
0x33 (internal temp only)
0x34—0x3D (unused)
0x3E (temp self test 1; all TMP=0x555)
0x3F (temp self test 2; all TMP=0xAAA)
Poll A/D Converter Status
Poll Interrupt Status
PLADC
PLINT
0x40
0x50
Start Cell Voltage A/D Conversions and Poll Status, with
Discharge Permitted
STCVDC
0x60 (all cell voltage inputs)
0x61 (cell 1 only)
0x62 (cell 2 only)
…
0x6A (cell 10 only)
0x6B (cell 11 only, if CELL10 bit=0)
0x6C (cell 12 only, if CELL10 bit=0)
0x6D (unused)
0x6E (cell self test 1; all CV=0x555)
0x6F (cell self test 2; all CV=0xAAA)
Start Open Wire A/D Conversions and Poll Status, with
Discharge Permitted
STOWDC
0x70 (all cell voltage inputs)
0x71 (cell 1 only)
0x72 (cell 2 only)
…
0x7A (cell 10 only)
0x7B (cell 11 only, if CELL10 bit=0)
0x7C (cell 12 only, if CELL10 bit=0)
0x7D (unused)
0x7E (cell self test 1; all CV=0x555)
0x7F (cell self test 2; all CV=0xAAA)
68021p
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LTC6802-1
APPLICATIONS INFORMATION
Memory Map
Table 7 through Table 12 show the memory map for the
LTC6802-1. Table 12 gives bit descriptions.
Table 7. Configuration (CFG) Register Group
REGISTER
CFGR0
CFGR1
CFGR2
CFGR3
CFGR4
CFGR5
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
BIT 7
WDTEN
DCC8
BIT 6
GPIO2
DCC7
BIT 5
GPIO1
DCC6
BIT 4
LVLPL
DCC5
BIT 3
CELL10
DCC4
BIT 2
CDC[2]
DCC3
BIT 1
CDC[1]
DCC2
BIT 0
CDC[0]
DCC1
MC4I
MC3I
MC2I
MC1I
DCC12
MC8I
DCC11
MC7I
DCC10
MC6I
DCC9
MC12I
VUV[7]
VOV[7]
MC11I
VUV[6]
VOV[6]
MC10I
VUV[5]
VOV[5]
MC9I
MC5I
VUV[4]
VOV[4]
VUV[3]
VOV[3]
VUV[2]
VOV[2]
VUV[1]
VOV[1]
VUV[0]
VOV[0]
Table 8. Cell Voltage (CV) Register Group
REGISTER
CVR00
CVR01
CVR02
CVR03
CVR04
CVR05
CVR06
CVR07
CVR08
CVR09
CVR10
CVR11
CVR12
CVR13
CVR14
CVR15*
CVR16*
CVR17*
RD/WR
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
BIT 7
C1V[7]
BIT 6
C1V[6]
BIT 5
C1V[5]
C2V[1]
C2V[9]
C3V[5]
C4V[1]
C4V[9]
C5V[5]
C6V[1]
C6V[9]
C7V[5]
C8V[1]
C8V[9]
C9V[5]
C10V[1]
C10V[9]
C11V[5]
C12V[1]
C12V[9]
BIT 4
C1V[4]
C2V[0]
C2V[8]
C3V[4]
C4V[0]
C4V[8]
C5V[4]
C6V[0]
C6V[8]
C7V[4]
C8V[0]
C8V[8]
C9V[4]
C10V[0]
C10V[8]
C11V[4]
C12V[0]
C12V[8]
BIT 3
C1V[3]
C1V[11]
C2V[7]
C3V[3]
C3V[11]
C4V[7]
C5V[3]
C5V[11]
C6V[7]
C7V[3]
C7V[11]
C8V[7]
C9V[3]
C9V[11]
C10V[7]
C11V[3]
C11V[11]
C12V[7]
BIT 2
C1V[2]
C1V[10]
C2V[6]
C3V[2]
C3V[10]
C4V[6]
C5V[2]
C5V[10]
C6V[6]
C7V[2]
C7V[10]
C8V[6]
C9V[2]
C9V[10]
C10V[6]
C11V[2]
C11V[10]
C12V[6]
BIT 1
C1V[1]
C1V[9]
C2V[5]
C3V[1]
C3V[9]
C4V[5]
C5V[1]
C5V[9]
C6V[5]
C7V[1]
C7V[9]
C8V[5]
C9V[1]
C9V[9]
C10V[5]
C11V[1]
C11V[9]
C12V[5]
BIT 0
C1V[0]
C1V[8]
C2V[4]
C3V[0]
C3V[8]
C4V[4]
C5V[0]
C5V[8]
C6V[4]
C7V[0]
C7V[8]
C8V[4]
C9V[0]
C9V[8]
C10V[4]
C11V[0]
C11V[8]
C12V[4]
C2V[3]
C2V[2]
C2V[11]
C3V[7]
C2V[10]
C3V[6]
C4V[3]
C4V[2]
C4V[11]
C5V[7]
C4V[10]
C5V[6]
C6V[3]
C6V[2]
C6V[11]
C7V[7]
C6V[10]
C7V[6]
C8V[3]
C8V[2]
C8V[11]
C9V[7]
C8V[10]
C9V[6]
C10V[3]
C10V[11]
C11V[7]
C12V[3]
C12V[11]
C10V[2]
C10V[10]
C11V[6]
C12V[2]
C12V[10]
*Registers CVR15, CVR16, and CVR17 can only be read if the CELL10 bit in register CFGR0 is low
68021p
20
LTC6802-1
APPLICATIONS INFORMATION
Table 9. Flag (FLG) Register Group
REGISTER
FLGR0
RD/WR
RD
BIT 7
C4OV
BIT 6
C4UV
BIT 5
C3OV
BIT 4
C3UV
BIT 3
C2OV
C6OV
C10OV
BIT 2
C2UV
C6UV
C10UV
BIT 1
C1OV
C5OV
C9OV
BIT 0
C1UV
C5UV
C9UV
FLGR1
RD
C8OV
C8UV
C7OV
C7UV
FLGR2
RD
C12OV*
C12UV*
C11OV*
C11UV*
* Bits C11UV, C12UV, C11OV, and C12OV are always low if the CELL10 bit in register CFGR0 is high
Table 10. Temperature (TMP) Register Group
REGISTER
TMPR0
TMPR1
TMPR2
TMPR3
TMPR4
RD/WR
RD
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ETMP1[7]
ETMP2[3]
ETMP2[11]
ITMP[7]
ETMP1[6]
ETMP2[2]
ETMP2[10]
ITMP[6]
ETMP1[5]
ETMP2[1]
ETMP2[9]
ITMP[5]
REV[0]
ETMP1[4]
ETMP2[0]
ETMP2[8]
ITMP[4]
THSD
ETMP1[3]
ETMP1[11]
ETMP2[7]
ITMP[3]
ETMP1[2]
ETMP1[10]
ETMP2[6]
ITMP[2]
ETMP1[1]
ETMP1[9]
ETMP2[5]
ITMP[1]
ITMP[9]
ETMP1[0]
ETMP1[8]
ETMP2[4]
ITMP[0]
ITMP[8]
RD
RD
RD
RD
REV[2]
REV[1]
ITMP[11]
ITMP[10]
Table 11. Packet Error Code (PEC)
REGISTER
RD/WR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PEC
RD
PEC[7]
PEC[6]
PEC[5]
PEC[4]
PEC[3]
PEC[2]
PEC[1]
PEC[0]
68021p
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LTC6802-1
APPLICATIONS INFORMATION
Table 12. Memory Bit Descriptions
NAME
DESCRIPTION
VALUES
CDC
UV/OV COMPARATOR
PERIOD
V
POWERED DOWN
CELL VOLTAGE
MEASUREMENT TIME
REF
BETWEEN MEASUREMENTS
0
N/A (Comparator Off)
Standby Mode
Yes
N/A
(default)
1
N/A (Comparator Off)
13ms
No
No
13ms
13ms
13ms
13ms
21ms
21ms
21ms
2
CDC
Comparator Duty Cycle
3
130ms
No
4
500ms
No
5*
6
130ms
Yes
Yes
Yes
500ms
7
2000ms
*when MMB pin is low, the CDC value is set to 5
CELL10
LVLPL
10-Cell Mode
0=12-cell mode (default); 1=10-cell mode
Level Polling Mode
0=toggle polling (default); 1=level polling
Write: 0=GPIO1 pin pull down on; 1=GPIO1 pin pull down off (default)
Read: 0=GPIO1 pin at logic ‘0’; 1=GPIO1 pin at logic ‘1’
Write: 0=GPIO2 pin pull down on; 1=GPIO2 pin pull down off (default)
Read: 0=GPIO2 pin at logic ‘0’; 1=GPIO2 pin at logic ‘1’
Write: 0=watchdog timer disabled; 1=watchdog timer enabled (default)
Read: 0=WDTB pin at logic ‘0’; 1=WDTB pin at logic ‘1’
GPIO1
GPIO2
GPIO1 Pin Control
GPIO2 Pin Control
WDTEN
DCCx
VUV
Watchdog Timer Enable
Discharge Cell x
x=1..12 0=turn off shorting switch for cell ‘x’ (default); 1=turn on shorting switch
Comparison voltage = VUV * 16 * 1.5mV
Undervoltage Comparison Voltage*
(default VUV=0. When MMB pin is low a factory programmed comparison voltage is used)
Comparison voltage = VOV * 16 * 1.5mV
VOV
Overvoltage Comparison Voltage*
Mask Cell x Interrupts
(default VOV=0. When MMB pin is low a factory programmed comparison voltage is used)
x=1..12 0=enable interrupts for cell ‘x’ (default)
1=turn off interrupts and clear flags for cell ‘x’
MCxI
x=1..12 12-bit ADC measurement value for cell ‘x’
cell voltage for cell ‘x’ = CxV * 1.5mV
CxV
Cell x Voltage*
reads as 0xFFF while A/D conversion in progress
x=1..12 cell voltage compared to VUV comparison voltage
0=cell ‘x’ not flagged for under voltage condition; 1=cell ‘x’ flagged
CxUV
Cell x Undervoltage Flag
x=1..12 cell voltage compared to VOV comparison voltage
0=cell ‘x’ not flagged for over voltage condition; 1=cell ‘x’ flagged
CxOV
Cell x Overvoltage Flag
ETMPx
External Temperature Measurement*
Temperature measurement voltage = ETMPx * 1.5mV
0= thermal shutdown has not occurred; 1=thermal shutdown has occurred
Status cleared to ‘0’ on read of Thermal Register Group
Device revision code
THSD
Thermal Shutdown Status
REV
ITMP
PEC
Revision Code
Internal Temperature Measurement*
Packet Error Code
Temperature measurement voltage = ITMP * 1.5mV = 8mV * T(°K)
CRC value for reads
*Voltage determinations use the decimal value of the registers, 0 to 4095 for 12-bit and 0 to 255 for 8-bit registers
68021p
22
LTC6802-1
APPLICATIONS INFORMATION
SERIAL COMMAND EXAMPLES
LTC6802-1 (Daisy Chained Configuration)
Examples below use a configuration of three stacked
devices: bottom (B), middle (M), and top (T)
Write Configuration Registers
1. Pull CSBI low
2. Send WRCFG command byte
3. Send CFGR0 byte for top device, then CFGR1 (T), CFGR2 (T), … CFGR5 (T)
4. Send CFGR0 byte for middle device, then CFGR1 (M), CFGR2 (M), … CFGR5 (M)
5. Send CFGR0 byte for bottom device, then CFGR1 (B), CFGR2 (B), … CFGR5 (B)
6. Pull CSBI high; data latched into all devices on rising edge of CSBI
Calculation of serial interface time for sequence above:
Number of devices in stack= N
Number of bytes in sequence = B = 1 command byte and 6 data bytes per device = 1+6*N
Serial port frequency per bit = F
Time = (1/F) * B * 8 bits/byte = (1/F) * (1+6*N) * 8
Time for 3-cell example above, with 1MHz serial port = (1/1000000) * (1+6*3)*8 = 152us
Read Cell Voltage Registers (12 Cell Mode)
1. Pull CSBI low
2. Send RDCV command byte
3. Read CVR00 byte of bottom device, then CVR01 (B), CVR02 (B), … CVR17 (B), and then PEC (B)
4. Read CVR00 byte of middle device, then CVR01 (M), CVR02 (M), … CVR17 (M), and then PEC (M)
5. Read CVR00 byte for top device, then CVR01 (T), CVR02 (T), … CVR17 (T), and then PEC (T)
6. Pull CSBI high
Calculation of serial interface time for sequence above:
Number of devices in stack= N
Number of bytes in sequence = B = 1 command byte, and 18 data bytes plus 1 PEC byte per device = 1+19*N
Serial port frequency per bit = F
Time = (1/F) * B * 8 bits/byte = (1/F) * (1+19*N) * 8
Time for 3-cell example above, with 1MHz serial port = (1/1000000) * (1+19*3)*8 =464us
Start Cell Voltage A/D Conversions and Poll Status (Toggle Polling)
1. Pull CSBI low
2. Send STCVAD command byte (all devices in stack start A/D conversions simultaneously)
3. SDO output from bottom device pulled low for approximately 12ms
4. SDO output toggles at 1kHz rate, indicating conversions complete for all devices in daisy chain
5. Pull CSBI high to exit polling
68021p
23
LTC6802-1
APPLICATIONS INFORMATION
Poll Interrupt Status (Level Polling)
1. Pull CSBI low
2. Send PLINT command byte
3. SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high
4. Pull CSBI high to exit polling
FAULT PROTECTION
Overview
assembly and service procedures that might affect a bat-
tery system during its useful lifespan. Table 13 shows the
various situations that should be considered when plan-
ning protection circuitry. The first five scenarios are to be
anticipated during production and appropriate protection
is included within the LTC6802-1 device itself.
Care should always be taken when using high energy
sources such as batteries. There are numerous ways that
systems can be [mis-]configured when considering the
Table 13. LTC6802-1 Failure Mechanism Effect Analysis
SCENARIO
EFFECT
DESIGN MITIGATION
+
–
Cell input open-circuit (random)
Power-up sequence at IC inputs
Clamp diodes at each pin to V & V (within IC) provide
alternate power-path.
Cell input open-circuit (random)
Differential input voltage overstress
Zener diodes across each cell voltage input pair (within IC)
limits stress.
+
+
–
Top cell input connection loss (V ) Power will come from highest connected cell input
or via data port fault current
Clamp diodes at each pin to V & V (within IC) provide
alternate power-path. Diode conduction at data ports will impair
communication with higher-potential units.
+
–
Bottom cell input connection loss Power will come from lowest connected cell input or Clamp diodes at each pin to V & V (within IC) provide
–
(V )
via data port fault current
alternate power-path. Diode conduction at data ports will impair
communication with higher-potential units.
+
–
Disconnection of a harness
between a group of battery cells
and the IC (in a system of stacked
groups)
Loss of supply connection to the IC
Clamp diodes at each pin to V & V (within IC) provide an
alternate power-path if there are other devices (which can
supply power) connected to the LTC6802-1. Diode conduction
at data ports will impair communication with higher-potential
units.
Data link disconnection between
stacked LTC6802-1 units.
Break of "daisy chain" communication (no stress
to ICs). Communication will be lost to devices
above the disconnection. The devices below the
disconnection are still able to communicate and
perform all functions, however, the polling feature is
disabled.
If the watchdog timer is enabled, all units above the
disconnection will enter standby mode within 2 seconds of
disconnect. Discharge switches are disabled in standby mode.
Cell-pack integrity, break between Daisy-chain voltage reversal up to full stack potential Use series protection diodes with top-port I/O connections
stacked units
during pack discharge
(RS07J for up to 600V). Use isolated data link at bottom-most
data port.
Cell-pack integrity, break between Daisy-chain positive overstress during charging
stacked units
Add redundant current path link
Cell-pack integrity, break within
stacked unit
Cell input reverse overstress during discharge
Add parallel Schottky diodes across each cell for load-path
redundancy. Diode and connections must handle full operating
current of stack, will limit stress on IC
Cell-pack integrity, break within
stacked unit
Cell input positive overstress during charge
Add SCR across each cell for charge-path redundancy. SCR
and connections must handle full charging current of stack, will
limit stress on IC by selection of trigger Zener
68021p
24
LTC6802-1
APPLICATIONS INFORMATION
Battery Interconnection Integrity
unpredictable voltage clamping or current flow. Limiting
the current flow at any pin to 10mA will prevent damage
to the IC.
TheFMEAscenariosinvolvingabreakinthestackofbattery
cells are potentially the most damaging. In the case where
the battery stack has a discontinuity between groupings
of cells monitored by LTC6802-1 ICs, any load will force
a large reverse potential on the daisy-chain connection.
This situation might occur in a modular battery system
during initial installation or a service procedure. The daisy
chain ports are protected from the reverse potential in this
scenariobyexternalserieshigh-voltagediodesrequiredin
the upper-port data connections as shown in Figure 11.
LTC6802-1
+
V
SCKO
C12
S12
SDOI
C11
S11
ZCLAMP
CSBO
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C3
S3
C2
S2
C1
S1
V–
During the charging phase of operation, this fault would
lead to forward biasing of daisy-chain ESD clamps that
would also lead to part damage. An alternative connection
to carry current during this scenario will avoid this stress
from being applied (Figure 11).
LTC6802-1
ZCLAMP
(NEXT HIGHER IN STACK)
−
V
SDO SDI SCKI CSBI
PROTECT
AGAINST
BREAK
OPTIONAL
REDUNDANT
CURRENT
PATH
RS07J (3x)
CSBI
SDO
SDI
HERE
SDOI SCKO CSBO
+
V
LTC6802-1
(NEXT LOWER IN STACK)
68021 F11
SCKI
V
Figure 11. Reverse-Voltage Protection for the
Daisy-Chain (One Link Connection Shown)
MODE
ZCLAMP
GPIO2
GPIO1
WDTB
MMB
TOS
Internal Protection Diodes
Each pin of the LTC6802-1 has protection diodes to help
prevent damage to the internal device structures caused
by external application of voltages beyond the supply rails
as shown in Figure 12.
68021 F12
Figure 12. Internal Protection Diodes
The diodes shown are conventional silicon diodes with a
forward breakdown voltage of 0.5V. The unlabeled zener
diode structures have a reverse breakdown characteristic
which initially breaks down at 12V then snaps back to a 7V
clamping potential. The zener diodes labeled ZCLAMP are
higher voltage devices with an initial reverse breakdown
of 30V snapping back to 25V. The forward voltage drop
of all zeners is 0.5V. Refer to this diagram in the event of
Cell-Voltage Filtering
The LTC6802-1 employs a sampling system to perform
its analog-to-digital conversions and provides a conver-
sion result that is essentially an average over the 0.5ms
conversionwindow,providedthereisn’tnoisealiasingwith
respect to the delta-sigma modulator rate of 512kHz. This
indicates that a lowpass filter with useful attenuation at
68021p
25
LTC6802-1
APPLICATIONS INFORMATION
500kHz may be beneficial. Since the delta-sigma integra-
tion bandwidth is about 1kHz, the filter corner need not
be lower than this to assure accurate conversions.
LTC6802-1
100k
100k
V
V
REG
REF
V
V
TEMP2
Series resistors of 100Ω may be inserted in the input
paths without introducing meaningful measurement
error, provided only external discharge switch FETs are
being used. Shunt capacitors may be added from the cell
TEMP1
NC
100k
NTC
1μF
−
V
1μF
100k
NTC
–
inputs to V , creating RC filtering as shown in Figure 13.
68021 F14
Note that this filtering is not compatible with use of the
internal discharge switches to carry current since this
would induce settling errors at the time of conversion as
any activated switches temporarily open to provide Kelvin
modecellsensing.Asadischargeswitchopens,cellwiring
resistance will also form a small voltage step (recovery
of the small IR drop), so keeping the frequency cutoff of
the filter relatively high will allow adequate settling prior
to the actual conversion. A guard time of about 60μs is
provided in the ADC timing, so a 16kHz LP is optimal and
offers about 30dB of noise rejection.
Figure 14. Driving Thermistors Directly from VREF
For sensors that require higher drive currents, a buffer op
amp may be used as shown in Figure 15. Power for the
sensor is actually sourced indirectly from the V
pin
REG
in this case. Probe loads up to about 1mA maximum are
supported in this configuration. Since V is shutdown
REF
during the LTC6802-1 idle and shutdown modes, the
thermistor drive is also shut off and thus power dissipa-
tion minimized. Since V
remains always on, the buffer
REG
op amp (LT6000 shown) is selected for its ultralow power
consumption (10μA).
–
No resistor should be placed in series with the V pin.
–
Because the supply current flows from the V pin, any
resistance on this pin could generate a significant conver-
sion error for CELL1.
+
LTC6000
–
C(n)
100Ω
100nF
LTC6802-1
V
V
S(n)
REG
10k
10k
REF
V
V
TEMP2
C(n – 1)
TEMP1
NC
100Ω
100nF
10k
NTC
68021 F13
−
V
Figure 13. Adding RC Filtering to the Cell Inputs
(One Cell Connection Shown)
10k
NTC
68021 F15
READING EXTERNAL TEMPERATURE PROBES
Using Dedicated Inputs
Figure 15. Buffering VREF for Higher-Current Sensors
Expanding Probe Count
TheLTC6802-1includestwochannelsofADCinput,V
TEMP1
The LTC6802-1 provides general purpose I/O pins, GPIO1
and GPIO2, that may be used to control multiplexing of
several temperature probes. Using just one of the GPIO
pins, the sensor count can double to four as shown in
and V
, that are intended to monitor thermistors
TEMP2
(tempco about –4%/°C generally) or diodes (–2.2mV/°C
typical) located within the cell array. Sensors can be
powered directly from V as shown in Figure 14 (up to
REF
60μA total).
68021p
26
LTC6802-1
APPLICATIONS INFORMATION
Figure 16. Using both GPIO pins, up to eight sensor inputs
can be supported.
ADDING CALIBRATION AND
FULL-STACK MEASUREMENTS
Another method of multiple sensor support is possible
without the use of any GPIO pins. If the sensors are PN
diodes and several used in parallel, then the hottest diode
will produce the lowest forward voltage and effectively
By adding multiplexing hardware, additional signals can
be digitized by the CELL1 ADC channel. One useful signal
to provide is a high-accuracy voltage reference, such as
from an LT1461A-4. By periodic readings of this signal,
host software can provide correction of the LTC6802-1
readings to improve the accuracy over that of the internal
LTC6802-1 reference, and/or validate ADC operation. An-
otherusefulsignalisameasureofthetotalstackpotential.
Thisprovidesaredundantoperationalmeasurementofthe
cells in the event of a malfunction in the normal acquisi-
tion process, or as a faster means of monitoring the entire
stackpotential.Figure18showsameansofprovidingboth
of these features. A resistor divider is used to provide a
low-voltage representation of the full stack potential (C12
to C0 voltage) with MOSFETs that decouple the divider
current under unneeded conditions. Other MOSFETs, in
conjunction with an op amp having a shutdown mode,
form a voltage selector that allows measurement of the
normal cell1 potential (when GPIO1 is low) or a buffered
MUX signal. When the MUX is active (GPIO1 is high),
selection can be made between the reference (4.096V) or
the full-stack voltage divider (GPOI2 set low will select the
reference).DuringidletimewhentheLTC6802-1WTBsignal
goes low, the external circuitry goes into a power down
condition, reducing battery drain to a minimum. When not
actively performing measurements, GPIO1 should be set
low and GPIO2 should be set high to achieve the lowest
power state for the configuration shown.
establishtheinputsignaltotheV
input(s).Thehottest
TEMP
diode will therefore dominate the readout from the V
TEMP
inputs that the diodes are connected to. In this scenario,
the specific location or distribution of heat is not known,
but such information may not be important in practice.
Figure 17 shows the basic concept.
In any of the sensor configurations shown, a full-scale
cold readout would be an indication of a failed-open sen-
sor connection to the LTC6802-1.
LTC6802-1
GPIO1
SN74LVC1G3157
OR SIMILAR DEVICE
100k
100k
100k
NTC
V
V
REG
100k
REF
100k
NTC
V
V
TEMP2
TEMP1
NC
V
100k
NTC
1μF
−
100k
NTC
68021 F16
Figure 16. Expanding Sensor Count with Multiplexing
200k
LTC6802-1
V
V
REG
200k
PROVIDING HIGH-SPEED OPTO-ISOLATION
OF THE SPI DATA-PORT
REF
V
V
TEMP2
TEMP1
NC
Isolation techniques that are capable of supporting the
1Mbps data rate of the LTC6802-1 require more power
on the isolated (battery) side than can be furnished by
−
V
the V
output of the LTC6802-1. To keep battery drain
REG
68021 F17
minimal, this means that a DC/DC function must be imple-
mented along with a suitable data isolation circuit, such as
shown in Figure 19. Here an optimal Avago 4-channel (3/1
bidirectional) opto-coupler is used, with a simple isolated
supplygeneratedbyanLTC1693-2configuredasa200kHz
oscillator. The DC/DC function provides an unregulated
Figure 17. Using Diode Sensors as Hot-Spot Detectors
68021p
27
LTC6802-1
APPLICATIONS INFORMATION
TP0610K
CELL12
1M
V
2.2M
0 = REF_EN
GPIO2
0 = CELL1
STACK12
GPIO1
WDTB
LT1461A-4
DNC DNC
1M
1M
10M
1M
V
V
SD
DNC
V
OUT
REG
IN
4.096V
2N7002
GND DNC
LTC6802-1
90.9k
1μF
2N7002
−
V
2.2μF
C1
150Ω
TP0610K
+
TP0610K TP0610K
V
CH0 CH1 SEL
DD
CELL1
LT1636
SD
100Ω
TC4W53FU
COM INH
100nF
–
V
V
SS
EE
1M
68021 F18
Figure 18. Providing Measurement of Calibration Reference and Full-Stack Voltage Through CELL1 Port
+5V_HOST
CSBI
330Ω
100k
3.57k
3.57k
3.57k
100k
CSBI
SDO
SDI
SDI
TP0610K
330Ω
100k
SCKI
TP0610K
330Ω
TP0610K
SCKI
V
REG
SDO
100nF
4.99k
249Ω
LTC6802-1
GND_HOST
ACSL-6410
ISOLATED V
LOGIC
1μF
470pF
20k
BAT54S
BAT54S
6
V
IN1
OUT1 GND1
IN2
CC1
1μF
1
•
•
33nF
V
CC2
10k
4
3
OUT2 GND2
−
V
PE68386
LTC1693-2
68021 F19
Figure 19. Providing an Isolated High-Speed Data Interface
68021p
28
LTC6802-1
APPLICATIONS INFORMATION
logic voltage (~4V) to the opto-coupler isolated side,
from energy provided by host-furnished 5V. This circuit
provides totally galvanic isolation between the batteries
and the host processor, with an insulation rating of 560V
continuous, 2500V transient.
ADVANTAGES OF DELTA-SIGMA ADCS
The LTC6802-1 employs a delta sigma analog to digital
converter for voltage measurement. The architecture of
delta sigma converters can vary considerably, but the
common characteristic is that the input is sampled many
times over the course of a conversion and then filtered or
averaged to produce the digital output code. In contrast,
a SAR converter takes a single snapshot of the input
voltage and then performs the conversion on this single
sample. For measurements in a noisy environment, a
delta sigma converter provides distinct advantages over
a SAR converter.
PCB LAYOUT CONSIDERATIONS
The V
and V
pins should be bypassed with a 1μF
REF
REG
capacitor for best performance.
The LTC6802-1 is capable of operation with as much as
+
–
60V between V and V . Care should be taken on the PCB
layouttomaintainphysicalseparationoftracesatdifferent
potentials. The pinout of the LTC6802-1 was chosen to
facilitate this physical separation. Figure 20 shows the DC
WhileSARconverterscanhavehighsamplerates, thefull-
power bandwidth of a SAR converter is often greater than
1MHz, which means the converter is sensitive to noise out
to this frequency. And many SAR converters have much
higher bandwidths – up to 50MHz and beyond. It is pos-
sible to filter the input, but if the converter is multiplexed
to measure several input channels a separate filter will be
required for each channel. A low frequency filter cannot
reside between a multiplexer and an ADC and achieve a
high scan rate across multiple channels. Another conse-
quence of filtering a SAR ADC is that any noise reduction
gained by filtering the input cancels the benefit of having
a high sample rate in the first place, since the filter will
take many conversion cycles to settle.
–
voltage on each pin with respect to V when twelve 3.6V
battery cells are connected to the LTC6802-1. There is no
more then 5.5V between any two adjacent pins. The pack-
age body is used to separate the highest voltage (43.5V)
from the lowest voltage (0V).
LTC6802-1
42.5V
42.5V
42.5V
43.2V
43.2V
43.2V
39.6V
39.6V
36V
CSBO
SDOI
SCKO
CSBI
SDO
SDI
SCKI
V
MODE
GPIO2
GPIO1
WDTB
MMB
TOS
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
0V TO 5.5V
5.5V
3.1V
1.5V
1.5V
0V
0V
3.6V
3.6V
7.2V
+
V
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
For a given sample rate, a delta sigma converter can
achieve excellent noise rejection while settling completely
inasingleconversion–somethingthatafilteredSARcon-
verter cannot do. Noise rejection is particularly important
in high voltage switching controllers, where switching
noise will invariably be present in the measured voltage.
Other advantages of delta sigma converters are that they
are inherently monotonic, meaning they have no missing
codes, and they have excellent DC specifications.
36V
32.4V
32.4V
28.8V
28.8V
25.2V
25.2V
21.6V
21.6V
18V
V
REG
V
REF
V
V
TEMP2
TEMP1
NC
−
V
S1
C1
S2
C2
S3
18V
14.4V
14.4V
7.2V
10.8V
10.8V
C3
68021 F20
Figure 20. Typical Pin Voltages for 12 3.6V Cells
68021p
29
LTC6802-1
APPLICATIONS INFORMATION
Converter Details
10
0
The LTC6802-1’s ADC has a second order delta sigma
modulator followed by a Sinc2, finite impulse response
(FIR) digital filter. The front-end sample rate is 512ksps,
which greatly reduces input filtering requirements. A
simple 16kHz, 1 pole filter composed of a 100Ω resistor
and a 0.1ꢀF capacitor at each input will provide adequate
filtering for most applications. These component values
will not degrade the DC accuracy of the ADC.
–10
–20
–30
–40
–50
–60
10
100
1k
10k
100k
Each conversion consists of two phases – an autozero
phase and a measurement phase. The ADC is autozeroed
at each conversion, greatly improving CMRR. The second
half of the conversion is the actual measurement.
FREQUENCY (Hz)
68021 F20
Figure 21. Noise Filtering of the LTC6802-1 ADC
the SAR will have a slower response to input signals. For
example,astepinputappliedtotheinputofthe850Hzfilter
will take 1.55ms to settle to 12 bits of precision, while the
LTC6802-1 ADC settles in a single 1ms conversion cycle.
Thisalsomeansthatveryhighsampleratesdonotprovide
any additional information because the analog filter limits
the frequency response.
Noise Rejection
Figure 21 shows the frequency response of the ADC.
The rolloff follows a Sinc2 response, with the first notch
at 4kHz. Also shown is the response of a 1 pole, 850Hz
filter(187ꢀstimeconstant)whichhasthesameintegrated
response to wideband noise as the LTC6802-1’s ADC,
which is about 1350Hz. This means that if wideband noise
is applied to the LTC6802-1 input, the increase in noise
seen at the digital output will be the same as an ADC with
a wide bandwidth (such as a SAR) preceded by a perfect
1350Hz brickwall lowpass filter.
While higher order active filters may provide some im-
provement, their complexity makes them impractical for
high-channel count measurements as a single filter would
be required for each input.
Also note that the Sinc2 response has a 2nd order rolloff
envelope, providing an additional benefit over a single
pole analog filter.
Thus if an analog filter is placed in front of a SAR converter
toachievethesamenoiserejectionastheLTC6802-1ADC,
68021p
30
LTC6802-1
PACKAGE DESCRIPTION
G Package
44-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1754 Rev Ø)
12.50 – 13.10*
(.492 – .516)
1.25 0.12
5.3 – 5.7
40 38
44 43 42 41 39 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
7.8 – 8.2
7.40 – 8.20
(.291 – .323)
0.50
BSC
0.25 0.05
5
7
8
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18 19 20 21 22
2.0
(.079)
MAX
5.00 – 5.60*
(.197 – .221)
1.65 – 1.85
(.065 – .073)
PARTING
0° – 8°
LINE
SEATING
PLANE
0.50
(.01968)
BSC
0.10 – 0.25
(.004 – .010)
0.55 – 0.95**
(.022 – .037)
1.25
(.0492)
REF
0.05
(.002)
MIN
†
0.20 – 0.30
(.008 – .012)
TYP
G44 SSOP 0607 REV Ø
NOTE:
1.DRAWING IS NOT A JEDEC OUTLINE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS,
BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT
THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED .15mm PER SIDE
2. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
3. DIMENSIONS ARE IN
(INCHES)
**LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE
†
THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS.
DAMBAR PROTRUSIONS DO NOT EXCEED 0.13mm PER SIDE
4. DRAWING NOT TO SCALE
5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN 0.08mm AT SEATING PLANE
68021p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC6802-1
RELATED PARTS
PART NUMBER
DESCRIPTION
Multicell Battery Stack Monitor with Parallel Addressed Functionality equivalent to LTC6802-1, Allows for Individually Addressable
Serial Interface Battery Stack Topologies
COMMENTS
LTC6802-2
68021p
LT 0808 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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