LTC6903IMS8#TR_技术文档

LTC6903/LTC6904

1kHz to 68MHz Serial

Port Programmable Oscillator

FeaTures

DescripTion

TheLTC^®6903/LTC6904arelowpowerselfcontaineddigital

frequency sources providing a precision frequency from

1kHz to 68MHz, set through a serial port. The LTC6903/

LTC6904 require no external components other than a

power supply bypass capacitor, and they operate over a

single wide supply range of 2.7V to 5.5V.

n

1kHz to 68MHz Square Wave Output

n

0.5% (Typ) Initial Frequency Accuracy

n

Frequency Error <1.1% Over All Settings

10ppm/°C Typical Frequency Drift Over

Temperature

0.1% Resolution

1.7mA Typical Supply Current (f < 1MHz, V = 2.7V)

2.7V to 5.5V Single- Supply Operation

Jitter <0.4% Typical 1kHz to 8MHz

Easy to Use SPI (LTC6903) or I C (LTC6904) Serial

Interface

n

S

TheLTC6903/LTC6904featureaproprietaryfeedbackloop

that linearizes the relationship between digital control set-

ting and frequency, resulting in a very simple frequency

setting equation:

n

2

n

Output Enable Pin

–55°C to 125°C Operation

MS8 Package

2078(Hz)

f = 2^OCT

•

;1kHz < f < 68MHz





DAC

2 –









1024

where OCT is a 4-bit digital code and DAC is a 10-bit

digital code.

applicaTions

n

Precision Digitally Controlled Oscillator

TheLTC6903iscontrolledbyaconvenientSPIcompatible

serial interface. The LTC6904 uses an industry standard

n

Power Management

n

Direct Digital Frequency Synthesis (DDS)

2

I C compatible interface.

Replacement

Replacement for DAC and VCO

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents, including 6342817 and 6614313.

n

Switched Capacitor Filter Clock

Typical applicaTion

LTC6903 Frequency Error

Distribution

A Microcontroller Controlling Its Clock

40

V

= 3V

S

A

T

= 25°C

5V

f = 1039Hz

443

UNITS

TESTED

+

GND

V

30

20

10

0

MICROCONTROLLER

OSC1/CLKIN

SDI

OE

CLK

OSC2/CLKOUT

RC5/SDO

10k

LTC6903

MCLR/V

P–P

10Ω

SCK

SEN

RC3/SCK/SCL

RC2/CCP1

1µF

5V

0.1µF

V

DD

V

SS

V

SS

0.01µF

POWER-UP CLOCK

FREQUENCY IS 1039Hz

PIC16F73

–1.0

–0.5

0

0.5

1.0

69034 AT01

FREQUENCY ERROR (%)

69034 TA01b

69034fe

1

LTC6903/LTC6904

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

+

Total Supply Voltage (V to GND)................................6V

TOP VIEW

+

GND

SDI

SCK

1

2

3

4

8 V

Maximum Voltage

7 OE

6 CLK

5 CLK

+

on any Pin.............(GND – 0.3V) ≤ V ≤ (V + 0.3V)

SEN/ADR*

Output Short-Circuit Duration (Note 2) ............ Indefinite

MS8 PACKAGE

8-LEAD PLASTIC MSOP

Operating Temperature Range (Note 3)

LTC6903CMS8/LTC6904CMS8............–40°C to 85°C

LTC6903IMS8/LTC6904IMS8..............–40°C to 85°C

LTC6903HMS8/LTC6904HMS8 ......... –40°C to 125°C

LTC6904MPMS8 ............................... –55°C to 125°C

Specified Temperature Range (Note 4)

T

= 150°C, θ = 200°C/W

JA

JMAX

*SEN (LTC6903)

ADR (LTC6904)

LTC6903CMS8/LTC6904CMS8................ 0°C to 70°C

LTC6903IMS8/LTC6904IMS8..............–40°C to 85°C

LTC6903HMS8/LTC6904HMS8 ......... –40°C to 125°C

LTC6904MPMS8 ............................... –55°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

orDer inForMaTion

LEAD FREE FINISH

LTC6903CMS8#PBF

LTC6903IMS8#PBF

LTC6903HMS8#PBF

LTC6904CMS8#PBF

LTC6904IMS8#PBF

LTC6904HMS8#PBF

LTC6904MPMS8#PBF

TAPE AND REEL

PART MARKING*

LTABN

PACKAGE DESCRIPTION

8-Lead Plastic MSOP

SPECIFIED TEMPERATURE RANGE

LTC6903CMS8#TRPBF

LTC6903IMS8#TRPBF

LTC6903HMS8#TRPBF

LTC6904CMS8#TRPBF

LTC6904IMS8#TRPBF

LTC6904HMS8#TRPBF

0°C to 70°C

LTABN

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

LTABN

LTAES

–40°C to 85°C

–40°C to 125°C

–55°C to 125°C

LTAES

LTC6904MPMS8#TRPBF LTFDX

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

69034fe

2

LTC6903/LTC6904

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V⁺= 2.7V to 5.5V, GND = 0V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

∆fi

∆f

Initial Frequency Accuracy

Total Frequency Accuracy (Note 7)

f = 1.039kHz, V = 3V, C

= 5pF

0.75

%

LOAD

Single Output Active:

+

Over All Settings, V = 2.7V, C

= 5pF

0.5

1.1

1.6

%

LOAD

Over All Settings, V = 5.5V, C

LTC6903CMS8, LTC6904CMS8:

+

l

Over All Settings, V = 2.7V, C

= 5pF

0.5

1.65

2

%

LOAD

+

Over All Settings, V = 5.5V, C

LTC6903HMS8, LTC6903IMS8,

LTC6904HMS8, LTC6904IMS8,

LTC6904MPMS8:

+

l

Over All Settings, V = 2.7V, C

= 5pF

0.5

1.9

2.2

%

LOAD

Over All Settings, V = 5.5V, C

f

Maximum Operating Frequency

Minimum Operating Frequency

Frequency Drift Over Temperature

Frequency Drift Over Supply

Long-Term Frequency Stability

Timing Jitter (See Graph)

68

1.039

10

MHz

kHz

MAX

MIN

∆f/∆T

∆f/∆V

ppm/°C

%/V

0.05

300

ppm/√kHr

1.039kHz to 8.5MHz

1.039kHz to 68MHz

0.4

1

%

l

Duty Cycle

1.039kHz to 1MHz

1.039kHz to 68MHz

49

50

51

%

+

R

OUT

Output Resistance

CLK, CLK Pins, V = 2.7V

45

Ω

+

l

V

OH

High Level Output Voltage

V = 5.5V, 4mA Load

4.8

2

5.3

2.3

V

V = 2.7V, 4mA Load

+

l

V = 5.5V, 1mA Load

5.2

2.3

5.45

2.55

V

V = 2.7V, 1mA Load

+

l

V

OL

Low Level Output Voltage

V = 5.5V, 4mA Load

0.15

0.25

0.3

0.45

V

V = 2.7V, 4mA Load

+

l

V = 5.5V, 1mA Load

0.05

0.15

0.2

V

V = 2.7V, 1mA Load

+

t

Output Rise Time (10% - 90%)

Output Fall Time (10% - 90%)

V = 5.5V, R

= ∞, C

= 5pF

1

ns

r

LOAD

V = 2.7V, R

+

V = 5.5V, R

= ∞, C

= 5pF

1

ns

f

LOAD

+

V = 2.7V, R

power requireMenTs ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. V⁺= 2.7V to 5.5V, GND = 0V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

Applied Between V and GND

V = 2.7V

MIN

TYP

MAX

UNITS

+

l

V

Supply Voltage

2.7

5.5

V

S

+

l

I , SHDN

S

V Supply Current, Shutdown

0.25

0.6

2.2

mA

S

V = 5.5V

S

+

l

I , DC

S

V Supply Current, Single Output

f = 68MHz, 5pF Load, V = 2.7V

3.6

1.7

7

mA

+

Enabled

f < 1MHz, V = 2.7V

3.1

15

4.5

+

f = 68MHz, 5pF Load, V = 5.5V

+

f < 1MHz, V = 5.5V

1.9

69034fe

3

LTC6903/LTC6904

serial porT elecTrical characTerisTics ^Thel denotes the specifications which apply over

the full operating temperature range, otherwise specifications are at T_A= 25°C. V⁺= 2.7V to 5.5V, GND = 0V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

l

V

Min High Level Input Voltage

0.67 V

V

IH

IL

SEN, SCK, SDI Pins

+

V

Max Low Level Input Voltage

SEN, SCK, SDI Pins

0.33 V

V

I

Digital Input Leakage

SEN, SCK, SDI Pins

10

µA

IN

TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. V⁺= 2.7V to 5.5V, GND = 0V, unless otherwise noted.

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

LTC6903 (Notes 5, 6)

l

f

t

Serial Port Clock Frequency

Min Clock HIGH Time

20

25

MHz

ns

SCK

CKHI

CKLO

SU

Min Clock LOW Time

25

ns

Min Setup Time – SDI to SCK

Min Hold Time – SCK to SDI

Min Latch Time – SEN to SEN

Min First Clock – SEN to SCK

10

ns

10

ns

HLD

LCH

FCK

400

20

ns

LTC6904 (Notes 5, 6)

l

f

t

SMBus Operating Frequency

10

4.7

4.0

4.7

4.0

100

kHz

µs

SMB

Bus Free Time Between STOP and START Condition

Hold Time After (Repeated) START Condition

Repeated START Condition Setup Time

STOP Condition Setup Time

BUF

µs

HD,STA

SU,STA

SU,STO

µs

LTC6904 (Notes 5, 6)

l

t

Data Hold Time

300

250

4.7

4.0

ns

µs

ns

HD,DAT

SU,DAT

LOW

HIGH

f

Data Setup Time

Clock LOW Period

Clock HIGH Period

Clock, Data Fall Time

Clock, Data Rise Time

50

300

1000

r

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: A heat sink may be required to keep the junction temperature

below the absolute maximum when the output is shorted indefinitely.

Note 3: The LTC6903CMS8, LTC6904CMS8, LTC6903IMS8 and

LTC6904IMS8 are guaranteed functional over the operating temperature

range of –40°C to 85°C.

performance from –40°C to 85°C but are not tested or QA sampled

at these temperatures. The LTC6903IMS8 and LTC6904IMS8 are

guaranteed to meet the specified performance limits over the –40°C to

85°C temperature range. The LTC6903HMS8 and LTC6904HMS8 are

guaranteed to meet the specified performance limits over the –40°C to

125°C temperature range. The LTC6904MPMS8 is guaranteed to meet the

specified performance limits over the –55°C to 125°C temperature range.

Note 5: All values are referenced to V and V levels.

IH

IL

Note 6: Guaranteed by design and not subject to test.

Note 4: The LTC6903CMS8 and LTC6904CMS8 are guaranteed to meet

the specified performance limits over the 0°C to 70°C temperature range

and are designed, characterized and expected to meet the specified

Note 7: Parts with tighter frequency accuracy are available. Consult LTC

Marketing for details.

69034fe

4

LTC6903/LTC6904

Typical perForMance characTerisTics

Integral Nonlinearity

Differential Nonlinearity

Frequency vs Temperature

1.0

0.8

1.0

0.8

0.10

0.08

0.06

0.04

0.02

0

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.02

–0.04

–0.06

–0.08

–0.10

0

200

400

600

800

1000

0

200

400

600

800

1000

–40 –20

0

20 40 60 80 100 120

DAC SETTING

TEMPERATURE (°C)

69034 G01

69034 G03

Supply Current vs Output

Frequency

Output Resistance vs Supply

Voltage

Peak-to-Peak Jitter vs Frequency

60

50

40

30

20

10

0

10

9

8

7

6

5

4

3

2

1

0

+

V

= 3V

1

0.1

+

V

1

= 5V

+

V

= 3V

0.01

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0.1

1

10

100

0.001

0.01

0.1

10

100

SUPPLY VOLTAGE (V)

FREQUENCY (MHz)

69034 G06

69034 G04

69034 G05

Output Spectrum at 20MHz

Output Waveform at 68MHz

Output Waveform at 20MHz

20

0

C

V

= 10pF

= 3V

5ns/DIV

69034 G08

C

V

= 10pF

= 3V

10ns/DIV

69034 G08

L

+

L

+

–80

15MHz

20MHz

25MHz

69034 G07

69034fe

5

LTC6903/LTC6904

pin FuncTions

GND (Pin 1): Negative Power Supply (Ground). Should

be tied directly to a ground plane for best performance.

CLK (Pin 5): Auxiliary Clock Output. Frequency set by

serial port.

SDI (Pin 2): Serial Data Input. Data for serial transfer is

CLK(Pin6):MainClockOutput.Frequencysetbyserialport.

presented on this pin.

OE (Pin 7): Asynchronous Output Enable. CLK and CLK

are set LOW when this pin is LOW.

SCK (Pin 3): Serial Port Clock. Input, positive edge trig-

gered. Clocks serial data in on rising edge.

+

V (Pin 8): Positive Power Supply. This supply must be

SEN (Pin 4): Serial Port Enable (LTC6903 Only). Input,

activeLOW.InitiatesserialtransactionwhenbroughtLOW,

finalizes transaction when brought HIGH after 16 clocks.

kept free from noise and ripple. It should be bypassed

directly to a ground plane with a quality 0.1µF capacitor.

Additional bypass may be necessary for operation at high

frequency or under larger loads.

ADR (Pin 4): Serial Port Address (LTC6904 Only). Sets

2

the I C serial port address.

block DiagraM

+

V

OE

7

CLK

6

CLK

8

5

+

–

+

–

MASTER

PROGRAMMABLE

DIVIDER

A1

OSCILLATOR

I

SET

I

SET

f

= 68MHz • kΩ

MO

+

V

– V

SET

V

SET

DAC

OCT

SERIAL PORT

1

2

SDI

3

4

69034 BD

GND

SCK

SEN (LTC6903)

ADR (LTC6904)

69034fe

6

LTC6903/LTC6904

TiMing DiagraMs

LTC6903 Timing Diagram

SEN

SCK

SDI

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

69034 TD01

LTC6904 Timing Diagram

SDA

SCL

t

SU, STA

BUF

SU, DAT

t

SU, STO

t

LOW

HD, STA

HD, DAT

69034 TD02

t

HIGH

HD, STA

t

f

r

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

START

CONDITION

LTC6904 Typical Input Waveform—

Programming Frequency to 68MHz (ADR Pin Set LOW)

ADDRESS

0

1

0

1

ADR WR

OCT3 OCT2 OCT1 OCT0 DAC9 DAC8 DAC7 DAC6

DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CNF1 CNF0

START

STOP

SDA

SCL

0

1

0

1

7

0

8

ACK

9

1

2

1

3

1

4

1

5

1

6

1

7

1

8

ACK

9

1

2

1

3

1

4

1

5

1

6

0

7

0

8

ACK

9

1

2

3

4

5

6

69034 TD03

69034fe

7

LTC6903/LTC6904

Theory oF operaTion

The LTC6903/LTC6904 contain an internal feedback loop

which controls a high frequency square wave VCO oper-

ating between 34MHz and 68MHz. The internal feedback

loop frequency is set over an octave by a 10-bit resistor

DAC. The VCO tracks the internal feedback loop frequency

and the output frequency of the VCO is divided by one of

sixteen possible powers of two.

lower frequency ranges is very low because of the high

output divisor.

The higher frequency settings will display some deter-

ministic jitter from coupling between the control loop

and the output. This shows up in the frequency spectrum

as spurs separated from the fundamental frequency by

1MHz to 2MHz.

Higher VCO frequencies and lower output divider settings

can result in higher output jitter. Random jitter at the

applicaTions inForMaTion

Frequency Setting Information

4.25MHz and 8.5MHz yielding an OCT value of 12 or

1100. Substituting the OCT value of 12 and the desired

frequencyof6.5MHzintothepreviousequationresultsin:

The frequency output of the LTC6903/LTC6904 is deter-

mined by the following equation:

2078(Hz)•2^(10+12)

2078(Hz)

f = 2^OCT

•

DAC = 2048–

= 707.113

DAC













6.5e6(Hz)

2 –

1024

Rounding 707.113 to the nearest integer yields a DAC

value of 707 (or a 10-bit digital word of 1011000011.)

where DAC is the integer value from 0-1023 represented

by the serial port register bits DAC[9:0] and OCT is the

integer value from 0-15 represented by the serial port

register bits OCT [3:0].

Table 1. Output Frequency Range vs OCT Settling

(Frequency Resolution 0.001 • f)

f ≥

f <

OCT

15

14

13

12

11

10

9

34.05MHz

17.02MHz

8.511MHz

4.256MHz

2.128MHz

1.064MHz

532kHz

68.03MHz

34.01MHz

17.01MHz

8.503MHz

4.252MHz

2.126MHz

1063kHz

531.4kHz

265.7kHz

132.9kHz

66.43kHz

33.22kHz

16.61kHz

8.304kHz

4.152kHz

2.076kHz

Use the following two steps to choose binary numbers

“OCT” and “DAC” in order to set frequency “f”:

1) Use Table 1 to Choose “OCT” or use the following

formula, rounding down to the integer value less than or

equal to the result.

f











OCT = 3.322log



266kHz

8

1039

133kHz

7

2) Choose “DAC” by the following formula, rounding DAC

to the nearest integer:

66.5kHz

6

33.25kHz

16.62kHz

8.312kHz

4.156kHz

2.078kHz

1.039kHz

5

4

2078(Hz)•2^(10+OCT)

DAC = 2048–

3

f

2

1

For example, to set a frequency of 6.5MHz, first look

at Table 1 to find an OCT value. 6.5MHz falls between

0

69034fe

8

LTC6903/LTC6904

applicaTions inForMaTion

Power-Up State

Power Supply Bypass

When power is first applied to the LTC6903/LTC6904, In order to obtain the accuracies represented in this data

all register values are automatically reset to 0. This results

sheet, it is necessary to provide excellent bypass on the

inanoutputfrequencyof1.039kHzwithbothoutputsactive. power supply. Adequate bypass is a 1µF capacitor in

parallel with a 0.01µF capacitor connected within a few

Output Spectrum

millimeters of the power supply leads.

In most frequency ranges, the output of the LTC6903/

LTC6904 is generated as a division of the higher internal

Monotonicity and Linearity

clock frequency. This helps to minimize jitter and sub- The DAC in the LTC6903/LTC6904 is guaranteed to be

harmonics at the output of the device. In the highest

frequency ranges, the division ratio is reduced, which

will result in greater cycle-to-cycle jitter as well as spurs

at the internal sampling frequency. Because the internal

control loop runs at 1MHz to 2MHz without regard to the

output frequency, output spurs separated from the set

frequency by 1MHz to 2MHz may be observed. These

spurs are characteristically more than 30dB below the

level of the set frequency.

10-bitmonotonic. NonlinearityoftheDACislessthan1%.

Additionally, the LTC6903/LTC6904 is guaranteed to be

monotonic when switching between octaves with the

OCT setting bits. For example, the frequency output with

a DAC setting of “1111111111” and an OCT setting of

“1100” will always be lower than the frequency output

with a DAC setting of “0000000000” and an OCT setting

of “1101”. Linearity at these transition points is typically

around 3 LSBs.

Frequency Settling

Output Loading and Accuracy

When frequency settings change, the settling time and

shapedifferdependingonwhichbitsarechanged.Changing

only the OCT bits will result in an instantaneous change

in frequency for OCT values below 10. Values of 10 and

above may take up to 100µs to settle due to the action of

internal power conservation circuitry.

ImproperloadingoftheoutputsoftheLTC6903/LTC6904,

especially with poorpowersupply bypassing, willresult in

accuracyproblems. Atlowfrequencies, capacitiveloading

ofthe outputis not a concern. Atfrequencies above 1MHz,

attention should be paid to minimize the capacitive load

on the CLK and CLK pins.

Changing the DAC bits will result in a smooth transition

between the frequencies, occupying at most 100µs, with

little overshoot.

The LTC6903/LTC6904 is designed to drive up to 5pF

on each output with no degradation in accuracy. 5pF is

equivalent to one to two HC series logic inputs. A standard

10x oscilloscope probe usually presents between 10pF

and 15pF of capacitive load.

Changing both the OCT and DAC bits simultaneously may

result in considerable excursion beyond the frequencies

requested before settling.

It is strongly suggested that a high speed buffer is used

It should be noted that changing the DAC bits at the lower when driving more than one or two logic inputs, when

frequency ranges will result in a seemingly instantaneous driving a line more than 5 centimeters in length, or a

frequency change because the settling time depends on capacitive load greater than 5pF.

the internal loop frequency rather than the set frequency.

69034fe

9

LTC6903/LTC6904

applicaTions inForMaTion

Output Control

Serial Port Register Description

The CLK and CLK outputs of the LTC6903/LTC6904 are

individually controllable through the serial port as de-

scribed in Table 2 below. The low power mode may also

be accessed through these control bits. It is preferred

that unused outputs be disabled in order to reduce power

dissipation and improve accuracy.

OCT[3:0] – Frequency Divider Setting. (See Frequency

Setting Information Section)

DAC[9:0] – Master Oscillator Frequency Setting. (See

Frequency Setting Information Section)

CNF[1:0] – Output Configuration. This controls outputs

CLK and CLK according to Table 2.

Disabling an unused output will improve accuracy of

operation at frequencies above 1MHz. An unused output

running with no load typically degrades frequency ac-

curacy up to 0.2% at 68MHz. An unused output running

into a 5pF load typically degrades frequency accuracy up

to 0.5% at 68MHz.

LTC6903 SPI Compatible Interface

A serial data transfer is composed of sixteen (16) bits of

data labeled D15 through D0. D15 is the first bit of data

presented in each transaction. All serial port register bits

are set LOW on power-up.

Table 2. Output Configuration

Writing Data (LTC6903 Only)

CNF1

CNF0

CLK

ON

CLK

CLK + 180°

ON

0

1

0

1

0

1

When the SEN line is brought LOW, serial data presented

on the SDI input is clocked in on the rising edges of SCK

until SEN is brought HIGH. On every eighth rising edge

of SCK, the preceding 8-bits of data are clocked into the

internal register. It is therefore possible to clock in only

the 8 {D15 - D8} most significant bits of data rather than

completing an entire transfer.

OFF

ON

OFF

Powered-Down*

*Powered-Down: When in this mode, the chip is in a low power state

and will require approximately 100µs to recover. This is not the same

effect as the OE pin, which is fast, but uses more power supply current.

Serial Port Bitmap (LTC6903/LTC6904)

(All serial port register bits default LOW at power up)

Table 3

The serial data transfer starts with the most significant

bit and ends with the least significant bit of the data, as

shown in the Timing Diagrams section.

D15

OCT3

D7

D14

OCT2

D6

D13

OCT1

D5

D12

D11

D10

D9

D8

OCT0 DAC9 DAC8 DAC7 DAC6

D4

D3

D2

D1

D0

DAC5 DAC4 DAC3 DAC2 DAC1 DAC0

CNF1

CNF0

69034fe

10

LTC6903/LTC6904

applicaTions inForMaTion

LTC6904 I C Interface

2

generated by the slave lets the master know that the latest

byteofinformationwasreceived.Theacknowledgerelated

clockpulseisgeneratedbythemaster.Themasterreleases

the SDA line (HIGH) during the acknowledge clock pulse.

The slave-receiver must pull down the SDA line during the

acknowledge clock pulse so that it remains a stable LOW

during the HIGH period of this clock pulse.

TheLTC6904communicateswithahost(master)usingthe

2

standard I C 2-wire interface. The Timing Diagram shows

the timing relationship of the signals on the bus. The two

bus lines, SDA and SCL, must be HIGH when the bus is

not in use. External pull-up resistors or current sources,

such as the LTC1694 SMBus accelerator, are required on

2

theselines. IftheI Cinterfaceisnotdrivenwithastandard

Write Word Protocol

2

I C compatible device, care must be taken to ensure that

The master initiates communication with the LTC6904

with a START condition and a 7-bit address followed by

the write bit (Wr) = 0. The LTC6904 acknowledges and

the master delivers the most significant data byte. Again

the LTC6904 acknowledges and the data is latched into

the most significant data byte input register. The master

then delivers the least significant data byte. The LTC6904

acknowledges once more and latches the data into the

leastsignificantdatabyteinputregister. Lastly, themaster

terminates the communication with a STOP condition.

the SDA line is released during the ACK cycle to prevent

bus contention.

The LTC6904 is a receive-only (slave) device. The master

can communicate with the LTC6904 using the write word

protocols as explained later.

The START and STOP Conditions

When the bus is not in use, both SCL and SDA must be

HIGH.Abusmastersignalsthebeginningofacommunica-

tion to a slave device by transmitting a START condition. A

START condition is generated by transitioning SDA from

HIGH to LOW while SCL is HIGH.

Slave Address

The LTC6904 can respond to one of two 7-bit addresses.

The first 6 bits (MSBs) have been factory programmed

to 001011. The address pin, ADR (Pin 4) is programmed

by the user and determines the LSB of the slave address,

as shown in the table below:

When the master has finished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from LOW to HIGH while

SCL is HIGH. The bus is then free for communication with

another SMBus device.

ADR (Pin 4)

LTC6904 Address

0010111

0

1

Acknowledge

0010110

The acknowledge signal is used for handshaking between

the master and the slave. An acknowledge (active LOW)

Write Word Protocol Used by the LTC6904

1

7

1

8

1

8

1

S

Slave Address Wr

A

MS Data Byte

A

LS Data Byte

A

P

S = START Condition, Wr = Write Bit = 0, A = Acknowledge, P = STOP Condition

69034 F01

69034fe

11

LTC6903/LTC6904

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660 Rev F)

0.889 0.127

(.035 .005)

5.23

3.20 – 3.45

(.206)

(.126 – .136)

MIN

3.00 0.102

(.118 .004)

(NOTE 3)

0.52

(.0205)

REF

0.65

(.0256)

BSC

0.42 0.038

(.0165 .0015)

TYP

8

7 6 5

RECOMMENDED SOLDER PAD LAYOUT

3.00 0.102

(.118 .004)

(NOTE 4)

4.90 0.152

(.193 .006)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

1

2

3

4

0.53 0.152

(.021 .006)

1.10

(.043)

MAX

0.86

(.034)

REF

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

0.1016 0.0508

(.009 – .015)

(.004 .002)

0.65

(.0256)

BSC

TYP

MSOP (MS8) 0307 REV F

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

69034fe

12

LTC6903/LTC6904

revision hisTory ^{(Revision history begins at Rev D)}

REV

DATE

DESCRIPTION

PAGE NUMBER

D

12/11 Corrected LTC6903 Timing Diagram.

7

Corrected references to Frequency Setting Information section within Serial Port Register Description section.

Updated Absolute Maximum Ratings and Order Information.

10

2

E

3/12

Revised Notes 3 and 4 in Timing Characteristics.

4

69034fe

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

13

LTC6903/LTC6904

Typical applicaTion

Wide Range Time Interval Generator (1.97 Seconds to 4 Microseconds)

+

V

1

CLK

< TRIGGER PULSE WIDTH < OUTPUT PULSE WIDTH

f

4

2

5

6

D

PS

U4

R

Q

TRIG

+

V

3

C2

CLK

Q

0.1µF

1

74HC74-A

PHILIPS SEMICONDUCTOR

1

2

3

4

8

7

6

5

+

GND

V

C1, 0.1µF

SDI

OE

CLK

+

V

+

U6

LTC6903

V

16

CLK

C3

10

9

Q1

7

0.1µF

SCK

SEN

n

OUTPUT

PULSE

WIDTH

2

f

CLK

=

Q2

6

f

CLK

Q3

5

10

PS

16

SEN

Q4

3

12

11

9

8

4

3

2

6

5

D

Q

V

OUT

D0

D1

D2

D3

D4

D5

D6

D7

S0

S1

S2

OE

Y

Q5

2

U5

R

Q6

4

Y

CLK

Q

Q7

13

Q8

12

Q9

14

Q10

15

Q11

1

OUT

1

Q

OUT

13

15

14

13

12

11

10

9

+

V

U1

74HC74-B

PHILIPS

SEMICONDUCTOR

11

MR

Q12

8

74HC4040

PHILIPS

SEMICONDUCTOR

7

S0

S1

S2

8

74HC251

PHILIPS

SEMICONDUCTOR

MUX SELECT ADDRESS LINES

69034 TA02

MUX INPUTS

S1

Output

Pulse Width

S2

S0

n

0

1

0

1

0

4

5

6

16/f

32/f

64/f

CLK

1

0

1

0

1

0

1

0

1

7

8

128/f

256/f

512/f

CLK

9

10

1024/f

CLK

1

11

2048/f

CLK

relaTeD parTs

PART NUMBER

LTC1799

DESCRIPTION

COMMENTS

™

1kHz to 30MHz ThinSOT Oscillator

1kHz to 20MHz ThinSOT Oscillator

Single Output, Higher Frequency Operation

Single Output, Lower Power

LTC6900

LTC6902

Mulitphase Oscillator with Spread Spectrum Modulation

1, 3 or 4-Phase Outputs

69034fe

LT 0312 REV E • PRINTED IN USA

14 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2003

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC6903IMS8#TR
厂家：	Linear
描述：	LTC6903 - 1kHz - 68MHz Serial Port Programmable Oscillator; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C 机械输出元件振荡器
文件：	总14页 (文件大小：228K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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