LTC6904CMS8#PBF [Linear]
LTC6904 - 1kHz - 68MHz Serial Port Programmable Oscillator; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LTC6904CMS8#PBF |
| 厂家： | 
Linear |
| 描述： | LTC6904 - 1kHz - 68MHz Serial Port Programmable Oscillator; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C 振荡器 |
| 文件： | 总12页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6903/LTC6904
1kHz - 68MHz Serial
Port Programmable Oscillator
U
DESCRIPTIO
FEATURES
The LTC®6903/LTC6904 are low power self contained
digital frequency sources providing a precision frequency
from 1kHz to 68MHz, set through a serial port. The
LTC6903/LTC6904 require no external components other
than a power supply bypass capacitor, and they operate
over a single wide supply range of 2.7V to 5.5V.
■
1kHz to 68MHz Square Wave Output
■
0.5% (Typ) Initial Frequency Accuracy
■
Frequency Error <1.1% Over All Settings
10ppm/°C Typical Frequency Drift Over
Temperature
0.1% Resolution
■
■
■
1.7mA Typical Supply Current (f < 1MHz, VS = 2.7V)
The LTC6903/LTC6904 feature a proprietary feedback
loopthatlinearizestherelationshipbetweendigitalcontrol
settingandfrequency,resultinginaverysimplefrequency
setting equation:
■
2.7V to 5.5V Single Supply Operation
■
Jitter <0.4% Typical 1kHz to 8MHz
Easy to Use SPI (LTC6903) or I2C (LTC6904) Serial
■
Interface
Output Enable Pin
–40°C to 125°C Operation
2078(Hz)
f = 2OCT
•
;1kHz < f < 68MHz
■
DAC
1024
■
2 –
■
MS8 Package
WhereOCTisa4-bitdigitalcodeandDACisa10-bitdigital
code.
U
APPLICATIO S
TheLTC6903iscontrolledbyaconvenientSPIcompatible
serial interface. The LTC6904 uses an industry standard
I2C compatible interface.
■
Precision Digitally Controlled Oscillator
■
Power Management
■
Direct Digital Frequency Synthesis (DDS)
, LTC and LT are registered trademarks of Linear Technology Corporation.
U.S. Patent Numbers 6342817 and 6614313.
Replacement
■
Replacement for DAC and VCO
Switched Capacitor Filter Clock
■
U
TYPICAL APPLICATIO
LTC6903 Frequency Error
Distribution
A Microcontroller Controlling Its Clock
40
V
= 3V
= 25°C
f = 1039Hz
443
UNITS
TESTED
S
A
T
5V
+
30
20
10
0
GND
SDI
V
MICROCONTROLLER
OSC1/CLKIN
OE
OSC2/CLKOUT
RC5/SDO
10k
LTC6903
MCLR/V
P–P
10Ω
SCK
SEN
CLK
CLK
RC3/SCK/SCL
RC2/CCP1
1µF
5V
0.1µF
V
DD
V
SS
V
SS
0.01µF
POWER-UP CLOCK
FREQUENCY IS 1039Hz
PIC16F73
–1.0
–0.5
0
0.5
1.0
6903 TA01
FREQUENCY ERROR (%)
6903 TA01b
69034fa
1
LTC6903/LTC6904
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
Total Supply Voltage (V+ to GND) .............................. 6V
Maximum Voltage on any Pin
........................... (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V)
Output Short Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range (Note 3)
LTC6903CMS8
LTC6903IMS8
LTC6903HMS8
LTC6904CMS8
LTC6904IMS8
LTC6904HMS8
TOP VIEW
+
GND
SDI
SCK
1
2
3
4
8 V
7 OE
6 CLK
5 CLK
LTC6903CMS8/LTC6904CMS8 ........... –40°C to 85°C
LTC6903IMS8/LTC6904IMS8 ............. –40°C to 85°C
LTC6903HMS8/LTC6904HMS8 ......... –40°C to 125°C
Specified Temperature Range (Note 4)
LTC6903CMS8/LTC6904CMS8 ........... –40°C to 85°C
LTC6903IMS8/LTC6904IMS8 ............. –40°C to 85°C
LTC6903HMS8/LTC6904HMS8 ......... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10sec)................... 300°C
SEN/ADR*
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 200°C/W
MS8 PART MARKING*
LTABN
LTAES
*SEN (LTC6903)
ADR (LTC6904)
*The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
∆fi
∆f
Initial Frequency Accuracy
Total Frequency Accuracy (Note 7)
f = 1.039kHz, V = 3V, C
= 5pF
±0.75
%
LOAD
Single Output Active:
Over All Settings, V = 2.7V, C
Over All Settings, V = 5.5V, C
+
= 5pF
= 5pF
0.5
0.5
1.1
1.6
%
%
LOAD
LOAD
+
LTC6903CMS8, LTC6904CMS8:
+
Over All Settings, V = 2.7V, C
= 5pF
= 5pF
●
●
0.5
0.5
1.65
2
%
%
LOAD
+
Over All Settings, V = 5.5V, C
LOAD
LTC6903HMS8, LTC6903IMS8,
LTC6904HMS8, LTC6904IMS8:
+
Over All Settings, V = 2.7V, C
= 5pF
= 5pF
●
●
0.5
0.5
1.9
2.2
%
%
LOAD
LOAD
+
Over All Settings, V = 5.5V, C
f
f
Maximum Operating Frequency
Minimum Operating Frequency
Frequency Drift Over Temperature
Frequency Drift Over Supply
68
1.039
10
MHz
kHz
MAX
MIN
∆f/∆T
∆f/∆V
ppm/°C
%/V
0.05
300
Long Term Frequency Stability
ppm/√kHr
Timing Jitter
(See Graph)
1.039kHz to 8.5MHz
1.039kHz to 68MHz
0.4
1
%
%
Duty Cycle
1.039kHz to 1MHz
1.039kHz to 68MHz
●
49
50
50
51
%
%
+
R
OUT
Output Resistance
CLK, CLK Pins, V = 2.7V
45
Ω
+
V
High Level Output Voltage
V = 5.5V, 4mA Load
●
●
4.8
2
5.3
2.3
V
V
OH
+
V = 2.7V, 4mA Load
+
V = 5.5V, 1mA Load
●
●
5.2
2.3
5.45
2.55
V
V
+
V = 2.7V, 1mA Load
+
V
Low Level Output Voltage
V = 5.5V, 4mA Load
●
●
0.15
0.25
0.3
0.45
V
V
OL
+
V = 2.7V, 4mA Load
+
V = 5.5V, 1mA Load
●
●
0.05
0.05
0.15
0.2
V
V
+
V = 2.7V, 1mA Load
69034fa
2
LTC6903/LTC6904
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
t
Output Rise Time (10% - 90%)
V = 5.5V, R
V = 2.7V, R
= ∞, C
= ∞, C
= 5pF
= 5pF
1
1
ns
ns
r
f
LOAD
LOAD
LOAD
LOAD
+
+
t
Output Fall Time (10% - 90%)
V = 5.5V, R
= ∞, C
= ∞, C
= 5pF
= 5pF
1
1
ns
ns
LOAD
LOAD
LOAD
LOAD
+
V = 2.7V, R
W U
POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. V+ = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
Applied Between V and GND
V = 2.7V
MIN
TYP
MAX
UNITS
+
V
Supply Voltage
●
2.7
5.5
V
S
+
I , SHDN
S
V Supply Current, Shutdown
●
●
0.25
0.6
0.6
2.2
mA
mA
S
V = 5.5V
S
+
+
I , DC
S
V Supply Current, Single Output
f = 68MHz, 5pF Load, V = 2.7V
f < 1MHz, V = 2.7V
f = 68MHz, 5pF Load, V = 5.5V
●
●
●
●
3.6
1.7
7
7
mA
mA
mA
mA
+
Enabled
3.1
15
4.5
+
+
f < 1MHz, V = 5.5V
1.9
SERIAL PORT ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
V
V
Min High Level Input Voltage
SEN, SCK, SDI Pins
●
●
●
0.67 V
V
IH
IL
+
Max Low Level Input Voltage
SEN, SCK, SDI Pins
0.33 V
V
I
Digital Input Leakage
SEN, SCK, SDI Pins
10
µA
IN
W U
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. V+ = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
LTC6903 (Notes 5, 6)
f
t
t
t
t
t
t
Serial Port Clock Frequency
Min Clock High Time
●
●
●
●
●
●
●
20
25
MHz
ns
SCK
CKHI
CKLO
su
Min Clock Low Time
25
ns
Min Setup Time - SDI to SCK
Min Hold Time - SCK to SDI
Min Latch Time - SEN to SEN
Min First Clock - SEN to SCK
10
ns
10
ns
hLD
LCH
FCK
400
20
ns
ns
LTC6904 (Notes 5, 6)
f
t
t
t
t
SMBus Operating Frequency
●
●
●
●
●
10
4.7
4.0
4.7
4.0
100
kHz
µs
SMB
Bus Free Time Between Stop and Start Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
BUF
µs
HD, STA
SU, STA
SU, STO
µs
µs
69034fa
3
LTC6903/LTC6904
W U
The ● denotes specifications which apply over the full operating temperature
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. V+ = 2.7V to 5.5V, GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
LTC6904 (Notes 5, 6)
t
t
t
t
t
t
Data Hold Time
●
●
●
●
●
●
300
250
4.7
4.0
ns
ns
µs
µs
ns
ns
HD, DAT
Data Setup Time
SU, DAT
Clock Low Period
Clock High Period
Clock, Data Fall Time
Clock, Data Rise Time
LOW
50
HIGH
300
f
1000
r
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: A heatsink may be required to keep the junction temperature
below the absolute maximum when the output is shorted indefinitely.
Note 3: The LTC6903CMS8, LTC6904CMS8, LTC6903IMS8, and
LTC6904IMS8 are guaranteed functional over the operating temperature
range of –40°C to 85°C. The LTC6903HMS8 and LTC6904HMS8 are
guaranteed functional over the extended operating temperature range of
–40°C to 125°C.
and are designed, characterized and expected to meet the specified
performance from –40°C to 85°C but are not tested or QA sampled at
these temperatures. The LTC6903IMS8 and LTC6904IMS8 are guaranteed
to meet the specified performance limits over the –40°C to 85°C
temperature range. The LTC6903HMS8 and LTC6904HMS8 are
guaranteed to meet the specified performance limits over the –40°C to
125°C temperature range.
Note 5: All values are referenced to V and V levels.
IH
IL
Note 6: Guaranteed by design and not subject to test.
Note 4: The LTC6903CMS8 and LTC6904CMS8 are guaranteed to meet
the specified performance limits over the 0°C to 70°C temperature range
Note 7: Parts with tighter frequency accuracy are available. Consult LTC
Marketing for details.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Differential Nonlinearity
Frequency vs Temperature
Integral Nonlinearity
0.10
0.08
0.06
0.04
0.02
0
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–40 –20
0
20 40 60 80 100 120
0
200
400
600
800
1000
0
200
400
600
800
1000
TEMPERATURE (°C)
DAC SETTING
DAC SETTING
6903 G03
6903 G01
6903 G01
69034fa
4
LTC6903/LTC6904
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Output
Output Resistance vs Supply
Frequency
Peak-to-Peak Jitter vs Frequency
Voltage
10
10
9
8
7
6
5
4
3
2
1
0
60
+
V
= 3V
50
40
30
20
10
0
1
0.1
+
V
1
= 5V
+
V
= 3V
0.01
0.1
1
10
100
0.001
0.01
0.1
10
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
FREQUENCY (MHz)
FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
6903 G04
6903 G05
6903 G06
Output Waveform at 20MHz
Output Spectrum at 20MHz
Output Waveform at 68MHz
20
0
CL = 10pF
V+ = 3V
5ns/DIV
CL = 10pF
V+ = 3V
10ns/DIV
3468 G08
3468 G09
–80
15MHz
20MHz
25MHz
6903 G07
U
U
U
PI FU CTIO S
GND (Pin 1):Negative Power Supply (Ground). Should be
tied directly to a ground plane for best performance.
CLK (Pin 5): Auxiliary Clock Output. Frequency set by
serial port.
SDI ( Pin 2 ): Serial Data Input. Data for serial transfer is
presented on this pin.
CLK (Pin 6): Main Clock Output. Frequency set by serial
port.
SCK (Pin 3): Serial Port Clock. Input, positive edge trig-
gered. Clocks serial data in on rising edge.
OE(Pin7):AsynchronousOutputEnable.CLKandCLKare
set LOW when this pin is LOW.
SEN (Pin 4): Serial Port Enable (6903 Only). Input, active
LOW. Initiates serial transaction when brought LOW,
finalizes transaction when brought HIGH after 16 clocks.
ADR(Pin4):SerialPortAddress(6904Only). SetstheI2C
serial port address.
V+ (Pin 8): Positive Power Supply. This supply must be
kept free from noise and ripple. It should be bypassed
directly to a ground plane with a quality 0.1µF capacitor.
Additional bypass may be necessary for operation at high
frequency or under larger loads.
69034fa
5
LTC6903/LTC6904
W
BLOCK DIAGRA
+
V
OE
7
CLK
6
CLK
5
8
+
–
+
–
MASTER
PROGRAMMABLE
DIVIDER
A1
OSCILLATOR
I
SET
I
SET
f
= 68MHz • kΩ
MO
+
V
– V
SET
V
SET
DAC
OCT
SERIAL PORT
1
2
SDI
3
4
6903 BD
GND
SCK
SEN (LTC6903)
ADR (LTC6904)
U
THEORY OF OPERATIO
The LTC6903/LTC6904 contain an internal feedback loop
which controls a high frequency square wave VCO operat-
ing between 34MHz and 68MHz. The internal feedback
loop frequency is set over an octave by a 10-bit resistor
DAC. The VCO tracks the internal feedback loop frequency
and the output frequency of the VCO is divided by one of
sixteen possible powers of two.
frequency ranges is very low because of the high output
divisor.
The higher frequency settings will display some determin-
istic jitter from coupling between the control loop and the
output. This shows up in the frequency spectrum as spurs
separated from the fundamental frequency by 1MHz to
2MHz.
Higher VCO frequencies and lower output divider settings
canresultinhigheroutputjitter. Randomjitteratthelower
U
W U U
APPLICATIO S I FOR ATIO
Use the following two steps to choose binary numbers
“OCT” and “DAC” in order to set frequency “f”:
Frequency Setting Information
The frequency output of the LTC6903/LTC6904 is deter-
mined by the following equation:
1) Use Table 1 to Choose “OCT” or use the following
formula, rounding down to the integer value less than or
equal to the result.
2078(Hz)
f = 2OCT
•
DAC
2 –
f
OCT = 3.322log
1039
1024
where DAC is the integer value from 0-1023 represented
by the serial port register bits DAC[9:0] and OCT is the
integer value from 0-15 represented by the serial port
register bits OCT [3:0].
2) Choose “DAC” by the following formula, rounding DAC
to the nearest integer:
2078(Hz)• 2(10+OCT)
DAC = 2048 –
f
69034fa
6
LTC6903/LTC6904
U
W U U
APPLICATIO S I FOR ATIO
Table 1. Output Frequency Range vs OCT Setting
clock frequency. This helps to minimize jitter and sub-
harmonics at the output of the device. In the highest
frequency ranges, the division ratio is reduced, which will
result in greater cycle-to-cycle jitter as well as spurs at the
internal sampling frequency. Because the internal control
loop runs at 1MHz to 2MHz without regard to the output
frequency, output spurs separated from the set frequency
by 1MHz to 2MHz may be observed. These spurs are
characteristicallymorethan30dBbelowtheleveloftheset
frequency.
(Frequency Resolution 0.001 • f)
f ≥
f <
OCT
15
14
13
12
11
10
9
34.05MHz
17.02MHz
8.511MHz
4.256MHz
2.128MHz
1.064MHz
532kHz
68.03MHz
34.01MHz
17.01MHz
8.503MHz
4.252MHz
2.126MHz
1063kHz
531.4kHz
265.7kHz
132.9kHz
66.43kHz
33.22kHz
16.61kHz
8.304kHz
4.152kHz
2.076kHz
266kHz
8
Frequency Settling
133kHz
7
66.5kHz
6
When frequency settings change, the settling time and
shape differdepending onwhich bits are changed. Chang-
ingonlytheOCTbitswillresultinaninstantaneouschange
in frequency for OCT values below 10. Values of 10 and
above may take up to 100µs to settle due to the action of
internal power conservation circuitry.
33.25kHz
16.62kHz
8.312kHz
4.156kHz
2.078kHz
1.039kHz
5
4
3
2
1
0
Changing the DAC bits will result in a smooth transition
between the frequencies, occupying at most 100µs, with
little overshoot.
For example, to set a frequency of 6.5MHz, first look at
Table 1 to find an OCT value. 6.5MHz falls between
4.25MHz and 8.5MHz yielding an OCT value of 12 or 1100.
SubstitutingtheOCTvalueof12andthedesiredfrequency
of 6.5MHz into the previous equation results in:
Changing both the OCT and DAC bits simultaneously may
result in considerable excursion beyond the frequencies
requested before settling.
It should be noted that changing the DAC bits at the lower
frequency ranges will result in a seemingly instantaneous
frequency change because the settling time depends on
the internal loop frequency rather than the set frequency.
2078(Hz)• 2(10+12)
DAC = 2048 –
= 707.113
6.5e6(Hz)
Rounding 707.113 to the nearest integer yields a DAC
value of 707 (or a 10-bit digital word of 1011000011.)
Power Supply Bypass
In order to obtain the accuracies represented in this
datasheet, it is necessary to provide excellent bypass on
the power supply. Adequate bypass is a 1µF capacitor in
parallel with a 0.01µF capacitor connected within a few
millimeters of the power supply leads.
Power Up State
When power is first applied to the LTC6903/LTC6904, all
register values are automatically reset to 0. This results in
an output frequency of 1.039kHz with both outputs active.
Output Spectrum
Monotonicity and Linearity
In most frequency ranges, the output of the LTC6903/
LTC6904 is generated as a division of the higher internal
The DAC in the LTC6903/LTC6904 is guaranteed to be
10-bitmonotonic. NonlinearityoftheDACislessthan1%.
69034fa
7
LTC6903/LTC6904
U
W U U
APPLICATIO S I FOR ATIO
Additionally, the LTC6903/LTC6904 is guaranteed to be
monotonic when switching between octaves with the OCT
setting bits. For example, the frequency output with a DAC
settingof“1111111111”andanOCTsettingof“1100”will
always be lower than the frequency output with a DAC
setting of “0000000000” and an OCT setting of “1101”.
Linearity at these transition points is typically around
3 LSBs.
Output Control
The CLK and CLK outputs of the LTC6903/LTC6904 are
individually controllable through the serial port as
described in Table 2 below. The low power mode may also
be accessed through these control bits. It is preferred that
unused outputs be disabled in order to reduce power
dissipation and improve accuracy.
Disabling an unused output will improve accuracy of
operation at frequencies above 1MHz. An unused output
running with no load typically degrades frequency accu-
racy up to 0.2% at 68MHz. An unused output running into
a 5pF load typically degrades frequency accuracy up to
0.5% at 68MHz.
Output Loading and Accuracy
ImproperloadingoftheoutputsoftheLTC6903/LTC6904,
especiallywithpoorpowersupplybypassing, willresult in
accuracyproblems. Atlowfrequencies, capacitiveloading
of theoutputisnota concern. Atfrequenciesabove 1MHz,
attentionshouldbepaidtominimizethecapacitiveloadon
the CLK and CLK pins.
Table 2. Output Configuration
CNF1
CNF0
CLK
ON
CLK
CLK + 180°
ON
0
0
1
1
0
1
0
1
The LTC6903/LTC6904 is designed to drive up to 5pF on
each output with no degradation in accuracy. 5pF is
equivalent to one to two HC series logic inputs. A standard
10x oscilloscope probe usually presents between 10pF
and 15pF of capacitive load.
OFF
ON
OFF
Powered-Down*
*Powered-Down:Wheninthismode,thechipisinalowpowerstateandwillrequireapproximately100µs
to recover. This is not the same effect as the OE pin, which is fast, but uses more power supply current.
It is strongly suggested that a high speed buffer is used
when driving more than one or two logic inputs, when
driving a line more than 5 centimeters in length, or a
capacitive load greater than 5pF.
Serial Port Bitmap (LTC6903/LTC6904)
(All serial port register bits default LOW at power up)
Table 3
D15
OCT3 OCT2 OCT1 OCT0 DAC9 DAC8 DAC7 DAC6
D7 D6 D5 D4 D3 D2 D1 D0
DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CNF1 CNF0
D14
D13
D12
D11
D10
D9
D8
Timing Diagram (LTC6903)
SEN
SCK
SDI
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
6903 TD01
69034fa
8
LTC6903/LTC6904
U
W U U
APPLICATIO S I FOR ATIO
Serial Port Register Description
Writing Data (LTC6903 Only)
OCT[3:0] - Frequency Divider Setting. (See Frequency
Setting Section)
When the SEN line is brought LOW, serial data presented
on the SDI input is clocked in on the rising edges of SCK
until SEN is brought HIGH. On every eighth rising edge of
SCK, the preceding 8-bits of data are clocked into the
internalregister. Itisthereforepossibletoclockinonlythe
8 {D15 - D8} most significant bits of data rather than
completing an entire transfer.
DAC[9:0] - Master Oscillator Frequency Setting. (See
Frequency Setting Section)
CNF[1:0] - Output Configuration - This controls outputs
CLK and CLK according to Table 2.
The serial data transfer starts with the most significant bit
andendswiththeleastsignificantbitofthedata, asshown
in the timing diagram.
LTC6903 SPI Compatible Interface
A serial data transfer is composed of sixteen (16) bits of
data labeled D15 through D0. D15 is the first bit of data
presented in each transaction. All serial port register bits
are set LOW on power-up.
W U
W
TI I G DIAGRA S
Timing Diagram (LTC6904)
SDA
t
t
t
SU, DAT
SU, STA
BUF
t
SU, STO
t
t
t
LOW
HD, STA
HD, DAT
6903 TD02
SCL
t
t
HIGH
HD, STA
t
r
t
f
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Typical LTC6904 Input Waveform—Programming Frequency to 68MHz (ADR Pin Set LOW)
ADDRESS
0
0
1
0
1
1
ADR WR
OCT3 OCT2 OCT1 OCT0 DAC9 DAC8 DAC7 DAC6
DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 CNF1 CNF0
START
STOP
SDA
SCL
0
0
1
0
1
1
1
7
0
8
ACK
9
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
ACK
9
1
1
1
2
1
3
1
4
1
5
1
6
0
7
0
8
ACK
9
1
2
3
4
5
6
6903 TD03
69034fa
9
LTC6903/LTC6904
U
TYPICAL APPLICATIO S
LTC6904 I2C Interface
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge re-
lated clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
line during the Acknowledge clock pulse so that it remains
a stable LOW during the HIGH period of this clock pulse.
The LTC6904 communicates with a host (master) using
the standard I2C 2-wire interface. The Timing Diagram
shows the timing relationship of the signals on the bus.
The two bus lines, SDA and SCL, must be high when the
bus is not in use. External pull-up resistors or current
sources, such as the LTC1694 SMBus Accelerator, are
required on these lines. If the I2C interface is not driven
with a standard I2C compatible device, care must be taken
to ensure that the SDA line is released during the ACK
cycle to prevent bus contention.
Write Word Protocol
The master initiates communication with the LTC6904
withaSTARTconditionanda7-bitaddressfollowedbythe
Write Bit (Wr) = 0. The LTC6904 acknowledges and the
master delivers the most significant data byte. Again the
LTC6904 acknowledges and the data is latched into the
most significant data byte input register. The master then
delivers the least significant data byte. The LTC6904
acknowledges once more and latches the data into the
least significant data byte input register. Lastly, the master
terminates the communication with a STOP condition.
The LTC6904 is a receive-only (slave) device. The master
cancommunicatewiththeLTC6904usingtheWriteWord
protocols as explained later.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communi-
cation to a slave device by transmitting a START condi-
tion. ASTARTconditionisgeneratedbytransitioningSDA
from high to low while SCL is high.
Slave Address
The LTC6904 can respond to one of two 7-bit addresses.
The first 6 bits (MSBs) have been factory programmed to
001011. The address pin, ADR (Pin 4) is programmed by
the user and determines the LSB of the slave address, as
shown in the table below:
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another SMBus device.
ADR (Pin 4)
LTC6904 Address
0010111
0
1
Acknowledge
0010110
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
Write Word Protocol Used by the LTC6904
1
7
1
1
8
1
8
1
1
S
Slave Address Wr
A
MS Data Byte
A
LS Data Byte
A
P
6903 AI01
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition
69034fa
10
LTC6903/LTC6904
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
0.52
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
TYP
(.0205)
REF
(NOTE 3)
8
7 6 5
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.152
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
0.127 ± 0.076
(.009 – .015)
(.005 ± .003)
0.65
(.0256)
BSC
TYP
MSOP (MS8) 0204
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
69034fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC6903/LTC6904
U
TYPICAL APPLICATIO
Wide Range Time Interval Generator (1.97 Seconds to 4 Microseconds)
1
CLK
< TRIGGER PULSE WIDTH < OUTPUT PULSE WIDTH
+
f
V
TRIG
4
2
3
5
6
+
V
D
PS
U4
R
Q
Q
CLK
C2
0.1µF
1
74HC74-A
PHILIPS SEMICONDUCTOR
1
8
7
6
5
+
GND
V
C1
0.1µF
2
3
4
+
SDI
SCK
SEN
SDI
OE
CLK
CLK
V
U6
LTC6903
+
V
16
CLK
C3
10
9
Q1
7
0.1µF
SCK
SEN
OUTPUT
PULSE
WIDTH
n
2
f
CLK
=
Q2
6
f
CLK
Q3
5
10
16
Q4
3
12
11
9
8
4
3
2
6
5
D
PS
U5
R
Q
Q
V
V
OUT
D0
D1
D2
D3
D4
D5
D6
D7
S0
S1
S2
OE
Y
Y
Q5
2
Q6
4
CLK
13
Q7
13
Q8
12
Q9
14
Q10
15
Q11
1
OUT
1
Q
OUT
15
14
13
12
11
10
9
+
V
U1
74HC74-B
PHILIPS
SEMICONDUCTOR
11
MR
Q12
8
74HC4040
PHILIPS
SEMICONDUCTOR
7
8
74HC251
PHILIPS
SEMICONDUCTOR
6903 TA02
S0
S1
S2
MUX SELECT ADDRESS LINES
MUX Inputs
S1
Output
Pulsewidth
S2
S0
n
0
1
0
0
0
1
0
0
0
4
5
6
16/f
32/f
64/f
CLK
CLK
CLK
1
0
1
0
1
0
0
1
0
1
1
1
7
8
9
128/f
256/f
512/f
CLK
CLK
CLK
10
1024/f
CLK
1
1
1
11
2048/f
CLK
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1799
1kHz to 30MHz ThinSOT™ Oscillator
1kHz to 20MHz ThinSOT Oscillator
Single Output, Higher Frequency Operation
Single Output, Lower Power
LTC6900
LTC6902
Multiphase Oscillator with Spread Spectrum Modulation
2, 3 or 4-Phase Outputs
ThinSOT is a trademark of Linear Technology Corporation
69034fa
LT/TP 0404 1K REV A • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC6904CMS8#TRPBF
LTC6904 - 1kHz - 68MHz Serial Port Programmable Oscillator; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C
Linear
LTC6904HMS8#PBF
LTC6904 - 1kHz - 68MHz Serial Port Programmable Oscillator; Package: MSOP; Pins: 8; Temperature Range: -40°C to 125°C
Linear
LTC6904HMS8#TRPBF
LTC6904 - 1kHz - 68MHz Serial Port Programmable Oscillator; Package: MSOP; Pins: 8; Temperature Range: -40°C to 125°C
Linear
LTC6905CS5#TRM
LTC6905 - 17MHz to 170MHz Resistor Set SOT-23 Oscillator; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
Linear
LTC6905CS5#TRMPBF
LTC6905 - 17MHz to 170MHz Resistor Set SOT-23 Oscillator; Package: SOT; Pins: 5; Temperature Range: 0°C to 70°C
Linear
©2020 ICPDF网 联系我们和版权申明