LTC694CS8-3.3#TRPBF_技术文档

LTC694-3.3/LTC695-3.3

3.3V Microprocessor

Supervisory Circuits

FEATURES

DESCRIPTION

TheLTC^®694-3.3/LTC695-3.3providecomplete3.3Vpower

supply monitoring and battery control functions. These

include power-on reset, battery back-up, RAM write pro-

tection, power failure warning and watchdog timing. The

devicesarepincompatibleupgradesoftheLTC694/LTC695

that are optimized for 3.3V systems. Operating power

consumption has been reduced to 0.6mW (typical) and

3μW maximum in battery back-up mode. Microprocessor

reset and memory write protection are provided when the

supply falls below 2.9V. The RESET output is guaranteed

n

Guaranteed Reset Assertion at V = 1V

CC

n

Pin Compatible with LTC694/LTC695 for 3.3V Systems

n

200μA Typical Supply Current

Fast (30ns Typ) Onboard Gating of

RAM Chip Enable Signals

SO-8 and S16 Packages

2.90V Precision Voltage Monitor

n

Power OK/Reset Time Delay: 200ms or Adjustable

n

Minimum External Component Count

n

1μA Maximum Standby Current

n

Voltage Monitor for Power-Fail or

to remain logic low with V as low as 1V.

CC

Low-Battery Warning

Thermal Limiting

The LTC694-3.3/LTC695-3.3 power the active RAMs with

a charge pumped NMOS power switch to achieve low

dropout and low supply current. When primary power is

lost, auxiliary power, connected to the battery input pin,

powers the RAMs in standby through an efficient PMOS

switch.

n

Performance Specified Over Temperature

APPLICATIONS

n

3.3V Low Power Systems

n

For an early warning of impending power failure, the

LTC694-3.3/LTC695-3.3 provide an internal comparator

with a user-defined threshold. An internal watchdog timer

isalsoavailable,whichforcestheresetpinstoactivestates

when the watchdog input is not toggled prior to a preset

timeout period.

Critical μP Power Monitoring

n

Intelligent Instruments

n

Battery-Powered Computers and Controllers

n

Automotive Systems

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

RESET Output Voltage

vs Supply Voltage

LT1129-3.3

V

≥ 5V

IN

5

3.3V

V

POWER TO

μP

V

IN

OUT

CC

OUT

+

CMOS RAM POWER

0.1μF

100μF

0.1μF

2.4V

1μF

OUT SENSE

SHDN

GND

LTC695-3.3

μP

SYSTEM

DECODER OUTPUT

RAM CS

μP RESET

μP NMI

4

3

CE IN

BATT

CE OUT

RESET

PFO

51k

18k

PFI

WDI

I/O LINE

2

1

0

GND

MICROPROCESSOR RESET, BATTERY BACK-UP,

100Ω

RAM WRITE PROTECTION, POWER WARNING AND

WATCHDOG TIMING ARE ALL IN A SINGLE CHIP

FOR 3.3V MICROPROCESSOR SYSTEM

0.1μF

694/5-3.3 TA01

0

1

2

3

4

5

SUPPLY VOLTAGE (V)

694/5-3.3 TA02

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1

LTC694-3.3/LTC695-3.3

ABSOLUTE MAXIMUM RATINGS ^{(Notes 1 and 2)}

Terminal Voltage

V

Output Current ................. Short-Circuit Protected

OUT

V .......................................................... –0.3V to 6V

Power Dissipation............................................. 500mW

Operating Temperature Range

CC

V

...................................................... –0.3V to 6V

BATT

All Other Inputs ..................... –0.3V to (V

Input Current

+ 0.3V)

LTC694C-3.3/LTC695C-3.3...................... 0°C to 70°C

LTC694I-3.3/LTC695I-3.3 ....................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

OUT

V

..................................................................100mA

BATT

GND...................................................................10mA

CC

.................................................................25mA

PIN CONFIGURATION

TOP VIEW

V

1

2

16 RESET

BATT

V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

RESET

WDO

CE IN

CE OUT

WDI

BATT

V

OUT

V

15

14

13

12

RESET

OUT

V

CC

V

3

4

5

6

7

8

WDO

CC

GND

CE IN

BATT ON

LOW LINE

OSC IN

BATT ON

LOW LINE

OSC IN

CE OUT

11 WDI

PFO

10

9

OSC SEL

PFI

OSC SEL

SW PACKAGE

16-LEAD PLASTIC WIDE SO

N PACKAGE

16-LEAD PDIP

T

JMAX

= 110°C, θ = 130°C/W

JA

T

= 110°C, θ = 130°C/W

JMAX

JA

TOP VIEW

V

8

1

V

OUT

1

2

3

4

8

7

6

5

V

BATT

OUT

V

2

7

6

5

V

RESET

WDI

CC

WDI

3

4

GND

PFI

GND

PFI

PFO

S8 PACKAGE

8-LEAD PLASTIC SO

N8 PACKAGE

8-LEAD PDIP

T

JMAX

= 110°C, θ = 180°C/W

JA

T

= 110°C, θ = 130°C/W

JA

JMAX

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LTC694-3.3/LTC695-3.3

ORDER INFORMATION

LEAD FREE FINISH

LTC695CN-3.3#PBF

LTC695IN-3.3#PBF

LTC695CSW-3.3#PBF

LTC695ISW-3.3#PBF

LTC694CN8-3.3#PBF

LTC694IN8-3.3#PBF

LTC694CS8-3.3#PBF

LTC694IS8-3.3#PBF

TAPE AND REEL

PART MARKING

LTC695CN-3.3

LTC695IN-3.3

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC695CN-3.3#TRPBF

LTC695IN-3.3#TRPBF

16-Lead PDIP

–40°C to 85°C

0°C to 70°C

LTC695CSW-3.3#TRPBF LTC695CSW-3.3

16-Lead Plastic Wide SO

8-Lead PDIP

LTC695ISW-3.3#TRPBF

LTC694CN8-3.3#TRPBF

LTC694IN8-3.3#TRPBF

LTC694CS8-3.3#TRPBF

LTC694IS8-3.3#TRPBF

LTC695ISW-3.3

LTC694CN8-3.3

LTC694IN8-3.3

6943

–40°C to 85°C

0°C to 70°C

8-Lead PDIP

–40°C to 85°C

0°C to 70°C

8-Lead Plastic SO

694I3

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based finish parts.

Consult LTC Marketing for military grade parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

PRODUCT SELECTION GUIDE

RESET

THRESHOLD

(V)

CONDITIONAL

BATTERY

BACK-UP

WATCHDOG

TIMER

BATTERY

BACK-UP

POWER-FAIL RAM WRITE PUSH-BUTTON

PINS

8

WARNING

PROTECT

RESET

LTC694-3.3

LTC695-3.3

LTC690

2.90

X

16

8

X

4.65

LTC691

16

8

4.65

LTC694

4.65

LTC695

16

8

4.65

LTC699

4.65

LTC1232

LTC1235

8

4.37/4.62

4.65

X

16

X

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LTC694-3.3/LTC695-3.3

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 3.3V, V_BATT= 2V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Battery Back-Up Switching

Operating Voltage Range

l

V

3.0

1.5

5.50

2.75

V

CC

BATT

V

Output Voltage

I

= 1mA

V

– 0.1

V

– 0.01

V

OUT

CC

l

– 0.2

I

= 50mA

V

– 0.8

V – 0.4

CC

V

OUT

CC

V

in Battery Back-Up Mode

= 250μA, V < V

V

– 0.1

V

– 0.02

BATT

OUT

CC

BATT

Supply Current (Exclude I

)

≤ 50μA, V = 3.6V

0.2

0.6

1.0

mA

OUT

CC

l

Supply Current in Battery Back-Up Mode

V

= 0V, V

= 2V

BATT

0.04

1

5

μA

CC

Battery Standby Current (+ = Discharge, – = Charge) 3.6V > V > V

+ 0.2V

BATT

–0.02

–0.10

0.02

0.10

μA

CC

Battery Switchover Threshold (V – V

)

BATT

Power-Up

Power-Down

70

50

mV

CC

Battery Switchover Hysteresis

20

mV

V

l

BATT ON Output Voltage (Note 4)

I

= 800μA

0.3

25

SINK

BATT ON Output Short-Circuit Current (Note 4)

BATT ON = V , Sink Current

BATT ON = 0V, Source Current

25

1

mA

μA

OUT

0.5

2.8

Reset and Watchdog Timer

Reset Voltage Threshold

Reset Threshold Hysteresis

Reset Active Time

l

2.9

40

3.0

V

mV

OSC SEL HIGH, V = 3V

160

140

200

240

280

ms

CC

l

Watchdog Timeout Period, Internal Oscillator

Long Period, V = 3V

1.2

1.0

1.6

2.0

2.25

sec

CC

Short Period, V = 3V

80

70

100

120

140

ms

CC

l

Watchdog Timeout Period, External Clock (Note 5)

Long Period, V = 3V

4032

960

4097

1025

Clock

Cycles

CC

Short Period, V = 3V

CC

Reset Active Time PSRR

4

ms/V

Watchdog Timeout Period PSRR, Internal OSC

Short Period

Long Period

2

32

ms/V

l

Minimum WDI Input Pulse Width

V

= 0.4V, V = 3V

200

2.3

ns

IL

IH

RESET Output Voltage at V = 1V

I

= 10μA, V = 1V

4

200

0.3

mV

CC

SINK

CC

RESET and LOW^_LINE Output Voltage (Note 4)

I

= 400μA, V = 2.8V

V

l

SINK

SOURCE

CC

= 0.1μA, V = 3V

CC

l

RESET and WDO Output Voltage (Note 4)

I

= 400μA, V = 3V

0.3

25

V

SINK

CC

= 0.1μA, V = 2.8V

2.3

1

SOURCE

CC

RESET, RESET, WDO, LOW^_LINE

Output Short-Circuit Current (Note 4)

Output Source Current

Output Sink Current

3

9

μA

mA

l

WDI Input Threshold

WDI Input Current

Logic Low

Logic High

0.4

50

V

2.3

l

WDI = V

4

–8

μA

OUT

WDI = 0V

–50

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LTC694-3.3/LTC695-3.3

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 3.3V, V_BATT= 2V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power-Fail Detector

PFI Input Threshold

PFI Input Threshold PSRR

PFI Input Current

l

1.25

1.3

1.35

V

mV/V

nA

0.3

0.01

25

l

PFO Output Voltage (Note 4)

I

= 800μA

0.3

V

SINK

SOURCE

= 0.1μA

2.3

1

l

PFO Short-Circuit Source Current (Note 4)

PFI = HIGH, PFO = 0V

PFI = LOW, PFO = V

3

17

25

μA

OUT

PFI Comparator Response Time (Falling)

ΔV = –20mV, V = 15mV

2

μs

IN

OD

PFI Comparator Response Time (Rising) (Note 4)

ΔV = 20mV, V = 15mV

40

8

μs

IN

OD

with 10kꢀ Pull-Up

Chip Enable Gating

CE IN Threshold

V

0.45

V

IL

IH

1.9

CE IN Pull-Up Current (Note 6)

CE OUT Output Voltage

3

μA

l

I

= 800μA

0.3

50

V

SINK

= 400μA

V

– 0.50

– 0.05

SOURCE

OUT

= 1μA, V = 0V

CC

l

CE IN Propagation Delay

C = 20pF

30

ns

L

CE OUT Output Short-Circuit Current

Output Source Current

Output Sink Current

15

20

mA

Oscillator

OSC IN Input Current (Note 6)

OSC SEL Input Pull-Up Current (Note 6)

OSC IN Frequency Range

2

5

μA

l

OSC SEL = 0V

0

125

kHz

OSC SEL = 0V, C = 47pF

4

A

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: The external clock feeding into the circuit passes through the

oscillator before clocking the watchdog timer. Variation in the timeout

period is caused by phase errors which occur when the oscillator divides

the external clock by 64. The resulting variation in the timeout period is 64

plus one clock of jitter.

Note 2: All voltage values are with respect to GND.

Note 6: The input pins of CE IN, OSC IN and OSC SEL have weak internal

pull-ups which pull to the supply when the input pins are floating.

Note 3: For military temperature range parts, consult the factory.

Note 4: The output pins of BATT ON, LOW^_LINE, PFO, WDO, RESET and

RESET have weak internal pull-ups of typically 3μA. However, external pull-

up resistors may be used when higher speed is required.

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LTC694-3.3/LTC695-3.3

TYPICAL PERFORMANCE CHARACTERISTICS

Power Failure Input Threshold

vs Temperature

Output Voltage vs Load Current

2.40

2.39

2.38

2.37

2.36

2.35

1.310

1.308

1.306

1.304

1.302

1.300

1.298

1.296

1.294

3.30

3.25

3.20

3.15

3.10

3.05

3.00

V

= 3.3V

V

T

= 0V

= 2.4V

= 25°C

CC

V

T

= 3.3V

= 2.4V

= 25°C

CC

BATT

A

CC

BATT

A

SLOPE = 4.6Ω

SLOPE = 90Ω

0

100

200

300

400

500

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

0

10

20

30

40

50

LOAD CURRENT (μA)

LOAD CURRENT (mA)

694/5-3.3 G02

694/5-3.3 G03

694/5-3.3 G01

Power-Fail Comparator

Response Time with Pull-Up

Resistor

Power-Fail Comparator

Response Time

Power-Fail Comparator

Response Time

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

T

= 3.3V

V

T

= 3.3V

V

T

= 3.3V

CC

A

CC

A

CC

A

= 25°C

V

+

–

PFI

3.3V

10k

PFO

30pF

V

+

–

PFI

1.3V

PFO

30pF

V

+

–

PFI

1.3V

30pF

V

= 20mV STEP

1.315V

1.295V

1.305V

1.285V

1.315V

1.295V

PFI

2

V

= 20mV STEP

V

= 20mV STEP

PFI

60

PFI

6

0

1

3

4

5

7

8

14

12 16 18

6

9

0

140

160 180

2

4

8

10

0

120

80 100

20 40

TIME (μs)

694/5-3.3 G04

694/5-3.3 G06

694/5-3.3 G05

Reset Active Time

vs Temperature

Reset Voltage Threshold

vs Temperature

RESET Output Voltage

vs Supply Voltage

2.90

2.89

2.88

2.87

2.86

2.85

2.84

5

220

210

200

190

180

170

160

150

V

= 3.3V

V

= 3.3V

CC

4

3

2

1

0

50

TEMPERATURE (°C)

100 125

1

3

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

0

2

4

5

–50 –25

0

25

75

SUPPLY VOLTAGE (V)

694/5-3.3 G09

694/5-3.3 G08

694/5-3.3 G07

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LTC694-3.3/LTC695-3.3

PIN FUNCTIONS

BATT ON: Battery On Logic Output from Comparator C2.

PFI: Power Failure Input. PFI is the noninverting input

to the power-fail comparator, C3. The inverting input is

internallyconnectedtoa1.3Vreference. Thepowerfailure

output remains high when PFI is above 1.3V and goes

BATT ON goes low when V

is internally connected to

OUT

V . The output typically sinks 25mA and can provide

CC

base drive for an external PNP transistor to increase the

output current above the 50mA rating of V . BATT ON

low when PFI is below 1.3V. Connect PFI to GND or V

OUT

goes high when V

is internally switched to V

.

when C3 is not used.

OUT

BATT

CE IN: Logic Input to the Chip^_Enable Gating Circuit. CE IN

can be derived from microprocessor’s address line and/or

decoder output. See the Applications Information section

and Figure 5 for additional information.

PFO: Power Failure Output from C3. PFO remains high

when PFI is above 1.3V and goes low when PFI is below

1.3V. When V is lower than V

, C3 is shut down and

BATT

CC

PFO is forced low.

CE OUT: Logic Output on the Chip^_Enable Gating Circuit.

RESET: Active High Logic Output. It is the inverse of

RESET.

When V is above the reset voltage threshold, CE OUT is

CC

a buffered replica of CE IN. When V is below the reset

CC

RESET: Logic Output for μP Reset Control. Whenever V

CC

voltage threshold CE OUT is forced high (see Figure 5).

falls below either the reset voltage threshold (2.90V, typi-

GND: Ground Pin.

cally) or V , RESET goes active low. After V returns

BATT

CC

LOW^_LINE: Logic Output from Comparator C1. LOW^_LINE

to 3.3V, the reset pulse generator forces RESET to remain

active low for a minimum of 140ms. When the watchdog

timer is enabled but not serviced prior to a preset timeout

period, the reset pulse generator also forces RESET to ac-

tive low for a minimum of 140ms for every preset timeout

period (see Figure 11). The reset active time is adjustable

on the LTC695-3.3. An external push-button reset can be

used in connection with the RESET output. See Push-But-

ton Reset in the Applications Information section.

indicates a low line condition at the V input. When V

CC

falls below the reset voltage threshold (2.90V typically),

LOW^_LINE goes low. As soon as V rises above the reset

CC

voltage threshold, LOW^_LINE returns high (see Figure 1).

LOW^_LINE goes low when V drops below V

(see

CC

BATT

Table 1).

OSC IN: Oscillator Input. OSC IN can be driven by an

external clock signal or an external capacitor can be con-

nected between OSC IN and GND when OSC SEL is forced

low. Inthisconfigurationthenominalresetactivetimeand

watchdog timeout period are determined by the number

of clocks or set by the formula (see the Applications In-

formation section). When OSC SEL is high or floating, the

internal oscillator is enabled and the reset active time is

fixed at 200ms typical for the LTC695-3.3. OSC IN selects

between the 1.6 seconds and 100ms typical watchdog

timeout periods. In both cases, the timeout period im-

mediately after a reset is 1.6 seconds typical.

V

: Back-Up Battery Input. When V falls below V

,

BATT

CC

BATT

auxiliary power connected to V

, is delivered to V

BATT

OUT

through PMOS switch, M2. If back-up battery or auxiliary

power is not used, V should be connected to GND.

BATT

V : 3.3V Supply Input. The V pin should be bypassed

CC

with a 0.1μF capacitor.

V

: Voltage Output for Backed Up Memory. Bypass with

OUT

a capacitor of 0.1μF or greater. During normal operation,

V

obtains power from V through an NMOS power

OUT

CC

switch,M1,whichcandeliverupto50mAandhasatypical

OSC SEL: Oscillator Selection Input. When OSC SEL is

high or floating, the internal oscillator sets the reset active

time and watchdog timeout period. Forcing OSC SEL low,

allows OSC IN to be driven from an external clock signal

or an external capacitor can be connected between OSC

IN and GND.

on resistance of 5ꢀ. When V is lower than V

is internally switched to V

, V

CC

BATT OUT

. If V

BATT

and V are not

OUT

BATT

used, connect V

to V .

OUT

CC

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LTC694-3.3/LTC695-3.3

PIN FUNCTIONS

WDI: Watchdog Input. WDI is a three-level input. Driving

WDIeitherhighorlowforlongerthanthewatchdogtimeout

period, forces both RESET and WDO low. Floating WDI

disables the watchdog timer. The timer resets itself with

each transition of the watchdog input (see Figure 11).

WDO: Watchdog Logic Output. When the watchdog input

remains either high or low for longer than the watchdog

timeout period, WDO goes low. WDO is set high whenever

there is a transition on the WDI pin, or LOW^_LINE goes

low. The watchdog timer can be disabled by floating WDI

(see Figure 11).

BLOCK DIAGRAM

M2

V

OUT

BATT

M1

V

CC

CHARGE

PUMP

–

+

BATT ON

C2

LOW LINE

+

C1

–

CE OUT

1.3V

GND

CE IN

–

C3

PFO

+

PFI

RESET

OSC IN

RESET PULSE

GENERATOR

OSC

OSC SEL

RESET

WATCHDOG

TIMER

WDO

TRANSITION

DETECTOR

WDI

694/5-3.3 BD

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LTC694-3.3/LTC695-3.3

APPLICATIONS INFORMATION

Microprocessor Reset

Battery Switchover

The battery switchover circuit compares V to the V

The LTC694-3.3/LTC695-3.3 use a bandgap voltage refer-

enceandaprecisionvoltagecomparatorC1tomonitorthe

CC

BATT

input, and connects V

to whichever is higher. When

OUT

3.3V supply input on V (see the Block Diagram). When

V

rises to 70mV above V

comparator, C2, connects V

, the battery switchover

CC

BATT

V

fallsbelowtheresetvoltagethreshold,theRESETout-

to V through a charge

CC

OUT

putisforcedtoactivelowstate.Theresetvoltagethreshold

pumpedNMOSpowerswitch,M1.WhenV fallsto50mV

CC

accounts for a 10% variation on V , so the RESET output

above V

, C2 connects V

to V

through a PMOS

CC

BATT

OUT

BATT

becomes active low when V falls below 3.0V (2.9V typi-

switch, M2. C2hastypically20mVofhysteresistoprevent

CC

cal).Onpower-up,theRESETsignalisheldactivelowfora

minimumof140msafterresetvoltagethresholdisreached

toallowthepowersupplyandmicroprocessortostabilize.

The reset active time is adjustable on the LTC695-3.3.

On power-down, the RESET signal remains active low

spuriousswitchingwhenV remainsnearlyequaltoV

.

CC

BATT

The response time of C2 is approximately 20μs.

During normal operation, the LTC694-3.3/LTC695-3.3 use

a charge-pumped NMOS power switch to achieve low

dropout and low supply current. This power switch can

even with V as low as 1V. This capability helps hold the

CC

deliver up to 50mA to V

from V and has a typical on

OUT

CC

microprocessor in stable shutdown condition. Figure 1

resistance of 5ꢀ. The V

pin should be bypassed with

OUT

shows the timing diagram of the RESET signal.

a capacitor of 0.1μF or greater to ensure stability. Use of

a larger bypass capacitor is advantageous for supplying

current to heavy transient loads.

The precision voltage comparator, C1, typically has 40mV

of hysteresis which ensures that glitches at V pin do

CC

not activate the RESET output. Response time is typically

When operating currents larger than 50mA are required

10ms.Tohelppreventmistriggeringduetotransientloads,

from V , or a lower dropout (V – V voltage dif-

OUT

CC

OUT

the V pin should be bypassed with a 0.1μF capacitor

CC

ferential) is desired, the LTC695-3.3 should be used. This

product provides BATT ON output to drive the base of

an external PNP transistor (Figure 2). If higher currents

are needed with the LTC694-3.3, a high current Schottky

with the leads trimmed as short as possible.

The LTC695-3.3 has two additional outputs: RESET and

LOW^_LINE.RESETisanactivehighoutputandistheinverse

ofRESET. LOW^_LINEistheoutputoftheprecisionvoltage

diode can be connected from the V pin to the V

CC

OUT

comparator C1. When V falls below the reset voltage

to supply the extra current.

CC

threshold,LOW^_LINEgoeslow.LOW^_LINEreturnshighas

soon as V rises above the reset voltage threshold.

CC

V2

V1

V1 = RESET VOLTAGE THRESHOLD

V2 = RESET VOLTAGE THRESHOLD +

RESET THRESHOLD HYSTERESIS

V

CC

RESET

t

1

t

1

t

= RESET ACTIVE TIME

1

LOW LINE

694/5-3.3 F01

Figure 1. Reset Active Time

69453fb

9

LTC694-3.3/LTC695-3.3

APPLICATIONS INFORMATION

V

– V

R

ANY PNP POWER TRANSISTOR

OUT

R

BATT

I =

V

5

V

3.3V

0.1μF

OUT

CC

BATT ON

3

2

0.1μF

3.3V

V

OUT

CC

LTC694-3.3

LTC695-3.3

0.1μF

LTC695-3.3

1

V

BATT

GND

V

BATT

GND

2.4V

4

694/5-3.3 F02

694/5-3.3 F03

Figure 2. Using BATT ON to Drive External PNP Transistor

Figure 3. Charging External Battery Through V_OUT

The LTC694-3.3/LTC695-3.3 are protected for safe area

operation with short-circuit limit. Output current is limited

to approximately 200mA. If the device is overloaded for

a long period of time, thermal shutdown turns the power

switch off until the device cools down. The threshold

temperatureforthermalshutdownisapproximately155°C

with about 10°C of hysteresis which prevents the device

from oscillating in and out of shutdown.

The operating voltage at the V

pin ranges from 1.5V

BATT

to 2.75V. The charging resistor for rechargeable batteries

should be connected to V since this eliminates the

OUT

discharge path that exists when the resistor is connected

to V (Figure 3).

CC

Replacing the Back-Up Battery

When changing the back-up battery with system power

on, spuriousresetscanoccurwhilethebatteryisremoved

due to battery standby current. Although battery standby

current is only a tiny leakage current, it can still charge

ThePNPswitchusedincompetitivedeviceswasnotchosen

for the internal power switch because it injects unwanted

current into the substrate. This current is collected by the

up the stray capacitance on the V

pin. The oscillation

V

pin in competitive devices and adds to the charging

BATT

cycle is as follows: When V

reaches within 50mV of

current of the battery which can damage lithium batteries.

The LTC694-3.3/LTC695-3.3 use a charge-pumped NMOS

powerswitchtoeliminateunwantedchargingcurrentwhile

achieving low dropout and low supply current. Since no

current goes to the substrate, the current collected by

BATT

V ,theLTC694-3.3/LTC695-3.3switchtobatterybackup.

CC

V

OUT

pulls V

low and the device goes back to normal

BATT

operation. The leakage current then charges up the V

pin again and the cycle repeats.

BATT

V

pin is strictly junction leakage.

BATT

If spurious resets during battery replacement pose no

problems, thennoactionisrequired. Otherwise, aresistor

A 125ꢀ PMOS switch connects the V

input to V

OUT

BATT

from V

to GND will hold the pin low while changing

in battery back-up mode. The switch is designed for very

low dropout voltage (input-to-output differential). This

feature is advantageous for low current applications such

as battery back-up in CMOS RAM and other low power

CMOS circuitry. The supply current in battery back-up

mode is 1μA maximum.

BATT

the battery. For example, the battery standby current is

1μA maximum over temperature so the external resistor

required to hold V

below V is:

BATT

CC

V_CC– 50mV

1µA

R≤

With V = 3V, a 2.7M resistor will work. With a 2V battery,

CC

this resistor will draw only 0.7μA from the battery, which

is negligible in most cases.

69453fb

10

LTC694-3.3/LTC695-3.3

APPLICATIONS INFORMATION

If battery connections are made through long wires, a

10ꢀ to 100ꢀ series resistor and a 0.1μF capacitor are

recommended to prevent any overshoot beyond V due

to the lead inductance (Figure 4).

10Ω

V

BATT

0.1μF

2.7M

LTC694-3.3

LTC695-3.3

CC

Table1showsthestateofeachpinduringbatteryback-up.

When the battery switchover section is not used, connect

GND

694/5-3.3 F04

V

to GND and V

to V .

BATT

Table 1. Input and Output Status in Battery Back-Up Mode

SIGNAL STATUS

C2 monitors V for active switchover.

OUT

CC

Figure 4. 10Ω/0.1μF Combination Eliminates Inductive

Overshoot and Prevents Spurious Resets During Battery

Replacement. The 2.7M Pulls the V_BATTPin to Ground

While the Battery is Removed, Eliminating Spurious Resets

V

CC

V

is connected to V

through an internal PMOS switch.

OUT

BATT

OUT

BATT

Memory Protection

The supply current is 1μA maximum.

The LTC695-3.3 includes memory protection circuitry

which ensures the integrity of the data in memory by pre-

BATT ON Logic high. The open-circuit output voltage is equal to V

.

OUT

PFI

Power failure input is ignored.

venting write operations when V is at invalid level. Two

CC

additional pins, CE IN and CE OUT, control the Chip^_Enable

PFO

Logic low.

RESET

Logic low.

or Write inputs of CMOS RAM. When V is 3.3V, CE OUT

CC

Logic high. The open-circuit output voltage is equal to V

.

OUT

LOW^_LINE Logic low.

follows CE IN with a typical propagation delay of 30ns.

When V falls below the reset voltage threshold or V

,

CC

BATT

WDI

Watchdog input is ignored.

CE OUT is forced high, independent of CE IN. CE OUT is

an alternative signal to drive the CE, CS, or Write input of

battery backed up CMOS RAM. CE OUT can also be used

to drive the Store or Write input of an EEPROM, EAROM

or NOVRAM to achieve similar protection. Figure 5 shows

the timing diagram of CE IN and CE OUT.

WDO

Logic high. The open-circuit output voltage is equal to V

.

OUT

CE IN

CE OUT

OSC IN

Chip^_Enable input is ignored.

Logic high. The open-circuit output voltage is equal to V

OSC IN is ignored.

.

OUT

OSC SEL OSC SEL is ignored.

V2

V

V1 = RESET VOLTAGE THRESHOLD

V2 = RESET VOLTAGE THRESHOLD +

RESET THRESHOLD HYSTERESIS

CC

V1

CE IN

V

= V

BATT

OUT

CE OUT

V

= V

BATT

OUT

694/5-3.3 F05

Figure 5. Timing Diagram for CE IN and CE OUT

69453fb

11

LTC694-3.3/LTC695-3.3

APPLICATIONS INFORMATION

CE IN can be derived from the microprocessor’s address

decoderoutput.Figure6showsatypicalnonvolatileCMOS

RAM application.

V

3.3V

0.1μF

CC

OUT

CC

+

0.1μF

62512

RAM

10μF

LTC695-3.3

CE OUT

CS

GND

30ns PROPAGATION DELAY

FROM DECODER

Memory protection can also be achieved with the LTC694-

3.3 by using RESET as shown in Figure 7.

V

BATT

CE IN

RESET

2.4V

GND

RESET

694/5-3.3 F06

TO μP

Power-Fail Warning

TheLTC694-3.3/LTC695-3.3generateaPowerFailureOut-

put(PFO)forearlywarningoffailureinthemicroprocessor’s

power supply. This is accomplished by comparing the

power failure input (PFI) with an internal 1.3V reference.

Figure 6. A Typical Nonvolatile CMOS RAM Application

V

CC

62128

RAM

3.3V

0.1μF

CC

OUT

+

0.1μF

10μF

PFO goes low when the voltage at the PFI pin is less than

1.3V. Typically PFI is driven by an external voltage divider

(R1 and R2 in Figures 8 and 9) which senses either an

unregulated DC input or a regulated 3.3V output. The

voltage divider ratio can be chosen such that the voltage

at the PFI pin falls below 1.3V several milliseconds before

the 3.3V supply falls below the maximum reset voltage

threshold 3.0V. PFO is normally used to interrupt the

microprocessor to execute shutdown procedure between

PFO and RESET or RESET.

LTC694-3.3

CS1

CS

V

RESET

GND

CS2

BATT

2.4V

GND

694/5-3.3 F07

Figure 7. Write Protect for RAM with LTC694-3.3

V

≥ 5V

LT1129-3.3

3.3V

IN

V

OUT

CC

IN

+

10μF OUT SENSE

100μF

0.1μF

LTC694-3.3

LTC695-3.3

SHDN

R4

10k

The power-fail comparator, C3, does not have hysteresis.

Hysteresiscanbeaddedhowever, byconnectingaresistor

between the PFO output and the noninverting PFI input

pin as shown in Figures 8 and 9. The upper and lower trip

points in the comparator are established as follows:

R3

200k

ADJ

R1

51k

PFO

GND

PFI

R2

16k

TO μP

694/5-3.3 F08

When PFO output is low, R3 sinks current from the sum-

ming junction at the PFI pin.

Figure 8. Monitoring Unregulated DC Supply with the

LTC694-3.3/LTC695-3.3’s Power-Fail Comparator

R1 R1

+

⎛

⎞

V =1.3V 1+

⎜

⎟

⎠

H

LT1129-3.3

V

r 6.5V

0.1μF

10μF

⎝

R2 R3

IN

3.3V

V

CC

IN

OUT

+

When PFO output is high, the series combination of R3

and R4 source current into the PFI summing junction.

OUT SENSE

R4

10k

R1

27k

10μF

LTC694-3.3

LTC695-3.3

SHDN

R3

2.7M

ADJ

PFO

GND

PFI

⎛

R1 (3.3V 1.3V)R1⎞

R2 1.3V(R3+R4) ⎠

V_L=1.3V 1+

–

694/5-3.3 F09

R2

16k

⎜

⎝

⎟

TO μP

R5

5k

R1

R3

Assuming R4 << R3, V_HYSTERESIS= 3.3V

Figure 9. Monitoring Regulated DC Supply with the

LTC694-3.3/LTC695-3.3’s Power-Fail Comparator

69453fb

12

LTC694-3.3/LTC695-3.3

APPLICATIONS INFORMATION

Example 1: The circuit in Figure 8 demonstrates the use

of the power-fail comparator to monitor the unregulated

power supply input. Assuming the the rate of decay of the

Monitoring the Status of the Battery

C3 can also monitor the status of the memory back-up

battery (Figure 10). If desired, the CE OUT can be used to

applyatestloadtothebattery. SinceCEOUTisforcedhigh

in battery back-up mode, the test load will not be applied

to the battery while it is in use, even if the microprocessor

supplyinputV is100mV/msandthetotaltimetoexecutea

IN

shutdownprocedureis8ms.AlsothenoiseofV is200mV.

IN

With these assumptions in mind, we can reasonably set

V = 5V which is 1.6V greater than the sum of maximum

L

is not powered.

reset voltage threshold and the dropout voltage of the

3.3V

LT1129-3.3 (3V + 0.4V) and V

= 850mV.

HYSTERESIS

V

CC

V

BATT

R1

LOW-BATTERY SIGNAL

T0 μP I/O PIN

PFO

V_HYSTERESIS= 3.3V = 850mV

R1

1M

R3

LTC695-3.3

PFI

R3 ≈ 3.88 R1

R2

2.4V

1.6M

CE IN

GND

I/O PIN

Choose R3 = 200k and R1 = 51k. Also select R4 = 10k

which is much smaller than R3.

CE OUT

R

20k

L

⎛

51k (3.3V −1.3V)51k⎞

5V =1.3V 1−

−

⎜

⎝

⎟

OPTIONAL TEST LOAD

R2

1.3V(210k)

⎠

694/5-3.3 F10

R2 = 15.8k, Choose nearest 5% resistor 16k and recal-

culate V ,

Figure 10. Back-Up Battery Monitor with Optional Test Load

L

⎛

51k (3.3V −1.3V)51k⎞

Watchdog Timer

V_L=1.3V 1+

−

=4.96 V

⎜

⎝

⎟

16k

1.3V(210k) ⎠

The LTC694-3.3/LTC695-3.3 provide a watchdog timer

function to monitor the activity of the microprocessor. If

the microprocessor does not toggle the watchdog input

(WDI) within a selected timeout period, RESET is forced

to active low for a minimum of 140ms. The reset active

timeisadjustableontheLTC695-3.3. Sincemanysystems

can not service the watchdog timer immediately after a

reset, the LTC695-3.3 has a longer timeout period (1.0

second minimum) right after a reset is issued. The normal

timeoutperiod(70msminimum)becomeseffectivefollow-

ing the first transition of WDI after RESET is inactive. The

watchdog timeout period is fixed at 1.0 second minimum

on the LTC694-3.3. Figure 11 shows the timing diagram

of watchdog timeout period and reset active time. The

watchdog timeout period is restarted as soon as RESET is

inactive. When either a high-to-low or low-to-high transi-

tion occurs at the WDI pin prior to timeout, the watchdog

time is reset and begins to time out again. To ensure the

watchdog time does not time out, either a high-to-low or

low-to-high transition on the WDI pin must occur at or

less than the minimum timeout period. If the input to the

51k 51k

+

⎛

⎞

V =1.3V 1+

=5.77 V

⎜

⎟

⎠

H

⎝

16 k 200k

(4.96V − 3.4V)

=15.6ms

100mV /ms

V

= 5.77V – 4.96V = 810mV

HYSTERESIS

The15.6msallowsenoughtimetoexecuteshutdownpro-

cedureformicroprocessorand810mVofhysteresiswould

prevent PFO from going low due to the noise of V .

IN

Example 2: The circuit in Figure 9 can be used to measure

the regulated 3.3V supply to provide early warning of

power failure. Because of variations in the PFI threshold,

thiscircuitrequiresadjustmenttoensurethePFIcompara-

tor trips before the reset threshold is reached. Adjust R5

such that the PFO output goes low when the V supply

reaches the desired level (e.g., 3.1V).

CC

69453fb

13

LTC694-3.3/LTC695-3.3

APPLICATIONS INFORMATION

V

= 3.3V

CC

WDI

t

1

t

2

t

3

= RESET ACTIVE TIME

= NORMAL WATCHDOG TIMEOUT PERIOD

= WATCHDOG TIMEOUT PERIOD IMMEDIATELY

AFTER A RESET

WDO

t

3

2

RESET

t

1

694/5-3.3 F11

Figure 11. Watchdog Timeout Period and Reset Active Time

EXTERNAL OSCILLATOR

EXTERNAL CLOCK

8

3

4

8

7

3

4

OSC SEL

3.3V

V

CC

OSC SEL

CC

LTC695-3.3

7

GND

OSC IN

GND

INTERNAL OSCILLATOR

1.6 SECOND WATCHDOG

INTERNAL OSCILLATOR

100ms WATCHDOG

3

8

3

8

7

FLOATING

OR HIGH

FLOATING

OR HIGH

V

3.3V

OSC SEL

CC

OSC SEL

CC

LTC695-3.3

7

4

FLOATING

OR HIGH

4

OSC IN

GND

694/5-3.3 F12

Figure 12. Oscillator Configurations

TheLTC695-3.3hastwoadditionalpins,OSCSELandOSC

IN, which allow reset active time and watchdog timeout

period to be adjusted per Table 2. Several configurations

are shown in Figure 12.

WDI pin remains either high or low, reset pulses will be

issued every 1.6 seconds typically. The watchdog time

can be deactivated by floating the WDI pin. The timer

is also disabled when V falls below the reset voltage

CC

threshold or V

.

BATT

OSC IN can be driven by an external clock signal or an

external capacitor can be connected between OSC IN and

GND when OSC SEL is forced low. In these configura-

tions, the nominal reset active time and watchdog timeout

period are determined by the number of clocks or set by

the formula in Table 2. When OSC SEL is high or floating,

The LTC695-3.3 provides an additional output (Watchdog

Output, WDO) which goes low if the watchdog timer is

allowed to time out and remains low until set high by the

next transition on the WDI pin. WDO is also set high when

V

falls below the reset voltage threshold or V

.

CC

BATT

69453fb

14

LTC694-3.3/LTC695-3.3

TYPICAL APPLICATION

Table 2. LTC695-3.3 Reset Active Time and Watchdog Timeout Selections

WATCHDOG TIMEOUT PERIOD

RESET ACTIVE TIME

IMMEDIATELY AFTER

OSC SEL

Low

OSC IN

NORMAL (SHORT PERIOD)

RESET (LONG PERIOD)

LTC695-3.3

External Clock Input

External Capacitor*

1024 CLKs

4096 CLKs

2048 CLKs

Low

400ms

•C

1.6s

•C

800ms

•C

70pF

Floating or High

Low

100ms

1.6 sec

200ms

Floating or High

184,000

C(pF) • 1025

*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is f

(Hz) =

OSC

the internal oscillator is enabled and the reset active time

is fixed at 140ms minimum for the LTC695-3.3. OSC IN

selects between the 1 second and 70ms minimum normal

watchdogtimeoutperiods.Inbothcases,thetimeoutperiod

immediately after a reset is at least 1 second.

The 100ꢀ resistor in series with the push-button is re-

quired to prevent the ringing, due to the capacitance and

lead inductance, from pulling the RESET pins of the MPU

and LTC69X below ground.

V

3.3V

RESET

LTC694-3.3

RESET

CC

Push-Button Reset

100ꢀ

0.1μF

MPU

(e.g. 68HC05)

LTC695-3.3

The LTC694-3.3/LTC695-3.3 do not provide a logic input

for direct connection to a push-button. However, a push-

button in series with a 100ꢀ resistor connected to the

RESET output pin (Figure 13) provides an alternative for

manual reset. Connecting a 0.1μF capacitor to the RESET

pin debounces the push-button input.

GND

694/5-3.3 F13

Figure 13. The External Push-Button Reset

TYPICAL APPLICATION

Capacitor Back-Up with 74HC4016 Switch

3.3V

V

CC

OUT

0.1μF

10 11 12 14

0.1μF

R1

10k

LTC695-3.3

2

1

LOW LINE

V

74HC4016

BATT

R2

30k

7

13

100μF

+

GND

694/5-3.3 TA03

69453fb

15

LTC694-3.3/LTC695-3.3

PACKAGE DESCRIPTION

N8 Package

8-Lead PDIP (Narrow 0.300)

(Reference LTC DWG # 05-08-1510)

.400*

(10.160)

MAX

.130 p .005

.300 – .325

.045 – .065

(3.302 p 0.127)

(1.143 – 1.651)

(7.620 – 8.255)

8

1

7

6

5

4

.065

(1.651)

TYP

.255 p .015*

(6.477 p 0.381)

.008 – .015

(0.203 – 0.381)

.120

.020

(0.508)

MIN

(3.048)

MIN

+.035

–.015

2

3

.325

.018 p .003

(0.457 p 0.076)

.100

(2.54)

BSC

+0.889

8.255

ꢀ

ꢁ

N8 1002

–0.381

NOTE:

INCHES

1. DIMENSIONS ARE

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

S8 Package

8-Lead Plastic Small Outline (Narrow 0.150)

(Reference LTC DWG # 05-08-1610)

.189 – .197

(4.801 – 5.004)

.045 .005

.160 .005

NOTE 3

.050 BSC

7

5

8

6

.245

MIN

.150 – .157

(3.810 – 3.988)

NOTE 3

.228 – .244

(5.791 – 6.197)

.030 .005

TYP

1

3

4

2

RECOMMENDED SOLDER PAD LAYOUT

.010 – .020

(0.254 – 0.508)

× 45°

.053 – .069

(1.346 – 1.752)

.004 – .010

(0.101 – 0.254)

.008 – .010

(0.203 – 0.254)

0°– 8° TYP

.016 – .050

(0.406 – 1.270)

.050

(1.270)

BSC

.014 – .019

(0.355 – 0.483)

TYP

NOTE:

INCHES

1. DIMENSIONS IN

(MILLIMETERS)

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

SO8 0303

69453fb

16

LTC694-3.3/LTC695-3.3

PACKAGE DESCRIPTION

N Package

16-Lead PDIP (Narrow 0.300)

(Reference LTC DWG # 05-08-1510)

.770*

(19.558)

MAX

14

12

10

9

8

15

13

11

16

.255 .015*

(6.477 0.381)

2

1

3

4

6

5

7

.300 – .325

(7.620 – 8.255)

.130 .005

(3.302 0.127)

.045 – .065

(1.143 – 1.651)

.020

(0.508)

MIN

.065

(1.651)

TYP

.008 – .015

(0.203 – 0.381)

+.035

–.015

.325

.120

(3.048)

MIN

.018 .003

(0.457 0.076)

.100

(2.54)

BSC

+0.889

8.255

(

)

–0.381

NOTE:

INCHES

MILLIMETERS

1. DIMENSIONS ARE

N16 1002

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

69453fb

17

LTC694-3.3/LTC695-3.3

PACKAGE DESCRIPTION

SW Package

16-Lead Plastic Small Outline (Wide 0.300)

(Reference LTC DWG # 05-08-1620)

.050 BSC .045 .005

.030 .005

TYP

.398 – .413

(10.109 – 10.490)

NOTE 4

15 14

12

10

9

N

16

N

13

11

.325 .005

.420

MIN

.394 – .419

(10.007 – 10.643)

NOTE 3

N/2

8

1

2

3

N/2

RECOMMENDED SOLDER PAD LAYOUT

2

3

5

7

1

4

6

.291 – .299

(7.391 – 7.595)

NOTE 4

.037 – .045

(0.940 – 1.143)

.093 – .104

(2.362 – 2.642)

.010 – .029

× 45°

(0.254 – 0.737)

.005

(0.127)

RAD MIN

0° – 8° TYP

.050

(1.270)

BSC

.004 – .012

.009 – .013

(0.102 – 0.305)

NOTE 3

(0.229 – 0.330)

.014 – .019

.016 – .050

(0.356 – 0.482)

TYP

(0.406 – 1.270)

NOTE:

1. DIMENSIONS IN

INCHES

(MILLIMETERS)

S16 (WIDE) 0502

2. DRAWING NOT TO SCALE

3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.

THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

69453fb

18

LTC694-3.3/LTC695-3.3

REVISION HISTORY ^{(Revision history begins at Rev B)}

REV

DATE

DESCRIPTION

PAGE NUMBER

B

3/10

Removed “UL Recognized” and UL file number from the Features section.

1

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTC694-3.3/LTC695-3.3

TYPICAL APPLICATION

Write Protect for Additional RAMs

3.3V

V

CC

V

OUT

CC

+

0.1μF

10μF

LH5168SH

RAM A

0.1μF

LTC695-3.3

CS

CE OUT

30ns PROPAGATION

DELAY

CS A

BATT

CE IN

2.4V

LOW LINE

GND

V

CC

0.1μF

LH5116S

RAM B

CS1

CS B

CS2

V

CC

LH5116S

RAM C

CS C

CS1

CS2

OPTIONAL CONNECTION FOR

ADDITIONAL RAMs

694/5-3.3 TA04

RELATED PARTS

PART NUMBER

LTC1326

DESCRIPTION

Micropower Precision Triple Supply Monitor

Micropower Triple Supply Monitor for PCI Applications

COMMENTS

4.725V, 3.118V, 1V Thresholds (0.75%)

Meets PCI t Timing Specifications

LTC1536

FAIL

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LT 0310 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC694CS8-3.3#TRPBF
厂家：	Linear
描述：	LTC694-3.3 - 3.3V Microprocessor Supervisory Circuits; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 光电二极管
文件：	总20页 (文件大小：192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC694CS8-3.3#TRPBF [Linear]

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