LTC694IS8-3.3#TR_技术文档

LTC694-3.3/ LTC695-3.3

3.3V Mic ro p ro c e sso r

Sup e rviso ry Circ uits

U

FEATURES

DESCRIPTIO

■

UL Recognized _®

File # E145770

The LTC^®694-3.3/LTC695-3.3 provide complete 3.3V

power supply monitoring and battery control functions.

Theseincludepower-onreset,batteryback-up,RAMwrite

protection, power failure warning and watchdog timing.

The devices are pin compatible upgrades of the LTC694/

LTC695 that are optimized for 3.3V systems. Operating

power consumption has been reduced to 0.6mW (typical)

and 3µW maximum in battery back-up mode. Micropro-

cessor reset and memory write protection are provided

when the supply falls below 2.9V. The RESET output is

■

Guaranteed Reset Assertion at V_CC= 1V

Pin Compatible with LTC694/LTC695

for 3.3V Systems

■

200µA Typical Supply Current

Fast (30ns Typ) On-Board Gating of

RAM Chip Enable Signals

■

SO-8 and S16 Packages

2.90V Precision Voltage Monitor

Power OK/Reset Time Delay: 200ms or Adjustable

Minimum External Component Count

1µA Maximum Standby Current

Voltage Monitor for Power-Fail or

Low-Battery Warning

guaranteed to remain logic low with V as low as 1V.

CC

The LTC694-3.3/LTC695-3.3 power the active RAMs with

a charge pumped NMOS power switch to achieve low

dropout and low supply current. When primary power is

lost, auxiliary power, connected to the battery input pin,

powers the RAMs in standby through an efficient PMOS

switch.

■

Thermal Limiting

Performance Specified Over Temperature

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APPLICATIO S

For an early warning of impending power failure, the

LTC694-3.3/LTC695-3.3 provide an internal comparator

with a user-defined threshold. An internal watchdog timer

is also available, which forces the reset pins to active

states when the watchdog input is not toggled prior to a

preset time-out period.

■

3.3V Low Power Systems

Critical µP Power Monitoring

Intelligent Instruments

Battery-Powered Computers and Controllers

■

Automotive Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

U

TYPICAL APPLICATIO

RESET Output Voltage vs

Supply Voltage

5

LT1129-3.3

V

IN

≥ 5V

3.3V

V

IN

V

POWER TO

CMOS RAM POWER

µP

V

OUT

CC

OUT

+

0.1µF

4

3

100µF

0.1µF

1µF

OUT SENSE

SHDN

GND

LTC695-3.3

µP

SYSTEM

DECODER OUTPUT

RAM CS

µP RESET

µP NMI

CE IN

BATT

CE OUT

RESET

PFO

2.4V

51k

18k

2

1

0

PFI

WDI

I/O LINE

GND

MICROPROCESSOR RESET, BATTERY BACK-UP,

100Ω

RAM WRITE PROTECTION, POWER WARNING AND

WATCHDOG TIMING ARE ALL IN A SINGLE CHIP

FOR 3.3V MICROPROCESSOR SYSTEM

0.1µF

0

1

2

3

4

5

694/5-3.3 TA01

SUPPLY VOLTAGE (V)

694/5-3.3 TA02

1

LTC694-3.3/ LTC695-3.3

W W W

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ABSOLUTE AXI U RATI GS ^{(Notes 1 and 2)}

Terminal Voltage

V_OUTOutput Current ................. Short-Circuit Protected

V ...................................................... – 0.3V to 6V Power Dissipation............................................. 500mW

CC

Operating Temperature Range

V_BATT.................................................. – 0.3V to 6V

All Other Inputs .................. – 0.3V to (V_OUT+ 0.3V)

LTC694C-3.3/LTC695C-3.3 .................. 0°C to 70°C

LTC694I-3.3/LTC695I-3.3 ............... –40°C to 85°C

Storage Temperature Range ................ –65°C to 150°C

Input Current

V .............................................................. 100mA

CC

V_BATT............................................................ 25mA Lead Temperature (Soldering, 10 sec)................. 300°C

GND .............................................................. 10mA

W

U

/O

PACKAGE RDER I FOR ATIO

(Note 3)

TOP VIEW

ORDER PART

NUMBER

ORDER PART

V

1

2

16 RESET

BATT

V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

NUMBER

RESET

WDO

CE IN

CE OUT

WDI

BATT

V

15

14

13

12

RESET

WDO

OUT

V

OUT

V

3

4

5

6

7

8

CC

V

CC

LTC695CN-3.3

LTC695IN-3.3

LTC695CSW-3.3

LTC695ISW-3.3

GND

BATT ON

LOW LINE

OSC IN

CE IN

GND

BATT ON

LOW LINE

OSC IN

CE OUT

11 WDI

PFO

PFI

PFO

10

9

OSC SEL

PFI

OSC SEL

SW PACKAGE

16-LEAD PLASTIC WIDE SO

N PACKAGE

16-LEAD PDIP

T_JMAX= 110°C, θ_JA= 130°C/W

TOP VIEW

LTC694CN8-3.3

LTC694IN8-3.3

LTC694CS8-3.3

LTC694IS8-3.3

V

1

2

3

4

8

7

6

5

V

OUT

1

2

3

4

8

7

6

5

V

BATT

V

RESET

WDI

V

CC

RESET

WDI

CC

S8 PART

MARKING

GND

PFI

GND

PFI

PFO

N8 PACKAGE

8-LEAD PDIP

S8 PACKAGE

8-LEAD PLASTIC SO

6943

694I3

T_JMAX= 110°C, θ_JA= 180°C/W

T_JMAX= 110°C, θ_JA= 130°C/W

Consult factory for Military grade parts.

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PRODUCT SELECTIO GUIDE

RESET

CONDITIONAL

BATTERY

BACK-UP

THRESHOLD WATCHDOG

BATTERY

POWER-FAIL

WARNING

RAM WRITE PUSH-BUTTON

PINS

8

(V)

TIMER

BACK-UP

PROTECT

RESET

LTC694-3.3

LTC695-3.3

LTC690

2.90

X

16

8

2.90

X

4.65

LTC691

16

8

4.65

LTC694

4.65

LTC695

16

8

4.65

LTC699

4.65

LTC1232

LTC1235

8

4.37/4.62

4.65

X

16

X

2

LTC694-3.3/ LTC695-3.3

The ● denotes specifications which apply over the operating temperature

range, otherwise specifications are at T_A= 25°C. V_CC= 3.3V, V_BATT= 2V, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Battery Back-Up Switching

Operating Voltage Range

V

BATT

●

3.0

1.5

5.50

2.75

V

CC

V

Output Voltage

I

= 1mA

V

CC

– 0.1

– 0.2

V

– 0.01

V – 0.01

CC

V

OUT

CC

●

I

= 50mA

V

CC

– 0.8

V – 0.4

CC

V

OUT

V

OUT

in Battery Back-Up Mode

I

= 250µA, V < V

V

BATT

– 0.1

V – 0.02

BATT

OUT

CC

BATT

Supply Current (Exclude I

)

I

≤ 50mA, V = 3.6V

0.2

0.6

1.0

mA

OUT

CC

●

Supply Current in Battery Back-Up Mode

V

= 0V, V

= 2V

0.04

1

5

µA

CC

BATT

Battery Standby Current (+ = Discharge, – = Charge)

3.6V > V > V

+ 0.2V

–0.02

–0.10

0.02

0.10

µA

CC

BATT

Battery Switchover Threshold (V – V

)

Power Up

Power Down

70

50

mV

CC

BATT

Battery Switchover Hysteresis

BATT ON Output Voltage (Note 4)

20

mV

V

I

= 800µA

●

0.3

25

SINK

BATT ON Output Short-Circuit Current (Note 4)

BATT ON = V , Sink Current

BATT ON = 0V, Source Current

25

1

mA

µA

OUT

0.5

2.8

Reset and Watchdog Timer

Reset Voltage Threshold

Reset Threshold Hysteresis

Reset Active Time

●

2.9

40

3.0

V

mV

OSC SEL HIGH, V = 3V

160

140

200

240

280

ms

CC

●

Watchdog Time-Out Period, Internal Oscillator

Long Period, V = 3V

1.2

1.0

1.6

2.0

2.25

sec

CC

Short Period, V = 3V

80

70

100

120

140

ms

CC

Watchdog Time-Out Period, External Clock (Note 5)

Long Period, V = 3V

●

4032

960

4097

1025

Clock

Cycles

CC

Short Period, V = 3V

CC

Reset Active Time PSRR

4

ms/V

Watchdog Time-Out Period PSRR, Internal OSC

Short Period

Long Period

2

32

ms/V

Minimum WDI Input Pulse Width

V = 0.4V, V = 3V

●

200

2.3

ns

IL

IH

RESET Output Voltage at V = 1V

I

= 10µA, V = 1V

4

200

0.3

mV

CC

SINK

CC

RESET and LOW LINE Output Voltage (Note 4)

I

= 400µA, V = 2.8V

●

V

SINK

CC

I

= 0.1µA, V = 3V

CC

SOURCE

RESET and WDO Output Voltage (Note 4)

I

= 400µA, V = 3V

●

0.3

25

V

SINK

CC

I

= 0.1µA, V = 2.8V

2.3

1

SOURCE

CC

RESET, RESET, WDO, LOW LINE

Output Short-Circuit Current (Note 4)

Output Source Current

Output Sink Current

●

3

9

µA

mA

3

LTC694-3.3/ LTC695-3.3

ELECTRICAL CHARACTERISTICS ^The● denotes specifications which apply over the operating temperature

range, otherwise specifications are at T_A= 25°C. V_CC= 3.3V, V_BATT= 2V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

2.3

TYP

MAX

UNITS

WDI Input Threshold

Logic Low

Logic High

●

0.4

V

WDI Input Current

WDI = V

WDI = 0V

●

4

–8

50

µA

OUT

–50

Power-Fail Detector

PFI Input Threshold

●

1.25

1.3

0.3

1.35

V

mV/V

nA

PFI Input Threshold PSRR

PFI Input Current

●

±0.01

±25

PFO Output Voltage (Note 4)

I

= 800µA

●

0.3

V

SINK

I

= 0.1µA

2.3

1

SOURCE

PFO Short-Circuit Source Current (Note 4)

PFI = HIGH, PFO = 0V

PFI = LOW, PFO = V

●

3

17

25

µA

mA

OUT

PFI Comparator Response Time (Falling)

∆V = –20mV, V = 15mV

2

µs

IN

OD

PFI Comparator Response Time (Rising) (Note 4)

∆V = 20mV, V = 15mV

with 10kΩ Pull-Up

40

8

µs

IN

OD

Chip Enable Gating

CE IN Threshold

V

IH

0.45

V

IL

1.9

CE IN Pull-Up Current (Note 6)

CE OUT Output Voltage

3

µA

I

= 800µA

●

0.3

50

V

SINK

I

= 400µA

= 1µA, V = 0V

V

OUT

– 0.50

– 0.05

SOURCE

OUT

I

SOURCE

CC

CE IN Propagation Delay

C = 20pF

●

30

ns

L

CE OUT Output Short-Circuit Current

Output Source Current

Output Sink Current

15

20

mA

Oscillator

OSC IN Input Current (Note 6)

OSC SEL Input Pull-Up Current (Note 6)

OSC IN Frequency Range

±2

µA

5

OSC SEL = 0V

OSC SEL = 0V, C

●

0

125

kHz

= 47pF

4

OSC

Note 1: Absolute Maximum Ratings are those values beyond which the life

Note 5: The external clock feeding into the circuit passes through the

of device may be impaired.

oscillator before clocking the watchdog timer. Variation in the time-out

period is caused by phase errors which occur when the oscillator divides

the external clock by 64. The resulting variation in the time-out period is

64 plus one clock of jitter.

Note 2: All voltage values are with respect to GND.

Note 3: For military temperature range parts, consult the factory.

Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and

RESET have weak internal pullups of typically 3µA. However, external pull-

up resistors may be used when higher speed is required.

Note 6: The input pins of CE IN, OSC IN and OSC SEL have weak internal

pull-ups which pull to the supply when the input pins are floating.

4

LTC694-3.3/ LTC695-3.3

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TYPICALPERFOR A CE CHARACTERISTICS

Power Failure Input Threshold

vs Temperature

Output Voltage vs Load Current

2.40

2.39

2.38

2.37

2.36

2.35

1.310

3.30

3.25

3.20

3.15

3.10

3.05

3.00

V

= 3.3V

V

= 0V

= 2.4V

= 25°C

V

= 3.3V

= 2.4V

CC

V

T

V

BATT

1.308

1.306

1.304

1.302

1.300

1.298

1.296

1.294

BATT

T

= 25

°

C

A

SLOPE = 4.6Ω

SLOPE = 90Ω

0

100

200

300

400

500

50

TEMPERATURE (

100 125

–50 –25

0

25

75

C)

0

10

20

30

40

50

LOAD CURRENT (µA)

°

LOAD CURRENT (mA)

694/5-3.3 G02

694/5-3.3 G03

694/5-3.3 G01

Power-Fail Comparator

Response Time with Pull-Up

Resistor

Power-Fail Comparator

Response Time

Power-Fail Comparator

Response Time

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= 3.3V

= 25°C

V

= 3.3V

= 25°C

V

= 3.3V

CC

T

T = 25°C

A

V

+

–

PFI

3.3V

10k

PFO

30pF

V

+

–

PFI

1.3V

PFO

30pF

V

+

–

PFI

1.3V

30pF

V

= 20mV STEP

1.305V

1.285V

1.315V

1.295V

1.315V

1.295V

PFI

V

= 20mV STEP

V

= 20mV STEP

PFI

0

1

2

3

4

5

7

8

6

9

140

14

12 16 18

0

60

120

160 180

0

6

20 40

80 100

2

4

8

10

TIME (µs)

694/5-3.3 G04

694/5-3.3 G05

694/5-3.3 G06

Reset Active Time vs

Temperature

Reset Voltage Threshold vs

Temperature

RESET Output Voltage vs

Supply Voltage

2.90

2.89

2.88

2.87

2.86

2.85

2.84

5

220

210

200

190

180

170

160

150

V

= 3.3V

V

= 3.3V

CC

4

3

2

1

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

0

1

3

4

5

2

50

TEMPERATURE (

100 125

–50 –25

0

25

75

C)

SUPPLY VOLTAGE (V)

°

694/5-3.3 TA02

694/5-3.3 G08

694/5-3.3 G07

5

LTC694-3.3/ LTC695-3.3

U U

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PI FU CTIO S

V_CC: 3.3V Supply Input. The V pin should be bypassed

with a 0.1µF capacitor.

every preset time-out period (see Figure 11). The reset

active time is adjustable on the LTC695-3.3. An external

push-button reset can be used in connection with the

RESET output. See Push-Button Reset in Applications

Information section.

CC

V_OUT:Voltage Output for Backed Up Memory. Bypass with

a capacitor of 0.1µF or greater. During normal operation,

V_OUTobtains power from V_CCthrough an NMOS power

switch,M1,whichcandeliverupto50mAandhas atypical

on resistance of 5Ω. When V_CCis lower than V_BATT, V_OUT

is internally switched to V_BATT. If V_OUTand V_BATTare not

RESET: Active High Logic Ouput. It is the inverse of

RESET.

LOW LINE: Logic Output from Comparator C1. LOW LINE

used, connect V_OUTto V .

CC

indicates a low line condition at the V_CCinput. When V

CC

V

_BATT:Back-UpBatteryInput.WhenV falls belowV

,

falls below the reset voltage threshold (2.90V typically),

CC

BATT

auxiliary power connected to V_BATT, is delivered to V

LOW LINE goes low. As soon as V rises above the reset

OUT

CC

through PMOS switch, M2. If back-up battery or auxiliary

voltage threshold, LOW LINE returns high (see Figure 1).

power is not used, V_BATTshould be connected to GND.

LOW LINE goes low when V drops below V_BATT(see

CC

Table 1).

GND: Ground Pin.

WDI: Watchdog Input. WDI is a three-level input. Driving

WDI either high or low for longer than the watchdog time-

outperiod,forces bothRESETandWDOlow.FloatingWDI

disables the watchdog timer. The timer resets itself with

each transition of the watchdog input (see Figure 11).

BATT ON: Battery On Logic Output from Comparator C2.

BATT ON goes low when V_OUTis internally connected to

V_CC.Theoutputtypicallysinks 25mAandcanprovidebase

drive for an external PNP transistor to increase the output

current above the 50mA rating of V_OUT. BATT ON goes

high when V_OUTis internally switched to V

.

WDO: Watchdog Logic Output. When the watchdog input

remains either high or low for longer than the watchdog

time-outperiod,WDOgoes low.WDOis sethighwhenever

thereis atransitionontheWDIpin, orLOWLINEgoes low.

The watchdog timer can be disabled by floating WDI (see

Figure 11).

BATT

PFI: Power Failure Input. PFI is the noninverting input to

the power-fail comparator, C3. The inverting input is

internallyconnectedtoa1.3Vreference. Thepowerfailure

output remains high when PFI is above 1.3V and goes low

when PFI is below 1.3V. Connect PFI to GND or V_OUTwhen

C3 is not used.

CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN

can be derived from microprocessor’s address line and/or

decoder output. See Applications Information section and

Figure 5 for additional information.

PFO: Power Failure Output from C3. PFO remains high

when PFI is above 1.3V and goes low when PFI is below

1.3V. When V_CCis lower than V_BATT, C3 is shut down and

PFO is forced low.

CE OUT: Logic Output on the Chip Enable Gating Circuit.

When V is above the reset voltage threshold, CE OUT is

a buffered replica of CE IN. When V_CCis below the reset

voltage threshold CE OUT is forced high (see Figure 5).

CC

RESET: Logic Output for µP Reset Control. Whenever V

CC

falls below either the reset voltage threshold (2.90V,

typically) or V_BATT, RESET goes active low. After V

CC

returns to 3.3V, the reset pulse generator forces RESET to

remain active low for a minimum of 140ms. When the

watchdog timer is enabled but not serviced prior to a

preset time-out period, the reset pulse generator also

forces RESET to active low for a minimum of 140ms for

OSC SEL: Oscillator Selection Input. When OSC SEL is

high or floating, the internal oscillator sets the reset active

timeandwatchdogtime-outperiod. ForcingOSCSELlow,

allows OSC IN to be driven from an external clock signal or

an external capacitor can be connected between OSC IN

and GND.

6

LTC694-3.3/ LTC695-3.3

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PI FU CTIO S

OSC IN: Oscillator Input. OSC IN can be driven by an

external clock signal or an external capacitor can be

connected between OSC IN and GND when OSC SEL is

forced low. In this configuration the nominal reset active

time and watchdog time-out period are determined by the

number of clocks or set by the formula (see Applications

Information section). When OSC SEL is high or floating,

the internal oscillator is enabled and the reset active time

is fixed at 200ms typical for the LTC695-3.3. OSC IN

selects between the 1.6 seconds and 100ms typical

watchdog time-out periods. In both cases, the time-out

period immediately after a reset is 1.6 seconds typical.

W

BLOCK DIAGRA

M2

V

OUT

BATT

M1

V

CC

CHARGE

PUMP

–

BATT ON

C2

+

LOW LINE

+

C1

–

CE OUT

1.3V

GND

CE IN

–

C3

+

PFO

PFI

RESET

OSC IN

RESET PULSE

GENERATOR

OSC

OSC SEL

RESET

WATCHDOG

TIMER

WDO

TRANSITION

DETECTOR

WDI

694/5-3.3 BD

7

LTC694-3.3/ LTC695-3.3

O U

W

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PPLICATI

S I FOR ATIO

A

Microprocessor Reset

Battery Switchover

TheLTC694-3.3/LTC695-3.3useabandgapvoltagerefer-

enceandaprecisionvoltagecomparatorC1tomonitorthe

3.3V supply input on V (see Block Diagram). When V

The battery switchover circuit compares V to the V

input, and connects V_OUTto whichever is higher. When

V_CCrises to 70mV above V_BATT, the battery switchover

CC

BATT

CC

falls below the reset voltage threshold, the RESET output

is forced to active low state. The reset voltage threshold

comparator, C2, connects V_OUTto V through a charge-

CC

pumped NMOS power switch, M1. When V_CCfalls to

50mV above V_BATT, C2 connects V_OUTto V_BATTthrough a

PMOS switch, M2. C2 has typically 20mV of hysteresis to

prevent spurious switching when V_CCremains nearly

equal to V_BATT. The response time of C2 is approximately

20µs.

accounts for a 10% variation on V , so the RESET output

CC

becomes active low when V falls below 3.0V (2.9V

CC

typical). On power-up, the RESET signal is held active low

for a minimum of 140ms after reset voltage threshold is

reached to allow the power supply and microprocessor to

stabilize.Theresetactivetimeis adjustableontheLTC695-

3.3. On power-down, the RESET signal remains active low

During normal operation, the LTC694-3.3/LTC695-3.3

use a charge-pumped NMOS power switch to achieve low

dropout and low supply current. This power switch can

even with V as low as 1V. This capability helps hold the

CC

microprocessor in stable shutdown condition. Figure 1

shows the timing diagram of the RESET signal.

deliver up to 50mA to V_OUTfrom V and has a typical on

CC

resistance of 5Ω. The V_OUTpin should be bypassed with

a capacitor of 0.1µF or greater to ensure stability. Use of

a larger bypass capacitor is advantageous for supplying

current to heavy transient loads.

The precision voltage comparator, C1, typically has 40mV

of hysteresis which ensures that glitches at V pin do not

CC

activate the RESET output. Response time is typically

10µs.Tohelppreventmistriggeringduetotransientloads,

When operating currents larger than 50mA are required

theV pinshouldbebypassedwitha0.1µFcapacitorwith

CC

from V_OUT, or a lower dropout (V -V_OUTvoltage differen-

CC

the leads trimmed as short as possible.

tial) is desired, the LTC695-3.3 should be used. This

product provides BATT ON output to drive the base of an

external PNP transistor (Figure 2). If higher currents are

needed with the LTC694-3.3, a high current Schottky

diode can be connected from the V_CCpin to the V_OUTpin

to supply the extra current.

The LTC695-3.3 has two additional outputs: RESET and

LOW LINE. RESET is an active high output and is the

inverse of RESET. LOW LINE is the output of the precision

voltage comparator C1. When V_CCfalls below the reset

voltage threshold, LOW LINE goes low. LOW LINE returns

highassoonasV_CCrises abovetheresetvoltagethreshold.

V2

V1

V1 = RESET VOLTAGE THRESHOLD

V

CC

V2 = RESET VOLTAGE THRESHOLD +

RESET THRESHOLD HYSTERESIS

RESET

t

1

t

1

t

= RESET ACTIVE TIME

1

LOW LINE

694/5-3.3 F01

Figure 1. Reset Active Time

8

LTC694-3.3/ LTC695-3.3

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PPLICATI

A

S I FOR ATIO

ANY PNP POWER TRANSISTOR

V

– V

BATT

R

OUT

I =

R

5

V

3.3V

0.1µF

V

OUT

CC

BATT ON

3

0.1µF

1

2

3.3V

V

CC

0.1µF

OUT

LTC694-3.3

LTC695-3.3

0.1µF

LTC695-3.3

V

BATT

V

BATT

GND

2.4V

GND

2.4V

4

694/5-3.3 F02

694/5-3.3 F03

Figure 3. Charging External Battery Through V_OUT

Figure 2. Using BATT ON to Drive External PNP Transistor

The LTC694-3.3/LTC695-3.3 are protected for safe area

operation with short-circuit limit. Output current is limited

to approximately 200mA. If the device is overloaded for a

long period of time, thermal shutdown turns the power

switch off until the device cools down. The threshhold

temperatureforthermalshutdownis approximately155°C

with about 10°C of hysteresis which prevents the device

from oscillating in and out of shutdown.

Replacing the Back-Up Battery

When changing the back-up battery with system power

on, spurious resets canoccurwhilethebatteryis removed

due to battery standby current. Although battery standby

current is only a tiny leakage current, it can still charge up

the stray capacitance on the V_BATTpin. The oscillation

cycle is as follows: When V_BATTreaches within 50mV of

V , the LTC694-3.3/LTC695-3.3 switch to battery back-

CC

The PNP switch used in competitive devices was not

chosen for the internal power switch because it injects

unwanted current into the substrate. This current is col-

lected by the V_BATTpin in competitive devices and adds to

the charging current of the battery which can damage

lithiumbatteries.TheLTC694-3.3/LTC695-3.3useacharge-

pumpedNMOSpowerswitchtoeliminateunwantedcharg-

ing current while achieving low dropout and low supply

current. Sincenocurrentgoes tothesubstrate, thecurrent

collected by V_BATTpin is strictly junction leakage.

up. V

pulls V_BATTlow and the device goes back to

OUT

normaloperation.Theleakagecurrentthencharges upthe

_BATTpin again and the cycle repeats.

V

If spurious resets during battery replacement pose no

problems, then no action is required. Otherwise, a resistor

fromV_BATTtoGNDwillholdthepinlowwhilechangingthe

battery. For example, the battery standby current is 1µA

maximum over temperature so the external resistor re-

quired to hold V_BATTbelow V is:

CC

V – 50mV

A 125Ω PMOS switch connects the V_BATTinput to V_OUTin

battery back-up mode. The switch is designed for very low

dropout voltage (input-to-output differential). This feature

is advantageous for low current applications such as

batteryback-upinCMOSRAMandotherlowpowerCMOS

circuitry. The supply current in battery back-up mode is

1µA maximum.

CC

R ≤

1µA

WithV =3V, a2.7Mresistorwillwork. Witha2Vbattery,

CC

this resistor will draw only 0.7µA from the battery, which

is negligible in most cases.

Ifbatteryconnections aremadethroughlongwires, a10Ω

to 100Ω series resistor and a 0.1µF capacitor are recom-

mended to prevent any overshoot beyond V due to the

The operating voltage at the V_BATTpin ranges from 1.5V to

2.75V. The charging resistor for rechargeable batteries

should be connected to V_OUTsince this eliminates the

discharge path that exists when the resistor is connected

CC

lead inductance (Figure 4).

to V (Figure 3).

CC

9

LTC694-3.3/ LTC695-3.3

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PPLICATI

S I FOR ATIO

A

10Ω

Table1shows thestateofeachpinduringbatteryback-up.

When the battery switchover section is not used, connect

V

BATT

0.1µF

2.7M

LTC694-3.3

LTC695-3.3

V

_BATTto GND and V_OUTto V .

CC

Memory Protection

GND

The LTC695-3.3 includes memory protection circuitry

which ensures the integrity of the data in memory by

preventing write operations when V_CCis at invalid level.

Two additional pins, CE IN and CE OUT, control the Chip

Enable or Write inputs of CMOS RAM. When V_CCis 3.3V,

CE OUT follows CE IN with a typical propagation delay of

694/5-3.3 F04

Figure 4. 10Ω/0.1µF Combination Eliminates Inductive

Overshoot and Prevents Spurious Resets During Battery

Replacement. The 2.7M Pulls the V_BATTPin to Ground

While the Battery is Removed, Eliminating Spurious Resets

30ns. When V falls below the reset voltage threshold or

CC

Table 1. Input and Output Status in Battery Back-Up Mode

V_BATT, CE OUT is forced high, independent of CE IN. CE

OUT is an alternative signal to drive the CE, CS, or Write

input of battery backed up CMOS RAM. CE OUT can also

be used to drive the Store or Write input of an EEPROM,

EAROM or NOVRAM to achieve similar protection. Figure

5 shows the timing diagram of CE IN and CE OUT.

SIGNAL

STATUS

V

CC

C2 monitors V for active switchover

CC

V

OUT

V

OUT

is connected to V

through an internal PMOS switch

BATT

V

BATT

The supply current is 1µA maximum.

BATT ON Logic high. The open-circuit output voltage is equal to V

OUT

PFI

Power failure input is ignored

Logic low

CE IN can be derived from the microprocessor’s address

decoder output. Figure 6 shows a typical nonvolatile

CMOS RAM application.

PFO

RESET

Logic low

Logic high. The open-circuit output voltage is equal to V

OUT

LOW LINE Logic low

MemoryprotectioncanalsobeachievedwiththeLTC694-

3.3 by using RESET as shown in Figure 7.

WDI

Watchdog input is ignored.

Logic high. The open-circuit output voltage is equal to V

WDO

OUT

CE IN

CE OUT

OSC IN

Chip Enable input is ignored.

Logic high. The open-circuit output voltage is equal to V

Power-Fail Warning

OUT

The LTC694-3.3/LTC695-3.3 generate a Power Failure

Output (PFO) for early warning of failure in the

microprocessor’s power supply. This is accomplished by

OSC IN is ignored

OSC SEL OSC SEL is ignored

V2

V

V1 = RESET VOLTAGE THRESHOLD

V2 = RESET VOLTAGE THRESHOLD +

RESET THRESHOLD HYSTERESIS

CC

V1

CE IN

V

= V

BATT

OUT

CE OUT

V

= V

BATT

OUT

694/5-3.3 F05

Figure 5. Timing Diagram for CE IN and CE OUT

10

LTC694-3.3/ LTC695-3.3

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PPLICATI

A

I FOR ATIO

comparing the power failure input (PFI) with an internal

1.3V reference.

V

CC

3.3V

CC

OUT

+

0.1µF

62512

RAM

10µF

LTC695-3.3

CE OUT

CS

PFO goes low when the voltage at the PFI pin is less than

1.3V. Typically PFI is driven by an external voltage divider

(R1 and R2 in Figures 8 and 9) which senses either an

unregulated DC input or a regulated 3.3V output. The

voltage divider ratio can be chosen such that the voltage

at the PFI pin falls below 1.3V several milliseconds before

the 3.3V supply falls below the maximum reset voltage

threshold 3.0V. PFO is normally used to interrupt the

microprocessor to execute shutdown procedure between

PFO and RESET or RESET.

GND

30ns PROPAGATION DELAY

FROM DECODER

V

BATT

CE IN

RESET

2.4V

GND

RESET

694/5-3.3 F06

TO µP

Figure 6. A Typical Nonvolatile CMOS RAM Application

V

CC

3.3V

0.1µF

CC

OUT

+

0.1µF

62128

RAM

10µF

LTC694-3.3

The power-fail comparator, C3, does not have hysteresis.

Hysteresis can be added however, by connecting a resis-

tor between the PFO output and the noninverting PFI input

pin as shown in Figures 8 and 9. The upper and lower trip

points in the comparator are established as follows:

CS1

CS2

CS

V

RESET

GND

BATT

2.4V

GND

694/5-3.3 F07

Figure 7. Write Protect for RAM with LTC694-3.3

When PFO output is low, R3 sinks current from the

summing junction at the PFI pin.

V

≥ 5V

LT1129-3.3

3.3V

IN

R1 R1

V

OUT

CC

IN

V =1.3V 1+

+

H

R2 R3

10µF OUT SENSE

100µF

0.1µF

LTC694-3.3

LTC695-3.3

SHDN

ADJ

R4

10k

R3

200k

R1

51k

WhenPFOoutputis high,theseries combinationofR3and

R4 source current into the PFI summing junction.

PFO

PFI

GND

R2

16k

TO µP

R1 (3.3V –1.3V)R1

V =1.3V 1+

–

694/5-3.3 F08

L

R2 1.3V(R3 +R4)

Figure 8. Monitoring Unregulated DC Supply with the

LTC694-3.3/LTC695-3.3’s Power-Fail Comparator

R1

R3

Assuming R4 << R3,V

=3.3V

HYSTERESIS

Example 1:The circuit in Figure 8 demonstrates the use of

the power-fail comparator to monitor the unregulated

power supply input. Assuming the the rate of decay of the

LT1129-3.3

V

≥ 6.5V

10µF

0.1µF

10µF

IN

3.3V

V

OUT

CC

IN

+

OUT SENSE

R4

10k

R1

LTC694-3.3

LTC695-3.3

27k

SHDN

ADJ

R3

2.7M

supplyinputV is 100mV/ms andthetotaltimetoexecute

IN

PFO

PFI

a shutdown procedure is 8ms. Also the noise of V is

IN

GND

200mV. With these assumptions in mind, we can reason-

R2

16k

ably set V = 5V which is 1.6V greater than the sum of

TO µP

L

R5

5k

maximum reset voltage threshold and the dropout voltage

of the LT1129-3.3 (3V + 0.4V) and V_HYSTERESIS= 850mV.

694/5-3.3 F09

Figure 9. Monitoring Regulated DC Supply with the

LTC694-3.3/LTC695-3.3’s Power-Fail Comparator

11

LTC694-3.3/ LTC695-3.3

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PPLICATI

S I FOR ATIO

A

3.3V

R1

V

= 3.3V = 850mV

HYSTERESIS

R3

V

CC

V

BATT

LOW-BATTERY SIGNAL

TO µP I/O PIN

PFO

R3 ≈ 3.88 R1

R1

1M

LTC695-3.3

PFI

Choose R3 = 200k and R1 = 51k. Also select R4 = 10k

which is much smaller than R3.

R2

1.6M

2.4V

CE IN

GND

I/O PIN

CE OUT

51k (3.3V –1.3V)51k

5V =1.3V 1+

–

R

L

R2

R2 = 15.8k, Choose nearest 5% resistor 16k and recalcu-

late V ,

1.3V(210k)

20k

OPTIONAL TEST LOAD

694/5-3.3 F10

L

Figure 10. Back-Up Battery Monitor with Optional Test Load

51k (3.3V – 1.3V)51k

V = 1.3V 1+

–

= 4.96V

L

Watchdog Timer

16k

1.3V(210k)

The LTC694-3.3/LTC695-3.3 provide a watchdog timer

function to monitor the activity of the microprocessor. If

the microprocessor does not toggle the watchdog input

(WDI)withinaselecedtime-outperiod, RESETis forcedto

active low for a minimum of 140ms. The reset active time

is adjustable on the LTC695-3.3. Since many systems can

not service the watchdog timer immediately after a reset,

the LTC695-3.3 has a longer time-out period (1.0 second

minimum) right after a reset is issued. The normal time-

out period (70ms minimum) becomes effective following

the first transition of WDI after RESET is inactive. The

watchdog time-out period is fixed at 1.0 second minimum

ontheLTC694-3.3. Figure11shows thetimingdiagramof

watchdog time-out period and reset active time. The

watchdog time-out period is restarted as soon as RESET

is inactive. When either a high-to-low or low-to-high

transition occurs at the WDI pin prior to time-out, the

watchdog time is reset and begins to time out again. To

ensure the watchdog time does not time out, either a high-

to-low or low-to-high transition on the WDI pin must

occur at or less than the minimum time-out period. If the

input to the WDI pin remains either high or low, reset

pulses will be issued every 1.6 seconds typically. The

watchdog time can be deactivated by floating the WDI pin.

51k 51k

V = 1.3V 1+

+

= 5.77V

H

16 k 200k

(4.96V – 3.4V)

100mV/ms

= 15.6ms

V

_HYSTERESIS= 5.77V – 4.96V = 810mV

The 15.6ms allows enough time to execute shutdown

procedure for microprocessor and 810mV of hysteresis

would prevent PFO from going low due to the noise of V .

IN

Example 2: The circuit in Figure 9 can be used to measure

the regulated 3.3V supply to provide early warning of

power failure. Because of variations in the PFI threshold,

this circuit requires adjustment to ensure the PFI com-

parator trips before the reset threshold is reached. Adjust

R5suchthatthePFOoutputgoes lowwhentheV supply

reaches the desired level (e.g., 3.1V).

CC

Monitoring the Status of the Battery

C3 can also monitor the status of the memory back-up

battery (Figure 10). If desired, the CE OUT can be used to

applyatestloadtothebattery. SinceCEOUTis forcedhigh

in battery back-up mode, the test load will not be applied

to the battery while it is in use, even if the microprocessor

is not powered.

The timer is also disabled when V falls below the reset

CC

voltage threshold or V

.

BATT

12

LTC694-3.3/ LTC695-3.3

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PPLICATI

I FOR ATIO

A

V

= 3.3V

CC

WDI

t

= RESET ACTIVE TIME

1

2

3

= NORMAL WATCHDOG TIME-OUT PERIOD

= WATCHDOG TIME-OUT PERIOD IMMEDIATELY

AFTER A RESET

WDO

t

3

2

RESET

t

1

694/5-3.3 F11

Figure 11. Watchdog Time-Out Period and Reset Active Time

EXTERNAL OSCILLATOR

EXTERNAL CLOCK

8

3

8

7

3

4

OSC SEL

3.3V

V

CC

OSC SEL

OSC IN

CC

LTC695-3.3

7

4

GND

OSC IN

GND

INTERNAL OSCILLATOR

1.6 SECOND WATCHDOG

INTERNAL OSCILLATOR

100ms WATCHDOG

3

8

3

8

7

FLOATING

OR HIGH

FLOATING

OR HIGH

V

3.3V

OSC SEL

CC

OSC SEL

CC

LTC695-3.3

7

4

FLOATING

OR HIGH

4

OSC IN

GND

694/5-3.3 F12

Figure 12. Oscillator Configurations

The LTC695-3.3 provides an additional output (Watchdog

Output, WDO) which goes low if the watchdog timer is

allowed to time out and remains low until set high by the

next transition on the WDI pin. WDO is also set high when

OSC IN can be driven by an external clock signal or an

external capacitor can be connected between OSC IN and

GNDwhenOSCSELis forcedlow. Intheseconfigurations,

the nominal reset active time and watchdog time-out

period are determined by the number of clocks or set by

the formula in Table 2. When OSC SEL is high or floating,

the internal oscillator is enabled and the reset active time

is fixed at 140ms minimum for the LTC695-3.3. OSC IN

selects between the 1 second and 70ms minimum normal

watchdog time-out periods. In both cases, the time-out

period immediately after a reset is at least 1 second.

V falls below the reset voltage threshold or V

.

CC

BATT

TheLTC695-3.3has twoadditonalpins,OSCSELandOSC

IN, which allow reset active time and watchdog time-out

period to be adjusted per Table 2. Several configurations

are shown in Figure 12.

13

LTC694-3.3/ LTC695-3.3

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PPLICATI

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A

Table 2. LTC695-3.3 Reset Active Time and Watchdog Time-Out Selections

WATCHDOG TIME-OUT PERIOD

RESET ACTIVE TIME

IMMEDIATELY

AFTER RESET

(Long Period)

NORMAL

(Short Period)

OSC SEL

OSC IN

LTC695-3.3

Low

External Clock Input

1024 CLKs

4096 CLKs

2048 CLKs

400ms

• C

1.6 sec

• C

800ms

• C

Low

External Capacitor*

70pF

Floating or High

Low

100ms

1.6 sec

200ms

Floating or High

184,000

C(pF) • 1025

*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is f

(Hz) =

OSC

Push-Button Reset

V

3.3V

RESET

LTC694-3.3

RESET

MPU

CC

100Ω

0.1µF

The LTC694-3.3/LTC695-3.3 do not provide a logic input

for direct connection to a push-button. However, a push-

button in series with a 100Ω resistor connected to the

RESET output pin (Figure 13) provides an alternative for

manual reset. Connecting a 0.1µF capacitor to the RESET

pin debounces the push-button input.

(e.g. 68HC05)

LTC695-3.3

GND

694/5-3.3 F13

Figure 13. The External Push-Button Reset

The 100Ω resistor in series with the push-button is

required to prevent the ringing, due to the capacitance and

lead inductance, from pulling the RESET pins of the MPU

and LTC69X below ground.

U

O

TYPICAL APPLICATI

Capacitor Back-Up with 74HC4016 Switch

3.3V

V

CC

OUT

0.1µF

10 11 12 14

0.1µF

R1

10k

LTC695-3.3

LOW LINE

2

1

V

74HC4016

BATT

R2

30k

7

13

100µF

+

GND

694/5-3.3 TA03

14

LTC694-3.3/ LTC695-3.3

U

Dimensions in inches (millimeters) unless otherwise noted.

PACKAGE DESCRIPTIO

N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)

0.400*

(10.160)

MAX

0.130 ± 0.005

0.300 – 0.325

0.045 – 0.065

(3.302 ± 0.127)

(1.143 – 1.651)

(7.620 – 8.255)

8

7

6

5

0.065

(1.651)

TYP

0.255 ± 0.015*

(6.477 ± 0.381)

0.009 – 0.015

0.125

(0.229 – 0.381)

0.020

(3.175)

MIN

+0.035

–0.015

(0.508)

MIN

1

2

4

3

0.325

N8 1197

0.100 ± 0.010

(2.540 ± 0.254)

0.018 ± 0.003

+0.889

–0.381

8.255

(

)

(0.457 ± 0.076)

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610)

0.189 – 0.197*

(4.801 – 5.004)

0.010 – 0.020

(0.254 – 0.508)

7

5

8

6

× 45°

0.053 – 0.069

(1.346 – 1.752)

0.004 – 0.010

(0.101 – 0.254)

0.008 – 0.010

(0.203 – 0.254)

0°– 8° TYP

0.150 – 0.157**

(3.810 – 3.988)

0.228 – 0.244

(5.791 – 6.197)

0.016 – 0.050

0.406 – 1.270

0.050

(1.270)

TYP

0.014 – 0.019

(0.355 – 0.483)

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

SO8 0996

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1

2

3

4

N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)

0.770*

(19.558)

MAX

0.300 – 0.325

0.130 ± 0.005

0.045 – 0.065

(7.620 – 8.255)

(3.302 ± 0.127)

(1.143 – 1.651)

14

12

10

9

15

13

11

16

0.020

(0.508)

MIN

0.255 ± 0.015*

(6.477 ± 0.381)

0.065

0.009 – 0.015

(1.651)

TYP

(0.229 – 0.381)

+0.035

–0.015

2

1

3

4

6

8

5

7

0.325

0.125

0.018 ± 0.003

0.100 ± 0.010

(2.540 ± 0.254)

N16 1197

+0.889

–0.381

(3.175)

MIN

(0.457 ± 0.076)

8.255

(

)

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

SW Package 16-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620)

0.291 – 0.299**

(7.391 – 7.595)

0.398 – 0.413*

(10.109 – 10.490)

0.037 – 0.045

(0.940 – 1.143)

0.093 – 0.104

(2.362 – 2.642)

15 14

12

10

11

9

16

13

0.010 – 0.029

(0.254 – 0.737)

× 45°

0° – 8° TYP

0.050

(1.270)

TYP

0.394 – 0.419

(10.007 – 10.643)

NOTE 1

0.009 – 0.013

(0.229 – 0.330)

NOTE 1

0.014 – 0.019

0.004 – 0.012

(0.102 – 0.305)

0.016 – 0.050

(0.356 – 0.482)

TYP

(0.406 – 1.270)

NOTE:

1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.

THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

S16 (WIDE) 0396

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

2

3

5

7

8

1

4

6

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofits circuits as describedhereinwillnotinfringeonexistingpatentrights.

15

LTC694-3.3/ LTC695-3.3

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O

TYPICAL APPLICATI

Write Protect for Additional RAMs

3.3V

V

OUT

+

CC

0.1µF

10µF

LH5168SH

RAM A

0.1µF

LTC695-3.3

CS

CE OUT

30ns PROPAGATION

DELAY

V

BATT

CE IN

CS A

2.4V

LOW LINE

GND

V

CC

0.1µF

LH5116S

RAM B

CS1

CS B

CS2

V

CC

LH5116S

RAM C

CS C

CS1

CS2

OPTIONAL CONNECTION FOR

ADDITIONAL RAMs

694/5-3.3 TA04

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1326

Micropower Precision Triple Supply Monitor

4.725V, 3.118V, 1V Thresholds (±0.75%)

Meets PCI t Timing Specifications

LTC1536

Micropower Triple Supply Monitor for PCI Applications

FAIL

69453fa LT/TP 0399 2K REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

LINEAR TECHNOLOGY CORPORATION 1993

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com


型号：	LTC694IS8-3.3#TR
厂家：	Linear
描述：	LTC694-3.3 - 3.3V Microprocessor Supervisory Circuits; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C 电源电路电源管理电路微处理器监控
文件：	总16页 (文件大小：142K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC694IS8-3.3#TR [Linear]

相关型号：

LTC694IS8-3.3#TRPBF

LTC694IS8-PBF

LTC694IS8PBF

LTC694_15

LTC695

LTC695-3.3

LTC695-3.3CSW

LTC695-3.3_15

LTC6957-1

LTC6957-1

LTC6957-1_15

LTC6957-2