LTC694IS8PBF [Linear]
Microprocessor Supervisory Circuits; 微处理器监控电路型号: | LTC694IS8PBF |
厂家: | Linear |
描述: | Microprocessor Supervisory Circuits |
文件: | 总18页 (文件大小:217K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC690/LTC691
LTC694/LTC695
Microprocessor
Supervisory Circuits
FEATURES
DESCRIPTION
The LTC®690 family provides complete power supply
monitoringandbatterycontrolfunctionsformicroprocessor
reset,batteryback-up,CMOSRAMwriteprotection,power
failure warning and watchdog timing. A precise internal
voltagereferenceandcomparatorcircuitmonitorthepower
supply line. When an out-of-tolerance condition occurs,
the reset outputs are forced to active states and the chip
enable output unconditionally write-protects external
memory. In addition, the RESET output is guaranteed to
n
Guaranteed Reset Assertion at V = 1V
CC
n
1.5mA Maximum Supply Current
n
Fast (35ns Max) Onboard Gating of RAM Chip
Enable Signals
SO-8 and S16 Packaging
4.65V Precision Voltage Monitor
n
n
n
Power OK/Reset Time Delay: 50ms, 200ms
or Adjustable
n
Minimum External Component Count
n
1µA Maximum Standby Current
remain logic low even with V as low as 1V.
CC
n
Voltage Monitor for Power-Fail
The LTC690 family powers the active CMOS RAMs with a
charge pumped NMOS power switch to achieve low drop-
out and low supply current. When primary power is lost,
auxiliary power, connected to the battery input pin, powers
the RAMs in standby through an efficient PMOS switch.
or Low-Battery Warning
Thermal Limiting
n
n
Performance Specified Over Temperature
n
Superior Upgrade for MAX690 Family
APPLICATIONS
Foranearlywarningofimpendingpowerfailure,theLTC690
family provides an internal comparator with a user-defined
threshold.Aninternalwatchdogtimerisalsoavailable,which
forces the reset pins to active states when the watchdog
input is not toggled prior to a preset timeout period.
n
Critical μP Power Monitoring
n
Intelligent Instruments
n
Battery-Powered Computers and Controllers
n
Automotive Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
RESET Output Voltage
vs Supply Voltage
5
T
= 25°C
A
LT®1086-5
EXTERNAL PULL-UP = 10μA
= 0V
V
≥ 7.5V
5V
IN
V
BATT
POWER TO
μP
V
V
V
CC
4
3
V
IN
OUT
OUT
+
+
CMOS RAM POWER
0.1μF
3V
0.1μF
LTC690/LTC691
LTC694/LTC695
100μF
10μF
ADJ
μP
SYSTEM
V
BATT
μP RESET
μP NMI
RESET
PFO
2
1
0
51k
10k
I/O LINE
PFI
WDI
GND
690 TA01
0.1μF 100Ω
MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE
WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR MICROPROCESSOR SYSTEMS
0
1
2
3
4
5
SUPPLY VOLTAGE (V)
690 TA02
690fe
1
LTC690/LTC691
LTC694/LTC695
ABSOLUTE MAXIMUM RATINGS
(Notes 1 and 2)
Terminal Voltage
V
Output Current ...................Short-Circuit Protected
OUT
V
V
.....................................................–0.3V to 6.0V
.................................................. –0.3V to 6.0V
Power Dissipation...............................................500mW
Operating Temperature Range
CC
BATT
All Other Inputs ....................–0.3V to (V
+ 0.3V)
LTC690/91/94/95C ............................... 0°C to 70°C
LTC690/91/94/95I ............................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec.) ................. 300°C
OUT
Input Current
V
................................................................200mA
BATT
CC
V
...............................................................50mA
GND.................................................................20mA
PIN CONFIGURATION
TOP VIEW
TOP VIEW
V
RESET
RESET
WDO
CE IN
CE OUT
WDI
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
RESET
RESET
WDO
16
15
14
13
BATT
BATT
V
V
OUT
OUT
V
V
CC
3
4
5
6
7
8
CC
GND
GND
BATT ON
LOW⎯LINE
OSC IN
CE IN
BATT ON
LOW⎯LINE
OSC IN
12
CE OUT
11 WDI
PFO
PFO
10
9
OSC SEL
PFI
PFI
OSC SEL
SW PACKAGE
16-LEAD WIDE PLASTIC SO
N PACKAGE
16-LEAD PDIP
T
JMAX
= 110°C, θ = 130°C/W CONDITIONS: PCB MOUNT ON
JA
FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE
T
= 110°C, θ = 130°C/W
JMAX
JA
TOP VIEW
TOP VIEW
V
V
1
2
3
4
V
BATT
8
7
6
5
1
2
8
7
6
5
V
BATT
OUT
OUT
V
V
RESET
RESET
WDI
CC
CC
WDI
GND
PFI
GND
PFI
3
4
PFO
PFO
S8 PACKAGE
8-LEAD PLASTIC SO
N8 PACKAGE
8-LEAD PDIP
T
= 110°C, θ = 180°C/W CONDITIONS; PCB MOUNT ON
JA
T
= 110°C, θ = 130°C/W (N8)
JA
JMAX
JMAX
FR4 MATERIAL, STILL AIR AT 25°C, COPPER TRACE
690fe
2
LTC690/LTC691
LTC694/LTC695
ORDER INFORMATION
LEAD FREE FINISH
LTC691CN#PBF
LTC691IN#PBF
TAPE AND REEL
LTC691CN#PBF
LTC691IN#PBF
LTC695CN#PBF
LTC695IN#PBF
LTC691CSW#PBF
LTC691ISW#PBF
LTC695CSW#PBF
LTC695ISW#PBF
LTC690CN8#PBF
LTC690IN8#PBF
LTC694CN8#PBF
LTC694IN8#PBF
LTC690CS8#PBF
LTC690IS8#PBF
LTC694CS8#PBF
LTC694IS8#PBF
PART MARKING
LTC691CN
PACKAGE DESCRIPTION
16-Lead PDIP
TEMPERATURE RANGE
0°C to 70°C
LTC691IN
16-Lead PDIP
–40°C to 85°C
0°C to 70°C
LTC695CN#PBF
LTC695IN#PBF
LTC695CN
16-Lead PDIP
LTC695IN
16-Lead PDIP
–40°C to 85°C
0°C to 70°C
LTC691CSW#PBF
LTC691ISW#PBF
LTC695CSW#PBF
LTC695ISW#PBF
LTC690CN8#PBF
LTC690IN8#PBF
LTC694CN8#PBF
LTC694IN8#PBF
LTC690CS8#PBF
LTC690IS8#PBF
LTC694CS8#PBF
LTC694IS8#PBF
LTC691CSW
LTC691ISW
LTC695CSW
LTC695ISW
LTC690CN8
LTC690IN8
LTC694CN8
LTC694IN8
LTC690CS8
LTC690IS8
LTC694CS8
LTC694IS8
16-Lead Wide Plastic SO
16-Lead Wide Plastic SO
16-Lead Wide Plastic SO
16-Lead Wide Plastic SO
8-Lead PDIP
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
8-Lead PDIP
–40°C to 85°C
0°C to 70°C
8-Lead PDIP
8-Lead PDIP
–40°C to 85°C
0°C to 70°C
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic SO
8-Lead Plastic SO
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
PRODUCT SELECTION GUIDE
CONDITIONAL
BATTERY
BACK-UP
WATCHDOG
TIMER
BATTERY
BACK-UP
POWER-FAIL
WARNING
RAM WRITE
PROTECT
PUSHBUTTON
RESET
PINS
8
RESET
LTC690
LTC691
LTC694
LTC695
LTC699
LTC1232
LTC1235
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
16
8
X
X
16
8
8
X
X
16
X
X
X
X
690fe
3
LTC690/LTC691
LTC694/LTC695
ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Battery Back-Up Switching
Operating Voltage Range
V
V
4.75
2.00
5.50
4.25
V
V
CC
BATT
V
OUT
Output Voltage
I
= 1mA
V
V
– 0.05
– 0.10
V
CC
V
CC
– 0.005
– 0.005
V
V
OUT
CC
CC
l
I
I
I
= 50mA
V
– 0.50
V
– 0.250
V
V
OUT
OUT
OUT
CC
CC
V
in Battery Back-Up Mode
= 250μA, V < V
V
– 0.1
V
– 0.2
BATT
OUT
CC
BATT
BATT
Supply Current (Exclude I
)
= 50mA
0.6
0.6
1.5
2.5
mA
mA
OUT
l
l
l
Supply Current in Battery Back-Up Mode
V
= 0V, V
= 2.8V
0.04
0.04
1
5
μA
μA
CC
BATT
Battery Standby Current (+ = Discharge, – = Charge) 5.5 > V > V
+ 0.2V
BATT
–0.1
–0.1
+0.02
+0.10
μA
μA
CC
Battery Switchover Threshold, V – V
Power Up
Power Down
70
50
mV
mV
CC
BATT
Battery Switchover Hysteresis
20
mV
V
BATT ON Output Voltage (Note 4)
I
= 3.2mA
0.4
25
SINK
BATT ON Output Short-Circuit Current (Note 4)
BATT ON = V
Sink Current
35
1
m
OUT
BATT ON = 0V Source Current
0.5
4.5
μA
Reset and Watchdog Timer
Reset Voltage Threshold
l
4.65
40
4.75
V
Reset Threshold Hysteresis
Reset Active Time (LTC690/91) (Note 5)
mV
OSC SEL HIGH, V = 5V
40
35
50
50
60
70
ms
ms
CC
l
l
l
l
Reset Active Time (LTC694/95) (Note 5)
OSC SEL HIGH, V = 5V
160
140
200
200
240
280
ms
ms
CC
Watchdog Timeout Period, Internal Oscillator
Long Period, V = 5V
1.2
1
1.6
1.6
2.00
2.25
sec
sec
CC
Short Period, V = 5V
80
70
100
100
120
140
ms
ms
CC
Watchdog Timeout Period, External Clock (Note 6)
Long Period
Short Period
4032
960
4097
1025
Clock
Cycles
Reset Active Time PSRR
1
1
ms/V
ms/V
ns
Watchdog Timeout Period PSRR, Internal OSC
Minimum WDI Input Pulse Width
l
V
IL
= 0.4V, V = 3.5V
200
IH
RESET Output Voltage at V = 1V
I
= 10μA, V = 1V
4
200
0.4
mV
CC
SINK
CC
RESET and LOW⎯LINE Output Voltage (Note 4)
I
I
= 1.6mA, V = 4.25V
V
V
SINK
CC
= 1μA, V = 5V
3.5
3.5
SOURCE
CC
RESET and WDO Output Voltage (Note 4)
I
I
= 1.6mA, V = 5V
0.4
V
V
SINK
CC
= 1μA, V = 4.25V
SOURCE
CC
690fe
4
LTC690/LTC691
LTC694/LTC695
ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the operating temperature
range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
3
MAX
UNITS
μA
RESET, RESET, WDO, LOW⎯LINE
Output Short-Circuit Current (Note 4)
Output Source Current
Output Sink Current
1
25
25
mA
V
WDI Input Threshold
WDI Input Current
Logic Low
Logic high
0.8
50
3.5
l
l
WDI = V
4
–8
μA
OUT
WDI = 0V
–50
Power-Fail Detector
PFI Input Threshold
l
V
CC
= 5V
1.25
1.3
1.35
V
mV/V
nA
PFI Input Threshold PSRR
PFI Input Current
0.3
0.01
25
PFO Output Voltage (Note 4)
I
I
= 3.2mA
SOURCE
0.4
V
SINK
= 1μA
3.5
1
PFO Short-Circuit Source Current (Note 4)
PFI = HIGH, PFO = 0V
PFI = LOW, PFO = V
3
25
2
25
μA
mA
μs
OUT
PFI Comparator Response Time (Falling)
ΔV = –20mV, V = 15mV
IN OD
PFI Comparator Response Time (Rising) (Note 4)
ΔV = 20mV, V = 15mV
40
8
μs
IN
OD
with 10kΩ Pull-Up
Chip Enable Gating
CE IN Threshold
V
V
0.8
0.4
V
IL
IH
2
CE IN Pull-Up Current (Note 7)
CE OUT Output Voltage
3
μA
V
I
I
I
= 3.2mA
SINK
SOURCE
SOURCE
= 3.0mA
V
OUT
V
OUT
– 1.50
– 0.05
= 1μA, V = 0V
CC
CE Propagation Delay
V
CC
= 5V, C = 20pF
20
20
35
45
ns
L
l
CE OUT Output Short-Circuit Current
Output Source Current
Output Sink Current
30
35
mA
Oscillator
OSC IN Input Current (Note 7)
OSC SEL Input Pull-Up Current (Note 7)
OSC IN Frequency Range
2
5
μA
μA
l
OSC SEL = 0V
0
250
kHz
kHz
OSC IN Frequency with External Capacitor
OSC SEL = 0V, C
= 47pF
4
OSC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms
(50ms typically) while the LTC694 and LTC695 have longer minimum
reset active time of 140ms (200ms typically). The reset active time of
the LTC691 and LTC695 can be adjusted (see Table 2 in Applications
Information section).
Note 2: All voltage values are with respect to GND.
Note 6: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer (See Block Diagram).
Variation in the timeout period is caused by phase errors which occur
when the oscillator divides the external clock by 64. The resulting variation
in the timeout period is 64 clocks plus one clock of jitter.
Note 3: For military temperature range parts or for the LTC692 and
LTC693, consult the factory.
Note 4: The output pins of BATT ON, LOW⎯LINE, PFO, WDO, RESET and
RESET have weak internal pull-ups of typically 3μA. However, external pull-
up resistors may be used when higher speed is required.
Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pullups which pull to the supply when the input pins are floating.
690fe
5
LTC690/LTC691
LTC694/LTC695
BLOCK DIAGRAM
M2
V
V
BATT
OUT
M1
V
CC
CHARGE
PUMP
–
+
BATT ON
C2
LOW⎯LINE
+
C1
–
CE OUT
1.3V
GND
CE IN
–
C3
PFO
+
PFI
RESET
RESET
OSC IN
RESET PULSE
GENERATOR
OSC
OSC SEL
WATCHDOG
TIMER
WDO
690 BD
TRANSITION
DETECTOR
WDI
PIN FUNCTIONS
V : 5V Supply Input. The V pin should be bypassed
GND: Ground pin.
BATT ON: Battery On Logic Output from Comparator C2.
CC
CC
with a 0.1μF capacitor.
V
: Voltage Output for Backed Up Memory. Bypass with
BATT ON goes low when V
is internally connected to
OUT
OUT
a capacitor of 0.1μF or greater. During normal operation,
V . The output typically sinks 35mA and can provide
CC
V
OUT
obtains power from V through an NMOS power
base drive for an external PNP transistor to increase the
CC
switch,M1,whichcandeliverupto50mAandhasatypical
output current above the 50mA rating of V . BATT ON
OUT
on resistance of 5Ω. When V is lower than V , V
goes high when V
is internally switched to V
.
CC
BATT OUT
OUT
BATT
is internally switched to V
used, connect V
. If V
BATT
and V
are not
OUT
BATT
PFI: Power Failure Input. PFI is the noninverting input
to the power-fail comparator, C3. The inverting input is
internallyconnectedtoa1.3Vreference. Thepowerfailure
output remains high when PFI is above 1.3V and goes
to V .
OUT
CC
V
: Back-Up Battery Input. When V falls below V
,
BATT
CC
BATT
auxiliary power, connected to V
, is delivered to V
BATT
OUT
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, V
low when PFI is below 1.3V. Connect PFI to GND or V
when C3 is not used.
OUT
should be connected to GND.
BATT
690fe
6
LTC690/LTC691
LTC694/LTC695
PIN FUNCTIONS
PFO: Power Failure Output from C3. PFO remains high
WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
timeout period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOW⎯LINE goes
low. The watchdog timer can be disabled by floating WDI
(see Figure 11).
when PFI is above 1.3V and goes low when PFI is below
1.3V. When V is lower than V
, C3 is shut down and
CC
BATT
PFO is forced low.
RESET: Logic Output for μP Reset Control. Whenever
falls below either the reset voltage threshold (4.65V,
V
CC
typically)orV
,RESETgoesactivelow.AfterV returns
BATT
CE IN: Logic input to the Chip⎯Enable gating circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.
CC
to 5V, reset pulse generator forces RESET to remain active
lowforaminimumof35msfortheLTC690/LTC691(140ms
for the LTC694/LTC695). When the watchdog timer is
enabled but not serviced prior to a preset timeout period,
reset pulse generator also forces RESET to active low for a
minimum of 35ms for the LTC690/LTC691 (140ms for the
LTC694/5)foreverypresettimeoutperiod(seeFigure11).
The reset active time is adjustable on the LTC691/LTC695.
Anexternalpushbuttonresetcanbeusedinconnectionwith
the RESET output. See Pushbutton Reset in Applications
Information section.
CE OUT: Logic Output on the Chip⎯Enable Gating Circuit.
When V is above the reset voltage threshold, CE OUT is
CC
a buffered replica of CE IN. When V is below the reset
CC
voltage threshold CE OUT is forced high (see Figure 5).
OSCSEL:OscillatorSelectionInput.WhenOSCSELishigh
or floating, the internal oscillator sets the reset active time
andwatchdogtimeoutperiod.ForcingOSCSELlow,allows
OSC IN be driven from an external clock signal or external
capacitor be connected between OSC IN and GND.
RESET: RESET is an active high logic ouput. It is the
inverse of RESET.
OSC IN: Oscillator Input. OSC IN can be driven by
an external clock signal or external capacitor can be
connected between OSC IN and GND when OSC SEL is
forced low. In this configuration the nominal reset active
time and watchdog timeout period are determined by the
number of clocks or set by the formula (see Applications
Information section). When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 50ms typical for the LTC691 and 200ms typical
for the LTC695. OSC IN selects between the 1.6 seconds
and 100ms typical watchdog timeout periods. In both
cases, the timeout period immediately after a reset is 1.6
seconds typical.
LOWꢀLINE:LogicOutputfromComparatorC1.LOW⎯LINE
indicates a low line condition at the V input. When V
CC
CC
falls below the reset voltage threshold (4.65V typically),
LOW⎯LINE goes low. As soon as V rises above the reset
CC
voltage threshold, LOW⎯LINE returns high (see Figure 1).
LOW⎯LINE goes low when V drops below V
(see
CC
BATT
Table 1).
WDI: Watchdog Input, WDI, is a three level input. Driving
WDIeitherhighorlowforlongerthanthewatchdogtimeout
period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).
690fe
7
LTC690/LTC691
LTC694/LTC695
TYPICAL PERFORMANCE CHARACTERISTICS
Power Failure Input Threshold
vs Temperature
VOUT vs IOUT
VOUT vs IOUT
5.00
2.80
2.78
2.76
2.74
2.72
1.308
1.306
V
V
T
= 5V
= 2.8V
= 25°C
V
V
T
= 0V
= 2.8V
= 25°C
V
= 5V
CC
CC
BATT
A
CC
BATT
A
4.95
4.90
1.304
1.302
1.300
1.298
1.296
1.294
SLOPE = 125Ω
SLOPE = 5Ω
4.85
4.80
4.75
0
10
20
30
40
50
0
100
200
300
400
500
–50 –25
0
25
50
TEMPERATURE (°C)
75
100 125
LOAD CURRENT (mA)
LOAD CURRENT (μA)
690 G01
690 G02
690 G03
Reset Active Time
Reset Active Time
Reset Voltage Threshold
vs Temperature
vs Temperature LTC690-1
vs Temperature LTC694-5
58
56
54
52
232
224
216
208
4.66
V
= 5V
V
= 5V
CC
CC
4.65
4.64
4.63
4.62
50
48
46
200
192
184
4.61
4.60
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50
25
75
–50
25
75
–25
0
–25
0
690 G04
690 G05
690 G06
Power-Fail Comparator
Response Time
Power-Fail Comparator
Response Time
Power-Fail Comparator Response
Time with Pull-Up Resistor
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
V
T
= 5V
V
T
= 5V
V
T
= 5V
CC
A
CC
A
CC
A
= 25°C
= 25˚C
= 25°C
V
+
PFI
PFO
V
30pF
+
–
1.3V
PFI
PFO
5V
30pF
–
1.3V
V
+
–
10k
PFI
PFO
30pF
1.3V
1.305V
1.285V
1.315V
1.295V
1.315V
1.295V
V
= 20mV STEP
V
= 20mV STEP
V
= 20mV STEP
PFI
2
PFI
PFI
4
0
1
3
4
5
7
8
6
140
14
0
60
120
160 180
0
6
12
16 18
20 40
80 100
2
8
10
TIME (μs)
TIME (μs)
TIME (μs)
690 G07
690 G08
690 G09
690fe
8
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
Microprocessor Reset
below the reset voltage threshold, LOW⎯LINE goes low.
LOW⎯LINE returns high as soon as V rises above the
CC
TheLTC690familyusesabandgapvoltagereferenceanda
precision voltage comparator C1 to monitor the 5V supply
reset voltage threshold.
input on V (see Block Diagram). When V falls below
CC
CC
Battery Switchover
the reset voltage threshold, the RESET output is forced
The battery switchover circuit compares V to the V
to active low state. The reset voltage threshold accounts
CC
BATT
input, and connects V
to whichever is higher. When
for a 5% variation on V , so the RESET output becomes
OUT
CC
V
rises to 70mV above V
comparator, C2, connects V
, the battery switchover
active low when V falls below 4.75V (4.65V typical).
CC
BATT
CC
to V through a charge
On power-up, the RESET signal is held active low for a
minimum of 35ms for the LTC690/LTC691 (140ms for the
LTC694/LTC695)afterresetvoltagethresholdisreachedto
allow the power supply and microprocessor to stabilize.
The reset active time is adjustable on the LTC691/LTC695.
On power-down, the RESET signal remains active low
OUT
CC
pumpedNMOSpowerswitch,M1.WhenV fallsto50mV
CC
above V
, C2 connects V
to V
through a PMOS
BATT
OUT
BATT
switch, M2. C2hastypically20mVofhysteresistoprevent
spuriousswitchingwhenV remainsnearlyequaltoV
.
CC
BATT
The response time of C2 is approximately 20μs.
even with V as low as 1V. This capability helps hold the
CC
During normal operation, the LTC690 family uses a charge
pumped NMOS power switch to achieve low dropout and
low supply current. This power switch can deliver up to
microprocessor in stable shutdown condition. Figure 1
shows the timing diagram of the RESET signal.
50mA to V
5Ω. The V
from V and has a typical on resistance of
The precision voltage comparator, C1, typically has 40mV
OUT
OUT
CC
pin should be bypassed with a capacitor of
of hysteresis which ensures that glitches at V pin do
CC
0.1μF or greater to ensure stability. Use of a larger bypass
capacitor is advantageous for supplying current to heavy
transient loads.
not activate the RESET output. Response time is typically
10μs.Tohelppreventmistriggeringduetotransientloads,
V
pin should be bypassed with a 0.1μF capacitor with
CC
the leads trimmed as short as possible.
When operating currents larger than 50mA are required
fromV ,oralowerdropout(V -V voltagedifferential)
The LTC691 and LTC695 have two additional outputs:
RESET and LOW⎯LINE. RESET is an active high output
and is the inverse of RESET. LOW⎯LINE is the output
OUT
CC OUT
is desired, the LTC691 and LTC695 should be used. These
products provide BATT ON output to drive the base of
of the precision voltage comparator C1. When V falls
CC
V2
V2
V1
V1
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
V
CC
RESET
t
1
t
1
t
= RESET ACTIVE TIME
1
LOW LINE
690 F01
Figure 1. Reset Active Time
690fe
9
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
external PNP transistor (Figure 2). If higher currents
farad-size double layer capacitors, can be used for short
term memory back-up instead of a battery. The charging
resistor for both capacitors and rechargeable batteries
are needed with the LTC690 and LTC694, a high current
Schottky diode can be connected from the V pin to the
CC
V
OUT
pin to supply the extra current.
should be connected to V
since this eliminates the
OUT
discharge path that exists when the resistor is connected
ANY PNP POWER TRANSISTOR
to V (Figure 3).
CC
V
– V
R
5
OUT
BATT
I =
V
BATT ON
3
1
2
5V
0.1μF
V
OUT
V
CC
R
LTC691
LTC695
0.1μF
5V
V
CC
OUT
V
BATT
0.1μF
0.1μF
LTC690
LTC691
LTC694
LTC695
GND
4
3V
690 F02
V
BATT
GND
Figure 2. Using BATT ON to Drive External PNP Transistor
3V
690 F03
The LTC690 family is protected for safe area operation
with short-circuit limit. Output current is limited to
approximately 200mA. If the device is overloaded for
long period of time, thermal shutdown turns the power
switch off until the device cools down. The threshhold
temperatureforthermalshutdownisapproximately155°C
with about 10°C of hysteresis which prevents the device
from oscillating in and out of shutdown.
Figure 3. Charging External Battery Through VOUT
Replacing the Back-Up Battery
When changing the back-up battery with system power
on, spurious resets can occur while battery is removed
due to battery standby current. Although battery standby
current is only a tiny leakage current, it can still charge
up the stray capacitance on the V
pin. The oscillation
reaches within 50mV of
BATT
ThePNPswitchusedincompetitivedeviceswasnotchosen
for the internal power switch because it injects unwanted
current into the substrate. This current is collected by the
cycle is as follows: When V
BATT
V , the LTC690 switches to battery back-up. V
pulls
CC
OUT
V
BATT
low and the device goes back to normal operation.
V
pin in competitive devices and adds to the charging
BATT
The leakage current then charges up the V
and the cycle repeats.
pin again
BATT
current of the battery which can damage lithium batteries.
The LTC690 family uses a charge pumped NMOS power
switch to eliminate unwanted charging current while
achieving low dropout and low supply current. Since no
current goes to the substrate, the current collected by
If spurious resets during battery replacement pose no
problems, thennoactionisrequired. Otherwise, aresistor
to GND will hold the pin low while changing
the battery. For example, the battery standby current is
1μA maximum over temperature and the external resistor
from V
BATT
V
pin is strictly junction leakage.
BATT
A 125Ω PMOS switch connects the V
input to V
OUT
BATT
required to hold V
below V is:
BATT
CC
in battery back-up mode. The switch is designed for very
low dropout voltage (input-to-output differential). This
feature is advantageous for low current applications such
as battery back-up in CMOS RAM and other low power
CMOS circuitry. The supply current in battery back-up
mode is 1μA maximum.
V –50mV
CC
R≤
1μA
With V = 4.5V, a 4.3M resistor will work. With a 3V
CC
battery, this resistor will draw only 0.7μA from the battery,
which is negligible in most cases.
The operating voltage at the V
pin ranges from 2.0V
BATT
to 4.25V. High value capacitors, such as electrolytic or
690fe
10
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
If battery connections are made through long wires, a
input of battery-backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.
10Ω to 100Ω series resistor and a 0.1μF capacitor are
recommended to prevent any overshoot beyond V due
CC
to the lead inductance (Figure 4).
CE IN can be derived from the microprocessor’s address
decoderoutput.Figure6showsatypicalnonvolatileCMOS
RAM application.
10Ω
V
BATT
LTC690
0.1μF
4.3M
LTC691
LTC694
LTC695
Memory protection can also be achieved with the LTC690
and LTC694 by using RESET as shown in Figure 7.
GND
690 F04
Table 1. Input and Output Status in Battery Back-Up Mode
SIGNAL
STATUS
Figure 4. 10Ω/0.1μF Combination Eliminates Inductive
Overshoot and Prevents Spurious Resets During Battery
Replacement
V
C2 monitors V for active switchover.
CC
CC
V
V
V
OUT
is connected to V
through an internal PMOS switch.
OUT
BATT
The supply current is 1μA maximum.
Logic high. The open-circuit output voltage is equal to V
Power failure input is ignored.
Logic low
BATT
Table1showsthestateofeachpinduringbatteryback-up.
When the battery switchover section is not used, connect
BATT ON
PFI
.
.
OUT
V
to GND and V to V .
OUT CC
BATT
PFO
Memory Protection
RESET
RESET
Logic low
Logic high. The open-circuit output voltage is equal to V
OUT
The LTC691 and LTC695 include memory protection
circuitry that ensures the integrity of the data in memory
LOW⎯LINE Logic low
WDI
Watchdog input is ignored.
by preventing write operations when V is at invalid level.
CC
WDO
Logic high. The open-circuit output voltage is equal to V
.
OUT
Two additional pins, CE IN and CE OUT, control the Chip
CE IN
Chip⎯Enable Input is ignored.
Enable or Write inputs of CMOS RAM. When V is 5V,
CC
CE OUT
OSC IN
OSC SEL
Logic high. The open-circuit output voltage is equal to V
OSC IN is ignored.
.
OUT
CE OUT follows CE IN with a typical propagation delay of
20ns. When V falls below the reset voltage threshold
CC
or V , CE OUT is forced high, independent of CE IN. CE
OSC SEL is ignored.
BATT
OUT is an alternative signal to drive the CE, CS, or Write
V2
V
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS
CC
V1
CE IN
V
= V
BATT
OUT
CE OUT
V
= V
BATT
OUT
690 F05
Figure 5. Timing Diagram for CE IN and CE OUT
690fe
11
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
Power-Fail Warning
5V
0.1μF
V
V
V
CC
OUT
CC
+
0.1μF
LTC691
LTC695
62512
RAM
10μF
The LTC690 family generates a Power Failure Output
(PFO) for early warning of failure in the microprocessor’s
power supply. This is accomplished by comparing the
Power Failure Input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulatedDCinputoraregulated5Voutput.Thevoltage
divider ratio can be chosen such that the voltage at the PFI
pin falls below 1.3V several milliseconds before the 5V
supply falls below the maximum reset voltage threshold
4.75V.PFOisnormallyusedtointerruptthemicroprocessor
to execute shutdown procedure between PFO and RESET
or RESET.
CE OUT
CS
20ns PROPAGATION DELAY
FROM DECODER
GND
V
BATT
GND
CE IN
RESET
3V
RESET
TO μP
690 F06
Figure 6. A Typical Nonvolatile CMOS RAM Application
5V
0.1μF
V
V
V
CC
OUT
CC
+
0.1μF
CS
62128
RAM
CS1
10μF
LTC690
LTC694
V
RESET
GND
CS2
BATT
3V
GND
690 F07
The power-fail comparator, C3, does not have hysteresis.
Hysteresiscanbeaddedhowever, byconnectingaresistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
Figure 7. Write Protect for RAM with LTC690 or LTC694
LT1086-5
V
≥ 7.5V
IN
5V
V
V
IN
OUT
V
CC
+
+
0.1μF
R4
10k
ADJ
10μF
100μF
LTC690/LTC691
LTC694/LTC695
WhenPFOoutputislow,R3sinkscurrentfromthesumming
junction at the PFI pin.
R3
300k
R1
51k
PFO
GND
PFI
⎛
⎞
R1 R1
R2 R3
R2
10k
V =1.3V 1+
+
⎜
⎟
H
690 F08
TO μP
⎝
⎠
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
Figure 8. Monitoring Unregulated DC Supply
with the LTC690’s Power-Fail Comparator
⎛
⎞
R1 (5V –1.3V)R1
R2 1.3V(R3 + R4)
V = 1.3V 1+
–
⎜
⎟
L
LT1086-5
5V
V
≥ 6.5V
10μF
IN
⎝
⎠
V
V
V
OUT
IN
CC
+
+
R4
0.1μF
R1
27k
ADJ
10μF
LTC690/LTC691
LTC694/LTC695
R1
R3
10k
Assuming R4 << R3,V
= 5V
R3
2.7M
HYSTERESIS
PFO
GND
PFI
Example 1: The circuit in Figure 8 demonstrates the use
of the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
R2
8.2k
1690 F09
TO μP
R5
3.3k
supplyinputV is100mV/msandthetotaltimetoexecutea
IN
shutdownprocedureis8ms.AlsothenoiseofV is200mV.
IN
Figure 9. Monitoring Regulated DC Supply
with the LTC690’s Power-Fail Comparator
With these assumptions in mind, we can reasonably set
V = 7.5V which 1.25V greater than the sum of maximum
L
resetvoltagethresholdandthedropoutvoltageofLT1086-5
(4.75V + 1.5V) and V
= 850mV.
HYSTERESIS
690fe
12
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
5V
R1
V
= 5V
= 850V
HYSTERESIS
R3
V
CC
V
BATT
LOW-BATTERY SIGNAL
TO μP I/O PIN
PFO
R1
1M
R3 ≈ 5.88 R1
LTC691
LTC695
PFI
R2
1M
Choose R3 = 300k and R1 = 51k. Also select R4 = 10k
which is much smaller than R3.
3V
CE IN
I/O PIN
CE OUT
GND
R
690 F10
L
⎛
⎞
51k (5V –1.3V)51k
20k
7.5V =1.3V 1+
–
⎜
⎟
R2
1.3V(310k)
⎝
⎠
OPTIONAL TEST LOAD
Figure 10. Back-Up Battery Monitor with Optional Test Load
R2 = 9.7kΩ, Choose nearest 5% resistor 10k and recalcu-
late V ,
L
Watchdog Timer
⎛
⎞
51k (5V – 1.3V)51k
V = 1.3V 1+
–
= 7.32V
L
⎜
⎟
The LTC690 family provides a watchdog timer function
to monitor the activity of the microprocessor. If the
microprocessor does not toggle the Watchdog Input
(WDI) within a seleced timeout period, RESET is forced to
active low for a minimum of 35ms for the LTC690/LTC691
(140ms for the LTC694/LTC695). The reset active time is
adjustable on the LTC691/LTC695. Since many systems
can not service the watchdog timer immediately after
a reset, the LTC691 and LTC695 have longer timeout
period (1.0 second minimum) right after a reset is issued.
The normal timeout period (70ms minimum) becomes
effective following the first transition of WDI after RESET
is inactive. The watchdog timeout period is fixed at 1.0
second minimum on the LTC690 and LTC694. Figure 11
showsthetimingdiagramofwatchdogtimeoutperiodand
resetactivetime.Thewatchdogtimeoutperiodisrestarted
as soon as RESET is inactive. When either a high-to-low
or low-to-high transition occurs at the WDI pin prior to
timeout, the watchdog time is reset and begins to time
out again. To ensure the watchdog time does not time
out, either a high-to-low or low-to-high transition on the
WDI pin must occur at or less than the minimum timeout
period. If the input to the WDI pin remains either high or
low,resetpulseswillbeissuedevery1.6secondstypically.
The watchdog time can be deactivated by floating the WDI
10k
1.3V(310k)
⎝
⎠
⎛
⎞
51k 51k
10k 300k
VH = 1.3V 1+
+
= 8.151V
⎜
⎟
⎝
⎠
(7.32V – 6.25V)
100mV/ms
= 10.7ms
V
= 8.151V – 7.32V = 831mV
HYSTERESIS
The 10.7ms allows enough time to execute shutdown
procedure for microprocessor and 831mV of hysteresis
would prevent PFO from going low due to the noise of V .
IN
Example 2: The circuit in Figure 9 can be used to measure
the regulated 5V supply to provide early warning of power
failure. Because of variations in the PFI threshold, this
circuit requires adjustment to ensure the PFI comparator
trips before the reset threshold is reached. Adjust R5 such
thatthePFOoutputgoeslowwhentheV supplyreaches
the desired level (e.g., 4.85V).
CC
Monitoring the Status of the Battery
C3 can also monitor the status of the memory back-up
battery (Figure 10). If desired, the CE OUT can be used to
applyatestloadtothebattery. SinceCEOUTisforcedhigh
in battery back-up mode, the test load will not be applied
to the battery while it is in use, even if the microprocessor
is not powered.
pin. The timer is also disabled when V falls below the
CC
reset voltage threshold or V
.
BATT
690fe
13
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
The LTC691 and LTC695 provide an additional output
(Watchdog Output, WDO) which goes low if the watchdog
timer is allowed to time out and remains low until set high
by the next transition on the WDI pin. WDO is also set high
GND when OSC SEL is forced low. In these configurations,
the nominal reset active time and watchdog timeout
period are determined by the number of clocks or set by
the formula in Table 2. When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 35ms minimum for the LTC691 and 140ms
minimum for the LTC695. OSC IN selectes between the
1 second and 70ms minimum normal watchdog timeout
periods. In both cases, the timeout period immediately
after a reset is at least 1 second.
when V falls below the reset voltage threshold or V
.
CC
BATT
The LTC691 and LTC695 have two additonal pins OSC SEL
and OSC IN, which allow reset active time and watchdog
timeout period to be adjusted per Table 2. Several
configurations are shown in Figure 12.
OSC IN can be driven by an external clock signal or an
external capacitor can be connected between OSC IN and
V
= 5V
CC
WDI
t
1
t
2
t
3
= RESET ACTIVE TIME
= NORMAL WATCHDOG TIME-OUT PERIOD
= WATCHDOG TIME-OUT PERIOD IMMEDIATELY
AFTER A RESET
WDO
t
t
3
2
RESET
t
t
1
1
690 F11
Figure 11. Watchdog Timeout Period and Reset Active Time
EXTERNAL OSCILLATOR
EXTERNAL CLOCK
3
8
7
8
3
4
V
OSC SEL
5V
5V
V
OSC SEL
CC
CC
LTC691
LTC695
LTC691
LTC695
7
4
GND
OSC IN
GND
OSC IN
INTERNAL OSCILLATOR
1.6 SECOND WATCHDOG
INTERNAL OSCILLATOR
100ms WATCHDOG
3
8
3
8
7
FLOATING
OR HIGH
FLOATING
OR HIGH
5V
5V
V
OSC SEL
V
OSC SEL
CC
CC
LTC691
LTC695
LTC691
LTC695
4
7
FLOATING
OR HIGH
4
GND
OSC IN
GND
OSC IN
690 F12
Figure 12. Oscillator Configurations
690fe
14
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
Table 2. LTC691 and LTC695 Reset Active Time and Watchdog Timeout Selections
WATCHDOG TIME-OUT PERIOD
RESET ACTIVE TIME
IMMEDIATELY
AFTER RESET
(Long Period)
NORMAL
(Short Period)
OSC SEL
OSC IN
LTC691
LTC695
External Clock Input
1024 clks
4096 clks
512 clks
2048 clks
Low
1.6sec
70pF
200ms
70pF
800ms
70pF
•C
•C
•C
External Capacitor*
Low
Floating or High
Floating or High
Low
100ms
1.6 sec
1.6 sec
1.6 sec
50ms
50ms
200ms
200ms
Floating or High
184,000
C (pF)•1025
*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is f
Pushbutton Reset
(Hz) =
OSC
The LTC690 family does not provide a logic input for direct
V
5V
RESET
RESET
CC
connection to a pushbutton. However, a pushbutton in
serieswitha100ΩresistorconnectedtotheRESEToutput
pin (Figure 13) provides an alternative for manual reset.
Connecting a 0.1μF capacitor to the RESET pin debounces
the pushbutton input.
100Ω
0.1μF
MPU
(e.g. 6805)
LTC690/LTC691
LTC694/LTC695
690 F13
GND
The100Ωresistorinserieswiththepushbuttonisrequired
to prevent the ringing, due to the capacitance and lead
inductance, from pulling the RESET pins of the MPU and
LTC69X below ground.
Figure 13. The External Pushbutton Reset
V
5V
RESET
LTC1235
RESET
CC
MPU
(e.g. 6805)
Ifadedicatedpushbuttonresetinputisdesired,theLTC1235
is a good choice (Figure 14). It has all the functions of the
LTC695andprovidespushbuttonresetasanextrafeature.
Its pushbutton is internally debounced and invokes the
normal 200ms reset sequence. This eliminates the need
for the 100Ω resistor and 0.1μF capacitor. It also provides
a more consistent reset pulse.
PBRST
GND
690 F14
Figure 14. The External Pushbutton Reset with the LTC1235
690fe
15
LTC690/LTC691
LTC694/LTC695
PACKAGE DESCRIPTION
SW Package 16-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620)
0.291 – 0.299**
(7.391 – 7.595)
0.398 – 0.413*
(10.109 – 10.490)
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
15 14
12
10
11
9
16
13
0.010 – 0.029
(0.254 – 0.737)
s 45°
0° – 8° TYP
0.050
(1.270)
TYP
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.009 – 0.013
NOTE 1
(0.229 – 0.330)
0.014 – 0.019
0.004 – 0.012
(0.102 – 0.305)
0.016 – 0.050
(0.356 – 0.482)
TYP
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
S16 (WIDE) 0396
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
2
3
5
7
8
1
4
6
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
0.130 0.005
0.045 – 0.065
0.300 – 0.325
(3.302 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
8
7
6
5
4
0.065
(1.651)
TYP
0.255 0.015*
(6.477 0.381)
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
–0.015
1
2
3
0.325
N8 1197
0.100 0.010
(2.540 0.254)
0.018 0.003
+0.889
8.255
(
)
(0.457 0.076)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
(0.254 – 0.508)
7
5
8
6
s 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
SO8 0996
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
0.300 – 0.325
0.130 0.005
0.045 – 0.065
(7.620 – 8.255)
(3.302 0.127)
(1.143 – 1.651)
14
12
10
9
15
13
11
16
0.020
(0.508)
MIN
0.255 0.015*
(6.477 0.381)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
2
1
3
4
6
8
5
7
0.325
–0.015
0.125
(3.175)
MIN
0.018 0.003
(0.457 0.076)
0.100 0.010
(2.540 0.254)
N16 1197
+0.889
8.255
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
690fe
16
LTC690/LTC691
LTC694/LTC695
REVISION HISTORY (Revision history begins at Rev D)
REV
DATE
3/10
4/10
DESCRIPTION
PAGE NUMBER
D
Removed “UL Recognized” and UL File Number From Features
Remove LTC690MJ8
1
3
E
690fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC690/LTC691
LTC694/LTC695
TYPICAL APPLICATION
Capacitor Back-Up with 74HC4016 Switch
Write Protect for Additional RAMs
5V
5V
V
V
V
V
OUT
CC
V
CC
V
CC
OUT
+
0.1μF
62512
RAM A
LTC691
LTC695
0.1μF
10μF
0.1μF
0.1μF
LTC691
LTC695
R1
10k
10 11 12 14
CS
CE OUT
20ns PROPAGATION
DELAY
2
1
BATT
LOW⎯LINE
V
74HC4016
7
BATT
CE IN
CS⎯A
3V
R2
30k
LOW⎯LINE
13
100μF
+
GND
GND
V
CC
0.1μF
0.1μF
62128
RAM B
CS⎯1
LTC690 TA03
CS⎯B
CS⎯C
CS2
V
CC
62128
RAM C
CS⎯1
CS2
OPTIONAL CONNECTION FOR
ADDITIONAL RAMs
690 TA04
RELATED PARTS
PART NUMBER
LTC1326
DESCRIPTION
Micropower Precision Triple Supply Monitor
Micropower Triple Supply Monitor for PCI Applications
COMMENTS
4.725V, 3.118V, 1V Thresholds ( 0.75%)
Meets PCI t Timing Specifications
LTC1536
FAIL
690fe
LT 0410 REV E • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
18
●
●
© LINEAR TECHNOLOGY CORPORATION 1992
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号:
LTC695-3.3CSW
IC 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16, 0.300 INCH, PLASTIC, SOP-16, Power Management Circuit
Linear
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