LTC6957-3 [Linear]
280MHz, 2.9ns Comparator Family with Rail-to-Rail Inputs and CMOS Outputs;
| 型号： | LTC6957-3 |
| 厂家： | 
Linear |
| 描述： | 280MHz, 2.9ns Comparator Family with Rail-to-Rail Inputs and CMOS Outputs |
| 文件： | 总30页 (文件大小：700K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
280MHz, 2.9ns Comparator
Family with Rail-to-Rail Inputs
and CMOS Outputs
FeaTures
DescripTion
The LTC®6752 is a family of very high speed comparators
capable of supporting toggle rates up to 280MHz. These
comparators exhibit low propagation delays of 2.9ns, and
fast rise/fall times of 1.2ns. There are a total of 5 members
in the LTC6752 family, with different options for separate
inputandoutputsupplies, shutdown, outputlatch, adjust-
able hysteresis, complementary outputs, and package.
n
Very High Toggle Rate: 280MHz
n
Low Propagation Delay: 2.9ns
n
Rail-to-Rail Inputs Extend Beyond Both Rails
n
Output Current Capability: 22mꢀ
n
Low Quiescent Current: 4.5mꢀ
n
Features within the LTC6752 Family:
n
2.45V to 5.25V Input Supply and 1.71V to 3.5V
Output Supply (Separate Supply Option)
The LTC6752 comparators have rail-to-rail inputs that
operate from 2.45V, up to 3.5V or 5.25V, depending on
the option. The outputs are CMOS and the separate supply
options can operate down to 1.71V, allowing for directly
interfacing to 1.8V logic devices.
n
2.45V to 3.5V Supply (Single Supply Option)
n
Shutdown Pin for Reduced Power
n
Output Latch and ꢀdjustable Hysteresis
n
Complementary Outputs
n
Packages: TSOT-23, SC70, MSOP, 3mm × 3mm QFN
n
n
The low propagation delay of only 2.9ns combined with
low dispersion of only 1.8ns (10mV to 125mV overdrive
variation) makes these comparators an excellent choice
for critical timing applications. Similarly, the fast toggle
Direct Replacement for ꢀDCMP60X Family
Fully Specified from –55°C to 125°C
applicaTions
rate and the low jitter of 4.5ps RMS (100mV , 100MHz
P-P
input) make the LTC6752 family ideally suited for high
n
Clock and Data Recovery
frequency line driver and clock recovery circuits.
n
Level Shifting
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of ꢀnalog
Devices, Inc. ꢀll other trademarks are the property of their respective owners.
High Speed Data ꢀcquisition Systems
n
Window Comparators
n
High Speed Line Receivers
n
Fast Crystal Oscillators
n
Time of Flight Measurements
n
Time Domain Reflectometry
Typical applicaTion
Q
–IN +IN
High Speed Differential Line Receiver with Excellent
Common Mode Rejection
SMALL DIFFERENTIAL SIGNAL WITH
LARGE COMMON MODE COMPONENT
500mV/DIV
V
= 5V
V
CC
+IN
–IN
+
= 2.7V
Q
DD
LTC6752-2
–
V
6752 T01a
EE
50ns/DIV
6752 T01a
6752fc
1
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
absoluTe MaxiMuM raTings
(Note 1)
Total Supply Voltage (V to V )
Specified Temperature Range (Note 4)
CC
EE
(LTC6752-2/LTC6752-3/LTC6752-4)....................5.5V
(LTC6752/LTC6752-1)..........................................3.6V
LTC6752I .............................................–40°C to 85°C
LTC6752H.......................................... –40°C to 125°C
LTC6752MP....................................... –55°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
Maximum Junction Temperature (Note 3)............. 150°C
Lead Temperature Soldering (10s)........................300°C
Total Supply Voltage (V to V )............................3.6V
DD
EE
Input Current (+IN, –IN, SHDN, LE/HYST)
(Note 2)................................................................ 10mꢀ
Output Current (Q, Q) (Note 3)............................ 50mꢀ
pin conFiguraTion
LTC6752
LTC6752-1
LTC6752-2
TOP VIEW
TOP VIEW
TOP VIEW
Q 1
6 V
CC
V
+IN
–IN
1
2
3
4
8 V
DD
Q 1
5 V
CC
CC
7 Q
6 V
V
2
5 LE/HYST
EE
V
2
EE
EE
+IN 3
4 –IN
+IN 3
4 –IN
SHDN
5 LE/HYST
SC6 PACKAGE
6-LEAD PLASTIC SC70
MS8 PACKAGE
S5 PACKAGE
8-LEAD PLASTIC MSOP
5-LEAD PLASTIC TSOT-23
WITH LꢀTCHING/ꢀDJUSTꢀBLE HYSTERESIS
T
JMꢀX
= 150°C, θ = 163°C/W (NOTE 3)
Jꢀ
T
= 150°C,
= 215°C/W (NOTE 3)
Jꢀ
JMꢀX
T
JMꢀX
= 150°C, θ = 270°C/W (NOTE 3)
Jꢀ
LTC6752-3
LTC6752-4
TOP VIEW
12 11 10
TOP VIEW
V
1
9
8
7
V
EE
Q 1
2
6 V
5 V
DD
CC
DD
13
EE
V
2
3
LE/HYST
V
CC
EE
V
V
SHDN
+IN 3
4 –IN
EE
4
5
6
SC6 PACKAGE
6-LEAD PLASTIC SC70
WITH SEPꢀRꢀTE INPUT/OUTPUT SUPPLIES
T
JMꢀX
= 150°C, θ = 270°C/W (NOTE 3)
Jꢀ
UD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC QFN
= 150°C, θ = 68°C/W (NOTE 3)
T
JMꢀX
Jꢀ
EXPOSED PꢀD (PIN 13) IS V , MUST BE SOLDERED TO PCB
EE
Table 1. Features and Part Numbers
LATCHING/ADJUSTABLE
SEPARATE INPUT/
OUTPUT SUPPLIES
COMPLEMENTARY
OUTPUTS
PART#
HYSTERESIS
SHUTDOWN
PACKAGE OFFERING
TSOT-23-5
SC70-6
LTC6752
l
l
l
LTC6752-1
LTC6752-2
LTC6752-3
LTC6752-4
l
l
l
l
l
MS8
l
3mm × 3mm QFN
SC70-6
6752fc
2
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
http://www.linear.com/product/LTC6752#orderinfo
orDer inForMaTion
Lead Free Finish
TAPE AND REEL (MINI)
LTC6752IS5#TRMPBF
LTC6752HS5#TRMPBF
LTC6752MPS5#TRMPBF
LTC6752ISC6-1#TRMPBF
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
–40°C to 85°C
LTC6752IS5#TRPBF
LTC6752HS5#TRPBF
LTC6752MPS5#TRPBF
LTC6752ISC6-1#TRPBF
LTGKT
LTGKT
LTGKT
LGQK
LGQK
LGQM
LGQM
5-Lead Plastic TSOT-23
5-Lead Plastic TSOT-23
5-Lead Plastic TSOT-23
6-Lead Plastic SC-70
6-Lead Plastic SC-70
6-Lead Plastic SC-70
6-Lead Plastic SC-70
–40°C to 125°C
–55°C to 125°C
–40°C to 85°C
LTC6752HSC6-1#TRMPBF LTC6752HSC6-1#TRPBF
LTC6752ISC6-4#TRMPBF LTC6752ISC6-4#TRPBF
LTC6752HSC6-4#TRMPBF LTC6752HSC6-4#TRPBF
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
–40°C to 85°C
LEAD FREE FINISH
LTC6752IMS8-2#PBF
LTC6752HMS8-2#PBF
LTC6752IUD-3#PBF
LTC6752HUD-3#PBF
LTC6752IMS8-2#TRPBF
LTC6752HMS8-2#TRPBF
LTC6752IUD-3#TRPBF
LTC6752HUD-3#TRPBF
LTGKW
LTGKW
LGKV
8-Lead Plastic MSOP
8-Lead Plastic MSOP
–40°C to 125°C
12-Lead Plastic QFN (3mm × 3mm) –40°C to 85°C
12-Lead Plastic QFN (3mm × 3mm) –40°C to 125°C
LGKV
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
elecTrical characTerisTics (VCC = 2.5V, VDD = 2.5V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
- V
EE
Supply Voltage (Note 5)
LTC6752/LTC6752-1 (Total Supply)
LTC6752-2/LTC6752-3/LTC6752-4 (Input Stage)
2.45
2.45
3.5
5.25
V
V
CC
l
l
V
V
V
- V
Output Stage Supply Voltage (Note 5)
Input Voltage Range (Note 7)
Input Offset Voltage (Note 6)
LTC6752-2/LTC6752-3/LTC6752-4
1.71
3.5
V
V
DD
EE
V
– 0.2
V
+ 0.1
CC
CMR
OS
EE
–5.5
–8.5
1.2
5.5
8.5
mV
mV
l
l
TCV
Input Offset Voltage Drift
Input Hysteresis Voltage (Note 6)
Input Capacitance
18
5
µV/°C
mV
pF
OS
HYST
IN
V
C
LE/HYST Pin Floating
1.1
57
R
R
Differential Mode Resistance
Common Mode Resistance
Input Bias Current
kΩ
DM
6.4
–1.35
MΩ
CM
I
B
V
V
= V + 0.3V
–3.8
–4
µꢀ
µꢀ
CM
CM
EE
l
= V – 0.3V
0.3
1.25
2.1
µꢀ
µꢀ
CC
l
l
I
Input Offset Current
–0.75
0.1
69
0.75
µꢀ
OS
CMRR_
LVCM
Common Mode Input Range, Low V
Region
V
= V – 0.2V to V – 1.5V
51
46
dB
dB
CM
CM
EE
CC
l
l
CMRR_FR
Common Mode Rejection Ratio (Measured at V = V – 0.2V to V + 0.1V
50
45.5
65
dB
dB
CM
EE
CC
Extreme Ends of V
)
CMR
6752fc
3
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
elecTrical characTerisTics (VCC = 2.5V, VDD = 2.5V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
= 0.3V, V = 2.5V, V Varied from 2.45V
to 5.25V (LTC6752-2/LTC6752-3/LTC6752-4)
MIN
TYP
MAX
UNITS
PSRR_V
Input Power Supply Rejection Ratio
V
59
57
74
dB
dB
CC
CM
DD
CC
l
l
l
Total Power Supply Rejection Ratio
Output Power Supply Rejection Ratio
Open Loop Gain
V
CM
= 0.3V, V Varied from 2.45V to 3.5V
53
51
73
71
dB
dB
CC
(LTC6752/LTC6752-1)
PSRR_V
V
= 0.3V, V Varied from 1.71V to 3.5V
56
51
dB
dB
DD
CM
DD
(LTC6752-2/LTC6752-3/LTC6752-4)
ꢀ
V
LTC6752-1/LTC6752-2/LTC6752-3, Hysteresis
Removed (Note 12)
6000
130
V/V
VOL
OH
Output High Voltage (ꢀmount Below
I
= 8mꢀ
260
340
mV
mV
SOURCE
l
V
V
(LTC6752-2/LTC5752-3/LTC6752-4),
(LTC6752/LTC6752-1))
DD
CC
V
Output Low Voltage (Referred to V
)
I
= 8mꢀ
SINK
200
30
340
400
mV
mV
OL
EE
l
l
l
l
l
l
l
l
l
I
I
I
I
Output Short-Circuit Current
Source
Sink
16
12
mꢀ
mꢀ
SC
15
9
22
mꢀ
mꢀ
V
V
Supply Current, Device On
Supply Current, Device On
LTC6752/LTC6752-1
LTC6752-2/LTC6752-3/LTC6752-4
LTC6752-2/LTC6752-4
LTC6752-3
4.5
1.9
2.6
4.3
4.5
6.2
5.0
5.9
mꢀ
mꢀ
VCC
CC
DD
2.25
2.5
mꢀ
mꢀ
3.2
3.4
mꢀ
mꢀ
VDD
4.75
5.2
mꢀ
mꢀ
Total Supply Current, Device On
LTC6752/LTC6752-1/LTC6752-2/LTC6752-4
LTC6752-3
5.0
5.9
mꢀ
mꢀ
TOTꢀL
6.65
7.7
mꢀ
mꢀ
t , t
Rise/Fall time
10% to 90%
1.2
2.9
ns
R
F
t
Propagation Delay (Note 8)
V
= 50mV
OVERDRIVE
5
5.5
ns
ns
PD
l
t
Propagation Delay Skew, Rising to Falling
Transition (Note 9)
300
ps
SKEW
t
t
Overdrive Dispersion (Note 8)
Common Mode Dispersion
Toggle Rate (Note 11)
Overdrive Varied from 10mV to 125mV
Varied from V – 0.2V to V + 0.1V
1.8
ns
ps
ODD
V
240
CMD
CM
EE
CC
TR
100mV Input, LTC6752/LTC6752-1/
280
250
MHz
MHz
P-P
LTC6752-2/LTC6752-4
100mV Input, LTC6752-3
P-P
t
RMS Jitter
V
= 100mV
,
P-P
JITTER
IN
f
IN
f
IN
f
IN
= 100MHz, Jitter BW = 10Hz – 50MHz
= 61.44MHz, Jitter BW = 10Hz – 30.72MHz
= 10MHz, Jitter BW = 10Hz – 5MHz
4.5
6.0
30
ps
ps
ps
6752fc
4
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
elecTrical characTerisTics (VCC = 2.5V, VDD = 2.5V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Latching/Adjustable Hysteresis Characteristics (LTC6752-1/LTC6752-2/LTC6752-3 Only)
l
l
V
LE/HYST Pin Voltage
Open Circuit
1.05
15
1.25
20
1.45
25
V
kΩ
mV
V
LE/HYST
R
Resistance Looking Into LE/HYST
Hysteresis Voltage
LE/HYST Pin Voltage < Open Circuit Value
HYST
HYST_LꢀRGE
IL_LE
V
V
V
V
= 800mV
40
LE/HYST
l
l
l
l
Latch Pin Voltage, Latch Guaranteed
Latch Pin Voltage, Hysteresis Disabled
Latch Pin Current High
0.3
72
Output Not Latched
1.7
V
IH_LE
IH_LE
IL_LE
I
I
t
t
t
V
V
= 1.7V
= 0.3V
30
–47
–2
2
µꢀ
µꢀ
ns
ns
ns
LE/HYST
LE/HYST
Latch Pin Current Low
–70
Latch Setup Time (Note 10)
Latch Hold Time (Note 10)
Latch to Output Delay
SETUP
HOLD
7
PL
Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)
I
Shutdown Mode Input Stage Supply Current
V
V
V
= 0.6V
400
185
250
80
585
620
µꢀ
µꢀ
SD_VCC
SHDN
SHDN
SHDN
l
l
l
I
Shutdown Mode Output Stage Supply
Current
= 0.6V, LTC6752-2
= 0.6V, LTC6752-3
340
380
µꢀ
µꢀ
SD_VDD
650
680
µꢀ
µꢀ
t
Shutdown Time
Output Hi-Z
ns
V
SD
l
l
V
V
Shutdown Pin Voltage High
Shutdown Pin Voltage Low
Wake-Up Time from Shutdown
Part Guaranteed to Be Powered On
Part Guaranteed to Be Powered Off
1.3
IH_SD
IL_SD
0.6
V
t
V
= 100mV, Output Valid
OD
100
ns
WꢀKEUP
(VCC = 3.3V, VDD = 3.3V, VEE = 0). The l denotes the specifications which apply over the specified temperature range, otherwise
specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN +
VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
- V
EE
Supply Voltage (Note 5)
LTC6752/LTC6752-1 (Total Supply)
LTC6752-2/LTC6752-3/LTC6752-4 (Input Stage)
2.45
2.45
3.5
5.25
V
V
CC
l
l
V
V
V
- V
Output Supply Voltage (Note 5)
Input Voltage Range (Note 7)
Input Offset Voltage (Note 6)
LTC6752-2/LTC6752-3/LTC6752-4
1.71
3.5
V
V
DD
EE
V
– 0.2
V
+ 0.1
CC
CMR
OS
EE
–5.5
–9
1.2
5.5
9
mV
mV
l
l
TCV
Input Offset Voltage Drift
Input Hysteresis Voltage (Note 6)
Input Capacitance
18
4.7
1.1
57
µV/°C
mV
pF
OS
HYST
IN
V
C
LE/HYST Pin Floating
R
R
Differential Mode Resistance
Common Mode Resistance
Input Bias Current
kΩ
DM
CM
6.4
–1.4
MΩ
I
B
V
V
= V + 0.3V
–3.8
–4.1
µꢀ
µꢀ
CM
CM
EE
l
= V – 0.3V
0.33
0.1
1.5
2.3
µꢀ
µꢀ
CC
l
l
I
Input Offset Current
–0.75
0.75
µꢀ
OS
6752fc
5
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
elecTrical characTerisTics (VCC = 3.3V, VDD = 3.3V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
= V – 0.2V to V – 1.5V
MIN
TYP
MAX
UNITS
CMRR_
LVCM
Common Mode Input Range, Low V
Region
V
52
48
70
dB
dB
CM
CM
EE
CC
l
l
l
l
l
CMRR_FR
Common Mode Rejection Ratio (Measured at V = V – 0.2V to V + 0.1V
Extreme Ends of V
50
46
66
75
dB
dB
CM
CM
EE
CC
)
CMR
PSRR_V
Input Power Supply Rejection Ratio
Total Power Supply Rejection Ratio
Output Power Supply Rejection Ratio
Open Loop Gain
V
= 0.3V, V = 3.3V,V Varied from 2.45V
59
57
dB
CC
DD
CC
to 5.25V (LTC6752-2/LTC6752-3/LTC6752-4)
V
CM
= 0.3V,V Varied from 2.45V to 3.5V
53
51
73
dB
dB
CC
(LTC6752/LTC6752-1)
PSRR_V
V
= 0.3V, V Varied from 1.71V to 3.5V
56
51
71
dB
dB
DD
CM
DD
(LTC6752-2/LTC6752-3/LTC6752-4)
ꢀ
V
LTC6752-1/LTC6752-2/LTC6752-3,Hysteresis
Removed (Note 12)
7000
81
V/V
VOL
OH
Output High Voltage (ꢀmount Below V
(LTC6752-2/LTC5752-3/LTC6752-4), V
(LTC6752/LTC6752-1))
I
= 8mꢀ
SOURCE
200
300
mV
mV
DD
l
CC
V
Output Low Voltage (Referred to V
)
I
= 8mꢀ
SINK
155
70
320
350
mV
mV
OL
EE
l
l
l
l
l
l
l
l
l
I
I
I
I
Output Short-Circuit Current
Source
Sink
35
30
mꢀ
mꢀ
SC
20
15
39
mꢀ
mꢀ
V
V
Supply Current, Device On
Supply Current, Device On
LTC6752/LTC6752-1
LTC6752-2/LTC6752-3/LTC6752-4
LTC6752-2/LTC6752-4
LTC6752-3
4.8
1.9
2.9
4.75
4.8
6.6
5.8
6.2
mꢀ
mꢀ
VCC
CC
DD
2.35
2.55
mꢀ
mꢀ
3.45
3.65
mꢀ
mꢀ
VDD
5.35
5.75
mꢀ
mꢀ
Total Supply Current, Device On
LTC6752/LTC6752-1/LTC6752-2/LTC6752-4
LTC6752-3
5.8
6.2
mꢀ
mꢀ
TOTꢀL
7.7
8.3
mꢀ
mꢀ
t , t
Rise/Fall Time
10% to 90%
1.35
3.00
ns
R
F
t
Propagation Delay (Note 8)
V
= 50mV
OVERDRIVE
5
5.5
ns
ns
PD
l
t
Propagation Delay Skew, Rising to Falling
Transition (Note 9)
600
ps
SKEW
t
t
Overdrive Dispersion (Note 8)
Common Mode Dispersion
Toggle Rate (Note 11)
RMS jitter
Overdrive Varied from 10mV to 125mV
Varied from V —0.2V to V + 0.1V
1.8
240
215
4.8
ns
ps
ODD
V
CMD
CM
EE
CC
TR
100mV Input
MHz
ps
P-P
t
V = 100mV , f = 100MHz,
IN P-P IN
JITTER
Jitter BW = 10Hz – 50MHz
f
IN
f
IN
= 61.44MHz, Jitter BW = 10Hz – 30.72MHz
= 10MHz, Jitter BW = 10Hz – 5MHz
5.8
29
ps
ps
6752fc
6
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
elecTrical characTerisTics (VCC = 3.3V, VDD = 3.3V, VEE = 0). The l denotes the specifications which
apply over the specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF,
VOVERDRIVE = 50mV –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Latching/Adjustable Hysteresis Characteristics (LTC6752-1/LTC6752-2/LTC6752-3 Only)
l
l
V
LE/HYST Pin Voltage
Open Circuit
1.05
15
1.25
20
1.45
25
V
kΩ
mV
V
LE/HYST
R
Resistance Looking Into LE/HYST
Hysteresis Voltage
LE/HYST Pin Voltage < Open Circuit Value
HYST
HYST_LꢀRGE
IL_LE
V
V
V
V
= 800mV
40
LE/HYST
l
l
l
l
Latch Pin Voltage, Latch Guaranteed
Latch Pin Voltage, Hysteresis Disabled
Latch Pin Current High
0.3
72
Output Not Latched
1.7
V
IH_LE
IH_LE
IL_LE
I
I
t
t
t
V
V
= 1.7V
= 0.3V
30
–47
–2
2
µꢀ
µꢀ
ns
ns
ns
LE/HYST
LE/HYST
Latch Pin Current Low
–70
Latch Setup Time (Note 10)
Latch Hold Time (Note 10)
Latch to Output Delay
SETUP
HOLD
7
PL
Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)
I
Shutdown Mode Input Stage Supply Current
V
V
V
= 0.6V
430
200
300
80
600
660
µꢀ
µꢀ
SD_VCC
SHDN
SHDN
SHDN
l
l
l
I
Shutdown Mode Output Stage Supply
Current
= 0.6V, LTC6752-2
= 0.6V, LTC6752-3
420
450
µꢀ
µꢀ
SD_VDD
700
800
µꢀ
µꢀ
t
Shutdown Time
Output Hi-Z
ns
V
SD
l
l
V
V
Shutdown Pin Voltage High
Shutdown Pin Voltage Low
Wake-Up Time from Shutdown
Part Guaranteed to Be Powered On
Part Guaranteed to Be Powered Off
1.3
IH_SD
IL_SD
0.6
V
t
V
= 100mV, Output Valid
OD
100
ns
WꢀKEUP
(VCC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3/LTC6752-4 only). The l denotes the specifications which apply over the
specified temperature range, otherwise specifications are at TA = 25°C. LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV,
–IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
2.45
1.71
TYP
MAX
5.25
3.5
UNITS
l
l
l
V
V
V
V
- V
Input Supply Voltage (Note 5)
Output Supply Voltage (Note5)
Input Voltage Range (Note 7)
Input Offset Voltage (Note 6)
V
V
V
CC
DD
EE
- V
EE
V
– 0.2
V
+ 0.1
CC
CMR
OS
EE
–5.5
–9
1.2
5.5
9
mV
mV
l
l
TCV
Input Offset Voltage Drift
Input Hysteresis Voltage (Note 6)
Input Capacitance
14
5.2
1.1
57
µV/°C
mV
pF
OS
HYST
IN
V
C
LE/HYST Pin Floating
R
DM
R
CM
Differential Mode Resistance
Common Mode Resistance
Input Bias Current
kΩ
6.4
–1.5
MΩ
I
B
V
V
= V + 0.3V
–3.9
–4.2
µꢀ
µꢀ
CM
CM
EE
l
l
= V – 0.3V
0.36
1.6
2.5
µꢀ
µꢀ
CC
6752fc
7
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
elecTrical characTerisTics (VCC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3/LTC6752-4 only).
The l denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C.
LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
0.1
70
MAX
UNITS
l
l
l
l
l
I
Input Offset Current
–0.9
0.9
µꢀ
OS
CMRR_
LVCM
Common Mode Input Range, Low V
Region
V
= V – 0.2V to V – 1.5V
54
51
dB
dB
CM
CM
EE
CC
CMRR_FR
Common Mode Rejection Ratio (Measured at V = V – 0.2V to V + 0.1V
Extreme Ends of V
53
48
68
75
dB
dB
CM
CM
EE
CC
)
CMR
PSRR_V
PSRR_V
Input Power Supply Rejection Ratio
Output Power Supply Rejection Ratio
Open Loop Gain
V
= 0.3V, V = 1.8V,V Varied from 2.45V
59
57
dB
CC
DD
CC
to 5.25V
V
= 0.3V, V Varied from 1.71V to 3.5V
57
51
71
dB
dB
DD
CM
DD
ꢀ
V
V
LTC6752-2/LTC6752-3 Hysteresis Removed
(Note 12)
3500
200
200
17
V/V
VOL
OH
OL
Output High Voltage (ꢀmount Below V
)
DD
I = 5.5mꢀ
SOURCE
400
450
mV
mV
l
l
l
l
l
l
l
l
l
Output Low Voltage (Referred to V
)
I
= 5.5mꢀ
SINK
400
550
mV
mV
EE
I
Output Short-Circuit Current
Source
Sink
9
6.2
mꢀ
mꢀ
SC
11
6.2
19
mꢀ
mꢀ
I
I
V
V
Supply Current, Device On
Supply Current, Device On
2.1
2.5
3.4
4.5
6
2.65
2.85
mꢀ
mꢀ
VCC
VDD
CC
DD
LTC6752-2/LTC6752-4
LTC6752-3
3
3.25
mꢀ
mꢀ
4.4
4.8
mꢀ
mꢀ
I
Total Supply Current, Device On
LTC6752-2/LTC6752-4
LTC6752-3
5.65
6.1
mꢀ
mꢀ
TOTꢀL
7.05
7.65
mꢀ
mꢀ
t , t
Rise/Fall Time
10% to 90%
1.25
3.4
ns
R
F
t
Propagation Delay (Note 8)
V
= 50mV
OVERDRIVE
5.3
5.7
ns
ns
PD
l
t
Propagation Delay Skew, Rising to Falling
Transition (Note 9)
400
ps
SKEW
t
t
Overdrive Dispersion (Note 8)
Common Mode Dispersion
Toggle Rate (Note 11)
Overdrive Varied from 10mV to 125mV
Varied from V – 0.2V to V + 0.1V
1.8
ns
ps
ODD
V
240
CMD
CM
EE
CC
TR
100mV Input, LTC6752-2/LTC6752-4
230
185
MHz
MHz
P-P
100mV Input, LTC6752-3
P-P
t
RMS Jitter
V
= 100mV , f = 100MHz,
4.3
ps
JITTER
IN
P-P IN
Jitter BW = 10Hz – 50MHz
f
IN
f
IN
= 61.44MHz, Jitter BW = 10Hz – 30.72MHz
= 10MHz, Jitter BW = 10Hz – 5MHz
5.8
28
ps
ps
6752fc
8
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
elecTrical characTerisTics (VCC = 5V, VDD = 1.8V, VEE = 0, LTC6752-2/LTC6752-3 only).
The l denotes the specifications which apply over the specified temperature range, otherwise specifications are at TA = 25°C.
LE/HYST, SHDN pins floating, CL = 5pF, VOVERDRIVE = 50mV, –IN = VCM = 300mV, +IN = –IN + VOVERDRIVE, 150mV step size unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Latching/Adjustable Hysteresis Characteristics (LTC6752-2/LTC6752-3 Only)
l
l
V
LE/HYST Pin Voltage
Open Circuit
1.05
15
1.25
20
1.45
25
V
kΩ
mV
V
LE/HYST
R
Resistance Looking Into LE/HYST
Modified Input Hysteresis Voltage (Note 2)
Latch Pin Voltage, Latch Guaranteed
Latch Pin Voltage, Hysteresis Disabled
Latch Pin Current High
LE/HYST Pin Voltage < Open Circuit Value
HYST
HYST_LꢀRGE
IL_LE
V
V
V
V
= 800mV
40
LE/HYST
l
l
l
l
0.3
72
Output Not Latched
1.7
V
IH_LE
IH_LE
IL_LE
I
I
t
t
t
V
V
= 1.7V
= 0.3V
30
–47
–2
2
µꢀ
µꢀ
ns
ns
ns
LE/HYST
LE/HYST
Latch Pin Current Low
–70
Latch Setup Time (Note 10)
Latch Hold Time (Note 10)
SETUP
HOLD
Latch To Output Delay
7
PL
Shutdown Characteristics (LTC6752-2/LTC6752-3 Only)
I
Shutdown Mode Input Stage Supply Current
V
V
V
= 0.6V
500
170
240
80
650
750
µꢀ
µꢀ
SD_VCC
SHDN
SHDN
SHDN
l
l
l
I
Shutdown Mode Output Stage Supply
Current
= 0.6V, LTC6752-2
= 0.6V, LTC6752-3
400
450
µꢀ
µꢀ
SD_VDD
600
650
µꢀ
µꢀ
t
Shutdown Time
Output Hi-Z
ns
V
SD
l
l
V
V
Shutdown Pin Voltage High
Shutdown Pin Voltage Low
Wake-Up Time from Shutdown
Part Guaranteed to Be Powered On
Part Guaranteed to Be Powered Off
1.3
IH_SD
IL_SD
0.6
V
t
V
= 100mV, Output Valid
OD
100
ns
WꢀKEUP
Note 1: Stresses beyond those listed under ꢀbsolute Maximum Ratings
may cause permanent damage to the device. Exposure to any ꢀbsolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 6: Both hysteresis and offset are measured by determining positive
and negative trip points (input values needed to change the output in the
opposite direction). Hysteresis is defined as the difference of the two trip
points and offset as the average of the two trip points.
Note 2: Reverse biased ESD protection diodes exist on all input,
shutdown, latching/hysteresis and output pins. If the voltage on these
pins goes 300mV beyond either supply rail, the current should be limited
to less than 10mꢀ. This parameter is guaranteed to meet specification
through design and/or characterization. It is not production tested.
Note 3: ꢀ heat sink may be required to keep the junction temperature
below the absolute maximum rating. This parameter is guaranteed to meet
specified performance through design and/or characterization. It is not
production tested.
Note 4: The LTC6752I/LTC6752-1I/LTC6752-2I/LTC6752-3I/LTC6752-4I
are guaranteed to meet specified performance from –40°C to 85°C. The
LTC6752H/LTC6752-1H/LTC6752-2H/LTC6752-3H/LTC6752-4H are
guaranteed to meet specified performance from –40°C to 125°C.
Note 7: Guaranteed by CMRR test.
Note 8: Propagation delays are measured with a step size of 150mV.
Note 9: Propagation delay skew is defined as the difference of the
propagation delays for positive and negative steps for the LTC6752,
LTC6752-1, LTC6752-2 and LTC6752-4, and the difference in propagation
delays between the complementary outputs for the LTC6752-3.
Note 10: Latch setup time is defined as the minimum time before the
LE/HYST pin is asserted low for an input signal change to be acquired and
held at the output. Latch hold time is defined as the minimum time before
an input signal change for a high to low transition on the LE/HYST pin to
prevent the output from changing. See Figure 7 for a graphical definition of
these terms.
Note 11: Toggling is defined to be valid if the output swings as follows:
Note 5: Total output supply voltage range is guaranteed by the PSRR_V
DD
from 10% of V - V to 90% of V - V for the LTC6752-2/
DD
EE
DD
EE
test. Total input supply voltage range for the LTC6752-2, LTC6752-3 and
LTC6752-4 is guaranteed by the PSRR_V test. For the LTC6752 and
LTC6752-3/LTC6752-4, and from 10% of V - V to 90% of V - V
for the LTC6752/LTC6752-1. It is tested with a 1kΩ load to V
Note 12: The devices have effectively infinite gain when hysteresis is
enabled.
CC
EE
CC
EE
CC
CM
LTC6752-1, the supply voltage range is guaranteed by the PSRR_V test.
CC
The LTC6752MP is guaranteed to meet specified performance from –55°C
to 125°C.
6752fc
9
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
VCC = VDD = 2.5V, CLOAD = 5pF,
Typical perForMance characTerisTics Dc
VOVERDRIVE = 50mV, VCM = 300mV,TA = 25°C unless otherwise noted. VCC ≠ VDD conditions applicable only to the LTC6752-2/LTC6752-3/
LTC6752-4.
Input Offset Voltage and
Hysteresis vs Temperature
Input Offset Voltage and
Hysteresis vs VCC Voltage
Input Offset Voltage and
Hysteresis vs VDD Voltage
8
6
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
HYSTERESIS
HYSTERESIS
4
2
0
OFFSET
OFFSET
–2
V
V
HYST
OS
–4
–55 –35 –15
5
25 45 65 85 105 125
2.45
3.15
3.85
4.55
5.25
1.6
2.1
2.6
3.1
3.6
TEMPERATURE (°C)
V
VOLTAGE (V)
V
VOLTAGE (V)
DD
CC
6752 G01
6752 G02
6752 G03
Input Bias Current vs Common
Mode Voltage
Input Offset Voltage and
Input Bias Current vs Temperature
Hysteresis vs Input Common Mode
7
6
0.8
0.6
0.5
HYSTERESIS
0.4
V
= V
OS
5
0
–0.5
–1.0
–1.5
–2.0
IN
V
= 2.2V
0.2
CM
4
0
3
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
2
OFFSET
1
0
V
= 300mV
CM
–1
–2
–3
–0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6
–55 –35 –15
5
25 45 65 85 105 125
–0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6
INPUT COMMON MODE VOLTAGE (V)
TEMPERATURE (°C)
INPUT COMMON MODE VOLTAGE (V)
6752 G04
6752 G05
6752 G06
Input Bias Current vs Differential
Input Voltage
Input Hysteresis vs LE/HYST Pin
Voltage
LE/HYST Pin I-V Characteristics
1.0
50
40
30
20
10
0
200
0.5
0
–IN
150
100
50
V
= 5V
CC
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
V
= 2.5V
V
CC
V
DD
V
CM
= 5V
= 2.5V
= 2.5V
CC
+IN
0
–50
–100
–5.4 –4.2 –3.0 –1.8 –0.6 0.6 1.8 3.0 4.2 5.4
0.75
1.00
1.25
1.50
1.75
–0.3 0.5 1.3 2.1 2.9 3.7 4.5 5.3
INPUT DIFFERENTIAL VOLTAGE (V)
LE/HYST VOLTAGE (V)
LE/HYST PIN VOLTAGE (V)
6752 G07
6752 G08
6752 G09
6752fc
10
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
VCC = VDD = 2.5V, CLOAD = 5pF,
Typical perForMance characTerisTics Dc
VOVERDRIVE = 50mV, VCM = 300mV,TA = 25°C unless otherwise noted. VCC ≠ VDD conditions applicable only to the LTC6752-2/ LTC6752-3/
LTC6752-4.
Output Short-Circuit Current vs
Temperature
Output Low Voltage vs Load
Current
Output High Voltage vs Sourcing
Current
80
60
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
MEASURED FROM V
EE
V
CC
V
DD
= 3.3V
= 3.3V
V
CC
V
DD
= 3.3V
= 3.3V
SINKING
40
20
V
CC
V
DD
= 2.5V
= 2.5V
V
CC
V
DD
= 2.5V
= 2.5V
V
CC
V
DD
= 5V
= 1.8V
0
SOURCING
–20
–40
–60
–80
V
CC
V
DD
= 5V
= 1.8V
V
V
V
= 5V, V = 1.8V
DD
CC
CC
CC
= V = 2.5V
DD
= V = 3.3V
DD
–55 –35 –15
5
25 45 65 85 105 125
0
5
10 15 20 25 30 35 40 45
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
SINKING CURRENT (mA)
SOURCING CURRENT (mA)
6752 G10
6752 G11
6752 G12
Supply Current vs Temperature
(LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4)
Supply Current vs Temperature
(LTC6752-3)
Output High/Low Voltage vs
Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
7
6
5
4
3
2
1
300
250
200
150
100
50
SOURCE/SINK CURRENT = 8mA
I
I
I
(LTC6752-2/LTC6752-4)
TOTAL
TOTAL
CC
(LTC6752/LTC6752-1)
MEASURED
V
V
OL
OH
FROM V
EE
I
I
VDD
MEASURED
FROM V
I
(LTC6752-2/LTC6752-4)
VDD
DD
VCC
5
I
(LTC6752-2/LTC6752-4)
VCC
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
6752 G14
6752 G15
6752 G13
Supply Current vs Input Common
Mode Voltage (LTC6752/LTC6752-1/
LTC6752-2/LTC6752-4)
Supply Current vs Supply Voltage
(LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4)
Supply Current vs Supply Voltage
(LTC6752-3)
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
4.85
4.80
4.75
4.70
4.65
4.60
4.55
4.50
4.45
V
= V
V
= V
CC DD
CC
DD
I
TOTAL
I
I
(LTC6752-2/LTC6752-4)
TOTAL
CC
(LTC6752/LTC6752-1)
I
VDD
I
(LTC6752-2/LTC6752-4)
VDD
I
VCC
I
(LTC6752-2/LTC6752-4)
VCC
2.45
2.75
3.05
3.35
3.65
2.45
2.75
3.05
3.35
3.65
–0.2
0.5
INPUT COMMON MODE VOLTAGE (V)
6752 G18
1.2
1.9
2.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6752 G16
6752 G17
6752fc
11
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
VCC = VDD = 2.5V, CLOAD = 5pF,
Typical perForMance characTerisTics Dc
VOVERDRIVE = 50mV, VCM = 300mV,TA = 25°C unless otherwise noted. VCC ≠ VDD conditions applicable only to the LTC6752-2/LTC6752-3/
LTC6752-4.
Supply Current vs Input Common
Mode Voltage (LTC6752-3)
Total Supply Current vs SHDN Pin
SHDN Pin I-V Characteristics
Voltage (LTC6752-2)
6.45
6.40
6.35
6.30
6.25
6.20
6.15
6.10
2
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 2.5V
CC
–2
–4
–6
–8
V
= 5V
CC
–10
–12
–14
–16
–0.2
0.5
1.2
1.9
2.6
–0.3 0.5 1.3 2.1 2.9 3.7 4.5 5.3
VOLTAGE BETWEEN SHDN PIN AND V (V)
–0.3
0.2
0.7
1.2
1.7
2.2
2.7
INPUT COMMON MODE VOLTAGE (V)
SHDN PIN VOLTAGE (V)
EE
6752 G19
6752 G20
6752 G21
Total Supply Current vs SHDN Pin
Voltage (LTC6752-3)
Supply Current vs Temperature,
Shutdown (LTC6752-3)
Supply Current vs Temperature,
Shutdown (LTC6752-2)
7
6
5
4
3
2
1
0
700
600
500
400
300
200
100
700
600
500
400
300
200
100
I
TOTAL
I
TOTAL
I
I
VDD
IV
IV
DD
CC
VCC
5
–55 –35 –15
5
25 45 65 85 105 125
–0.3
0.2
0.7
1.2
1.7
2.2
2.7
–55 –35 –15
25 45 65 85 105 125
TEMPERATURE (°C)
SHDN PIN VOLTAGE (V)
TEMPERATURE (°C)
6752 G24
6752 G22
6752 G23
6752fc
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
VCC = VDD = 2.5V, CLOAD = 5pF,
Typical perForMance characTerisTics ac
VOVERDRIVE = 50mV, VCM = 300mV, TA = 25°C, transient input voltage 10MHz, 150mVP-P square wave unless otherwise noted.
VCC ≠ VDD conditions applicable only to the LTC6752-2/LTC6752-3/LTC6752-4.
Propagation Delay vs Input
Overdrive
Propagation Delay vs Common
Mode Voltage
Propagation Delay vs
Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
3.5
3.0
2.5
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
tpd
tpd
tpd
HL
tpd
LH
HL
LH
tpd, OUTPUT FALLING (tpd
)
HL
V
= 5V, V = 1.8V
DD
CC
V
= 5V, V = 1.8V
DD
CC
tpd, OUTPUT RISING(tpd
)
HL
V
= 2.5V, V = 2.5V
DD
CC
V
= 2.5V, V = 2.5V
DD
CC
10 20 30 40 50 60 70 80 90 100110120
–0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6
–55 –35 –15
5
25 45 65 85 105 125
OVERDRIVE (mV)
INPUT COMMON MODE VOLTAGE (V)
TEMPERATURE (°C)
6752 G25
6752 G26
6752 G27
Propagation Delay vs Output
Stage Supply Voltage
Propagation Delay vs
Capacitive Load
Propagation Delay vs Input Stage
Supply Voltage
3.00
2.95
2.90
2.85
2.80
2.75
2.70
2.65
2.60
3.7
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
tpd
tpd
HL
LH
3.5
3.3
3.1
2.9
2.7
2.5
V
= 5V, V = 1.8V
DD
CC
tpd
HL
tpd
LH
tpd
HL
tpd
LH
V
= 2.5V, V = 2.5V
DD
CC
2.45 2.85 3.25 3.65 4.05 4.45 4.85 5.25
VOLTAGE (V)
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
VOLTAGE (V)
0
5
10
15
20
V
V
DD
LOAD CAPACITANCE (pF)
CC
6752 G28
6752 G29
6752 G30
Toggle Rate vs Input Amplitude,
LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4
Toggle Rate vs Input Amplitude,
LTC6752-3
Rise/Fall times vs
Capacitive Load
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
360
340
320
300
280
260
240
220
200
180
160
300
280
260
240
220
200
180
160
140
V
R
= 1V
V
R
= 1V
CM
L
CM
L
V
= 2.5V, V = 2.5V
DD
CC
= 1kΩ
= 1kΩ
V
= 2.5V, V = 2.5V
DD
CC
V
= 3.3V, V = 3.3V
DD
CC
V
= 5V, V = 1.8V
DD
CC
V
= 5V, V = 1.8V
DD
CC
t
RISE
FALL
t
V
= 3.3V, V = 3.3V
DD
CC
V
V
= 5V, V = 1.8V
DD
= 2.5V, V = 2.5V
CC
CC
DD
0
5
10
15
20
20
200
2000
20
200
2000
LOAD CAPACITANCE (pF)
INPUT AMPLITUDE (mV
)
P-P
INPUT AMPLITUDE (mV
)
P-P
6752 G31
6752 G32
6752 G33
6752fc
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
VCC = VDD = 2.5V, CLOAD = 5pF,
Typical perForMance characTerisTics ac
VCC ≠ VDD conditions applicable only to the LTC6752-2/ LTC6752-3/LTC6752-4.
VOVERDRIVE = 50mV, VCM = 300mV, TA = 25°C, transient input voltage 10MHz, 150mVP-P square wave unless otherwise noted.
Toggle Rate vs Capacitive Load,
(LTC6752/LTC6752-1/LTC6752-2/
LTC6752-4)
Toggle Rate vs Temperature, (LTC6752/
LTC6752-1/LTC6752-2/LTC6752-4)
Toggle Rate vs Temperature,
LTC6752-3
350
330
310
290
270
250
230
210
190
170
150
290
270
250
230
210
190
170
150
500
450
400
350
300
250
200
150
100
R
V
= 1kΩ
R
V
= 1kΩ
L
L
V
= 2.5V, V = 2.5V
DD
= 100mV
= 100mV
P-P
CC
IN
P-P
IN
V
= 2.5V, V = 2.5V
DD
CC
SINUSOID
SINUSOID
V
= 2.5V, V = 2.5V
DD
CC
V
= 3.3V, V = 3.3V
DD
V
= 5V, V = 1.8V
DD
CC
CC
V
V
CC
= 3.3V, V = 3.3V
DD
= 3.3V, V = 3.3V
CC
DD
V
= 5V, V = 1.8V
DD
CC
R
V
= 1kΩ
L
V
= 5V, V = 1.8V
DD
CC
= 100mV
IN
P-P
SINUSOID
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
0
5
10
15
20
TEMPERATURE (°C)
TEMPERATURE (°C)
LOAD CAPACITANCE (pF)
6752 G34
6752 G35
6752 G36
Toggle Rate vs Capacitive Load,
LTC6752-3
Output Jitter vs Input Amplitude
16
14
12
10
8
R
V
= 1kΩ
100MHz SINOSOIDAL INPUT
JITTER BANDWIDTH: 10Hz TO 50MHz
L
380
330
280
230
180
130
80
= 100mV
IN
P-P
SINUSOID
V
CC
= 3.3V, V = 3.3V
DD
V
= 2.5V, V = 2.5V
DD
CC
V
= 3.3V, V = 3.3V
DD
CC
V
= 5V, V = 1.8V
DD
CC
6
4
2
V
= 5V, V = 1.8V
DD
CC
V
= 2.5V, V = 2.5V
DD
CC
0
0
5
10
15
20
0
100 200 300 400 500 600 700
INPUT AMPLITUDE (mV
LOAD CAPACITANCE (pF)
)
P-P
6752 G37
6752 G38
Output Toggle Waveform,
LTC6752-2
Output Toggle Waveforms Q and
Q, LTC6752-3
500mV/DIV
500mV/DIV
6752 G39
6752 G40
2ns/DIV
2ns/DIV
LTC6752-2
LTC6752-3
V
C
= V = 2.5V
V
C
= V = 2.5V
CC
L
DD
CC DD
= 5pF
L
= 5pF
200MHz
200MHz
6752fc
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
pin FuncTions
+IN: Positive Input of the Comparator. The voltage range
SHDN: ꢀctive low comparator shutdown, threshold is
of this pin can go from V to V .
0.6V above V . The comparator is enabled when this pin
EE
CC
EE
is left unconnected.
–IN: Negative Input of the Comparator. The voltage range
of this pin can go from V to V .
LE/HYST: This pin allows the user to adjust the compara-
EE
CC
tor’s hysteresis as well as latch the output state if the pin
V :PositiveSupplyVoltagefortheLTC6752/LTC6752-1,
CC
voltage is taken within 300mV above V . Hysteresis can
EE
Positive Supply Voltage for the Input Stage of the
be increased or disabled by voltage, current or a resistor
LTC6752-2/LTC6752-3/LTC6752-4.
to V . Leaving the pin unconnected results in a typical
EE
V : Positive Supply Voltage for the Output Stage of the
hysteresis of 5mV.
DD
LTC6752-2/LTC6752-3/LTC6752-4. Typically the voltage
is from 1.71V to 3.5V. See the section High Speed Board
Design Techniques for proper power supply layout and
bypassing.
Q: Comparator Output. Q is driven high when +IN > –IN
and driven low when +IN < –IN.
Q: Comparator Complementary Output (ꢀvailable on
LTC6752-3 Only). Logical inversion of Q.
V : Negative power supply, normally tied to ground. This
EE
can be tied to a voltage other than ground as long as the
constraints for total supply voltage relative to V (and
CC
V
DD
for separate supply operation) are maintained.
6752fc
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
block DiagraM
V
DD
HYSTERESIS STAGE
+
–
V
V
EE
CC
V
CC
+
+IN
–IN
+
–
+
–
OUTPUT
DRIVER
STAGE
INPUT
STAGE
GAIN
STAGE
Q
+
V
EE
V
CC
V
V
EE
CC
+
–
20k
LE/HYST
V
+
CC
1.25V
–
V
V
EE
EE
350k
V
EE
LE/HYST PIN INTERFACE
6752 BD
SHDN
V
EE
Figure 1. LTC6752/LTC6752-1/LTC6752-2/LTC6752-4 Block Diagram
6752fc
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
applicaTions inForMaTion
Circuit Description
Input Voltage Range and Offset
The block diagram is shown in Figure 1. There are dif-
The LTC6752 family uses a rail-to-rail input stage that
consists of a pnp pair and an npn pair that are active over
different input common mode ranges. The pnp pair is ac-
ferential inputs (+IN, –IN), a negative power supply (V ),
EE
two positive supply pins: V for the input stage and V
CC
DD
for the output stage, an output pin (Q), a pin for latching
and adjusting hysteresis (LE/HYST), and a pin to put the
device in a low power mode (SHDN). In the LTC6752
and LTC6752-1, the two positive supply pins are bonded
tive for inputs between V – 0.2V and approximately V
EE
CC
– 1.5V (low common mode region of operation). The npn
pair is active for inputs between approximately V – 1V
CC
and V + 0.1V (high common mode region of operation).
CC
together and referred to as V . The signal path consists
CC
Partial activation of both pairs occurs when one input is in
the low common mode region of operation and the other
input is in the high common mode region of operation, or
of a rail-to-rail input stage, an intermediate gain stage,
and an output stage driving a pair of complementary FETs
capable of taking the output pin to either supply rail. ꢀ
Latching/Hysteresisinterfaceblockallowstheusertolatch
the output state and/or remove or adjust the comparator
input hysteresis. ꢀll of the internal signal paths make use
of low voltage swings for high speed at low power.
either of the inputs is between approximately V – 1.5V
CC
and V – 1V (transition region). The device has small,
CC
trimmed offsets as long as both inputs are completely
in the low or high common mode region of operation.
In the transition region, the offset voltage may increase.
ꢀpplications that require good DC precision should avoid
the transition region.
The LTC6752-3 has an additional inverted output stage
(not shown) for a complementary logic output signal.
Input Bias Current
Power Supply Configurations
When both inputs are in the low common mode region,
the input bias current is negative, with current flowing
out of the input pins. When both inputs are in the high
common mode region, the input bias current is positive,
with current flowing into the input pins.
The LTC6752-2/LTC6752-3/LTC6752-4 have separate
positive supply pins for the input and output stages that
allow for separate voltage ranges for the analog input,
and the output logic. Figure 2 shows a few possible con-
figurations. For reliable and proper operation, the input
supply pin should be between 2.45V and 5.25V above the
negative supply pin, and the output supply pin should be
between 1.71V and 3.5V above the negative supply pin.
There are no restrictions regarding the sequence in which
thesuppliesareapplied,aslongastheabsolute-maximum
ratings are not violated.
The input stage has been designed to accommodate
large differential input voltages without large increases
in input bias current. With one input at the positive input
supply rail and the other input at the negative supply rail,
the magnitude of the input bias currents at either pin is
typically less than 3.5μꢀ.
The LTC6752 and LTC6752-1 have only one positive sup-
ply pin. The supply voltage should be between 2.45V and
3.5V for proper and reliable operation.
3V
3V
5V 1.8V
2.5V 3.5V
2.5V 0V
V
V
V
V
CC
CC
CC
CC
+IN
–IN
+IN
–IN
+IN
–IN
+IN
–IN
+
–
+
–
+
–
+
–
V
V
V
V
DD
DD
DD
DD
Q
Q
Q
Q
V
EE
V
V
V
EE
EE
EE
0V
(a) SINGLE SUPPLY
0V
(b) OUTPUT SUPPLY < INPUT SUPPLY
0V
(c) OUTPUT SUPPLY > INPUT SUPPLY
–2.5V
(d) NEGATIVE OUTPUT LOGIC
6752 F02
Figure 2. Typical Power Supply Configurations (Applicable to the LTC6752-2/LTC6752-3/LTC6752-4)
6752fc
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LTC6752-4
applicaTions inForMaTion
Input Protection
ESD
The input stage is protected against damage from condi-
tions where the voltage on either pin exceeds the supply
The LTC6752 family members have reverse-biased ESD
protection diodes on pins as shown in Figure 1.
voltage (V to V ) without external protection. External
CC
EE
There are additional clamps between the positive and
negative supplies that further protect the device during
ESD strikes. Hot-plugging of the device into a powered
socketisnotrecommendedsincethiscantriggertheclamp
resultinginlargecurrentsflowingbetweenthesupplypins.
input protection circuitry is only needed if input currents
can exceed the absolute maximum rating. For example,
if an input is taken beyond 300mV of either the positive
or negative supply, an internal ESD protection diode will
conduct and an external resistor should be used to limit
the current to less than 10mꢀ.
Hysteresis
Comparators have very high open-loop gain. With slow
input signals that are close to each other, input noise can
cause the output voltage to switch randomly. This can be
addressed by hysteresis which is positive feedback that
increases the trip point in the direction of the input signal
transition when the output switches. This pulls the inputs
away from each other, and prevents continuous switching
back and forth. The addition of positive feedback also has
theeffectofmakingthesmallsignalgaininfinitearoundthe
trip points. Hysteresis is designed into most comparators
and the LTC6752 family has adjustable hysteresis with a
default hysteresis of 5mV.
Outputs
The LTC6752 family has excellent drive capability. The
comparators can deliver typically 22mꢀ output current
for an output supply of 2.5V, and 39mꢀ output current
for a 3.3V output supply. ꢀttention must be paid to keep
the junction temperature of the IC below 150°C should the
output have a continuous short-circuit condition.
Logic Drive Capability
The LTC6752 family has been designed to drive CMOS
logic with a supply of 3.3V, 2.5V and 1.8V. For device reli-
ability,theoutputpowersupply(V )shouldnotbehigher
than 3.6V above the negative supply. When V is 3V or
DD
The input-output transfer characteristic is illustrated in
DD
Figure 3 showing the definitions of V and HYST based
OS
higher the CMOS outputs of the LTC6752 family provide
valid TTL logic threshold levels and can easily interface
with TTL logic devices operating with a 5V supply. This is
possiblebecauseallofthethresholdlevelsassociatedwith
upon the two measurable trip points.
In some cases, additional noise immunity is required
above what is provided by the nominal 5mV hysteresis.
TTL logic (V /V /V /V ) are less than or equal to 2.4V
IH IL OH OL
V
OUT
Capacitive Loads
V
OH
The LTC6752 family can drive capacitive loads. Transient
performance parameters in the Electrical Characteristics
Tables and Typical Characteristics section are for a load
of 5pF, corresponding to a standard TTL/CMOS load. The
devices are fully functional for larger capacitive loads,
howeverspeedperformancewilldegrade.Thegraphstitled
Propagation Delay vs Capacitive Load and Toggle Rate vs
CapacitiveLoadillustratetheimpactofchangestothetotal
capacitive load. For optimal speed performance, output
load capacitance should be reduced as much as possible.
+
FOR V
= 3mV,
V
TRIP
TRIP
HYST
+
–
–
V
V
V
= –2mV,
(= V
– V
)
TRIP
TRIP
OS
HYST
= 0.5mV,
= 5mV
V
+
–
OL
∆V = V – V
IN
IN
IN
0
V
OS
–
+
V
V
TRIP
TRIP
+
–
V
+ V
2
TRIP
TRIP
6752 F03
V
=
OS
Figure 3
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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
applicaTions inForMaTion
Conversely, when processing small or fast differential sig-
nals, hysteresis may need to be eliminated. The LTC6752-1/
LTC6752-2/LTC6752-3 provide a hysteresis pin, LE/
HYST, that can be used to increase the internal hysteresis,
completely remove it, or enable the output to latch. For
these 3 options of the LTC6752, the internal hysteresis
is disabled when the LE/HYST pin voltage is above 1.7V.
ꢀlthough eliminating hysteresis does reduce the voltage
gain of the comparator to a finite value, in many cases it
will be high enough (typically 6000V/V) to process small
input signals. The output will latch when the LE/HYST pin
voltage is below 0.3V. The internal hysteresis will increase
as the voltage of the pin is adjusted from its default open
circuit value of 1.25V to 800mV.
In addition to adjusting hysteresis using the LE/HYST
pin, additional hysteresis can be added using positive
feedback from the output back to the positive input, as
shown in Figure 6.
R2
V
CC
R1
V
+
–
V
DD
REF
Q
SIGNAL
V
EE
6752 F06
Figure 6. Additional Hysteresis Using Positive Feedback
The LE/HYST pin can be modeled as a 1.25V voltage
source in series with a 20k resistor. The simplest method
to increase the internal hysteresis is to connect a single
resistorasshowninFigure4betweentheLE/HYSTpinand
The offset (with respect to the input signal) and hysteresis
become
V + V
R1
R2
(
)
DD
EE
VOS_FB
=
+ V
− VOS
2
R1+R2 REF R1+R2
V
to adjust hysteresis. Figure 5 shows how hysteresis
EE
VOH R1
R2
typically varies with the value of the resistor.
−
+ V
→(1)
2 R1+R2 OL R1+R2
V
CC
+IN
–IN
+
–
V
R1
R2
DD
Q
VHYST _FB = V − V
+ V
R1+R2 OL R1+R2
+
(
)
DD
EE
LE/HYST
R1
V
EE
V
+ VHYST →(2)
OH R1+R2
R
6752 F04
V
and V
denote the values of offset and
HYST_FB
OS_FB
hysteresis with positive feedback present. V
denotes
HYST
Figure 4. Adjusting Hysteresis Using an External
Resistor at the LE/HYST Pin
the hysteresis of the device without positive feedback.
For light loads, V (output swing high) and V (output
swing low) are typically a few mV (typically are less than
10mV for a 500µꢀ load).
OH
OL
50
V
V
T
= V = 2.5V
DD
CC
CM
45
40
35
30
25
20
15
10
5
= 0.3V
= 25°C
A
CONTROL RESISTOR CONNECTED
BETWEEN LE/HYST PIN AND V
On a 3.0V total supply with V = 0V, an increase in
hysteresis of approximately 300mV can be obtained with
EE
EE
V
= 1.25V, R2 = 4.53kΩ , R1 = 511Ω, with an induced
REF
offset of approximately 1.275V.
0
30 80 130 180 230 280 330 380 430 480
CONTROL RESISTANCE (kΩ)
6752 F05
Figure 5. Hysteresis vs Control Resistor
6752fc
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LTC6752-2/LTC6752-3/
LTC6752-4
applicaTions inForMaTion
Latching
LE/HYST
TheinternallatchoftheLTC6752-1/LTC6752-2/LTC6752-3
retains the output state when the LE/HYST pin is taken to
less than 300mV above the negative supply.
t < t
HOLD
Figures 7a to 7e illustrate the latch timing definitions. The
latch setup time is defined as the time for which the input
should be stable before the latch pin is asserted low to
ensure that the correct state will be held at the output. The
latch hold time is the interval after which the latch pin is
asserted in which the input signal must remain stable for
the output to be the correct state at the time latch was
+IN – –IN
Q
t
PD
6752 F07c
Figure 7c. Input State Not Held Long Enough.
Wrong Output State Latched
asserted. The latch to output delay (t ) is the time taken
PL
for the output to return to input control after the latch
pin is released. Latching is disabled if the LE/HYST pin
is left floating. Both outputs of the LTC6752-3 are latch
controlled simultaneously.
LE/HYST
t > t
t > t
HOLD
SETUP
+IN – –IN
Q
LE/HYST
t
PD
t > t
SETUP
6752 F07d
Figure 7d. Short Input Pulse Properly
Captured and Latched
+IN – –IN
Q
t
PD
6752 F07a
LE/HYST
Figure 7a. Input State Change Properly Latched
t
PL
+IN – –IN
Q
LE/HYST
6752 F07e
t < t
SETUP
Figure 7e. Latched Output Disabled
Shutdown
+IN – –IN
The LTC6752-2 and LTC6752-3 have shutdown pins
(SHDN, active low) that can reduce the total supply cur-
rent to a typical value of 580μꢀ for the LTC6752-2 and
650µꢀ for the LTC6752-3 (2.5V supply). When the part is
in shutdown, the outputs are placed in a high-impedance
state,sincePFETandNFEToutputtransistorswhosedrains
Q
6752 F07b
Figure 7b. Input Change Setup Time Too Short
6752fc
20
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
applicaTions inForMaTion
are tied to the output pins are cut off and cannot source/
sink any current. The shutdown pin needs to be taken to
within 600mV of the negative supply for the part to shut
down. When left floating, the shutdown pin is internally
pulled towards the positive supply, and the comparator
remains fully biased on.
The positive supply pins should be adequately bypassed
to the V pin to minimize transients on the supply. Low
EE
ESR and ESL capacitors are required due to the high speed
nature of the device. Even a few nanohenries of parasitic
trace inductance in series with the supply bypassing can
causeseveralhundredmillivoltsofdisturbanceonthesupply
pins during output transitions. ꢀ 2.2µF capacitor in parallel
withmultiplelowESL,lowESR100nFcapacitorsconnected
as close to the supply pins as possible to minimize trace
Dispersion
Dispersion is defined as the change in propagation delay
for different input conditions. It becomes very crucial in
timing sensitive applications. Overdrive dispersion from
10mV overdrive to 125mV overdrive is typically less than
1.8ns(150mVtotalstepsize).ThegraphtitledPropagation
Delay vs Common Mode Voltage shows the dispersion
due to shifts in input common mode voltage.
impedance is recommended. In many applications the V
EE
pin will be connected to ground. In applications where the
V
pin is not connected to ground, the positive supplies
EE
shouldstillbebypassedtoV .TheV pinshouldalsothen
EE
EE
be bypassed to a ground plane with a 2.2µF capacitor in
parallelwithlowESL, lowESR100nFcapacitorsifpossible.
For devices with separate positive input and output sup-
plies, capacitors should not be placed between the two
positive supplies; otherwise disturbances due to output
switching can couple back to the inputs.
Jitter
The LTC6752 family has been designed for low phase
noise and jitter. This allows it to be used in applications
where high frequency low amplitude sine waves need to
be converted to full-logic level square waves with mini-
mal additive jitter. The graph titled Output Jitter vs Input
ꢀmplitude demonstrates the additive jitter of the LTC6752
family for different amplitudes of a sinusoidal input. Refer
totheElectricalCharacteristicstabletoseehowjittervaries
with signal frequency.
Tominimizesupplybounce,theboardlayoutmustbemade
with careful consideration of the supply current return
paths. The output current will return back to the supply
via the lowest impedance path available. If the terminating
connection of the load is easily available on the board, V
EE
should be bypassed to the terminating connection using
2.2µF and 100nF capacitors as described previously.
DuetothefastriseandfalltimesoftheLTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/LTC6752-4,outputtracesshouldbe
shielded with a low impedance ground plane to minimize
electromagnetic interference. Due to the complementary
nature of its outputs, the LTC6752-3 can provide a first
order cancellation of EMI effects.
High Speed Board Design Techniques
Being very high speed devices, members of the LTC6752
family are prone to output oscillations if certain guidelines
are not followed at the board level. Low impedance supply
planes, especially for the V and V pins, help to reduce
DD
EE
supply bounce related oscillations. Supply bounce tends to
worsenathigheroutputsupplyvoltagesduetolargerswings
andhigheroutputcurrentdrivecapability.Parasiticfeedback
betweentheoutputandinputpinsshouldbeminimized.The
pinoutsoftheLTC6752familymembershavebeenarranged
to minimize parasitic feedback. Input and output traces on
the board should be placed away from each other. If that is
not possible a ground or supply trace should be used as a
guardtoisolatethem.Ifpossible,asupply/groundtracethat
is not directly connected to the supply pins of the device,
but rather directly connected to the supply terminal of the
board, should be used for such a purpose.
When the input slew rate is small, sustained oscillations
can occur at the output pin while the input is transitioning
due to even one millivolt of ground bounce. For applica-
tions where the input slew rate is low, internal hysteresis
should not be removed by taking the LE/HYST pin high,
as the addition of hysteresis makes the comparators more
immune to disturbances such as ground bounce. Increas-
ing hysteresis by adjusting the LE/HYST pin voltage or by
adding positive feedback as discussed in the section on
hysteresis can further improve noise immunity.
6752fc
21
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical applicaTions
High Speed Clock Restoration/Level Translation
Circuit
Figure 9 shows the input and output waveforms of the
LTC6752-2,usedtorecoveradistorted150mV 200MHz
P-P
signal at a common mode of 2.5V with respect to its nega-
tivesupply,intoafullscale1.8Voutputsignal.ꢀC-coupling
could have been used at the input of the comparator, how-
ever to preserve input duty cycle information DC-coupling
may be preferable, and that is where having a wide input
common mode range is an advantage.
High speed comparators are often used in digital systems
to recover distorted clock waveforms. The separate input/
output supplies feature of the LTC6752-2 allows it to be
used in applications where signals need to be shifted from
onevoltagedomaintoanother.Figure8showsacircuitthat
canperformbothrecoveryandleveltranslationfunctions.
In this application, the input clock signal comes from a
source operating from 5V, and the signal is required to
driveareceiveroperatingon1.8V.The5Vinputsupply/1.8V
outputsupplyfeatureofthispartisidealforsuchasituation.
Iftheinputsignalgetsdistortedanditsamplitudeseverely
reduced due to stray capacitance, stray inductance or due
to reflections on the transmission line, the LTC6752-2 can
be used to convert it into a full scale digital output signal
that can drive the receiver.
V
, 500mV/DIV
OUT
V
, 50mV/DIV
IN
V
REF
6752 F09
2ns/DIV
Figure 9
200MHz
CLOCK
SIGNAL
V
+ 5V
V
+ 1.8V
EE
EE
LONG
TRACE
Optical Receiver Circuit
V
CC
V
+ 1.8V
EE
CLOCK/DATA
SOURCE
The LTC6752, along with a high speed high performance
FET input operational amplifier like the LTC6268, can be
usedtoimplementanopticalreceiverasshowninFigure10.
+
V
DD
CLOCK/DATA
RECEIVER
LTC6752-2
~1.8V
P-P
V
= V + 2.5V
EE
200MHz,
CLOCK
–
REF
V
EE
ATTENUATED
150mV
V
EE
SIGNAL
Figure11showstheoutputoftheLTC6268drivingthe–IN
pin of the LTC6752-2, the +IN pin of the LTC6752-2, and
the LTC6752-2 output. The photodiode is being driven by
a light source of sinusoidally varying intensity.
P-P
200MHz,
= 2.5V
V
EE
V
6752 F08
CM
Figure 8. High Speed Clock Restoration/Level
Translation/Level Shifting Circuit
3.3V
3.3V
20k
5.49k
3.3V
V
CC
+
–
1k
3.3V
V
DD
LTC6752-2
Q
47.6k
V
EE
0V TO 3.3V
OUT
+
LE/HYST
FCI-125
LTC6268
SHDN
–
0.1µF
4.53k
0.1µF
1k
6752 F10
Figure 10. Optical Receiver Circuit
6752fc
22
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical applicaTions
5.0
4.5
4.0
3.5
3.0
a threshold of 11mV to overcome comparator and system
offsets, and establish a low output in the absence of an
input signal. ꢀn input pulse causes the output of U1 to go
high, which then causes the output of U2 to go high. The
output of U2 is fed back to the input of the 1st compara-
tor, Timing Capacitor C now begins charging through R.
ꢀfter 100ns, U2 goes low, allowing U1 also to go low. ꢀ
new pulse at the input of U2 can now restart the process.
Timing capacitor C can be increased without limit for
longer output pulses.
2.5
500mV/DIV
OUT
2.0
–
IN
1.5
1.0
0.5
0
+
IN
Figure13showsinputandoutputwaveformsforthepulse
stretcher circuit.
0
10
20
30
40
50
60
70
80
90
10ns/DIV
6752 F11
Figure 11
Pulse Stretcher Circuit/Monostable Multivibrator
OUTPUT, 2V/DIV
INPUT, 20mV/DIV
For detecting short pulses from a single sensor, a pulse
stretcher is often required. The circuit of Figure 12 acts as
a one-shot, stretching the width of an incoming pulse to a
consistent~100ns.Thecircuitworksasfollows:Compara-
tor U1 functions as a threshold detector, and Comparator
U2 functions as a one-shot. Comparator U1 is biased with
6752 F13
20ns/DIV
Figure 13
3.3V
Z
= 50Ω
OUT
COMPARATOR U1
V
CC
+
–
V
INPUT 15mV TO 3.3V PULSE
MINIMUM PULSE WIDTH 5ns
DD
49.9Ω
1k
3.3V
LTC6752-2
OUT
V
EE
OUTPUT 3.3V 100ns PULSE
LE/HYST
15k
SHDN
1000pF
49.9Ω
2k
22k
SOD-123
OSA
3.3V
22k
V
+
–
CC
COMPARATOR U2
OUT
V
DD
LTC6752-2
V
EE
TIMING
LE/HYST
SHDN
CAPACITOR C
100pF
6.65k
TIMING
RESISTOR R
Figure 12
6752fc
23
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical applicaTions
Common Mode Rejecting Line Receiver
Fast Event Capture
Differential electrical signals being transmitted over long
cables are often attenuated. Electrical noise on the cables
can take the form of common mode signals.
The circuit shown in Figure 16 can be used to capture
small and fast events. The comparator output is used to
signal the latch pin and hold the output in the HIGH state.
The circuit will reset when the RESET line is low. An open
drain 1.5ns NAND gate is used to both invert the output
signal and is used to MUX in the RESET line from the
supervising circuit. One important feature of the NAND is
that it is open drain which allows the comparator to use
either its default 5mV of hysteresis or a user programmed
hysteresis.Thelatchrecoverytimeofthiscircuitisroughly
210nsandisdominatedbythetimeconstantcreatedbythe
capacitance seen at the output of the NAND gate and the
20k series resistance of the LE/HYST pin. The waveforms
are shown in Figure 17.
The LTC6752 comparators can be used to retrieve attenu-
ated differential signals that have been corrupted by high
frequency common mode noise, as shown in Figure 14.
Figure 15 shows an LTC6752-2 retrieving a 200MHz,
200mV differentialinputsignalthathas2.5Vofrandom,
P-P
commonmodenoisesuperimposedonit.Theinputsupply
(V ) used was 5V and the output supply used was 2.7V.
CC
A small amount of modulation is seen at the output due
to a small amount of differential modulation at the inputs,
whichcausescycletocyclevariationsinpropagationdelay.
3.3V
2.2μF
Q
0.1μF
INPUT
EVENT IN
V
CC
+
–
50mV, 10ns
SMALL DIFFERENTIAL SIGNAL WITH
LARGE COMMON MODE COMPONENT
V
DD
OUT
LTC6752-2
V
EE
V
= 5V
V
3.3V
182k
CC
LE/HYST
+IN
–IN
REF
+
= 2.7V
Q
DD
SHDN
200Ω
LTC6752-2
–
0.1μF
V
EE
NXP 74LVC1G38
RESET
6752 F16
6752 F14
Figure 14
Figure 16
OUT
Q
–IN +IN
RESET
500mV/DIV
500mV/DIV
INPUT
REF
6752 F15
50ns/DIV
6752 F17
Figure 15
Figure 17
6752fc
24
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
package DescripTion
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
1.4 MIN
1.50 – 1.75
(NOTE 4)
2.80 BSC
3.85 MAX 2.62 REF
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S5 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3. DIMENSIONS ARE INCLUSIVE OF PLATING
6752fc
25
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
package DescripTion
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1ꢀꢀ0 Rev G)
3.00 0.102
(.118 .004)
0.889 0.127
0.52
(.0205)
REF
(.035 .005)
(NOTE 3)
8
7
ꢀ 5
5.10
(.201)
MIN
3.00 0.102
(.118 .004)
(NOTE 4)
3.20 – 3.45
(.12ꢀ – .13ꢀ)
4.90 0.152
(.193 .00ꢀ)
DETAIL “A”
0° – ꢀ° TYP
0.254
(.010)
GAUGE PLANE
0.ꢀ5
(.025ꢀ)
BSC
0.42 0.038
(.01ꢀ5 .0015)
TYP
1
2
3
4
0.53 0.152
(.021 .00ꢀ)
1.10
(.043)
MAX
0.8ꢀ
(.034)
REF
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
0.101ꢀ 0.0508
(.009 – .015)
(.004 .002)
0.ꢀ5
(.025ꢀ)
BSC
TYP
MSOP (MS8) 0213 REV G
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.00ꢀ") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6752fc
26
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
package DescripTion
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
SC6 Package
6-Lead Plastic SC70
(Reference LTC DWG # 05-08-1638 Rev B)
0.47
MAX
0.65
REF
1.80 – 2.20
(NOTE 4)
1.00 REF
INDEX AREA
(NOTE 6)
1.15 – 1.35
(NOTE 4)
1.80 – 2.40
2.8 BSC 1.8 REF
PIN 1
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.15 – 0.30
6 PLCS (NOTE 3)
0.65 BSC
0.10 – 0.40
0.80 – 1.00
0.00 – 0.10
REF
1.00 MAX
GAUGE PLANE
0.15 BSC
0.26 – 0.46
SC6 SC70 1205 REV B
0.10 – 0.18
(NOTE 3)
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE INDEX AREA
7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB
6752fc
27
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
package DescripTion
Please refer to http://www.linear.com/product/LTC6752#packaging for the most recent package drawings.
UD Package
12-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1855 Rev Ø)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
1.65 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ±0.05
3.00 ± 0.10
(4 SIDES)
11 12
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
1.65 ±0.10
(4-SIDES)
(UD12) QFN 0709 REV Ø
0.200 REF
0.25 ±0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6752fc
28
For more information www.linear.com/LTC6752
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/15 Addition of LTC6752-1 and LTC6752-4 options.
SC6 Package added.
All
2
Fast Event Capture added to Typical Applications.
24
B
C
06/15 Test condition for CMRR_LVCM updated: V = V – 0.2V to V – 1.5V
3, 6, 8
CM
EE
CC
Electrical Characteristics section updated to show that V
specified temperature range.
, R
, I
, I
specifications apply over the
5, 7, 9
LE/HYST HYST IH_LE IL_LE
Figure 1 updated to show hysteresis symbol.
16
20
The latched output disable description and Figure 7 corrected to show the latch to output delay (t ) instead of latch
PL
propagation delay (t ).
PDL
04/17 Addition of extended temperature range under Features
Addition of MP, extended temperature part
Addition of extended temperature range on Note 5
Updated web links
1
2, 3
9
25 to 28
6752fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
29
LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
Typical applicaTion
200MHz Clock Restoration/Level shifting
200MHz
CLOCK
SIGNAL
V
+ 5V
V
+ 1.8V
EE
EE
LONG
TRACE
V
CC
V
+ 1.8V
EE
V
, 500mV/DIV
, 50mV/DIV
OUT
CLOCK/DATA
SOURCE
+
V
DD
CLOCK/DATA
RECEIVER
LTC6752-2
~1.8V
P-P
V
= V + 2.5V
EE
200MHz,
CLOCK
–
REF
V
EE
V
V
ATTENUATED
150mV
REF
IN
V
EE
SIGNAL
P-P
200MHz,
= 2.5V
V
EE
V
6752 TA02a
CM
6752 TA02b
2ns/DIV
relaTeD parTs
PART NUMBER
High Speed Comparators
LT1715
DESCRIPTION
COMMENTS
4ns 150MHz Dual Comparators
4.6mA at 3V
LT1711
High Speed Rail-to-Rail Comparators
3V/5V/ 5V, 4.5ns at 20mV ꢀverdrive
2.7V/5V/ 5V, 7ns at 20mV ꢀverdrive
4mA/Comparator, 7ns at 5mV ꢀverdrive
6mA, 800μV ꢀffset
LT1713/LT1714
LT1719/LT1720
LT1394
Single/Dual Low Power Rail-to-Rail Comparators
Dual/Quad 4.5ns Rail-to-Rail ꢀutput Comparators
7ns Single Supply Ground Sensing Comparator
Clock Buffers/Logic Converters
LTC6957-1/LTC6957-2/ Low Phase Noise, Dual ꢀutput Buffer/Driver/Logic
LTC6957-3/LTC6957-4 Converter
LVPECL/LVDS/CMꢀS ꢀutputs, Additive Jitter 45f
(LTC6957-1)
sRMS
High Speed Operational Amplifiers
LTC6252/LTC6253/
LTC6254
Single/Dual/Quad 3.5mA 720MHz
Single/Dual/Quad 1mA, 180MHz
Single/Dual/Quad 65µA, 6.5MHz
18MHz, Low Noise, CMꢀS
280V/μs, 2.75nV/√Hz, Rail-to-Rail I/ꢀ
90V/μs, 4.2nV/√Hz,Rail-to-Rail I/ꢀ
LTC6246/LTC6247/
LTC6248
LTC6255/LTC6256/
LTC6257
LTC6240/LTC6241/
LTC6242
Rail-to-Rail ꢀutputs
LTC6406
LTC6409
3GHz, Differential Amplifier/Driver
Rail-to-Rail Inputs
10GHz Differential Amplifier/ADC Driver
1.1nV/√Hz
6752fc
LT 0417 REV C • PRINTED IN USA
www.linear.com/LTC6752
30
LINEAR TECHNOLOGY CORPORATION 2014
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