LTC6991CS6#TRMPBF [Linear]
LTC6991 - TimerBlox: Resettable, Low Frequency Oscillator; Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C;
| 型号： | LTC6991CS6#TRMPBF |
| 厂家： | 
Linear |
| 描述： | LTC6991 - TimerBlox: Resettable, Low Frequency Oscillator; Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C 机械 输出元件 振荡器 |
| 文件： | 总24页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6991
TimerBlox: Resettable, Low
Frequency Oscillator
FEATURES
DESCRIPTION
The LTC®6991 is a silicon oscillator with a program-
mable period range of 1.024ms to 9.54 hours (29.1µHz
to 977Hz), specifically intended for long duration timing
events. The LTC6991 is part of the TimerBlox® family of
versatile silicon timing devices.
n
Period Range: 1ms to 9.5 Hours
n
Configured with 1 to 3 Resistors
n
<1.5% Maximum Frequency Error
n
Output Reset Function
n
2.25V to 5.5V Single Supply Operation
n
55µA to 80µA Supply Current
A single resistor, R , programs the LTC6991’s inter
-
SET
n
(2ms to 9.5hr Clock Period)
nal master oscillator frequency. The output clock period
n
500µs Start-Up Time
is determined by this master oscillator and an internal
n
CMOS Output Driver Sources/Sinks 20mA
frequency divider, N , programmable to eight settings
DIV
n
–55°C to 125°C Operating Temperature Range
21
from 1 to 2 .
n
Available in Low Profile (1mm) SOT-23 (ThinSOT™)
NDIV •RSET
and 2mm × 3mm DFN Packages
tOUT
=
•1.024ms, NDIV = 1,8,64,...,221
50kΩ
APPLICATIONS
In normal operation, the LTC6991 oscillates with a 50%
duty cycle. A reset function is provided to truncate the
pulse (reducing the duty cycle). The reset pin can also be
used to prevent the output from oscillating.
n
“Heartbeat” Timers
n
Watchdog Timers
n
Intervalometers
Periodic “Wake-Up” Call
High Vibration, High Acceleration Environments
Portable and Battery-Powered Equipment
n
The RST and OUT pins can be configured for active-low
or active-high operation using a polarity function.
n
n
POL BIT
RST PIN
OUTPUT STATE
Oscillating
0 (reset)
1 (reset)
Oscillating
0
0
1
1
0
1
0
1
All registered trademarks and trademarks are the property of their respective owners.
For easy configuration of the LTC6991, download the
TimerBlox Designer tool at www.linear.com/timerblox.
Clock Period Range over Eight Divider Settings
1ꢎꢟꢠ
TYPICAL APPLICATION
Low Frequency Pulse Generator
1ꢟꢠ
1ꢎꢔꢕꢖ
1µs PULSE WIDTH
OUT
60 SECONDS
R
PW
1ꢔꢕꢖ
2.26k
1ꢎꢒꢓc
RST
GND
SET
OUT
6991 TA01a
C
PW
LTC6991
5V
1ꢒꢓc
1ꢎꢎꢛꢜ
1ꢎꢛꢜ
1ꢛꢜ
470pF
+
V
0.1µF
R1
R
SET
1M
715k
DIV
R2
392k
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1ꢘꢝꢞꢙ
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t
≈ R • C ≈ 1µs
6991 ꢇꢈꢎ1ꢚ
PULSE
PW
PW
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6991fc
1
For more information www.linear.com/LTC6991
LTC6991
ABSOLUTE MAXIMUM RATINGS (Note 1)
+
Supply Voltage (V ) to GND ........................................6V
Specified Temperature Range (Note 3)
Maximum Voltage
LTC6991C ................................................ 0°C to 70°C
LTC6991I .............................................–40°C to 85°C
LTC6991H.......................................... –40°C to 125°C
LTC6991MP ....................................... –55°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
+
on Any Pin ................(GND – 0.3V) ≤ V ≤ (V + 0.3V)
PIN
Operating Temperature Range (Note 2)
LTC6991C ............................................–40°C to 85°C
LTC6991I .............................................–40°C to 85°C
LTC6991H.......................................... –40°C to 125°C
LTC6991MP ....................................... –55°C to 125°C
S6 Package...........................................................300°C
PIN CONFIGURATION
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TOP VIEW
ꢍ
6
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ꢃ
1
ꢕ
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RST 1
GND 2
SET 3
6 OUT
ꢜ
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ꢌꢅꢀ
+
5 V
4 DIV
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S6 PACKAGE
6-LEAD PLASTIC TSOT-23
T
JMAX
= 150°C, θ = 192°C/W, θ = 51°C/W
T
= 150°C, θ = 64°C/W, θ = 10.6°C/W
JA
JC
JMAX
JA
JC
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
ORDER INFORMATION
http://www.linear.com/product/LTC6991#orderinfo
Lead Free Finish
TAPE AND REEL (MINI)
LTC6991CDCB#TRMPBF
LTC6991IDCB#TRMPBF
LTC6991HDCB#TRMPBF
LTC6991CS6#TRMPBF
LTC6991IS6#TRMPBF
LTC6991HS6#TRMPBF
LTC6991MPS6#TRMPBF
TAPE AND REEL
PART MARKING*
LDWZ
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
LTC6991CDCB#TRPBF
LTC6991IDCB#TRPBF
LTC6991HDCB#TRPBF
LTC6991CS6#TRPBF
LTC6991IS6#TRPBF
LTC6991HS6#TRPBF
LTC6991MPS6#TRPBF
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
LDWZ
–40°C to 85°C
LDWZ
–40°C to 125°C
0°C to 70°C
LTDWY
LTDWY
6-Lead Plastic TSOT-23
–40°C to 85°C
LTDWY
6-Lead Plastic TSOT-23
–40°C to 125°C
–55°C to 125°C
LTDWY
6-Lead Plastic TSOT-23
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult ADI Marketing for parts specified with wider operating temperature ranges.
Consult ADI Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
6991fc
2
For more information www.linear.com/LTC6991
LTC6991
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
1.024m
29.1µ
TYP
MAX
34,360
977
UNITS
Seconds
Hz
t
f
Output Clock Period
Output Frequency
OUT
OUT
∆f
Frequency Accuracy (Note 4)
29.1µHz ≤ f
≤ 977Hz
OUT
0.8
1.5
2.2
%
%
OUT
l
l
∆f /∆T
Frequency Drift Over Temperature
Frequency Drift Over Supply
0.005
%/°C
OUT
+
+
l
l
∆f /∆V
V = 4.5V to 5.5V
0.23
0.06
0.55
0.16
%/V
%/V
OUT
+
V = 2.25V to 4.5V
Long-Term Frequency Stability
Period Jitter (Note 10)
(Note 11)
90
ppm/√kHr
N
N
= 1
= 8
15
7
ppm
ppm
DIV
DIV
RMS
RMS
BW
Frequency Modulation Bandwidth
0.4 • f
Hz
OUT
t
Frequency Change Settling Time (Note 9)
1
Cycle
S
Analog Inputs
l
l
l
l
l
V
Voltage at SET Pin
0.97
1.00
75
1.03
800
V
µV/°C
kΩ
SET
∆V /∆T
V
Drift Over Temperature
SET
SET
R
Frequency-Setting Resistor
DIV Pin Voltage
50
0
SET
DIV
+
V
V
V
+
∆V /∆V
DIV Pin Valid Code Range (Note 5)
Deviation from Ideal
DIV
1.5
%
DIV
+
V
/V = (DIVCODE + 0.5)/16
l
DIV Pin Input Current
10
nA
Power Supply
+
l
l
V
Operating Supply Voltage Range
Power-On Reset Voltage
Supply Current
2.25
5.5
V
V
1.95
+
+
l
l
I
R = ∞, R = 50k
V = 5.5V
135
105
170
135
µA
µA
S
L
SET
V = 2.25V
+
+
l
l
R = ∞, R = 100k
V = 5.5V
100
80
130
105
µA
µA
L
SET
V = 2.25V
+
+
l
l
R = ∞, R = 800k
V = 5.5V
65
55
100
85
µA
µA
L
SET
V = 2.25V
6991fc
3
For more information www.linear.com/LTC6991
LTC6991
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital I/O
RST Pin Input Capacitance
RST Pin Input Current
2.5
pF
nA
V
+
RST = 0V to V
(Note 6)
10
+
l
l
V
V
High Level RST Pin Input Voltage
Low Level RST Pin Input Voltage
Output Current
0.7 • V
IH
+
(Note 6)
+
0.3 • V
V
IL
I
V = 2.7V to 5.5V
20
mA
OUT(MAX)
+
l
l
V
High Level Output Voltage (Note 7)
V = 5.5V
I
I
= –1mA
5.45
4.84
5.48
5.15
V
V
OH
OUT
OUT
= –16mA
+
l
l
V = 3.3V
I
I
= –1mA
= –10mA
3.24
2.75
3.27
2.99
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= –1mA
= –8mA
2.17
1.58
2.21
1.88
V
V
OUT
OUT
+
l
l
V
OL
Low Level Output Voltage (Note 7)
Reset Propagation Delay
V = 5.5V
I
I
= 1mA
= 16mA
0.02
0.26
0.04
0.54
V
V
OUT
OUT
+
l
l
V = 3.3V
I
I
= 1mA
= 10mA
0.03
0.22
0.05
0.46
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= 1mA
= 8mA
0.03
0.26
0.07
0.54
V
V
OUT
OUT
+
t
V = 5.5V
16
24
40
ns
ns
ns
RST
+
V = 3.3V
+
V = 2.25V
+
t
t
Minimum Input Pulse Width
Output Rise Time (Note 8)
V = 3.3V
5
ns
WIDTH
r
+
V = 5.5V
1.1
1.7
2.7
ns
ns
ns
+
V = 3.3V
+
V = 2.25V
+
t
Output Fall Time (Note 8)
V = 5.5V
1.0
1.6
2.4
ns
ns
ns
f
+
V = 3.3V
+
V = 2.25V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 2: The LTC6991C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 9: Settling time is the amount of time required for the output to settle
Note 3: The LTC6991C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6991C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6991I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6991H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC6991MP is
guaranteed to meet specified performance from –55°C to 125°C.
within 1% of the final frequency after a 0.5× or 2× change in I
.
SET
Note 10: Jitter is the ratio of the deviation of the period to the mean of the
period. This specification is based on characterization and is not 100%
tested.
Note 11: Long-term drift of silicon oscillators is primarily due to the
movement of ions and impurities within the silicon and is tested at 30°C
under otherwise nominal operating conditions. Long-term drift is specified
as ppm/√kHr due to the typically nonlinear nature of the drift. To calculate
drift for a set time period, translate that time into thousands of hours, take
the square root and multiply by the typical drift number. For instance, a
year is 8.77kHr and would yield a drift of 266ppm at 90ppm/√kHr. Drift
without power applied to the device may be approximated as 1/10th of the
drift with power, or 9ppm/√kHr for a 90ppm/√kHr device.
Note 4: Frequency accuracy is defined as the deviation from the f
OUT
equation, assuming R is used to program the frequency.
SET
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: The RST pin has hysteresis to accommodate slow rising or falling
+
signals. The threshold voltages are proportional to V . Typical values can
+
be estimated at any supply voltage using V
≈ 0.55 • V + 185mV
RST(RISING)
+
and V
≈ 0.48 • V – 155mV.
RST(FALLING)
6991fc
4
For more information www.linear.com/LTC6991
LTC6991
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Frequency Error vs Temperature
Frequency Error vs Temperature
Frequency Error vs Temperature
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1
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Frequency Error vs RSET
Frequency Drift vs Supply Voltage
Typical VSET Distribution
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GUARANTEED MAX OVER TEMPERATURE
3 PARTS
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–2
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GUARANTEED MIN OVER TEMPERATURE
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200
400
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600
800
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6991 ꢌꢆ6
6991 G04
6991 ꢉꢏꢑ
VSET Drift vs ISET
VSET Drift vs Supply
VSET vs Temperature
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6991fc
5
For more information www.linear.com/LTC6991
LTC6991
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Supply Current
vs RST Pin Voltage
Supply Current vs Supply Voltage
Supply Current vs Temperature
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ꢕꢈꢈ
1ꢔꢈ
1ꢈꢈ
ꢔꢈ
1ꢔꢎ
1ꢍꢔ
1ꢌꢍ
1ꢕꢌ
1ꢍꢍ
ꢖꢌ
ꢁ
ꢝ ꢗꢈꢈꢞ
ꢂꢌꢃ
ꢐ
ꢘ ꢔꢎꢙ
ꢀꢊꢇ
ꢔꢀ
ꢔꢀ
ꢁꢂꢃ ꢚꢓꢎꢎꢛꢑꢘ
ꢁꢂꢃ ꢁꢛꢂꢛꢑꢘ
ꢌꢘꢙ ꢄ
ꢚ 1ꢍꢍꢛ
ꢐꢁꢀ
1ꢎꢎ
ꢕꢔ
ꢐ
ꢀꢊꢇ
ꢘ 1ꢎꢎꢙ
ꢕꢜꢌꢘꢙ ꢄ
ꢚ 1ꢍꢍꢛ
ꢐꢁꢀ
ꢐ
ꢐ
ꢘ ꢍꢎꢎꢙ
ꢘ ꢚꢎꢎꢙ
ꢀꢊꢇ
ꢜꢖꢜꢀ
ꢜꢖꢜꢀ
ꢁꢂꢃ ꢁꢛꢂꢛꢑꢘ
ꢌꢘꢙ ꢄ
ꢚ ꢝꢍꢍꢛ
ꢚ ꢝꢍꢍꢛ
ꢐꢁꢀ
ꢁꢂꢃ ꢚꢓꢎꢎꢛꢑꢘ
ꢀꢊꢇ
ꢔꢎ
ꢍꢔ
ꢎ
ꢕꢜꢌꢘꢙ ꢄ
ꢌꢍ
ꢕꢌ
ꢍ
ꢐꢁꢀ
ꢈ
ꢈ
ꢈꢖꢕ
ꢈꢖꢙ
ꢈꢖ6
ꢈꢖꢗ
1ꢖꢈ
ꢍ
ꢖ
ꢗ
ꢔ
6
ꢌꢍ
ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ
1ꢍꢍ 1ꢕꢌ
ꢋꢌꢍ ꢋꢕꢌ
ꢍ
ꢕꢌ
ꢖꢌ
ꢅ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
ꢀ
ꢄꢀ ꢆꢀꢄꢀꢇ
ꢁꢂꢃ
6991 ꢘ1ꢕ
6991 ꢉ1ꢎ
6991 ꢗ11
RST Threshold Voltage
vs Supply Voltage
Supply Current vs RSET
Typical ISET Current Limit vs V+
1ꢐꢐꢐ
ꢒꢐꢐ
6ꢐꢐ
ꢑꢐꢐ
ꢓꢐꢐ
ꢐ
ꢑꢒꢓ
ꢑꢒꢔ
ꢕꢒꢓ
ꢕꢒꢔ
1ꢒꢓ
1ꢒꢔ
ꢔꢒꢓ
ꢔ
150
125
ꢀꢊꢇ ꢂꢍꢕ ꢀꢖꢆꢗꢇꢊꢘ ꢇꢆ ꢉꢕꢘ
+
ꢂꢆꢀꢎꢇꢎꢅꢊꢖꢉꢆꢎꢏꢉ
V
= 5V
100
75
+
V
= 3.3V
= 2.5V
ꢏꢊꢉꢈꢇꢎꢅꢊꢖꢉꢆꢎꢏꢉ
+
V
50
25
0
ꢓ
ꢔ
ꢑ
ꢏ
6
ꢕ
ꢑ
ꢐ
ꢓ
6
0
200
400
(kΩ)
600
800
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
R
SET
6991 ꢉ1ꢏ
6991 ꢉ1ꢐ
6991 G13
Reset Propagation Delay (tRST
)
Rise and Fall Time
vs Supply Voltage
Typical Frequency Error
vs Time (Long-Term Drift)
vs Supply Voltage
ꢕꢎ
ꢗꢕ
ꢗꢎ
ꢖꢕ
ꢖꢎ
ꢍꢕ
ꢍꢎ
1ꢕ
1ꢎ
ꢕ
ꢕꢖꢗ
ꢙꢖꢘ
ꢙꢖꢗ
1ꢖꢘ
1ꢖꢗ
ꢗꢖꢘ
ꢗ
ꢙꢗꢗ
1ꢖꢗ
1ꢗꢗ
ꢖꢗ
ꢘ
ꢙ ꢕꢚꢛ
6ꢖ ꢍꢎꢁꢀꢜ
ꢛ
ꢝ ꢘꢞꢐ
ꢃꢆꢈꢒ
ꢃꢆꢈꢜ
ꢜꢝꢀꢞꢙꢟ ꢉꢎꢇ ꢇꢊꢎ ꢠꢉꢋꢀꢜ
ꢀ
ꢡ ꢟꢗꢢꢏ
ꢉ
ꢟ
ꢍꢎꢀꢊ
ꢗ
ꢘꢖꢗ
ꢟ
ꢐꢈꢃꢃ
ꢘ1ꢗꢗ
ꢘ1ꢖꢗ
ꢘꢙꢗꢗ
ꢎ
ꢍ
ꢖ
ꢗ
ꢕ
6
ꢙ
ꢕ
ꢚ
ꢘ
6
ꢗ
ꢚꢗꢗ ꢛꢗꢗ 1ꢙꢗꢗ 16ꢗꢗ ꢙꢗꢗꢗ ꢙꢚꢗꢗ ꢙꢛꢗꢗ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃ ꢄꢅꢆ
6991 ꢉ1ꢔ
6991 ꢓ1ꢔꢕ
6991 ꢉ16
6991fc
6
For more information www.linear.com/LTC6991
LTC6991
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Output Resistance
vs Supply Current
50
Typical Start-Up with POL = 1
45
40
ꢁ
ꢀ
35
30
25
20
15
10
5
1ꢀꢂꢃꢄꢀ
OUTPUT SOURCING CURRENT
1ꢋꢌ ꢕꢖ
ꢙ ꢚꢄꢃꢐ
ꢗꢘꢒꢇꢐꢑ
ꢄꢛꢄꢇꢄꢘꢜ ꢝꢆꢜꢒꢐ
ꢉꢊꢊꢋꢌ
ꢅꢆꢇ
1ꢀꢂꢃꢄꢀ
OUTPUT SINKING CURRENT
0
ꢁ
6991 ꢔ19
ꢀ
ꢍ ꢈꢎꢉꢀ
ꢃꢄꢀꢏꢅꢃꢐ ꢍ 1ꢉ
ꢑ ꢍ ꢉꢊꢓ
ꢒꢐꢇ
ꢈꢉꢊꢋꢌꢂꢃꢄꢀ
2
3
4
5
6
SUPPLY VOLTAGE (V)
6991 G22
PIN FUNCTIONS (DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This
supply should be kept free from noise and ripple. It should
be bypassed directly to the GND pin with a 0.1µF capacitor.
and 50ppm/°C or better temperature coefficient. For lower
accuracy applications an inexpensive 1% thick film resis
-
tor may be used.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
+
Input. A V referenced A/D converter monitors the DIV
pin voltage (V ) to determine a 4-bit result (DIVCODE).
DIV
+
V
may be generated by a resistor divider between V
regulating the V voltage.
DIV
SET
and GND. Use 1% resistors to ensure an accurate result.
The DIV pin and resistors should be shielded from the
OUT pin or any other traces that have fast edges. Limit
the capacitance on the DIV pin to less than 100pF so that
ꢎ
ꢍ
ꢅꢆꢃ
ꢋꢌꢃ
ꢂꢃꢄ6991
ꢎ
ꢍ
ꢎ
ꢇꢈꢉ
ꢆꢊꢃ
ꢍ
V
settles quickly. The MSB of DIVCODE (POL) deter-
DIV
ꢄ1
ꢐꢑ1ꢒꢁ
ꢅ1
ꢅꢓ
mines the polarity of the RST and OUT pins. If POL = 0,
RST is active-high, and forces OUT low. If POL = 1, RST
is active-low and forces OUT high.
ꢉꢏꢍ
6991 ꢀꢁ
ꢅ
ꢆꢊꢃ
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (V ) is regulated to 1V above GND. The
SET
RST (Pin 4/Pin 1): Output Reset. The behavior of the RST
pin is dependent on the polarity bit (POL). The POL bit is
configured via the DIVCODE setting. When POL = 0, set-
ting RST high forces OUT low and setting RST low allows
the output to oscillate. When POL = 1, RST is active low.
In that case, setting RST low forces OUT high and setting
RST high allows the output to oscillate.
amount of current sourced from the SET pin (I ) pro-
SET
grams the master oscillator frequency. The I
current
SET
range is 1.25µA to 20µA. The output oscillation will stop
if I drops below approximately 500nA. A resistor con-
SET
nected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance
6991fc
7
For more information www.linear.com/LTC6991
LTC6991
PIN FUNCTIONS (DCB/S6)
GND (Pin 5/Pin 2): Ground. Tie to a low inductance
ground plane for best performance.
30Ω. When driving an LED or other low impedance load
a series output resistor should be used to limit source/
sink current to 20mA.
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
from GND to V+ with an output resistance of approximately
(S6 package pin numbers shown)
BLOCK DIAGRAM
5
+
V
R1
POL BIT
DIV
4-BIT A/D
CONVERTER
DIGITAL
FILTER
4
R2
OUT
OUTPUT
POLARITY
6
+
V
t
OUT
MASTER OSCILLATOR
D
Q
1µs
V
SET
FIXED
DIVIDER
÷ 1024
MCLK
=
t
=
PROGRAMMABLE
DIVIDER
MASTER
50kΩ
I
SET
R
÷1, 8, 64, 512
15 18 21
4096, 2 , 2 , 2
INPUT
POLARITY
HALT OSCILLATOR
IF I < 500nA
POR
SET
I
SET
+
–
+
–
1V
GND
V
SET
= 1V
RST
1
SET
3
2
6991 BD
I
SET
R
SET
6991fc
8
For more information www.linear.com/LTC6991
LTC6991
OPERATION
The LTC6991 is built around a master oscillator with a
DIVCODE
1MHz maximum frequency. The oscillator is controlled
+
The DIV pin connects to an internal, V referenced 4-bit
A/D converter that determines the DIVCODE value.
DIVCODE programs two settings on the LTC6991:
by the SET pin current (I ) and voltage (V ), with a
SET
SET
1MHz • 50k conversion factor that is accurate to 0.8%
under typical conditions.
1. DIVCODE determines the output frequency divider set-
1
I
SET
ting, N
.
f
=
= 1MHz • 50kΩ •
DIV
MASTER
t
V
SET
MASTER
2. DIVCODE determines the polarity of the RST and OUT
pins, via the POL bit.
A feedback loop maintains V at 1V 30mV, leaving I
as the primary means of conStrEoTlling the output frequency.
The simplest way to generate I is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET
The master oscillator equation reduces to:
SET
+
V
may be generated by a resistor divider between V
DIV
SET
and GND as shown in Figure 1.
.
ꢌꢍꢌꢎꢅ ꢃꢏ ꢎꢍꢎꢅ
ꢆ
ꢅ
1
1MHz • 50kΩ
ꢂꢃꢄ6991
ꢋ1
ꢋꢌ
f
=
=
MASTER
t
R
SET
MASTER
ꢇꢈꢅ
From this equation, it is clear that V drift will not affect
SET
ꢉꢊꢇ
the output frequency when using a single program resis-
tor (RSET). Error sources are limited to RSET tolerance and
6991 ꢀꢁ1
the inherent frequency accuracy ∆f
of the LTC6991.
Figure 1. Simple Technique for Setting DIVCODE
OUT
RSET may range from 50k to 800k (equivalent to ISET
between 1.25µA and 20µA).
Table 1 offers recommended 1% resistor values that accu-
rately produce the correct voltage division as well as the
corresponding NDIV and POL values for the recommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to 1.5% (including resis-
tor tolerances and temperature effects)
Before reaching the OUT pin, the oscillator frequency
passes through a fixed ÷1024 divider. The LTC6991
also includes a programmable frequency divider which
can further divide the frequency by 1, 8, 64, 512, 4096,
15 18
21
2 , 2 or 2 . The divider ratio N is set by a resistor
DIV
divider attached to the DIV pin.
2. The driving impedance (R1||R2) does not exceed
500kΩ.
1MHz • 50kΩ
I
SET
f
=
=
•
, or
OUT
If the voltage is generated by other means (i.e., the output
of a DAC) it must track the V+ supply voltage. The last
1024 • N
V
SET
DIV
1
N
V
SET
column in Table 1 shows the ideal ratio of V to the
DIV
DIV
t
=
•
• 1.024ms
OUT
supply voltage, which can also be calculated as:
f
50kΩ
I
SET
OUT
V
DIVCODE + 0.5
DIV
with R in place of V /I the equation reduces to:
=
± 1.5%
SET
SET SET
+
V
16
N
DIV
• R
SET
t
=
• 1.024ms
OUT
For example, if the supply is 3.3V and the desired DIVCODE
is 4, V = 0.281 • 3.3V = 928mV 50mV.
50kΩ
DIV
Figure 2 illustrates the information in Table 1, showing
that N is symmetric around the DIVCODE midpoint.
DIV
6991fc
9
For more information www.linear.com/LTC6991
LTC6991
OPERATION
Table 1. DIVCODE Programming
+
DIVCODE
POL
0
N
RECOMMENDED t
R1 (kΩ)
Open
976
R2 (kΩ)
Short
102
V
/V
DIV
DIV
OUT
0
1
1
1.024ms to 16.384ms
8.192ms to 131ms
65.5ms to 1.05sec
524ms to 8.39sec
4.19sec to 67.1sec
33.6sec to 537sec
268sec to 4,295sec
2,147sec to 34,360sec
2,147sec to 34,360sec
268sec to 4,295sec
33.6sec to 537sec
4.19sec to 67.1sec
524ms to 8.39sec
65.5ms to 1.05sec
8.192ms to 131ms
1.024ms to 16.384ms
≤0.03125 0.015
0.09375 0.015
0.15625 0.015
0.21875 0.015
0.28125 0.015
0.34375 0.015
0.40625 0.015
0.46875 0.015
0.53125 0.015
0.59375 0.015
0.65625 0.015
0.71875 0.015
0.78125 0.015
0.84375 0.015
0.90625 0.015
≥0.96875 0.015
0
8
2
0
64
512
976
182
3
0
1000
1000
1000
1000
1000
887
280
4
0
4,096
32,768
262,144
2,097,152
2,097,152
262,144
32,768
4,096
512
392
5
0
523
6
0
681
7
0
887
8
1
1000
1000
1000
1000
1000
976
9
1
681
10
11
12
13
14
15
1
523
1
392
1
280
1
64
182
1
8
102
976
1
1
Short
Open
ꢗꢇꢘ ꢙꢓꢉ ꢚ ꢀ
ꢗꢇꢘ ꢙꢓꢉ ꢚ 1
1ꢀꢀꢀꢀ
1ꢀꢀꢀ
1ꢀꢀ
1ꢀ
ꢝ
ꢞ
6
9
ꢂ
1ꢀ
11
ꢜ
1ꢒ
ꢛ
1
ꢒ
1ꢛ
ꢀꢁ1
1
1ꢜ
ꢀꢁꢀ1
ꢀꢁꢀꢀ1
ꢀ
1ꢂ
ꢅ
ꢅ
ꢀꢄ
ꢀꢁꢂꢃꢄ
ꢄ
ꢓꢎꢍꢔꢌꢕꢋꢓꢎꢖ ꢄ
ꢏꢓꢄ
6991 ꢑꢀꢒ
Figure 2. Frequency Range and POL Bit vs DIVCODE
6991fc
10
For more information www.linear.com/LTC6991
LTC6991
OPERATION
RST Pin and Polarity (POL) Bit
If POL = 0, the reset pin is active high and the output latch
is not inverted. Therefore, pulling the RST pin high will
reset the output latch and force the OUT pin low. Pulling
RST low will allow the output to oscillate, with the next
rising edge dependent on the internal oscillator.
The RST pin controls the state of the LTC6991’s output
as seen on the OUT pin. The active/inactive voltage levels
depend on the POL bit setting.
Table 2. Output States
If POL = 1, the reset pin is active low and the output latch
is inverted. Therefore, pulling the RST pin low will reset
the output latch and force the OUT pin high. Pulling RST
high will allow the output to oscillate, with the next falling
edge dependent on the internal oscillator.
POL BIT
RST PIN
OUTPUT STATE
Oscillating
0 (reset)
0
0
1
1
0
1
0
1
1 (reset)
Oscillating
Note that the master oscillator frequency and phase are
not affected by the RST pin; The LTC6991 continues to
oscillate, internally, even when RST is active. While the
reset function can block an output pulse, its exact place-
ment in time can only be changed by power cycling the
LTC6991.
Each period of the LTC6991’s internal oscillator clocks
the output state latch (see Block Diagram). The reset pin
(RST) can reset or hold off the output latch. The active
state of the reset pin is determined by the polarity func-
tion (POL). Similarly, the output latch is followed by a
buffer that can invert the output. The output polarity is
also controlled by the POL bit.
ꢀ
ꢆꢇꢈꢃꢉ
ꢄꢅꢃ
ꢁꢂꢃ
ꢇꢊꢃꢋꢄꢊꢌꢍ
ꢁꢅꢎꢇꢍꢍꢌꢃꢁꢄ
ꢀ
ꢄꢅꢃ
6991 ꢏꢐꢑ
ꢀ
ꢁꢂꢃ
Figure 3. RST Timing Diagram (POL = 0)
ꢄꢅꢃ
ꢁꢂꢃ
ꢀ
ꢄꢅꢃ
6991 ꢌꢍꢎ
ꢆꢇꢃꢈꢄꢇꢉꢊ
ꢁꢅꢋꢆꢊꢊꢉꢃꢁꢄ
ꢀ
ꢁꢂꢃ
Figure 4. RST Timing Diagram (POL = 1)
6991fc
11
For more information www.linear.com/LTC6991
LTC6991
OPERATION
Changing DIVCODE After Start-Up
The start-up time may increase if the supply or DIV pin
voltages are not stable. For this reason, it is recommended
to minimize the capacitance on the DIV pin so it will prop-
Following start-up, the A/D converter will continue moni-
toring V
for changes. The LTC6991 will respond to
DIV
+
erly track V . Less than 100pF will not affect performance.
DIVCODE changes in less than one cycle.
t
< 500 • t < t
Start-Up Behavior
DIVCODE
MASTER
OUT
The output may have an inaccurate pulse width during the
frequency transition. But the transition will be glitch-free
and no high or low pulse can be shorter than the mas-
ter clock period. A digital filter is used to guarantee the
DIVCODE has settled to a new value before making
changes to the output.
When first powered up, the output is held low. If the polar-
ity is set for non-inversion (POL = 0) and the output is
enabled (RST = 0) at the end of the start-up time, OUT will
begin oscillating. If the output is being reset (RST = 1) at
the end of the start-up time, the first pulse will be skipped.
Subsequent pulses will also be skipped until RST = 0.
In inverted operation (POL = 1), the start-up sequence is
similar. However, the LTC6991 does not know the correct
DIVCODE setting when first powered up, so the output
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, t
. The OUT pin
defaults low. At the end of t
, the value of DIVCODE
START
START
is held low during this time. The typical value for t
is recognized and OUT goes high (inactive) because
POL = 1. If RST = 1 (inactive) then OUT will quickly fall
START
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of N ):
after a single t
cycle. If RST = 0 at the end of the
DIV
MASTER
start-up time, the output is held in reset and remains high.
t
= 500 • t
MASTER
START(TYP)
Figures7to10detailthefourpossiblestart-upsequences.
During start-up, the DIV pin A/D converter must deter-
mine the correct DIVCODE before the output is enabled.
ꢀꢁꢂ
ꢃꢄꢄꢅꢂꢆꢀꢁꢂ
ꢁ
ꢀ
1ꢀꢂꢃꢄꢀ
ꢉꢊꢊꢋꢌ
ꢇꢈꢉ
1ꢂꢆꢀꢁꢂ
ꢅꢆꢇ
1ꢀꢂꢃꢄꢀ
ꢍ
ꢁ
6991 ꢋꢄꢌ
6991 ꢍꢊ6
ꢂ
ꢑ
ꢎ ꢏꢐꢏꢂ
ꢎ ꢃꢄꢄꢔ
1ꢄꢅꢊꢆꢀꢁꢂ
ꢀ
ꢎ ꢈꢏꢉꢀ
ꢈꢉꢊꢋꢌꢂꢃꢄꢀ
ꢃꢄꢀꢐꢅꢃꢑ ꢎ ꢊ
ꢎ ꢉꢊꢔ
ꢒꢓꢉ
ꢒ
ꢓꢑꢇ
Figure 5. DIVCODE Change from 1 to 0
Figure 6. Typical Start-Up
6991fc
12
For more information www.linear.com/LTC6991
LTC6991
OPERATION
ꢆꢄꢃ
ꢁꢂꢃ
6991 ꢍꢑꢒ
ꢀ
ꢀ
ꢁꢂꢃ
ꢄꢃꢅꢆꢃ
Figure 7. Start-Up Timing Diagram (RST = 0, POL = 0)
ꢆꢄꢃ
ꢁꢂꢃ
6991 ꢍꢑꢓ
ꢀ
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ꢉꢎꢃꢌꢏꢌꢆ ꢐꢂꢋꢃꢉꢇꢋꢌ ꢁꢍ ꢀ
ꢄꢃꢅꢆꢃ
ꢁꢂꢃ
Figure 8. Start-Up Timing Diagram (RST = 1, POL = 0)
ꢆꢄꢃ
ꢁꢂꢃ
6991 ꢍꢑ9
ꢀ
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ꢉꢎꢃꢌꢏꢌꢆ ꢐꢂꢋꢃꢉꢇꢋꢌ ꢁꢍ ꢀ
ꢄꢃꢅꢆꢃ
ꢁꢂꢃ
ꢀ
ꢐꢅꢄꢃꢌꢆ
Figure 9. Start-Up Timing Diagram (RST = 0, POL = 1)
ꢆꢄꢃ
ꢁꢂꢃ
6991 ꢍ1ꢑ
ꢀ
ꢀ
ꢁꢂꢃ
ꢄꢃꢅꢆꢃ
ꢀ
ꢐꢅꢄꢃꢌꢆ
Figure 10. Start-Up Timing Diagram (RST = 1, POL = 1)
6991fc
13
For more information www.linear.com/LTC6991
LTC6991
APPLICATIONS INFORMATION
Basic Operation
Example: Design a 1Hz oscillator with minimum power
consumption and active-high reset input.
The simplest and most accurate method to program the
LTC6991 is to use a single resistor, R , between the SET
Step 1: Select the POL Bit Setting
SET
and GND pins. The design procedure is a 3-step process.
For noninverted (active-high) functionality, choose
POL = 0.
First select the POL bit setting and N value, then cal-
DIV
culate the value for the R resistor.
SET
Step 2: Select the N Frequency Divider Value
Alternatively, Linear Technology offers the easy to use
TimerBlox Designer tool to quickly design any LTC6991
based circuit. Download the free TimerBlox Designer soft-
ware at www.linear.com/timerblox.
DIV
Choose an NDIV value that meets the requirements of
Equation (1), using t
= 1000ms:
OUT
61.04 ≤ N ≤ 976.6
DIV
Step 1: Select the POL Bit Setting
Potential settings for NDIV include 64 and 512. NDIV
64 is the best choice, as it minimizes supply current
by using a large R resistor. POL = 0 and N = 64
=
The LTC6991 can operate in normal (active-high) or
inverted (active-low) modes, depending on the set-
ting of the POL bit. The best choice depends on the the
application.
SET
DIV
requires DIVCODE = 2. Using Table 1, choose R1 = 976k
and R2 = 182k values to program DIVCODE = 2.
Step 3: Select R
Step 2: Select the N Frequency Divider Value
SET
DIV
Calculate the correct value for R using Equation (2).
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the NDIV
SET
50k
1000ms
64
R
=
SET
•
= 763k
value. For a given output clock period, N should be
DIV
1.024ms
selected to be within the following range.
Since 763k is not available as a standard 1% resistor,
substitute 768k if a –0.7% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 576k + 187k to attain a more precise resistance.
t
t
OUT
OUT
≤ N
≤
DIV
(1)
16.384ms
1.024ms
To minimize supply current, choose the lowest N value
(generally recommended). Alternatively, useDITVable 1
as a guide to select the best N
application.
The completed design is shown in Figure 11.
value for the given
DIV
With POL already chosen, this completes the selection of
ꢋꢌꢊ
ꢋꢌꢊ
ꢍꢎꢀ
ꢌꢅꢊ
ꢄꢏꢊ
ꢉꢊꢃ6991
ꢇꢕꢇꢖꢂ ꢊꢄ ꢖꢕꢖꢂ
DIVCODE. Use Table 1 to select the proper resistor divider
+
ꢐ
or V /V ratio to apply to the DIV pin.
ꢂ
DIV
ꢋ1
9ꢑ6ꢒ
Step 3: Calculate and Select R
SET
ꢀꢁꢂꢃꢄꢀꢅ ꢆ ꢇ
ꢋꢇ
1ꢓꢇꢒ
ꢀꢁꢂ
ꢋ
ꢑ6ꢔꢒ
ꢌꢅꢊ
The final step is to calculate the correct value for R
using the following equation.
SET
6991 ꢈ11
Figure 11. 1Hz Oscillator
50k
t
OUT
R
=
•
SET
(2)
1.024ms N
DIV
Select the standard resistor value closest to the calculated
value.
6991fc
14
For more information www.linear.com/LTC6991
LTC6991
APPLICATIONS INFORMATION
LTC6991 as “Wake-Up Timer”
input to filter start-up glitches from the system as it is
powered on.
The output latch reset function provided by the RST pin
allows the LTC6991 to enable a larger system at regular
intervals. The on-time can be controlled by the system.
This allows the system to shut itself down immediately
after performing its tasks, reducing power consumption.
If the LTC6991 is enabling a switching regulator that can
operate on supplies greater than 5.5V, it will be neces-
sary to limit the supply voltage provided to the LTC6991.
If the LTC6991 output is not heavily loaded, and if a large
R
resistor is used, the supply current will not be much
laSrgETer than 100µA, so a simple regulator circuit can be
constructed using a Zener diode.
Figure 12 shows an example using “black boxes” for a
switching regulator and the system being duty-cycled.
In some cases, an RC filter may be necessary at the RST
ꢡꢗ ꢁꢍ ꢜꢓꢗ
ꢗ
ꢚꢄꢎ
ꢗ
ꢗ
ꢍꢐꢁ
ꢙꢉ
ꢌ
ꢍꢐꢁ
ꢚ
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ꢚꢄꢎꢐꢀꢈꢁꢍꢚ
ꢅꢐꢑꢑꢀꢆ
ꢡꢒꢠꢓ ꢅꢄꢂꢍꢉꢋꢅ
ꢞꢟ99ꢛ
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ꢗ
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1ꢉꢞꢠꢡꢡꢈ
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1ꢇ
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ꢀꢁꢂ6991
ꢘ
ꢗ
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6ꢝ1ꢛ
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66ꢒꢛ
1ꢓꢓꢛ
ꢅꢄꢁ
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ꢂ
ꢕꢙꢀꢁ
6991 ꢕ1ꢜ
ꢓꢟ1ꢢꢕ
ꢁꢃꢄ ꢅꢆꢅꢁꢄꢇ ꢂꢈꢉ ꢄꢊꢁꢄꢉꢋ ꢌ ꢈꢅ ꢀꢍꢉꢎ ꢈꢅ ꢉꢄꢄꢋꢄꢋ ꢏꢐꢑ ꢁꢍ ꢒꢓꢔ ꢍꢕ ꢌ
ꢖ
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ꢍꢉ
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ꢍꢉ
ꢗ
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ꢋꢍꢉꢄꢤꢚꢅꢁ
ꢀꢁꢂ6991 ꢍꢐꢁ
ꢌ
ꢌ
ꢌ
ꢍꢐꢁ
ꢍꢐꢁ
ꢍꢐꢁ
Figure 12. Powering Up a System Once an Hour
6991fc
15
For more information www.linear.com/LTC6991
LTC6991
APPLICATIONS INFORMATION
OUT
R
V
PW
RST(RISING)
t
= –R • C • In 1–
PULSE
PW
PW
+
2.26k
(
)
V
RST
GND
SET
OUT
t
t
≈ –2.26kΩ • 470pF • In(1 – 0.61)
≈ 1µs
PULSE
PULSE
C
PW
LTC6991
2.25V TO 5.5V
470pF
+
1µs PULSE WIDTH
60 SECONDS
V
0.1µF
R1
1M
R
715k
SET
DIV
R2
392k
6991 F13a
Figure 13a. Self-Resetting Circuit (DIVCODE = 4)
OUT
R
PW
V
RST(FALLING)
2.26k
t
= –R • C • In
PW PW
PULSE
+
(
)
V
RST
GND
SET
OUT
t
t
≈ –2.26kΩ • 470pF • In(0.43)
≈ 0.9µs
PULSE
PULSE
C
PW
LTC6991
2.25V TO 5.5V
470pF
+
V
0.9µs PULSE WIDTH
60 SECONDS
0.1µF
R1
392k
R
715k
SET
DIV
R2
1M
6991 F13b
Figure 13b. Self-Resetting Circuit (DIVCODE = 11)
Figure 13.
Self-Resetting Circuits
Voltage Controlled Frequency
The RST pin has hysteresis to accommodate slow-
changing input voltages. Furthermore, the trip points
are proportional to the supply voltage (see Note 6 and
the RST Threshold Voltage vs Supply Voltage curve in
Typical Performance Characteristics). This allows an RC
time constant at the RST input to generate a delay that is
nearly independent of the supply voltage.
With one additional resistor, the LTC6991 output frequency
can be manipulated by an external voltage. As shown in
Figure 14, voltage V
sources/sinks a current through
CTRL
RVCO to vary the ISET current, which in turn modulates the
output frequency as described in Equation (3).
⎛
⎞
⎟
⎠
1MHz • 50kΩ
R
R
V
CTRL
VCO
SET
(3)
f
=
• 1+
−
⎜
OUT
1024 • N
• R
V
SET
⎝
DIV
VCO
A simple application of this technique allows the LTC6991
output to reset itself, producing a well-controlled pulse
once each cycle. Figure 13a and Figure 13b show circuits
that produce approximately 1µs pulses once a minute.
The only difference is in the POL bit setting, which con-
trols whether the pulse is positive or negative.
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ꢇꢈꢉ
ꢆꢊꢃ
ꢋꢌꢃ
ꢎ
ꢂꢃꢄ6991
ꢍ
ꢎ
ꢍ
ꢄ1
ꢐꢑ1ꢒꢀ
ꢅ1
ꢅ
ꢍꢄꢋ
ꢍ
ꢉꢏꢍ
ꢄꢃꢅꢂ
ꢅ
ꢆꢊꢃ
ꢅꢓ
6991 ꢀ1ꢁ
Figure 14. Voltage-Controlled Oscillator
6991fc
16
For more information www.linear.com/LTC6991
LTC6991
APPLICATIONS INFORMATION
RST
GND
SET
OUT
+
LTC6991
V
+
+
V
V
C1
0.1µF
0.1µF
R1
DIV
+
–
1/2
LTC6078
R2
+
V
6991 F15
0.1µF
1MHz • 50kΩ
R
D
IN
4096
VCO
SET
f
=
• 1 +
–
OUT
(
)
1024 • N • R
R
DIV
VCO
V
REF
CC
D
= 0 TO 4095
IN
D
IN
R
VCO
V
OUT
µP
LTC1659
CLK
ꢀꢁ/LD
R
SET
GND
Figure 15. Digitally-Controlled Oscillator
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Digital Frequency Control
The control voltage can be generated by a DAC (digital-
to-analog converter), resulting in a digitally-controlled
frequency. Many DACs allow for the use of an external
reference. If such a DAC is used to provide the VCTRL
voltage, the VSET dependency can be eliminated by buffer-
Frequency Modulation and Settling Time
The LTC6991 will respond to changes in I up to a –3dB
SET
bandwidth of 0.4 • f
.
ing V
and using it as the DAC’s reference voltage, as
OUT
SET
shown in Figure 15. The DAC’s output voltage now tracks
any V variation and eliminates it as an error source.
The SET pin cannot be tied directly to the reference input
of the DAC because the current drawn by the DAC’s REF
input would affect the frequency.
Following a 2× or 0.5× step change in I , the output
SET
SET
frequency takes less than one cycle to settle to within 1%
of the final value.
Power Supply Current
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under
any condition using the following equation. This equation
I
Extremes (Master Oscillator Frequency Extremes)
SET
When operating with ISET outside of the recommended
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
ignores C
(valid for C
< 1nF) and assumes the
LOAD
LOAD
output has 50% duty cycle.
+
+
V
V
+
The oscillator can still function with reduced accuracy
for I < 1.25µA. At approximately 500nA, the oscillator
I
≈ V • f
• 7.8pF +
+
S(TYP)
MASTER
420kΩ 2 • R
LOAD
SET
output will be frozen in its current state. The output could
halt in a high or low state. This avoids introducing short
pulses when frequency modulating a very low frequency
output.
+ 1.8 •I
+ 50µA
SET
6991fc
17
For more information www.linear.com/LTC6991
LTC6991
APPLICATIONS INFORMATION
ꢅꢆꢃ
ꢇꢈꢉ
ꢆꢊꢃ
ꢋꢌꢃ
ꢂꢃꢄ6991
ꢎ
ꢎ
ꢍ
ꢍ
ꢄ1
ꢐꢑ1ꢒꢀ
ꢅ1
ꢅꢓ
ꢉꢏꢍ
ꢅ
ꢆꢊꢃ
ꢎ
ꢍ
ꢎ
ꢄ1
ꢍ
ꢅ1
ꢄ1
ꢎ
ꢍ
ꢋꢌꢃ
ꢇꢈꢉ
ꢅꢆꢃ
ꢅꢆꢃ
ꢋꢌꢃ
ꢎ
ꢉꢏꢍ
ꢆꢊꢃ
ꢇꢈꢉ
ꢆꢊꢃ
ꢍ
ꢅꢓ
ꢉꢏꢍ
ꢅ1
ꢅ
ꢆꢊꢃ
ꢅ
ꢆꢊꢃ
ꢅꢓ
6991 ꢀ1ꢁ
DFN PACKAGE
TSOT-23 PACKAGE
Figure 16. Supply Bypassing and PCB Layout
Supply Bypassing and PCB Layout Guidelines
plane and the C1 connection to the ground plane are
recommended to minimize the inductance. Capacitor
C1 should be a 0.1µF ceramic capacitor.
The LTC6991 is a 2.2% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place R
as close as possible to the SET pin and
SET
Figure 16 shows example PCB layouts for both the TSOT-
23 and DFN packages using 0603 sized passive compo-
nents. The layouts assume a two layer board with a ground
plane layer beneath and around the LTC6991. These lay-
outs are a guide and need not be followed exactly.
make a direct, short connection. The SET pin is a cur-
rent summing node and currents injected into this pin
directly modulate the operating frequency. Having a
short connection minimizes the exposure to signal
pickup.
1. Connect the bypass capacitor, C1, directly to the V+ and
GND pins using a low inductance path. The connection
4. Connect R directly to the GND pin. Using a long path
or vias to SthEeT ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
+
from C1 to the V pin is easily done directly on the top
layer. For the DFN package, C1’s connection to GND
is also simply done on the top layer. For the TSOT-23,
OUT can be routed through the C1 pads to allow a good
C1 GND connection. If the PCB design rules do not
allow that, C1’s GND connection can be accomplished
through multiple vias to the ground plane. Multiple
vias for both the GND pin connection to the ground
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
6991fc
18
For more information www.linear.com/LTC6991
LTC6991
TYPICAL APPLICATIONS
5 Second On/Off Timed Relay Driver
1ꢌꢍ
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11ꢋꢄ
6991 ꢉꢒꢐꢌ
1.5ms Radio Control Servo Reference Pulse Generator
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ꢕꢃꢔ6991
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1ꢋ1ꢚ
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1ꢘ6ꢚ
ꢀꢓ
1ꢌꢋꢚ
ꢀꢋ
ꢋꢞꢌꢚ
6991 ꢃꢐꢌꢜ
Cycling (10 Seconds On/Off) Symmetrical Power Supplies
ꢂꢃ
ꢔꢕꢓꢓꢆꢅꢖꢗ
1ꢅꢉ
1ꢅꢉ
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1ꢄ
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ꢚꢎꢏ6991
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1ꢂ
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ꢒ6991 ꢎꢘꢇꢓ
6991fc
19
For more information www.linear.com/LTC6991
LTC6991
TYPICAL APPLICATIONS
Isolated AC Load Flasher
5V
0.1µF
R3
5
+
R4
R5
U2
40W LAMP
10k
215Ω
5.94k
MOC3041M
V
1
2
1
6
4
6
4
OPEN = OFF
GND = ON
HOT
117V AC
RST
OUT
R1
LTC6991
R7
100Ω
1M
3
U3
NTE5642
SET
DIV
5V
ZERO
CROSSING
GND
2
R
SET
R2
392k
C2
0.022µF
237k
R6
10k
NEUTRAL
AC
10 SECONDS ON/OFF
6991 TA05
ISOLATION BARRIER = 7500V
Interval (Wiper) Timer
ꢇꢈ
ꢉꢈ
1ꢉꢈ
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1ꢋ
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66ꢄꢉꢎ
ꢇꢏꢃꢎ
1ꢏꢇꢎ
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ꢀꢁꢂ6991
ꢀꢁꢂ699ꢊꢛ1
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ꢒ
ꢒ
ꢒ
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1ꢐ
1ꢐ
1ꢉꢈ
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ꢌ ꢐꢚꢖꢙꢁꢘꢔ
ꢊꢃꢈ
ꢗꢚꢑ
ꢗꢚꢑ
1ꢋ
ꢇꢋ
ꢌꢋ
ꢊꢏꢊꢎ
6ꢏ1ꢎ
ꢇꢈ
1ꢏꢄꢇꢎ
1ꢏꢇꢎ
ꢍꢆꢆ
6991 ꢁꢞꢃ6
ꢇꢈ
ꢇꢏꢃꢎ
11ꢊꢎ
1ꢊꢊꢎ
ꢉꢈ
1ꢉꢈ
ꢊꢃꢈ
1ꢋ
ꢇꢋ
ꢌꢋ
ꢍꢆꢆ
6991fc
20
For more information www.linear.com/LTC6991
LTC6991
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC6991#packaging for the most recent package drawings.
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
ꢂꢁꢥꢂ ±ꢂꢁꢂꢡ
1ꢁ6ꢡ ±ꢂꢁꢂꢡ
ꢀꢁꢡꢡ ±ꢂꢁꢂꢡ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢄꢁ1ꢡ ±ꢂꢁꢂꢡ
ꢖꢏꢕꢗꢏꢑꢈ
ꢋꢘꢌꢙꢆꢊꢈ
ꢂꢁꢄꢡ ± ꢂꢁꢂꢡ
ꢂꢁꢡꢂ ꢒꢅꢕ
1ꢁꢀꢡ ±ꢂꢁꢂꢡ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢎꢈꢕꢋꢓꢓꢈꢊꢇꢈꢇ ꢅꢋꢙꢇꢈꢎ ꢖꢏꢇ ꢖꢆꢌꢕꢟ ꢏꢊꢇ ꢇꢆꢓꢈꢊꢅꢆꢋꢊꢅ
ꢎ ꢦ ꢂꢁ11ꢡ
ꢄꢁꢂꢂ ±ꢂꢁ1ꢂ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢂꢁꢝꢂ ± ꢂꢁ1ꢂ
ꢌꢣꢖ
ꢎ ꢦ ꢂꢁꢂꢡ
ꢌꢣꢖ
ꢝ
6
ꢀꢁꢂꢂ ±ꢂꢁ1ꢂ 1ꢁ6ꢡ ± ꢂꢁ1ꢂ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢖꢆꢊ 1 ꢒꢏꢎ
ꢌꢋꢖ ꢓꢏꢎꢗ
ꢃꢅꢈꢈ ꢊꢋꢌꢈ 6ꢉ
ꢖꢆꢊ 1 ꢊꢋꢌꢕꢟ
ꢎꢂꢁꢄꢂ ꢋꢎ ꢂꢁꢄꢡ
× ꢝꢡ° ꢕꢟꢏꢓꢜꢈꢎ
ꢃꢇꢕꢒ6ꢉ ꢇꢜꢊ ꢂꢝꢂꢡ
ꢀ
1
ꢂꢁꢄꢡ ± ꢂꢁꢂꢡ
ꢂꢁꢡꢂ ꢒꢅꢕ
ꢂꢁꢥꢡ ±ꢂꢁꢂꢡ
ꢂꢁꢄꢂꢂ ꢎꢈꢜ
1ꢁꢀꢡ ±ꢂꢁ1ꢂ
ꢃꢄ ꢅꢆꢇꢈꢅꢉ
ꢒꢋꢌꢌꢋꢓ ꢛꢆꢈꢐꢤꢈꢞꢖꢋꢅꢈꢇ ꢖꢏꢇ
ꢂꢁꢂꢂ ꢧ ꢂꢁꢂꢡ
ꢊꢋꢌꢈꢍ
1ꢁ ꢇꢎꢏꢐꢆꢊꢑ ꢌꢋ ꢒꢈ ꢓꢏꢇꢈ ꢏ ꢔꢈꢇꢈꢕ ꢖꢏꢕꢗꢏꢑꢈ ꢋꢘꢌꢙꢆꢊꢈ ꢓꢂꢚꢄꢄ9 ꢛꢏꢎꢆꢏꢌꢆꢋꢊ ꢋꢜ ꢃꢌꢒꢇꢉ
ꢄꢁ ꢇꢎꢏꢐꢆꢊꢑ ꢊꢋꢌ ꢌꢋ ꢅꢕꢏꢙꢈ
ꢀꢁ ꢏꢙꢙ ꢇꢆꢓꢈꢊꢅꢆꢋꢊꢅ ꢏꢎꢈ ꢆꢊ ꢓꢆꢙꢙꢆꢓꢈꢌꢈꢎꢅ
ꢝꢁ ꢇꢆꢓꢈꢊꢅꢆꢋꢊꢅ ꢋꢜ ꢈꢞꢖꢋꢅꢈꢇ ꢖꢏꢇ ꢋꢊ ꢒꢋꢌꢌꢋꢓ ꢋꢜ ꢖꢏꢕꢗꢏꢑꢈ ꢇꢋ ꢊꢋꢌ ꢆꢊꢕꢙꢘꢇꢈ
ꢓꢋꢙꢇ ꢜꢙꢏꢅꢟꢁ ꢓꢋꢙꢇ ꢜꢙꢏꢅꢟꢠ ꢆꢜ ꢖꢎꢈꢅꢈꢊꢌꢠ ꢅꢟꢏꢙꢙ ꢊꢋꢌ ꢈꢞꢕꢈꢈꢇ ꢂꢁ1ꢡꢢꢢ ꢋꢊ ꢏꢊꢣ ꢅꢆꢇꢈ
ꢡꢁ ꢈꢞꢖꢋꢅꢈꢇ ꢖꢏꢇ ꢅꢟꢏꢙꢙ ꢒꢈ ꢅꢋꢙꢇꢈꢎ ꢖꢙꢏꢌꢈꢇ
6ꢁ ꢅꢟꢏꢇꢈꢇ ꢏꢎꢈꢏ ꢆꢅ ꢋꢊꢙꢣ ꢏ ꢎꢈꢜꢈꢎꢈꢊꢕꢈ ꢜꢋꢎ ꢖꢆꢊ 1 ꢙꢋꢕꢏꢌꢆꢋꢊ ꢋꢊ ꢌꢟꢈ
ꢌꢋꢖ ꢏꢊꢇ ꢒꢋꢌꢌꢋꢓ ꢋꢜ ꢖꢏꢕꢗꢏꢑꢈ
6991fc
21
For more information www.linear.com/LTC6991
LTC6991
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC6991#packaging for the most recent package drawings.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
ꢌꢀ9ꢂ ꢎꢏꢐ
ꢅꢆꢇꢈꢉ ꢊꢋ
ꢂꢀ6ꢌ
ꢗꢕꢛ
ꢂꢀ9ꢁ
ꢜꢉꢝ
1ꢀꢌꢌ ꢜꢉꢝ
1ꢀꢊ ꢗꢞꢆ
1ꢀꢁꢂ ꢃ 1ꢀꢄꢁ
ꢅꢆꢇꢈꢉ ꢊꢋ
ꢌꢀꢍꢂ ꢎꢏꢐ
ꢑꢀꢍꢁ ꢗꢕꢛ ꢌꢀ6ꢌ ꢜꢉꢝ
ꢒꢞꢆ ꢇꢆꢉ ꢞꢔ
ꢜꢉꢐꢇꢗꢗꢉꢆꢔꢉꢔ ꢏꢇꢓꢔꢉꢜ ꢒꢕꢔ ꢓꢕꢧꢇꢖꢈ
ꢒꢉꢜ ꢞꢒꢐ ꢐꢕꢓꢐꢖꢓꢕꢈꢇꢜ
ꢂꢀꢑꢂ ꢃ ꢂꢀꢊꢁ
6 ꢒꢓꢐꢏ ꢅꢆꢇꢈꢉ ꢑꢋ
ꢂꢀ9ꢁ ꢎꢏꢐ
ꢂꢀꢍꢂ ꢃ ꢂꢀ9ꢂ
ꢂꢀꢌꢂ ꢎꢏꢐ
ꢔꢕꢈꢖꢗ ꢘꢕꢙ
ꢂꢀꢂ1 ꢃ ꢂꢀ1ꢂ
1ꢀꢂꢂ ꢗꢕꢛ
ꢂꢀꢑꢂ ꢃ ꢂꢀꢁꢂ ꢜꢉꢝ
1ꢀ9ꢂ ꢎꢏꢐ
ꢂꢀꢂ9 ꢃ ꢂꢀꢌꢂ
ꢅꢆꢇꢈꢉ ꢑꢋ
ꢏ6 ꢈꢏꢇꢈꢚꢌꢑ ꢂꢑꢂꢌ
ꢆꢇꢈꢉꢟ
1ꢀ ꢔꢞꢗꢉꢆꢏꢞꢇꢆꢏ ꢕꢜꢉ ꢞꢆ ꢗꢞꢓꢓꢞꢗꢉꢈꢉꢜꢏ
ꢌꢀ ꢔꢜꢕꢠꢞꢆꢡ ꢆꢇꢈ ꢈꢇ ꢏꢐꢕꢓꢉ
ꢑꢀ ꢔꢞꢗꢉꢆꢏꢞꢇꢆꢏ ꢕꢜꢉ ꢞꢆꢐꢓꢖꢏꢞꢢꢉ ꢇꢝ ꢒꢓꢕꢈꢞꢆꢡ
ꢊꢀ ꢔꢞꢗꢉꢆꢏꢞꢇꢆꢏ ꢕꢜꢉ ꢉꢛꢐꢓꢖꢏꢞꢢꢉ ꢇꢝ ꢗꢇꢓꢔ ꢝꢓꢕꢏꢣ ꢕꢆꢔ ꢗꢉꢈꢕꢓ ꢎꢖꢜꢜ
ꢁꢀ ꢗꢇꢓꢔ ꢝꢓꢕꢏꢣ ꢏꢣꢕꢓꢓ ꢆꢇꢈ ꢉꢛꢐꢉꢉꢔ ꢂꢀꢌꢁꢊꢤꢤ
6ꢀ ꢥꢉꢔꢉꢐ ꢒꢕꢐꢦꢕꢡꢉ ꢜꢉꢝꢉꢜꢉꢆꢐꢉ ꢞꢏ ꢗꢇꢚ19ꢑ
6991fc
22
For more information www.linear.com/LTC6991
LTC6991
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
7/11
Updated Description, Typical Application, and Order Information sections
1, 2
3, 4
6
+
Added additional information to ∆f /∆V and included Note 11 in Electrical Characteristics section
OUT
Added Typical Frequency Error vs Time curve to Typical Performance Characteristics section
Added text to Basic Operation paragraph in Applications Information section
Added MP grade
14
B
C
1/12
1/18
1, 2, 4
Corrected I
parameter typo. Corrected Figure number.
4, 17, 18
OUT(MAX)
6991fc
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
23
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC6991
TYPICAL APPLICATION
Intervalometer for Time-Lapse Photography
ꢊꢂꢁꢋꢌꢊꢁꢈꢅ ꢅꢆꢇꢁꢁꢈꢉ ꢊꢁ
ꢍꢅꢈꢂ ꢁꢎ ꢍꢏꢐꢑꢋꢒ ꢋꢒꢁꢈꢉꢌꢊꢀꢅ
ꢉ
ꢜꢝ
1ꢖꢖꢕ
ꢅꢆꢇꢁꢁꢈꢉ
ꢉꢅꢁ
ꢙꢒꢚ
ꢅꢈꢁ
ꢎꢇꢁ
ꢂ
ꢜꢝ
ꢀꢁꢂ6991
ꢓꢓꢃꢄ
ꢛ
ꢌ
1ꢃꢄ
ꢉ1ꢊ
ꢉ1ꢞ
1ꢑ
ꢉ
ꢅꢓ
ꢓꢓꢔꢕ
9ꢐꢏꢓꢕ
ꢚꢋꢌ
ꢟꢅꢀꢎꢝ ꢉꢊꢒꢙꢈꢠ
1ꢏ1ꢑꢋꢒ ꢁꢎ ꢍꢏꢐ ꢑꢋꢒ
ꢍꢅꢈꢂ ꢁꢎ
6ꢘꢅꢈꢂ
ꢉ
ꢉ
ꢅ1
ꢅꢔ
1ꢑ
ꢔꢑ
ꢉꢔ
1ꢓꢖꢕ
6991 ꢁꢊꢖꢗ
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1799
1MHz to 33MHz ThinSOT Silicon Oscillator
1MHz to 20MHz ThinSOT Silicon Oscillator
Wide Frequency Range
Low Power, Wide Frequency Range
LTC6900
LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillators
Micropower, I
= 35µA at 400kHz
SUPPLY
LTC6930
LTC6990
LTC6992
LTC6993
LTC6994
Fixed Frequency Oscillator, 32.768kHz to 8.192MHz
TimerBlox: Voltage-Controlled Silicon Oscillator
0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
Fixed-Frequency or Voltage-Controlled Operation
Simple PWM with Wide Frequency Range
TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)
TimerBlox: Monostable Pulse Generator (One Shot)
TimerBlox: Delay Block/Debouncer
Resistor Programmable Pulse Width of 1µs to 34sec
Delays Rising, Falling or Both Edges 1µs to 34sec
6991fc
LT 0118 REV C • PRINTED IN USA
www.linear.com/LTC6991
24
ANALOG DEVICES, INC. 2018
相关型号：
LTC6991IS6#TRMPBF
LTC6991 - TimerBlox: Resettable, Low Frequency Oscillator; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C
Linear
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