LTC6992IS6-4#TRMPBF [Linear]
LTC6992 - TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM); Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C;
| 型号： | LTC6992IS6-4#TRMPBF |
| 厂家： | 
Linear |
| 描述： | LTC6992 - TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM); Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C 光电二极管 |
| 文件： | 总34页 (文件大小：530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TimerBlox:
Voltage-Controlled Pulse
Width Modulator (PWM)
FeaTures
DescripTion
The LTC®6992 is a silicon oscillator with an easy-to-use
analog voltage-controlled pulse width modulation (PWM)
capability. The LTC6992 is part of the TimerBlox® family
of versatile silicon timing devices.
n
Pulse Width Modulation (PWM) Controlled by
Simple 0V to 1V Analog Input
n
Four Available Options Define Duty Cycle Limits
– Minimum Duty Cycle at 0% or 5%
– Maximum Duty Cycle at 95% or 100%
A single resistor, R , programs the LTC6992’s inter-
SET
n
Frequency Range: 3.81Hz to 1MHz
nal master oscillator frequency. The output frequency
is determined by this master oscillator and an internal
n
Configured with 1 to 3 Resistors
n
<1.7% Maximum Frequency Error
frequency divider, N , programmable to eight settings
DIV
n
PWM Duty Cycle Error <3.7% Maximum
from 1 to 16384.
n
Frequency Modulation (VCO) Capability
1MHz 50kΩ
NDIV RSET
n
2.25V to 5.5V Single Supply Operation
fOUT
=
•
,NDIV = 1,4,16 …16384
n
115μA Supply Current at 100kHz
n
500μs Start-Up Time
Applying a voltage between 0V and 1V on the MOD pin
sets the duty cycle.
n
CMOS Output Driver Sources/Sinks 20mA
n
–55°C to 125°C Operating Temperature Range
n
The four versions differ in their minimum/maximum duty
cycle. Note that a minimum duty cycle limit of 0% or
maximum duty cycle limit of 100% allows oscillations to
stop at the extreme duty cycle settings.
Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN
applicaTions
DEVICE NAME
LTC6992-1
LTC6992-2
LTC6992-3
LTC6992-4
PWM DUTY CYCLE RANGE
0% to 100%
n
PWM Servo Loops
n
Heater Control
5% to 95%
0% to 95%
5% to 100%
n
LED Dimming Control
n
High Vibration, High Acceleration Environments
n
Portable and Battery-Powered Equipment
For easy configuration of the LTC6992, download the
TimerBlox Designer tool at www.linear.com/timerblox.
L, LT, LTC and LTM, Linear Technology, TimerBlox and the Linear logo are registered
trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
Typical applicaTion
1MHz Pulse Width Modulator
ANALOG PWM
DUTY CYCLE
MOD
MOD
GND
SET
OUT
CONTROL
(0V TO 1V)
0.5V/DIV
LTC6992
3.3V
+
V
C1
0.1µF
OUT
1V/DIV
DIV
6992 TA01a
R
SET
50k
6992 TA01b
2µs/DIV
69921234fc
1
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
(Note 1)
absoluTe MaxiMuM raTings
+
Supply Voltage (V ) to GND .........…………………….6V
Specified Temperature Range (Note 3)
Maximum Voltage On Any Pin
LTC6992C ................................................ 0°C to 70°C
LTC6992I .............................................–40°C to 85°C
LTC6992H.......................................... –40°C to 125°C
LTC6992MP ....................................... –55°C to 125°C
Junction Temperature .......................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
+
.............................(GND – 0.3V) ≤ V ≤ (V + 0.3V)
PIN
Operating Temperature Range (Note 2)
LTC6992C ............................................–40°C to 85°C
LTC6992I .............................................–40°C to 85°C
LTC6992H..........................................–40°C to 125°C
LTC6992MP ....................................... –55°C to 125°C
S6 Package.......................................................300°C
pin conFiguraTion
TOP VIEW
TOP VIEW
6
5
4
OUT
GND
MOD
V+
DIV
SET
1
2
3
MOD 1
GND 2
SET 3
6 OUT
7
GND
+
5 V
4 DIV
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
DCB PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
T
= 150°C, θ = 192°C/W, θ = 51°C/W
JMAX
JA
JC
T
= 150°C, θ = 64°C/W, θ = 10.6°C/W
JA JC
EXPOSED PAD (PIN 7) IS GND, PCB CONNECTION IS OPTIONAL
JMAX
orDer inForMaTion
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
LTC6992CDCB-1#TRMPBF LTC6992CDCB-1#TRPBF
LTC6992IDCB-1#TRMPBF LTC6992IDCB-1#TRPBF
LTC6992HDCB-1#TRMPBF LTC6992HDCB-1#TRPBF
LDXC
LDXC
LDXC
LTDXB
LTDXB
LTDXB
LDXF
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6992CS6-1#TRMPBF
LTC6992IS6-1#TRMPBF
LTC6992CS6-1#TRPBF
LTC6992IS6-1#TRPBF
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6992HS6-1#TRMPBF LTC6992HS6-1#TRPBF
LTC6992CDCB-2#TRMPBF LTC6992CDCB-2#TRPBF
LTC6992IDCB-2#TRMPBF LTC6992IDCB-2#TRPBF
LTC6992HDCB-2#TRMPBF LTC6992HDCB-2#TRPBF
6-Lead Plastic TSOT-23
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
LDXF
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LDXF
LTC6992CS6-2#TRMPBF
LTC6992IS6-2#TRMPBF
LTC6992CS6-2#TRPBF
LTC6992IS6-2#TRPBF
LTDXD
LTDXD
LTDXD
LFCP
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6992HS6-2#TRMPBF LTC6992HS6-2#TRPBF
LTC6992CDCB-3#TRMPBF LTC6992CDCB-3#TRPBF
LTC6992IDCB-3#TRMPBF LTC6992IDCB-3#TRPBF
LTC6992HDCB-3#TRMPBF LTC6992HDCB-3#TRPBF
6-Lead Plastic TSOT-23
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
LFCP
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LFCP
LTC6992CS6-3#TRMPBF
LTC6992IS6-3#TRMPBF
LTC6992CS6-3#TRPBF
LTC6992IS6-3#TRPBF
LTFCQ
LTFCQ
LTFCQ
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
LTC6992HS6-3#TRMPBF LTC6992HS6-3#TRPBF
6-Lead Plastic TSOT-23
69921234fc
2
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
orDer inForMaTion
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
LTC6992CDCB-4#TRMPBF LTC6992CDCB-4#TRPBF
LTC6992IDCB-4#TRMPBF LTC6992IDCB-4#TRPBF
LTC6992HDCB-4#TRMPBF LTC6992HDCB-4#TRPBF
LFCR
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
LFCR
–40°C to 85°C
LFCR
–40°C to 125°C
0°C to 70°C
LTC6992CS6-4#TRMPBF
LTC6992IS6-4#TRMPBF
LTC6992CS6-4#TRPBF
LTC6992IS6-4#TRPBF
LTFCS
LTFCS
LTFCS
LTDXB
LTDXD
LTFCQ
LTFCS
6-Lead Plastic TSOT-23
–40°C to 85°C
LTC6992HS6-4#TRMPBF LTC6992HS6-4#TRPBF
LTC6992MPS6-1#TRMPBF LTC6992MPS6-1#TRPBF
LTC6992MPS6-2#TRMPBF LTC6992MPS6-2#TRPBF
LTC6992MPS6-3#TRMPBF LTC6992MPS6-3#TRPBF
LTC6992MPS6-4#TRMPBF LTC6992MPS6-4#TRPBF
6-Lead Plastic TSOT-23
–40°C to 125°C
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
elecTrical characTerisTics
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET
DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
,
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillation Frequency
f
Output Frequency
3.81
1000000
Hz
OUT
Frequency Accuracy (Note 4)
3.81Hz ≤ f
≤ 1MHz
0.8
1.7
2.4
%
%
∆f
OUT
OUT
l
l
Frequency Drift Over Temperature
Frequency Drift Over Supply
0.005
%/°C
∆f /∆T
OUT
+
+
l
l
V = 4.5V to 5.5V
0.25
0.08
0.65
0.18
%/V
%/V
∆f /∆V
OUT
+
V = 2.25V to 4.5V
Long-Term Frequency Stability
Period Jitter (Note 9)
(Note 10)
90
ppm/√kHr
N
DIV
N
DIV
= 1
= 4
1.2
%
%
P-P
0.4
0.07
P-P
%
RMS
N
DIV
= 16
0.15
0.022
%
RMS
P-P
%
Pulse Width Modulation
PWM Duty Cycle Accuracy
V
= 0.2 • V to 0.8 • V
3.0
3.7
4.5
4.9
%
%
%
∆D
MOD
MOD
MOD
SET
SET
l
l
V
V
= 0.2 • V to 0.8 • V
SET SET
< 0.2 • V or V
> 0.8 • V
SET
MOD
SET
MOD
MOD
MOD
MOD
l
l
l
l
D
D
Maximum Duty Cycle Limit
Minimum Duty Cycle Limit
Duty Cycle Settling Time (Note 6)
LTC6992-1/LTC6992-4, POL = 0, V
LTC6992-2/LTC6992-3, POL = 0, V
LTC6992-1/LTC6992-3, POL = 0, V
LTC6992-2/LTC6992-4, POL = 0, V
= 1V
= 1V
= 0V
= 0V
100
%
%
%
%
µs
MAX
90.5
95
5
99
0
MIN
1
9.5
t
t
= t /N
OUT DIV
8•t
MASTER
S,PWM
MASTER
69921234fc
3
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET
DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
,
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
+
l
l
l
l
l
l
l
l
l
l
V
Operating Supply Voltage Range
Power-On Reset Voltage
Supply Current
2.25
5.5
1.95
450
285
420
280
390
265
170
150
V
V
+
I
R = ∞, R = 50k,
DIV
V = 5.5V
365
225
350
225
325
215
120
105
µA
µA
µA
µA
µA
µA
µA
µA
S
L
SET
N
= 1
+
V = 2.25V
+
R = ∞, R = 50k,
V = 5.5V
L
DIV
SET
N
= 4
+
V = 2.25V
+
R = ∞, R = 50k,
V = 5.5V
L
DIV
SET
N
≥ 16
+
V = 2.25V
+
R = ∞, R = 800k,
V = 5.5V
L
DIV
SET
N
= 1 to 16,384
+
V = 2.25V
Analog Inputs
l
l
l
V
Voltage at SET Pin
0.97
50
1.00
75
1.03
800
V
µV/°C
kΩ
SET
∆V /∆T
V
SET
Drift Over Temperature
SET
R
Frequency-Setting Resistor
MOD Pin Input Capacitance
MOD Pin Input Current
SET
2.5
pF
l
l
10
nA
V
V
V
V
Voltage for Maximum
LTC6992-1/LTC6992-4, POL = 0, D = 100%
LTC6992-2/LTC6992-3, POL = 0, D = 95%
0.90•V
0.86•V
0.936•V
SET
V
V
MOD,HI
MOD,LO
DIV
MOD
SET
SET
Duty Cycle
l
V
Voltage for Minimum
LTC6992-1/LTC6992-3, POL = 0, D = 0%
LTC6992-2/LTC6992-4, POL = 0, D = 5%
0.064•V
0.10•V
0.14•V
V
V
MOD
SET
SET
SET
Duty Cycle
+
l
l
DIV Pin Voltage
0
V
V
+
∆V /∆V
DIV Pin Valid Code Range (Note 5)
Deviation from Ideal
1.5
%
DIV
+
V
/V = (DIVCODE + 0.5)/16
DIV
l
DIV Pin Input Current
Output Current
10nA
Digital Output
+
I
V = 2.7V to 5.5V
20
mA
OUT(MAX)
+
l
l
V
High Level Output Voltage (Note 7) V = 5.5V
I
I
= –1mA
5.45
4.84
5.48
5.15
V
V
OH
OL
OUT
OUT
= –16mA
+
l
l
V = 3.3V
I
I
= –1mA
= –10mA
3.24
2.75
3.27
2.99
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= –1mA
= -8mA
2.17
1.58
2.21
1.88
V
V
OUT
OUT
+
l
l
V
Low Level Output Voltage (Note 7)
V = 5.5V
I
I
= 1mA
= 16mA
0.02
0.26
0.04
0.54
V
V
OUT
OUT
+
l
l
V = 3.3V
I
I
= 1mA
= 10mA
0.03
0.22
0.05
0.46
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= 1mA
= 8mA
0.03
0.26
0.07
0.54
V
V
OUT
OUT
+
+
t
t
Output Rise Time (Note 8)
Output Fall Time (Note 8)
V = 5.5V, R
= ∞
= ∞
LOAD
1.1
1.7
2.7
ns
ns
ns
r
LOAD
LOAD
V = 3.3V, R
+
V = 2.25V, R
= ∞
+
V = 5.5V, R
= ∞
1.0
1.6
2.4
ns
ns
ns
f
LOAD
LOAD
+
V = 3.3V, R
= ∞
= ∞
+
V = 2.25V, R
LOAD
69921234fc
4
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Jitter is the ratio of the peak-to-peak deviation of the period to the
mean of the period. This specification is based on characterization and is
not 100% tested.
Note 10: Long-term drift of silicon oscillators is primarily due to the
movement of ions and impurities within the silicon and is tested at 30°C
under otherwise nominal operating conditions. Long-term drift is specified
as ppm/√kHr due to the typically nonlinear nature of the drift. To calculate
drift for a set time period, translate that time into thousands of hours, take
the square root and multiply by the typical drift number. For instance, a
year is 8.77kHr and would yield a drift of 266ppm at 90ppm/√kHr. Drift
without power applied to the device may be approximated as 1/10th of the
drift with power, or 9ppm/√kHr for a 90ppm/√kHr device.
Note 2: The LTC6992C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 3: The LTC6992C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6992C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6992I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6992H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC6992MP is
guaranteed to meet specified performance from –55°C to 125°C.
Note 4: Frequency accuracy is defined as the deviation from the f
OUT
equation, assuming R is used to program the frequency.
SET
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: Duty cycle settling time is the amount of time required for the
output to settle within 1% of the final duty cycle after a 10% change in
the setting ( 80mV step in V
).
MOD
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Frequency Error vs Temperature
Typical perForMance characTerisTics
otherwise noted.
Frequency Error vs Temperature
Frequency Error vs Temperature
3
2
3
2
3
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MAX OVER TEMPERATURE
2
R
= 200k
R
= 50k
R
= 800k
SET
SET
SET
3 PARTS
3 PARTS
3 PARTS
1
1
1
0
0
0
–1
–2
–3
–1
–2
–3
–1
–2
–3
GUARANTEED MIN OVER TEMPERATURE
25 50 75 100 125
TEMPERATURE (°C)
GUARANTEED MIN OVER TEMPERATURE
25 50 75 100 125
TEMPERATURE (°C)
GUARANTEED MIN OVER TEMPERATURE
–50
0
–25
100 125
–50
0
–50
0
25
50
75
–25
–25
TEMPERATURE (°C)
6992 G02
6992 G01
6992 G03
69921234fc
5
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Typical perForMance characTerisTics
otherwise noted.
Frequency Error vs RSET
Frequency Drift vs Supply Voltage
Typical VSET Distribution
0.5
0.4
3
2
250
200
150
100
50
2 LOTS
DFN AND SOT-23
1274 UNITS
GUARANTEED MAX OVER TEMPERATURE
3 PARTS
0.3
0.2
1
R
= 50k
SET
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–1
–2
–3
R
= 800k
SET
R
= 200k
SET
+
REFERENCED TO V = 4.5V
GUARANTEED MIN OVER TEMPERATURE
0
2
4
5
6
3
800
0.98
0.996
V
SET
1.004
(V)
1.012
1.02
50
200
(k)
400
0.988
100
SUPPLY VOLTAGE (V)
R
SET
6992 G05
6992 G04
6992 G06
V
SET Drift vs ISET
VSET Drift vs Supply
VSET vs Temperature
1.0
0.8
1.0
0.8
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
3 PARTS
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
+
REFERENCED TO I
= 10µA
REFERENCED TO V = 4V
SET
0
10
(µA)
15
20
5
6
2
4
5
100 125
3
–50
0
25
50
75
–25
I
SUPPLY (V)
TEMPERATURE (°C)
SET
6992 G07
6992 G08
6992 G09
NDIV = 1 Duty Cycle Error vs RSET
NDIV = 1 Duty Cycle Error vs RSET
NDIV = 1 Duty Cycle Error vs RSET
5
4
5
4
5
4
V
/V
= 0.5 (50%)
V
/V
= 0.8 (87.5%)
V
/V
= 0.2 (12.5%)
MOD SET
MOD SET
MOD SET
DIVCODE = 0
3 PARTS
DIVCODE = 0
3 PARTS
DIVCODE = 0
3 PARTS
3
3
3
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
400
800
50
100
200
(k)
400
800
50
100
200
(k)
50
100
200
(k)
400
800
R
R
R
SET
SET
SET
6992 G11
6992 G10
6992 G12
69921234fc
6
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Typical perForMance characTerisTics
otherwise noted.
NDIV > 1 Duty Cycle Error vs RSET
NDIV > 1 Duty Cycle Error vs RSET
NDIV > 1 Duty Cycle Error vs RSET
5
4
5
4
5
4
V
/V
= 0.2 (12.5%)
V
/V
= 0.8 (87.5%)
V
/V
= 0.5 (50%)
MOD SET
MOD SET
MOD SET
DIVCODE = 4
3 PARTS
DIVCODE = 4
3 PARTS
DIVCODE = 4
3 PARTS
3
3
3
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
50
100
200
(k)
400
800
400
800
50
100
200
(k)
50
100
200
(k)
400
800
R
R
R
SET
SET
SET
6992 G13
6992 G15
6992 G14
NDIV = 1 Duty Cycle Clamps
vs RSET
N
DIV = 1 Duty Cycle Error
NDIV > 1 Duty Cycle Error vs RSET
vs Temperature
97
96
95
94
93
92
97
96
95
94
93
92
5
DIVCODE = 0
3 PARTS
DIVCODE = 4
3 PARTS
4
3
GUARANTEED MAX
= 0.2 (12.5%)
V
/V
MOD SET
DIVCODE = 0
3 PARTS
LTC6992-2/LTC6992-3
= V
2
V
LTC6992-2/LTC6992-3
MOD
SET
V
= V
1
MOD
SET
0
8
7
6
5
4
3
8
7
6
5
4
3
–1
–2
–3
–4
–5
LTC6992-2/LTC6992-4
= V
LTC6992-2/LTC6992-4
V
MOD
SET
V
= V
MOD
SET
GUARANTEED MIN
400
800
–50
0
25
50
75 100 125
50
100
200
400
800
50
100
200
(k)
–25
R
SET
(k)
R
TEMPERATURE (°C)
SET
6992 G16
6992 G17
6992 G18
NDIV = 1 Duty Cycle Error
vs Temperature
NDIV > 1 Duty Cycle Error
vs Temperature
NDIV = 1 Duty Cycle Error
vs Temperature
5
4
5
4
5
4
GUARANTEED MAX
GUARANTEED MAX
GUARANTEED MAX
V
/V
= 0.8 (87.5%)
V
/V
= 0.2 (12.5%)
V
/V
= 0.5 (50%)
MOD SET
MOD SET
MOD SET
3
3
3
DIVCODE = 0
3 PARTS
DIVCODE = 4
3 PARTS
DIVCODE = 0
3 PARTS
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
GUARANTEED MIN
GUARANTEED MIN
GUARANTEED MIN
–50
0
25
50
75 100 125
–25
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
6992 G20
6992 G21
6992 G19
69921234fc
7
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Typical perForMance characTerisTics
otherwise noted.
NDIV > 1 Duty Cycle Error
NDIV > 1 Duty Cycle Error
= 1 Duty Cycle Clamps
NDIV
vs Temperature
vs Temperature
vs Temperature
97
96
95
94
93
92
5
4
5
4
DIVCODE = 0
3 PARTS
GUARANTEED MAX
GUARANTEED MAX
V
/V
= 0.8 (87.5%)
V
/V
= 0.5 (50%)
MOD SET
MOD SET
3
3
DIVCODE = 4
3 PARTS
DIVCODE = 4
3 PARTS
LTC6992-2/LTC6992-3
= V
2
2
V
MOD
SET
1
1
0
0
8
7
6
5
4
3
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
LTC6992-2/LTC6992-4
MOD
V
= GND
GUARANTEED MIN
GUARANTEED MIN
–50 –25
0
25
50
75 100 125
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
6992 G24
6992 G23
6992 G22
N
DIV > 1 Duty Cycle Clamps
Duty Cycle Error vs DIVCODE
vs Temperature
Duty Cycle Error vs DIVCODE
5
4
97
96
95
94
93
92
5
4
DIVCODE = 4
3 PARTS
V
/V
= 0.5 (50%)
V
/V
= 0.2 (12.5%)
MOD SET
MOD SET
3 PARTS
3 PARTS
3
3
2
2
LTC6992-2/LTC6992-3
V
= V
1
1
MOD
SET
0
0
8
7
6
5
4
3
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
LTC6992-2/LTC6992-4
MOD
V
= GND
0
2
4
6
8
10
12
14
–50 –25
0
25
50
75 100 125
0
2
4
6
8
10
12
14
DIVCODE
TEMPERATURE (°C)
DIVCODE
6992 G27
6992 G25
6992 G26
NDIV > 1 Duty Cycle vs VMOD/ VSET
Duty Cycle Error vs DIVCODE
NDIV = 1 Duty Cycle vs VMOD/ VSET
100
90
80
70
60
50
40
30
20
10
0
5
4
100
90
80
70
60
50
40
30
20
10
0
DIVCODE = 4
LTC6992-1/
3 PARTS
DIVCODE = 0
3 PARTS
V
/V
= 0.8 (87.5%)
MOD SET
LTC6992-1/
LTC6992-4
3 PARTS
LTC6992-4
3
LTC6992-2/
LTC6992-3
LTC6992-2/
LTC6992-3
2
1
0
–1
–2
–3
–4
–5
LTC6992-2/
LTC6992-4
LTC6992-2/
LTC6992-4
LTC6992-1/LTC6992-3
LTC6992-1/LTC6992-3
0
0.2
0.4
0.6
0.8
1
0
2
4
6
8
10
12
14
1
0
0.2
0.4
0.6
0.8
V /V (V/V)
MOD SET
DIVCODE
V
/V
(V/V)
MOD SET
6992 G30
6992 G28
6992 G29
69921234fc
8
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Typical perForMance characTerisTics
otherwise noted.
NDIV > 1 Duty Cycle vs VMOD/ VSET
NDIV = 1 Duty Cycle Error vs Ideal
NDIV > 1 Duty Cycle Error vs Ideal
5
4
5
4
100
90
80
70
60
50
40
30
20
10
0
DIVCODE = 4
3 PARTS
DIVCODE = 0
3 PARTS
LTC6992-1/LTC6992-3
3
3
LTC6992-2/
LTC6992-4
2
2
PART C
1
1
PART C
PART B
PART B
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
PART A
LTC6992-2/
LTC6992-3
PART A
LTC6992-1/
LTC6992-4
DIVCODE = 11
3 PARTS
100
0
25
50
75
100
0
25
50
75
0
0.2
0.4
0.6
0.8
1
IDEAL DUTY CYCLE (%)
IDEAL DUTY CYCLE (%)
V
/V
(V/V)
MOD SET
6992 G33
6992 G32
6992 G31
Linearity Near 100% Duty Cycle
N
DIV > 1 Duty Cycle Error vs Ideal
Linearity Near 95% Duty Cycle
5
100
99
98
97
96
95
94
93
92
91
90
89
88
100
99
98
97
96
95
94
93
92
91
90
89
88
DIVCODE = 11
3 PARTS
DIVCODE = 4
LTC6992-1/LTC6992-4
3 PARTS
DIVCODE = 4
LTC6992-2/LTC6992-3
3 PARTS
4
3
PART A
2
PART C
1
0
PART B
–1
–2
–3
–4
–5
0
25
50
75
100
0.804
0.836
V
0.868
(V/V)
0.9
0.804
0.836
V
0.868
/V (V/V)
0.9
IDEAL DUTY CYCLE (%)
/V
MOD SET
MOD SET
6992 G34
6992 G35
6992 G36
Linearity Near 5% Duty Cycle
Linearity Near 0% Duty Cycle
Linearity Near 67% Duty Cycle
72
12
11
10
9
12
11
10
9
DIVCODE = 4
71 3 PARTS
DIVCODE = 4
LTC6992-2/LTC6992-4
3 PARTS
DIVCODE = 4
LTC6992-1/LTC6992-3
3 PARTS
70
69
68
67
66
65
64
63
62
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
0.596
0.612
0.628
/V
0.644
(V/V)
0.66
0.676
0.18
0.084
0.116
V
0.148
/V (V/V)
0.18
0.084
0.116
V
0.148
(V/V)
V
/V
MOD SET
MOD SET
MOD SET
6992 G37
6992 G39
6992 G38
69921234fc
9
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Typical perForMance characTerisTics
otherwise noted.
N
DIV > 1 Duty Cycle Drift
Linearity Near 31% Duty Cycle
= 1 Duty Cycle Drift vs Supply
NDIV
vs Supply
0.5
0.4
0.5
0.4
36
DIVCODE = 0
DIVCODE = 4
DIVCODE = 4
35 3 PARTS
5% CLAMP
0.3
0.3
34
33
32
31
30
29
28
27
26
0.2
0.2
V
/V
= 0.2
MOD SET
95% CLAMP
5% CLAMP
V
0.1
0.1
95% CLAMP
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
V
/V
= 0.5
/V
= 0.8
MOD SET
MOD SET
V
/V
= 0.2
MOD SET
V
/V
= 0.8
MOD SET
V
/V
= 0.5
MOD SET
+
+
REFERENCED TO V = 4V
REFERENCED TO V = 4V
2
3
4
5
6
6
0.308
0.324
0.34
/V
0.356
(V/V)
0.372
0.388
2
3
4
5
SUPPLY (V)
SUPPLY (V)
V
MOD SET
6992 G41
6992 G42
6992 G40
Supply Current vs Temperature
Supply Current vs VMOD
Supply Current vs Supply Voltage
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
LTC6992-2
R
SET
= 50k, ÷1
5.0V, R
= 50k, ÷1
SET
R
SET
= 50k, ÷4
5.0V, R
= 50k, ÷16
SET
R
SET
= 50k, ÷1
R
R
= 50k, ÷16
2.5V, R
= 50k, ÷1
SET
SET
R
= 50k, ÷16
SET
SET
= 100k, ÷1
= 800k, ÷1
SET
R
= 100k, ÷4
= 800k, ÷1
5.0V, R
= 800k, ÷1
= 800k, ÷1
SET
R
SET
R
SET
2.5V, R
SET
0
0
0
–50
0
25
50
75 100 125
–25
0
0.2
0.4
V
0.6
(V)
0.8
1
2
3
4
5
6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
MOD
6992 G45
6992 G43
6992 G44
Jitter vs Frequency
Supply Current vs Frequency, 5V
Supply Current vs Frequency, 2.5V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
+
+
PEAK-TO-PEAK PERIOD
DEVIATION MEASURED
OVER 30s INTERVALS
V
= 5V
V
= 2.5V
÷4
V
/V
= 0.5
MOD SET
+
÷1, V = 5V
÷16,384
÷4
+
÷16,384
÷1, V = 2.5V
+
÷4, V = 5V
÷1
÷1
+
÷4, V = 2.5V
÷16
÷64
0
0
0.01
0.1
1
10
100
1000
0.001 0.01
0.1
1
10
100 1000
0.001 0.01
0.1
1
10
100 1000
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
6992 G46
6992 G47
6992 G48
69921234fc
10
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Typical perForMance characTerisTics
otherwise noted.
Rise and Fall Time
vs Supply Voltage
3.0
Output Resistance
vs Supply Voltage
Typical Frequency Error vs
Time (Long-Term Drift)
50
45
40
35
30
25
20
15
10
5
200
150
100
50
C
= 5pF
65 UNITS
LOAD
SOT-23 AND DFN PARTS
2.5
2.0
1.5
1.0
0.5
0
T
= 30°C
A
OUTPUT SOURCING CURRENT
t
RISE
0
–50
t
FALL
OUTPUT SINKING CURRENT
–100
–150
–200
0
0
400 800 1200 1600 2000 2400 2800
2
3
4
5
6
2
3
4
5
6
TIME (h)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6992 G48a
6992 G50
6992 G51
Typical ISET Current Limit vs V+
Typical Start-Up, POL = 0
1000
800
600
400
200
0
SET PIN SHORTED TO GND
+
V
1V/DIV
OUT
1V/DIV
500µs
6992 G53
100µs/DIV
+
V
= 2.5V
DIVCODE = 3 (÷64)
R
MOD
= 50k
SET
2
3
4
5
6
V
= 0.3V (~25% DUTY CYCLE)
SUPPLY VOLTAGE (V)
6992 G52
Typical Start-Up, POL = 1
125kHz Full Modulation
LTC6992-1
V
MOD
0.5V/DIV
+
V
1V/DIV
OUT
1V/DIV
OUT
1V/DIV
500µs
6992 G54
6992 G55
100µs/DIV
+
50µs/DIV
+
V
= 2.5V
V = 3.3V
DIVCODE = 12 (÷64, POL = 1)
DIVCODE = 1
R = 100k
SET
R
MOD
= 50k
SET
V
= 0.2V (~87.5% DUTY CYCLE)
69921234fc
11
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
pin FuncTions (DCB/S6)
V (Pin1/Pin5):SupplyVoltage(2.25Vto5.5V).Thissup-
ply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1μF capacitor.
+
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the V voltage.
SET
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. The DIV pin voltage (V ) is internally converted
DIV
+
V
into a 4-bit result (DIVCODE). V may be generated by
DIV
+
MOD
OUT
a resistor divider between V and GND. Use 1% resistors
LTC6992
+
V
to ensure an accurate result. The DIV pin and resistors
should be shielded from the OUT pin or any other traces
that have fast edges. Limit the capacitance on the DIV pin
+
GND
SET
V
C1
0.1µF
R1
R2
DIV
to less than 100pF so that V settles quickly. The MSB of
DIV
6992 PF
R
SET
DIVCODE (POL) determines if the PWM signal is inverted
before driving the output. When POL = 1 the transfer func-
tionisinverted(dutycycledecreasingasV
increases).
MOD
MOD (Pin 4/Pin 1): Pulse-Width Modulation Input. The
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (V ) is regulated to 1V above GND. The
voltageontheMODpincontrolstheoutputdutycycle. The
SET
linear control range is between 0.1•V
and 0.9•V
SET
SET
amount of current sourced from the SET pin (I ) pro-
SET
(approximately 100mV to 900mV). Beyond those limits,
the output will either clamp at 5% or 95%, or stop oscil-
lating(0%or100%dutycycle), dependingontheversion.
grams the master oscillator frequency. The I
current
SET
range is 1.25μA to 20μA. The output oscillation will stop
if I drops below approximately 500nA. A resistor con-
SET
GND(Pin5/Pin2):Ground.Tietoalowinductanceground
plane for best performance.
nected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
50ppm/°C or better temperature coefficient. For lower ac-
curacy applications an inexpensive 1% thick film resistor
may be used.
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
+
fromGNDtoV withanoutputresistanceofapproximately
30Ω. The duty cycle is determined by the voltage on the
MOD pin. When driving an LED or other low-impedance
load a series output resistor should be used to limit the
source/sink current to 20mA.
69921234fc
12
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
block DiagraM (S6 Package Pin Numbers Shown)
+
V
5
R1
POL
DIV
4-BIT A/D
CONVERTER
DIGITAL
FILTER
4
R2
OUTPUT
POLARITY
MASTER OSCILLATOR
PULSE WIDTH MODULATOR
I
SET
MCLK
PROGRAMMABLE DIVIDER
÷1, 4, 16, 64, 256, 1024, 4096, 16384
f
= 1MHz • 50kΩ •
OSC
V
V
– 0.1•V
MOD(LIM) SET
t
SET
ON
DUTY CYCLE =
0.8•V
OUT
SET
6
t
OUT
DISABLE OUTPUT
UNTIL SETTLED
HALT OSCILLATOR
IF I < 500nA
SET
t
t
ON
D =
V
MOD(LIM)
OUT
POR
VOLTAGE LIMITER
+
–
V
+
–
REF
V
= 1V
SET
1V
V
MOD
1
3
2
6992 BD
SET
GND
MOD
I
SET
R
SET
69921234fc
13
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
operaTion
The LTC6992 is built around a master oscillator with a
DIVCODE
1MHz maximum frequency. The oscillator is controlled
+
TheDIVpinconnectstoaninternal,V referenced4-bitA/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6992:
by the SET pin current (I ) and voltage (V ), with a
SET
SET
1MHz • 50k conversion factor that is accurate to ±0.8%
under typical conditions.
1. DIVCODE determines the output frequency divider set-
ISET
VSET
1
fMASTER
=
=1MHz • 50k •
ting, N
.
DIV
tMASTER
2. DIVCODE determines the output polarity, via the POL
bit.
A feedback loop maintains V at 1V 30mV, leaving I
SET
SET
as the primary means of controlling the output frequency.
The simplest way to generate I is to connect a resistor
+
V
DIV
may be generated by a resistor divider between V
SET
and GND as shown in Figure 1.
(R ) between SET and GND, such that I = V /R .
SET
SET
SET SET
The master oscillator equation reduces to:
1
1MHz •50k
fMASTER
=
=
2.25V TO 5.5V
tMASTER
RSET
+
V
LTC6992
R1
R2
From this equation, it is clear that V drift will not affect
SET
theoutputfrequencywhenusingasingleprogramresistor
DIV
(R ). Error sources are limited to R
tolerance and
SET
SET
the inherent frequency accuracy ∆f
of the LTC6992.
GND
OUT
6992 F01
R
may range from 50k to 800k (equivalent to I
SET
SET
between 1.25μA and 20μA).
Figure 1. Simple Technique for Setting DIVCODE
The LTC6992 includes a programmable frequency divider
which can further divide the frequency by 1, 4, 16, 64,
256, 1024, 4096 or 16384 before driving the OUT pin.
The divider ratio N is set by a resistor divider attached
DIV
to the DIV pin.
ISET
VSET
1
tOUT
1MHz •50k
fOUT
=
=
•
NDIV
With R in place of V /I the equation reduces to:
SET
SET SET
1
1MHz •50k
fOUT
=
=
tOUT NDIV •RSET
69921234fc
14
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
operaTion
Table 1. DIVCODE Programming
+
DIVCODE
POL
0
N
RECOMMENDED f
R1 (kΩ)
Open
976
R2 (kΩ)
Short
102
V
/V
DIV
DIV
OUT
0
1
1
62.5kHz to 1MHz
15.63kHz to 250kHz
3.906kHz to 62.5kHz
976.6Hz to 15.63kHz
244.1Hz to 3.906kHz
61.04Hz to 976.6Hz
15.26Hz to 244.1Hz
3.815Hz to 61.04Hz
3.815Hz to 61.04Hz
15.26Hz to 244.1Hz
61.04Hz to 976.6Hz
244.1Hz to 3.906kHz
976.6Hz to 15.63kHz
3.906kHz to 62.5kHz
15.63kHz to 250kHz
62.5kHz to 1MHz
≤0.03125 0.015
0.09375 0.015
0.15625 0.015
0.21875 0.015
0.28125 0.015
0.34375 0.015
0.40625 0.015
0.46875 0.015
0.53125 0.015
0.59375 0.015
0.65625 0.015
0.71875 0.015
0.78125 0.015
0.84375 0.015
0.90625 0.015
≥0.96875 0.015
0
4
2
0
16
64
976
182
3
0
1000
1000
1000
1000
1000
887
280
4
0
256
1024
4096
16384
16384
4096
1024
256
64
392
5
0
523
6
0
681
7
0
887
8
1
1000
1000
1000
1000
1000
976
9
1
681
10
11
12
13
14
15
1
523
1
392
1
280
1
16
182
1
4
102
976
1
1
Short
Open
Table 1 offers recommended 1% resistor values that ac-
curatelyproducethecorrectvoltagedivisionaswellasthe
column in Table 1 shows the ideal ratio of V
to the
DIV
supply voltage, which can also be calculated as:
correspondingN andPOLvaluesfortherecommended
DIV
VDIV
V+
DIVCODE+ 0.5
=
1.5ꢀ
resistor pairs. Other values may be used as long as:
16
+
1. The V /V ratio is accurate to 1.5% (including resis-
DIV
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
tor tolerances and temperature effects).
is 4, V = 0.281 • 3.3V = 928mV ± 50mV.
DIV
2. Thedrivingimpedance(R1||R2)doesnotexceed500kΩ.
If the voltage is generated by other means (i.e. the output
Figure 2 illustrates the information in Table 1, showing
that N is symmetric around the DIVCODE midpoint.
DIV
+
of a DAC) it must track the V supply voltage. The last
POL BIT = 0
1000
POL BIT = 1
15
0
100
1
14
13
2
10
3
12
11
1
0.1
4
10
5
9
6
7
8
0.01
0.001
+
+
0V
0.5•V
V
INCREASING V
DIV
6992 F02
Figure 2. Frequency Range and POL Bit vs DIVCODE
69921234fc
15
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
operaTion
Pulse Width (Duty Cycle) Modulation
Output Polarity (POL Bit)
The MOD pin is a high impedance analog input providing
direct control of the output duty cycle. The duty cycle is
The duty cycle equation describes a proportional transfer
function, where duty cycle increases as V
increases.
MOD
proportional to the voltage applied to the MOD pin, V
.
The LTC6992 includes a POL bit (determined by the
DIVCODE as described earlier) that inverts the output
signal. This makes the duty cycle gain negative, reducing
MOD
VMOD
0.8 • VSET
1
8
Duty Cycle = D =
−
duty cycle as V
increases.
MOD
The PWM duty cycle accuracy ∆D specifies that the above
equation is valid to within 4.5% for V between 0.2 •
MOD
POL = 0
VMOD
1
8
V
and 0.8 • V (12.5% to 87.5% duty cycle).
SET
SET
D=
−
0.8 • VSET
D•t
OUT
Since V
= 1V 30mV, the duty cycle equation may be
SET
approximated by the following equation.
OUT
VMOD −100mV
Duty Cycle = D ≅
t
OUT
800mV
POL = 1
VMOD
1
8
The V
control range is approximately 0.1V to 0.9V.
MOD
D=1−
−
MOD
Driving V
D•t
OUT
0.8 • V
SET
+
beyond that range (towards GND or V ) will
have no further affect on the duty cycle.
OUT
Duty Cycle Limits
6992 F03
t
OUT
The only difference between the four versions of the
LTC6992 is the limits, or clamps, placed on the output
duty cycle. The LTC6992-1 generates output duty cycles
ranging from 0% to 100%. At 0% or 100% the output
Figure 3. POL Bit Functionality
+
will stop oscillating and rest at GND or V , respectively.
The LTC6992-2 will never stop oscillating, regardless of
the V
level. Internal clamping circuits limit its duty
MOD
cycle to a 5% to 95% range (1% to 99% guaranteed).
Therefore, its V control range is 0.14 • V to 0.86 •
MOD
SET
V
SET
(approximately 0.14V to 0.86V).
The LTC6992-3 and LTC6992-4 complete the family by
providing one-sided clamping. The LTC6992-3 allows
0% to 95% duty cycle, and the LTC6992-4 allows 5% to
100% duty cycle.
69921234fc
16
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
operaTion
Table 2. Duty Cycle Ranges
DUTY CYCLE RANGE vs V
POL = 1 forces a simple logic inversion, so it changes the
dutycyclerangeoftheLTC6992-3(makingit100%to5%)
and LTC6992-4 (making it 95% to 0%). These transfer
functions are detailed in Figure 4.
= 0V → 1V
MOD
PART NUMBER
LTC6992-1
LTC6992-2
LTC6992-3
LTC6992-4
POL = 0
POL = 1
0% to 100%
5% to 95%
0% to 95%
5% to 100%
100% to 0%
95% to 5%
100% to 5%
95% to 0%
100
100
90
80
70
60
50
40
30
20
10
0
V
/V
= 0.1
MOD SET
90
80
70
60
50
40
30
20
10
0
V
/V
= 0.14
MOD SET
POL = 0
POL = 1
POL = 0
POL = 1
V
/V
= 0.86
MOD SET
V
/V
= 0.9
MOD SET
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
/V (V/V)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
/V (V/V)
1
V
V
MOD SET
MOD SET
6992 F04a
6992 F04b
LTC6992-1
LTC6992-2
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
/V
= 0.14
V
/V
= 0.1
MOD SET
MOD SET
POL = 0
POL = 1
POL = 0
POL = 1
V
/V
= 0.9
V
/V
= 0.86
MOD SET
MOD SET
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
/V (V/V)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
/V (V/V)
1
V
V
MOD SET
MOD SET
6992 F02d
6992 F02c
LTC6992-3
LTC6992-4
Figure 4. PWM Transfer Functions for All LTC6992 Family Parts
69921234fc
17
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
operaTion
Changing DIVCODE After Start-Up
Start-Up Time
Following start-up, the A/D converter will continue
When power is first applied, the power-on reset (POR)
monitoring V for changes. Changes to DIVCODE will
circuit will initiate the start-up time, t
. The OUT pin
DIV
START
be recognized slowly, as the LTC6992 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
is held low during this time. The typical value for t
START
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of N ):
DIV
t
= 500 • t
MASTER
START(TYP)
The output will begin oscillating after t . If POL = 0
START
t
= 16 • (∆DIVCODE + 6) • t
MASTER
DIVCODE
the first pulse has the correct width. If POL = 1 (DIVCODE
≥ 8), the first pulse width can be shorter or longer than
expected, depending on the duty cycle setting, and will
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes.
AdigitalfilterisusedtoguaranteetheDIVCODEhassettled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
never be less than 25% of t
.
OUT
Duringstart-up,theDIVpinA/Dconvertermustdetermine
the correct DIVCODE before the output is enabled. The
start-up time may increase if the supply or DIV pin volt-
ages are not stable. For this reason, it is recommended to
minimize the capacitance on the DIV pin so it will properly
+
track V . Less than 100pF will not affect performance.
DIV
0.5V/DIV
512µs
+
V
OUT
1V/DIV
DIV
STABLE V
DIV
6992 F05
100µs/DIV
+
V
= 3.3V
R
= 200k
SET
t
DIVCODE
V
= 0.3V
MOD
t
START
OUT
Figure 5. DIVCODE Change from 3 to 1
6992 F06
1ST PULSE WIDTH MAY BE INACCURATE
Figure 6. Start-Up Timing Diagram
69921234fc
18
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
applicaTions inForMaTion
Basic Operation
To minimize supply current, choose the lowest N value
DIV
(generallyrecommended).Forfasterstart-upordecreased
The simplest and most accurate method to program the
jitter,chooseahigherN setting.Alternatively,useTable1
DIV
LTC6992 is to use a single resistor, R , between the
SET
as a guide to select the best N value for the given ap-
DIV
SET and GND pins. The design procedure is a four step
plication.
process. After choosing the proper LTC6992 version and
POL bit setting, select the N value and then calculate
With POL already chosen, this completes the selection of
DIV
the value for the R resistor.
DIVCODE. Use Table 1 to select the proper resistor divider
SET
+
or V /V ratio to apply to the DIV pin.
DIV
Alternatively, Linear Technology offers the easy to use
TimerBlox Designer tool to quickly design any LTC6992
based circuit. Download the free TimerBlox Designer
software at www.linear.com/timerblox.
Step 4: Calculate and Select R
SET
The final step is to calculate the correct value for R
using the following equation.
SET
Step 1: Selecting the POL Bit Setting
1MHz •50k
NDIV • fOUT
RSET
=
(1b)
Most applications will use POL = 0, resulting in a positive
transferfunction.However,someapplicationsmayrequire
Select the standard resistor value closest to the calculated
value.
a negative transfer function, where increasing V
re-
MOD
duces the output duty cycle. For example, if the LTC6992
is used in a feedback loop, POL = 1 may be required to
achieve negative feedback.
Example:DesignaPWMcircuitthatsatisfiesthefollowing
requirements:
• f
= 20kHz
Step 2: Selecting the LTC6992 Version
OUT
• Positive V
to duty cycle response
ThedifferencebetweentheLTC6992versionsisobservedat
theendpointsofthedutycyclecontrolrange. Applications
thatrequiretheoutputtoneverstoposcillatingshoulduse
the LTC6992-2. On the other hand, if the output should be
MOD
• Output can reach 100% duty cycle, but not 0%
• Minimum power consumption
+
allowed to rest at GND or V (0% or 100% duty cycle),
Step 1: Selecting the POL Bit Setting
select the LTC6992-1.
For positive transfer function (duty cycle increases with
MOD
The LTC6992-3 and LTC6992-4 clamp the duty cycle at
only one end of the control range, allowing the output to
stop oscillating at the other extreme. If POL = 1 the clamp
will swap from low duty cycle to high, or vice-versa. Refer
to Table 2 and Figure 4 for assistance in selecting the
proper version.
V
), choose POL = 0.
Step 2: Selecting the LTC6992 Version
To limit the minimum duty cycle, but allow the maximum
duty cycle to reach 100%, choose LTC6992-4. (Note that
if POL = 1 the LTC6992-3 would be the correct choice.)
Step 3: Selecting the N Frequency Divider Value
DIV
Step 3: Selecting the N Frequency Divider Value
DIV
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
Choose an N
value that meets the requirements of
DIV
Equation (1a).
N
value. For a given output frequency, N should be
DIV
DIV
selected to be within the following range.
3.125 ≤ N ≤ 50
DIV
62.5kHz
fOUT
1MHz
fOUT
Potential settings for N include 4 and 16. N = 4 is
DIV
DIV
≤ NDIV
≤
(1a)
the best choice, as it minimizes supply current by us-
69921234fc
19
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
applicaTions inForMaTion
Figure8demonstratestheworst-caseimpactofthisvaria-
ing a large R
resistor. POL = 0 and N = 4 requires
SET
DIV
tion (if V is at its 0.97V or 1.03V limits).
DIVCODE = 1. Using Table 1, choose the R1 and R2 values
to program DIVCODE = 1.
SET
This error is in addition to the inherent PWM duty cycle
accuracy spec ∆D ( 4.5%), so care should be taken if
Step 4: Select R
SET
accuracy at high duty cycles (V
near 0.9V) is critical.
MOD
Calculate the correct value for R using Equation (1b).
SET
Sensitivity to ∆V
can be eliminated by making V
MOD
SET
1MHz •50k
4•20kHz
proportionaltoV .Forexample,Figure9showsasimple
SET
RSET
=
= 625k
circuit for generating an arbitrary duty cycle. The equation
for duty cycle does not depend on V at all.
SET
Since 625k is not available as a standard 1% resistor,
substitute 619k if a 0.97% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
100
90
∆V
= –30mV
SET
80
70
60
50
40
30
20
10
0
The completed design is shown in Figure 7.
∆V
= 0mV
SET
∆V
= 30mV
SET
V
MOD
MOD
GND
SET
OUT
LTC6992-4
2.25V TO 5.5V
+
V
R1
976k
DIVCODE = 1
DIV
0
0.2
0.4
0.6
(V)
0.8
1
R2
102k
6992 F07
R
SET
V
MOD
625k
6992 F08
Figure 8. Duty Cycle Variation Due to ∆VSET
Figure 7. 20kHz PWM Oscillator
Duty Cycle Sensitivity to ∆V
SET
MOD
GND
SET
OUT
The output duty cycle is proportional to the ratio of V
/
MOD
LTC6992-X
2.25V TO 5.5V
R1
V
. Since V
can vary up to 30mV from 1V it can
SET
SET
+
V
effectively gain or attenuate V
, as shown below when
MOD
∆V is added to the equation.
SET
DIV
VMOD
0.8 • VSET + ∆VSET
1
8
6992 F09
R2
D=
−
R
R
SET1
(
)
RSET2
RSET1 +RSET2
5
4
1
8
D=
•
−
SET2
Formanydesigns,theabsoluteV
todutycycleaccuracy
MOD
is not critical. For others, making the simplifying assump-
tion of ∆V
= 0V creates the potential for additional
SET
Figure 9. Fixed-Frequency, Arbitrary Duty Cycle Oscillator
duty cycle error, which increases with V
, reaching a
MOD
maximum of 3.4% if ∆V = –30mV.
SET
VMOD ∆VSET
800mV VSET
1
8
∆VSET
•
∆D≅ −
•
≅ − D
+
IDEAL
VSET
69921234fc
20
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
applicaTions inForMaTion
I
Extremes (Master Oscillator Frequency Extremes)
Pulse Width Modulation Bandwidth and Settling Time
SET
When operating with I
outside of the recommended
TheLTC6992hasawidePWMbandwith,makingitsuitable
foravarietyoffeedbackapplications.Figure10showsthat
the frequency response is flat for modulation frequencies
up to nearly 1/10 of the output frequency. Beyond that
SET
1.25μA to 20μA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
point, some peaking may occur (depending on N and
DIV
The oscillator will still function with reduced accuracy for
average duty cycle setting).
I
<1.25µA.Atapproximately500nA,theoscillatoroutput
SET
will be frozen in its current state. The output could halt in
a high or low state. This avoids introducing short pulses
while frequency modulating a very low frequency output.
Duty cycle settling time depends on the master oscillator
frequency. Following a 80mV step change in V
, the
MOD
duty cycle takes approximately eight master clock cycles
(8 • t ) to settle to within 1% of the final value.
MASTER
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Examples are shown in Figures 11a and 11b.
10
5
÷4, 50%
÷16
÷1, 50%
0
÷1, 80%
÷4, 15%
–5
–10
–15
–20
0.001
0.01
0.1
1
f
/f
(Hz/Hz)
MOD OUT
6992 F10
Figure 10. PWM Frequency Response
V
MOD
V
MOD
0.1V/DIV
0.1V/DIV
OUT
2V/DIV
OUT
2V/DIV
DUTY CYCLE
5% DIV
DUTY CYCLE
5% DIV
6992 F11a
6992 F11b
10µs/DIV
10µs/DIV
+
+
V
= 3.3V
V
= 3.3V
DIVCODE = 0
DIVCODE = 0
R
V
= 200k
R
V
= 200k
SET
MOD
SET
MOD
= 0.3V ±±0ꢀV
= 0.5V ±±0ꢀV
Figure 11a. PWM Settling Time, 25% Duty Cycle
Figure 11b. PWM Settling Time, 50% Duty Cycle
69921234fc
21
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
applicaTions inForMaTion
Power Supply Current
+
1. Connect the bypass capacitor, C1, directly to the V and
GND pins using a low inductance path. The connection
from C1 to the V pin is easily done directly on the top
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under any
condition using the following equation:
+
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that,C1’sGNDconnectioncanbeaccomplishedthrough
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1μF ceramic capacitor.
If NDIV = 1 (DIVCODE = 0 or 15):
IS(TYP) ≈ V+ • fOUT • 39pF +C
(
)
LOAD
V+
V+ •Duty Cycle
+
+
+ 2.2•ISET + 85µA
320kΩ
RLOAD
If NDIV > 1 (DIVCODE = 1 or 14):
IS(TYP) ≈ V+ • NDIV • fOUT •27pF
+ V+ • fOUT • 28pF +C
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
(
)
LOAD
V+
320kΩ
V+ •Duty Cycle
3. Place R
as close as possible to the SET pin and
SET
+
+
+ 2.6 •ISET + 90µA
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
RLOAD
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
The LTC6992 is a 2.4% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
4. Connect R directly to the GND pin. Using a long path
SET
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
Figure14showsexamplePCBlayoutsforboththeTSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6992. These layouts are
a guide and need not be followed exactly.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
69921234fc
22
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
applicaTions inForMaTion
MOD
GND
SET
OUT
LTC6992
+
+
V
V
C1
0.1µF
R1
R2
DIV
R
SET
+
+
V
+
V
C1
R1
C1
V
OUT
GND
MOD
MOD
GND
SET
OUT
+
DIV
SET
V
R2
DIV
R1
R
SET
R
R2
SET
DFN PACKAGE
TSOT-23 PACKAGE
6992 F14
Figure 14. Supply Bypassing and PCB Layout
Constant On-Time Modulator
Typical applicaTions
V
MOD
OUT
C1
MOD
GND
SET
OUT
R
R
M2
M1
V
LTC6992-1
R
*
CC
IN
1.05k
9.31k
11.8k
V
CTRL
V
IN
+
V
R1
182k
DIVCODE = 2
(÷16, POL = 1)
0V TO 2V
R
44.2k
SET
0.1µF
V
SET
DIV
R2
6992 TA02
976k
*OPTIONAL RESISTOR ADJUSTS FOR DESIRED V RANGE.
IN
RSET
50k
RM2
RM1+RM2
IF
= 0.9 THEN tON = NDIV • 1.125µs •
AS V INCREASES, t
INCREASES AND DUTY CYCLE
IN
OUT
DECREASES (BECAUSE POL = 1) TO MAINTAIN A CONSTANT t
.
ON
FOR CONSTANT OFF-TIME, JUST CHANGE DIVCODE SO POL = 0.
69921234fc
23
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical applicaTions
Digitally Controlled Duty Cycle with Internal VREF Reference Variation Eliminated
MOD
GND
SET
OUT
+
LTC6992-X
V
+
V
+
0.1µF
V
C1
0.1µF
R1
R2
+
–
DIV
1/2
LTC6078
6992 TA03
R
SET
+
0.1µF
V
V
REF
CC
D
IN
LTC1659
V
OUT
µP
CLK
CS/LD
GND
Programming NDIV Using an 8-Bit DAC
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
DIVCODE DAC CODE
MOD
GND
SET
OUT
0
1
0
LTC6992-X
24
2
40
2.25V TO 5.5V
+
V
3
56
C1
0.1µF
C2
0.1µF
4
72
5
88
6
104
120
136
152
168
184
200
216
232
255
DIV
7
8
9
R
SET
V
CC
SDI
10
11
12
13
14
15
V
LTC2630-LZ8 SCK
µP
OUT
CS/LD
GND
6992 TA04
69921234fc
24
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical applicaTions
Changing Between Two Frequencies
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
MOD
GND
SET
OUT
MOD
GND
SET
OUT
LTC6992-X
LTC6992-X
+
+
+
+
V
V
V
V
+
V
0.1µF
0.1µF
R1
R2
R1
R2
f
MAX
R
VCO
DIV
DIV
f
MIN
+
R
R
SET2
R
SET1
V
SET
f
MIN
‘HC04
f
MAX
2N7002
‘HC04
6992 TA05
NOTES
NOTES
WHILE THIS CIRCUIT IS SIMPLER THAN THE CIRCUIT TO THE RIGHT,
1. WHEN THE NMOSFET IS OFF, THE FREQUENCY IS SET BY R
= R
SET1
= R
SET1
.
SET
SET
ITS FREQUENCY ACCURACY IS WORSE DUE TO THE EFFECT OF
2. WHEN THE NMOSFET IS ON, THE FREQUENCY IS SET BY R
|| R
.
SET2
+
+
V
SUPPLY VARIATION FROM SYSTEM TO SYSTEM AND OVER TEMPERATURE.
3. V SUPPLY VARIATION IS NOT A FACTOR AS THE SWITCHING RESISTOR IS
EITHER FLOATING OR CONNECTED TO GROUND.
Simple Diode Temperature Sensor
R8
84.5k
5V
5V
0.1µF
5V
0.1µF
R6
45.3k
R7
16.9k
+10mV/C
R9
–
+
365Ω
MOC207M
D3
MOD
GND
SET
OUT
D1
1N458
LT6003
Q1
LTC6992-2
+
5V
V
R4
1000k
OUTPUT
C1
1µF
0.1µF
R11
422Ω
DIV
R5
6992 TA06
R1
186k
130k
R2
N
= 16
50k
DIV
f = 10kHz
ADJUST FOR 50% DUTY CYCLE AT 25°C
R3
130k
PWM OUTPUT FOR ISOLATED MEASUREMENT
+1% DUTY CYCLE CHANGE PER DEGREE C
–10°C TO 65°C RANGE WITH OPTO-ISOLATOR (DC: 15% TO 95%)
69921234fc
25
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical applicaTions
Motor Speed/Direction Control for Full H-Bridge (Locked Anti-Phase Drive)
V
S
12V
A1
A2
2.6kHz, 5% TO 95% PWM
5% DC = CLOCKWISE
50% DC = STOPPED
CW CURRENT
FLOW
95% DC = COUNTER CLOCKWISE
MOTOR
INPUT 0V TO 1V
MOD
GND
SET
OUT
LTC6992-2
+
+
V
V
R1
1000k
0.1µF
POWER H-BRIDGE
HIGH = SWITCH ON
DIV
R3
300k
R2
280k
6992 TA07
Motor Speed/Direction Control for Full H-Bridge (Sign/Magnitude Drive)
V
S
12V
A5
A4
2.6kHz, 5% TO 95% PWM
5% DC = SLOW
95% DC = FAST
CW CURRENT
FLOW
MOTOR
INPUT 0V TO 1V
MOD
GND
SET
OUT
LTC6992-2
+
+
V
V
R4
1000k
0.1µF
POWER H-BRIDGE
HIGH = SWITCH ON
DIV
R3
300k
R5
280k
A3
DIRECTION
H = CCW, L = CW
6992 TA08
69921234fc
26
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical applicaTions
Ratiometric Sensor to Pulse Width, Non-Inverting Response
R6
9.09k
V
S
C2
0.22µF
0.1µF
C1
0.15µF
R4
90.9k
R5
10M
V
= 2.5V TO 5.5V
S
–
+
R3
10k
K = 1
OUTPUT
DUTY CYCLE = K • 100%
MOD
OUT
R
SENSOR
K = 0
LT1490
LTC6992-1
K• V
S
+
GND
SET
V
V
S
R1
1000k
0.1µF
DIV
R2
186k
6992 TA09
R
SET
316k
N
OUT
= 16
= 10kHz
DIV
f
Ratiometric Sensor to Pulse Width, Inverting Response
R6
9.09k
C2
0.22µF
V
S
0.1µF
V
S
= 2.5V TO 5.5V
R6
90.9k
C1
0.15µF
R3
100k
K = 1
R
SENSOR
K = 0
K • V
S
–
+
OUTPUT
DUTY CYCLE = (1–K) • 100%
R4
10k
MOD
GND
SET
OUT
LT1490
LTC6992-1
V
S
+
R5
10k
V
V
S
R1
0.1µF
1000k
DIV
R2
186k
6992 TA10
R
SET
316k
N
OUT
= 16
= 10kHz
DIV
f
69921234fc
27
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical applicaTions
Radio Control Servo Pulse Generator
R6
9.09k
R6
90.9k
C1
1µF
C2
0.22µF
V
S
V
S
= 2.5V TO 5.5V
0.1µF
R5
130k
–
+
OUTPUT
1ms TO 2ms PULSE EVERY 16ms
MOD
OUT
LT1490
LTC6992-1
R6
8.66k
+
GND
SET
V
V
S
R1
1000k
2ms
SERVO
CONTROL
POT
0.1µF
DIV
10k
R2
681k
1ms
6992 TA11
R
SET
196k
N
OUT
= 4096
= 62.5Hz, 16ms PERIOD
DIV
f
Direct Voltage Controlled PWM Dimming (0 to 15000 Cd/m2 Intensity)
R3
90.9Ω
V
MOD
GND
SET
OUT
DIMMING
LTC6992-1
D1
+
5V
V
HIGH INTENSITY LED
SSL-LX5093XUWC
C1
R1
1M
0.1µF
DIV
R2
280k
6992 TA12
R
SET
105k
f = 7.5kHz
= 64
N
DIV
69921234fc
28
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical applicaTions
Wide Range LED Dimming (0 to 85000 Cd/m2 Brightness)
R2
7.5k
V
FAST
5V
0.1µF
5V
FAST PWM
R1
10k
–
+
CONTROLS 6000 TO 85000
–
+
2
Cd/m BRIGHTNESS
MOD
OUT
LT6004
LT6004
LTC6992-4
+
GND
SET
V
R4
7.5k
R3
10k
5V
3.3V
3.3V
5V
PV
C4
R
DIV1
0.1µF
1M
V
REF
DIV
IN
IN
R
DIV2
+
LED
R
280k
SET1
61.9k
5–100%
= 64
A1
D1
D2
N
DIV
LT3518UF
f = 12.6kHz
PWM
V
DIMMING
0V TO 1.65V
SLOW PWM
CONTROLS 0 TO 6000
2
Cd/m BRIGHTNESS
V
SLOW
LUMILEDS LXHL-BW02
MOD
OUT
LTC6992-1
+
GND
SET
V
5V
C1
R
DIV3
0.1µF
1M
DIV
R
DIV4
R
681k
SET2
0–100%
124k
6992 TA13
N
= 4096
DIV
f
= 100Hz
OUT
69921234fc
29
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical applicaTions
Isolated PWM (5% to 95%) Controller
+
V
0.1µF
+
ISOV
R3
1k
0.1µF
R6
R14
10k
4.99k
ISOLATION
BARRIER
T1
R2
R9
R4
10k
–
+
–
+
LT1011
100k
20k
1kHz
SOURCE
PWM
ISOPWM
MOD
GND
OUT
MOD
GND
OUT
R16
100k
•
•
LT1011
C1
1µF
C2
0.1µF
LTC6992-2
LTC6992-2
R5
20k
R15
10k
L1
L2
+
+
+
V
V
ISOV
0.1µF
R7
1k
R8
10k
R1
10k
R12
1M
0.1µF
R17
10k
SET
DIV
SET
DIV
+
0.1µF
V
R11
787k
R13
280k
R10
499k
100kHz
1kHz
ISOLATED PWM
C3
1000pF
INTERMEDIATE PWM
–
+
6992 TA14
+
ISOV
0.1µF
R18
100k
LT1636
–
+
C4
1µF
LT1636
CONCEPT DESIGN USING SIMPLE R-C FILTERING FOR PWM CONTROL.
NOT OPTIMIZED FOR OFFSETS.
T1: PCA EPF8119S ETHERNET TRANSFORMER
69921234fc
30
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 0.05
1.65 0.05
3.55 0.05
(2 SIDES)
2.15 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
1.35 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
2.00 0.10
(2 SIDES)
0.40 0.10
TYP
R = 0.05
TYP
4
6
3.00 0.10 1.65 0.10
(2 SIDES)
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
(DCB6) DFN 0405
3
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
1.35 0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
69921234fc
31
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636 Rev B)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.4 MIN
1.50 – 1.75
(NOTE 4)
2.80 BSC
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302 REV B
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
69921234fc
32
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/11
2
4
Revised θ value for TSOT package in the Pin Configuration.
JA
Added Note 7 for V and V in the Electrical Characteristics table.
OH
OL
12
Minor edit to the Block Diagram.
19
Minor edit to the equation in the “Duty Cycle Sensitivity to ∆V ” section.
SET
25
Revised Typical Applications drawings.
B
C
07/11 Revised Description and Order Information sections
1 to 3
+
Added additional information to ∆f /∆V and included Note 11 in Electrical Characteristics section
3, 4
11
OUT
Added Typical Frequency Error vs Time curve to Typical Performance Characteristics section
Added text to Basic Operation paragraph in Applications Information section
19
Corrected f
value in Typical Applications drawing 6692 TA13
29
OUT
01/12 Added MP-Grade
1, 2, 3, 5
69921234fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Typical applicaTion
PWM Controller for LED Driver
L1
6.8µH
D1
V
IN
8V TO 16V
C1
0.22µF
R1
3.92M
SHDN
V
SW
FB
IN
R2
124k
LT3517
ANALOG PWM
DUTY CYCLE
CONTROL
300mA
PWM
TGEN
MOD
GND
SET
OUT
ISP
LTC6992-1
5V
C1
2.2µF
(0V TO 1V)
R
SENSE
V
REF
+
330mΩ
C2
4.7µF
V
CTRL
SYNC
ISN
TG
0.1µF
1M
DIV
V
C
R
SS GND
T
102k
681k
C4
0.1µF
C3
0.1µF
R
6.04k
2MHz
T
6992 TA15
C1: KEMET C0806C225K4RAC
C2: KEMET C1206C475K3RAC
C3, C4: MURATA GRM21BR71H104KA01B
C5: MURATA GRM21BR71H224KA01B
D1: DIODE DFLS160
L1: TOKO B992AS-6R8N
LEDS: LUXEON I (WHITE)
M1: ZETEX ZXMP6A13FTA
relaTeD parTs
PART NUMBER
LTC1799
DESCRIPTION
COMMENTS
Wide Frequency Range
Low Power, Wide Frequency Range
Micropower, I = 35µA at 400kHz
1MHz to 33MHz ThinSOT Silicon Oscillator
1MHz to 20MHz ThinSOT Silicon Oscillator
LTC6900
LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator
SUPPLY
LTC6930
LTC6990
LTC6991
LTC6993
LTC6994
Fixed Frequency Oscillator, 32.768kHz to 8.192MHz
TimerBlox, Voltage Controlled Oscillator
TimerBlox, Very Low Frequency Clock with Reset
TimerBlox, Monostable Pulse Generator
TimerBlox, Delay Block/Debouncer
0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
Frequency from 488Hz to 1MHz, No Caps, 2.2% Accurate
Cycle Time from 2ms to 9.5 Hours, No Caps, 2.2% Accurate
Resistor Set Pulse Width from 1µs to 34sec, No Caps, 3% Accurate
Resistor Set Delay from 1µs to 34sec, No Caps Required, 3% Accurate
69921234fc
LT 0112 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
34
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC6993CDCB-3#TRMPBF
LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C
Linear
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