LTM2883CY-3I#PBF_技术文档

LTM2883

2

SPI/Digital or I C µModule

Isolator with Adjustable 12.5V

and 5V Regulated Power

DESCRIPTION

FEATURES

n

2500V

for One Minute per UL1577

The LTM^®2883 is a complete galvanic 6-channel digital

µModule^®(micromodule)isolator.Noexternalcomponents

are required. A single 3.3V or 5V supply powers both

sides of the interface through an integrated, isolated DC/

DC converter. A logic supply pin allows easy interfacing

withdifferentlogiclevelsfrom1.62Vto5.5V, independent

of the main supply.

RMS

UL Recognized

File #E151738

®

n

Isolated Adjustable DC Power:

3V to 5V at Up to 30mA

12ꢀ5V at Up to 20mA

No External Components Required

n

2

SPI (LTM2883-S) or I C (LTM2883-I) Options

High Common Mode Transient Immunity: 30kV/μs

High Speed Operation:

2

Available options are compliant with SPI and I C (master

mode only) specifications.

10MHz Digital Isolation

The isolated side includes 12.5V and 5V nominal power

supplies, each capable of providing more than 20mA of

loadcurrent.Eachsupplymaybeadjustedfromitsnominal

value using a single external resistor.

4MHz/8MHz SPI Isolation

2

400kHz I C Isolation

n

3.3V (LTM2883-3) or 5V (LTM2883-5) Operation

1.62V to 5.5V Logic Supply

10kV ESD HBM Across the Isolation Barrier

Coupled inductors and an isolation power transformer

Maximum Continuous Working Voltage: 560V

Low Current Shutdown Mode (<10µA)

Low Profile (15mm × 11.25mm × 3.42mm)

BGA Package

PEAK

provide 2500V

of isolation between the input and out-

RMS

put logic interface. This device is ideal for systems where

the ground loop is broken, allowing for a large common

mode voltage range. Communication is uninterrupted for

common mode transients greater than 30kV/μs.

APPLICATIONS

All registered trademarks and trademarks are the property of their respective owners.

2

n

Isolated SPI or I C Interfaces

n

Industrial Systems

n

Test and Measurement Equipment

n

Breaking Ground Loops

TYPICAL APPLICATION

Isolated 4MHz SPI Interface

ꢇꢀꢈ2883ꢉꢊꢋ

ꢌ

ꢍꢍ2

LTM2883 Operating Through 35kV/µs CM Transient

ꢊꢌ ꢁꢀ 2ꢂꢗꢁ

ꢌ

ꢍꢍ

ꢁꢌ

ꢊꢌ

ꢍꢍ2

ꢇꢈꢉ

ꢇꢄꢀ

ꢇꢈꢉ2 ꢊ ꢇꢄꢀ2

ꢒ

ꢌ

ꢇ

ꢃ2ꢘꢊꢌ ꢁꢀ 2ꢂꢗꢁ

ꢓꢃ2ꢘꢊꢌ ꢁꢀ ꢃꢊꢗꢁ

ꢒ

ꢁꢌ

ꢌ

ꢅꢆ

ꢓ

2ꢆꢃꢄꢅꢆ

ꢁꢌ

SDOE

CS

CS2

ꢋꢏꢐ2

ꢋꢍꢑ2

ꢏꢐꢑꢐꢋꢅꢋꢅꢆꢐ

ꢈꢒꢓꢓꢒꢔ ꢓꢒꢄꢐ

ꢋꢏꢌꢔꢇꢅꢐꢔꢋꢇ

CS

ꢋꢏꢐ

CS

ꢋꢏꢐ

ꢋꢍꢑ

ꢏꢅ2

ꢋꢏꢅ

ꢏꢅꢃ

ꢐ2

ꢋꢏꢅ2

ꢐꢃ

2ꢀꢀꢆꢃꢄꢅꢆ

ꢋꢏꢅ

2883 ꢋꢌꢀꢍꢎ

2ꢀꢁꢂꢃꢄꢅꢆ

ꢎꢆꢏ

ꢎꢆꢏ2

2883 ꢀꢁꢂꢃꢄ

2883fd

1

For more information www.linear.com/LTM2883

LTM2883

ABSOLUTE MAXIMUM RATINGS

(Note 1)

V

to GND .................................................. –0.3V to 6V

Logic Outputs

CC

V to GND .................................................... –0.3V to 6V

L

DO1, DO2, SDO to GND ..............–0.3V to (V + 0.3V)

L

+

V

, AV , AV to GND2 ........................... –0.3V to 6V

O1, SCK2, SDI2, CS2,

CC2

+

V to GND2 ................................................ –0.3V to 16V

SCL2 to GND2 ........................–0.3V to (V

+ 0.3V)

CC2

–

V , AV to GND2 .........................................0.3V to –16V

Logic Inputs

Operating Temperature Range (Note 4)

LTM2883C.........................................0°C ≤ T ≤ 70°C

A

DI1, SCK, SDI, CS, SCL, SDA, SDOE,

LTM2883I ..................................... –40°C ≤ T ≤ 85°C

ON to GND..................................–0.3V to (V + 0.3V)

LTM2883H...................................–40°C ≤ T ≤ 105°C

L

A

I1, I2, SDA2,

SDO2 to GND2........................–0.3V to (V

Maximum Internal Operating Temperature............ 125°C

Storage Temperature Range .................. –40°C to 125°C

Peak Body Reflow Temperature ............................ 245°C

+ 0.3V)

CC2

PIN CONFIGURATION

LTM2883-I

LTM2883-S

ꢖꢅꢌ ꢀꢊꢎꢗ

ꢆ

2

3

ꢔ

ꢑ

ꢜ

ꢝ

8

ꢆ

2

3

ꢔ

ꢑ

ꢜ

ꢝ

8

ꢄꢅ2 ꢄꢃꢁ ꢞꢁꢚ ꢞꢄꢇ ꢄꢊꢆ ꢂꢃꢄ ꢅꢃ

ꢀ

ꢞꢄꢅ ꢄꢅ2 ꢞꢁꢍ ꢞꢄꢊ CS SDOE ꢅꢃ

ꢀ

ꢚ

ꢇ

ꢋ

ꢁ

ꢄ

ꢎ

ꢘ

ꢇ

ꢋ

ꢁ

ꢄ

ꢎ

ꢘ

ꢄꢅꢆ

ꢂꢃꢄ

ꢀ

ꢄꢅꢆ

ꢂꢃꢄ

ꢀ

ꢁꢁ

ꢂ

ꢙ

ꢛ

ꢂ

ꢙ

ꢛ

ꢉ

ꢈ

ꢉ

ꢈ

ꢊꢆ

ꢂꢃꢄ2

ꢇꢀ

ꢊꢆ

ꢂꢃꢄ2

ꢇꢀ

ꢁꢁ2

ꢍ

ꢚ

ꢍ

ꢚ

ꢉ

ꢈ

ꢉ

ꢈ

ꢊ2 ꢄꢃꢁ ꢞꢁꢚ2 ꢞꢄꢇ2 ꢅꢆ

ꢋꢂꢇ ꢌꢇꢁꢍꢇꢂꢎ

ꢀ

ꢞꢄꢅ2 ꢊ2 ꢞꢁꢍ2 ꢞꢄꢊ2 CS2

ꢀ

ꢁꢁ2

ꢋꢂꢇ ꢌꢇꢁꢍꢇꢂꢎ

32ꢏꢌꢊꢃ ꢐꢆꢑꢒꢒ × ꢆꢆꢓ2ꢑꢒꢒ × 3ꢓꢔ2ꢒꢒꢕ

T

= 125°C, θ = 30°C/W, θ = 15.7°C/W,

T

= 125°C, θ = 30°C/W, θ

= 15.7°C/W,

JMAX

JA

JC(BOTTOM)

JMAX

JA

JC(BOTTOM)

θ

= 25°C/W, θ

= 14.5°C/W

θ

= 25°C/W, θ

= 14.5°C/W

JC(TOP)

JBOARD

JC(TOP)

JBOARD

θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g

2883fd

2

For more information www.linear.com/LTM2883

LTM2883

ORDER INFORMATION

http://wwwꢀlinearꢀcom/product/LTM2883#orderinfo

PART NUMBER

INPUT

VOLTAGE

PAD OR BALL

FINISH

PART MARKING

PACKAGE

TYPE

MSL

RATING

TEMPERATURE

RANGE

DEVICE

FINISH CODE

LTM2883CY-3S#PBF

LTM2883IY-3S#PBF

LTM2883HY-3S#PBF

LTM2883CY-5S#PBF

LTM2883IY-5S#PBF

LTM2883HY-5S#PBF

LTM2883CY-3I#PBF

LTM2883IY-3I#PBF

LTM2883HY-3I#PBF

LTM2883CY-5I#PBF

LTM2883IY-5I#PBF

LTM2883HY-5I#PBF

0°C TO 70°C

–40°C TO 85°C

–40°C TO 105°C

0°C TO 70°C

3V TO 3.6V

4.5V TO 5.5V

3V TO 3.6V

LTM2883Y-3S

LTM2883Y-5S

LTM2883Y-3I

LTM2883Y-5I

–40°C TO 85°C

–40°C TO 105°C

0°C TO 70°C

SAC305

(RoHS)

e1

BGA

4

–40°C TO 85°C

–40°C TO 105°C

0°C TO 70°C

4.5V TO 5.5V

–40°C TO 85°C

–40°C TO 105°C

• Device temperature grade is indicated by a label on the shipping

container.

• Recommended BGA PCB Assembly and Manufacturing Procedures:

www.linear.com/BGA-assy

• Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Terminal Finish Part Marking: www.linear.com/leadfree

• BGA Package and Tray Drawings: www.linear.com/packaging

• This product is moisture sensitive. For more information, go to:

www.linear.com/BGA-assy

• This product is not recommended for second side reflow. For more

information, go to: www.linear.com/BGA-assy

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°Cꢀ LTM2883-3 V_CC= 3ꢀ3V, LTM2883-5 V_CC= 5V, V_L= 3ꢀ3V, and GND =

GND2 = 0V, ON = V_Lunless otherwise notedꢀ Specifications apply to all options unless otherwise notedꢀ

SYMBOL PARAMETER

Input Supplies

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Input Supply Range

Logic Supply Range

Input Supply Current

LTM2883-3

LTM2883-5

3

3.3

5

3.6

5.5

V

CC

4.5

l

V

LTM2883-S

LTM2883-I

1.62

3

5.5

V

L

5

l

I

ON = 0V

0

25

19

10

35

28

µA

mA

CC

LTM2883-3, ON = V , No Load

L

LTM2883-5, ON = V , No Load

l

Logic Supply Current

ON = 0V

0

10

µA

L

LTM2883-S, ON = V

L

LTM2883-I, ON = V

150

2883fd

3

For more information www.linear.com/LTM2883

LTM2883

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°Cꢀ LTM2883-3 V_CC= 3ꢀ3V, LTM2883-5 V_CC= 5V, V_L= 3ꢀ3V, and GND =

GND2 = 0V, ON = V_Lunless otherwise notedꢀ Specifications apply to all options unless otherwise notedꢀ

SYMBOL PARAMETER

Output Supplies

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Regulated Output Voltage

Output Voltage Operating Range

Line Regulation

No Load

(Note 2)

4.75

3

5

5.25

5.5

V

CC2

l

I

= 1mA, MIN ≤ V ≤ MAX

25

8

100

80

mV

LOAD

CC

Load Regulation

= 100µA to 20mA

= 20mA (Note 2)

= 0V

ADJ Pin Voltage

585

600

1

615

Voltage Ripple

mV

RMS

Efficiency

45

%

I

Output Short Circuit Current

Current Limit

V

mA

V

CC2

l

ΔV

= –5%

20

12

CC2

+

V

Regulated Output Voltage

Line Regulation

No Load

12.5

5

13

30

I

= 1mA, MIN ≤ V ≤ MAX

mV

LOAD

CC

Load Regulation

= 100µA to 20mA

= 20mA (Note 2)

200

1.260

ADJ Pin Voltage

1.170

1.220

3

Voltage Ripple

mV

RMS

Efficiency

45

%

LOAD

+

I

Output Short Circuit Current

Current Limit

V = 0V

70

mA

V

+

l

ΔV = –0.5V

20

–

V

Regulated Output Voltage

Line Regulation

No Load

–12

–12.5

4

–13

15

I

= –1mA, MIN ≤ V ≤ MAX

mV

LOAD

CC

+

Load Regulation

= 100µA to 15mA, V

= 1.5mA

35

LOAD

+

l

ADJ Pin Voltage

= 100µA to 15mA, V

–1.184

10

–1.220

2

–1.256

+

Voltage Ripple

= 15mA, V

= 1.5mA (Note 2)

mV

RMS

LOAD

Efficiency

= 15mA (Note 2)

45

%

LOAD

–

I

Output Short-Circuit Current

Current Limit

V = 0V

30

mA

–

+

l

ΔV = 0.5V, V = 1.5mA

15

Logic/SPI

l

V

ITH

Input Threshold Voltage

ON, DI1, SDOE, SCK, SDI, CS 1.62V ≤ V < 2.35V

0.25 • V

0.33 • V

0.75 • V

0.67 • V

V

L

ON, DI1, SDOE, SCK, SDI, CS 2.35V ≤ V

L

I1, I2, SDO2

0.33 • V

0.67 • V

CC2

l

I

Input Current

1

µA

mV

V

INL

V

Input Hysteresis

Output High Voltage

(Note 2)

150

HYS

OH

l

DO1, DO2, SDO

V – 0.4

L

I

= –1mA, 1.62V ≤ V < 3V

= –4mA, 3V ≤ V ≤ 5.5V

LOAD

L

l

O1, SCK2, SDI2, CS2, I

= –4mA

V

– 0.4

CC2

V

LOAD

V

Output Low Voltage

Short-Circuit Current

DO1, DO2, SDO

0.4

OL

I

= 1mA, 1.62V ≤ V < 3V

LOAD

L

= 4mA, 3V ≤ V ≤ 5.5V

L

l

O1, SCK2, SDI2, CS2, I

= 4mA

0.4

85

V

LOAD

I

0V ≤ (DO1, DO2, SDO) ≤ V

0V ≤ (O1, SCK2, SDI2, CS2) ≤ V

mA

SC

L

60

CC2

2883fd

4

For more information www.linear.com/LTM2883

LTM2883

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°Cꢀ LTM2883-3 V_CC= 3ꢀ3V, LTM2883-5 V_CC= 5V, V_L= 3ꢀ3V, and GND =

GND2 = 0V, ON = V_Lunless otherwise notedꢀ Specifications apply to all options unless otherwise notedꢀ

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

2

I C

l

V

Low Level Input Voltage

High Level Input Voltage

SCL, SDA

SDA2

0.3 • V

V

IL

L

0.3 • V

CC2

l

V

SCL, SDA

SDA2

0.7 • V

V

IH

L

0.7 • V

CC2

l

I

Input Current

SCL, SDA = V or 0V

1

µA

INL

L

V

Input Hysteresis

SCL, SDA

SDA2

0.05 • V

mV

HYS

L

0.05 • V

CC2

l

Output High Voltage

Output Low Voltage

SCL2, I

= –2mA

V

– 0.4

CC2

L

V

OH

LOAD

DO2, I

= –2mA

V – 0.4

LOAD

l

SDA, V = 3V, I

= 3mA

= 2mA

0.4

0.45

0.55

V

OL

L

LOAD

= 2mA

DO2, V = 3V, I

L

SCL2, I

LOAD

SDA2, No Load, SDA = 0V, 4.5V ≤ V

< 5.5V

CC2

SDA2, No Load, SDA = 0V, 3V < V

< 4.5V

0.3

l

C

Input Pin Capacitance

Bus Capacitive Load

SCL, SDA, SDA2 (Note 2)

10

pF

IN

B

l

SCL2, Standard Speed (Note 2)

SCL2, Fast Speed

SDA, SDA2, SR ≥ 1V/μs, Standard Speed (Note 2)

SDA, SDA2, SR ≥ 1V/μs, Fast Speed

400

200

400

200

pF

l

Minimum Bus Slew Rate

Short-Circuit Current

SDA, SDA2

1

V/µs

I

SDA2 = 0, SDA = V

100

mA

SC

L

0V ≤ SCL2 ≤ V

30

CC2

L

0V ≤ DO2 ≤ V

SDA = 0, SDA2 = V

6

CC2

SDA = V , SDA2 = 0

–1.8

L

ESD (HBM) (Note 2)

Isolation Boundary

+

–

(V , V , V , GND2) to (V , V , GND)

10

kV

CC2

CC

L

SWITCHING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°Cꢀ LTM2883-3 V_CC= 3ꢀ3V, LTM2883-5 V_CC= 5V, V_L= 3ꢀ3V, and GND =

GND2 = 0V, ON = V_Lunless otherwise notedꢀ Specifications apply to all options unless otherwise notedꢀ

SYMBOL PARAMETER

Logic

CONDITIONS

MIN

TYP

MAX

UNITS

l

Maximum Data Rate

10

35

MHz

ns

Ix → DOx, C = 15pF (Note 3)

L

t

, t

Propagation Delay

Rise Time

C = 15pF (Figure 1)

L

60

100

PHL PLH

l

C = 15pF (Figure 1)

3

20

12.5

35

ns

R

L

LTM2883-I, DO2, C = 15pF (Figure 1)

L

l

t

Fall Time

C = 15pF (Figure 1)

3

20

12.5

35

ns

F

L

LTM2883-I, DO2, C = 15pF (Figure 1)

L

SPI

l

Maximum Data Rate

Bidirectional Communication (Note 3)

Unidirectional Communication (Note 3)

4

8

MHz

l

t

, t

Propagation Delay

C = 15pF (Figure 1)

35

60

100

50

ns

PHL PLH

L

Output Pulse Width Uncertainty

SDI2, CS2 (Note 2)

–20

PWU

2883fd

5

For more information www.linear.com/LTM2883

LTM2883

SWITCHING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°Cꢀ LTM2883-3 V_CC= 3ꢀ3V, LTM2883-5 V_CC= 5V, V_L= 3ꢀ3V, and GND =

GND2 = 0V, ON = V_Lunless otherwise notedꢀ Specifications apply to all options unless otherwise notedꢀ

SYMBOL PARAMETER

CONDITIONS

C = 15pF (Figure 1)

MIN

TYP

3

MAX

12.5

50

UNITS

ns

l

t

Rise Time

R

F

L

Fall Time

C = 15pF (Figure 1)

L

3

ns

, t

Output Enable Time

Output Disable Time

ns

SDOE = ↓, R = 1kΩ, C = 15pF (Figure 2)

PZH PZL

L

, t

50

ns

SDOE = ↑, R = 1kΩ, C = 15pF (Figure 2)

PHZ PLZ

L

2

I C

l

Maximum Data Rate

Propagation Delay

(Note 3)

SCL → SCL2, C = 15pF (Figure 1)

400

–20

kHz

l

t

, t

150

200

225

250

350

ns

PHL PLH

L

SDA → SDA2, R = Open, C = 15pF (Figure 3)

L

SDA2 → SDA, R = 1.1kΩ, C = 15pF (Figure 3)

L

t

Output Pulse Width Uncertainty

Data Hold Time

SDA, SDA2 (Note 2)

50

ns

PWU

HD;DAT

R

(Note 2)

600

Rise Time

SDA2, C = 200pF (Figure 3)

40

250

300

250

ns

L

l

SDA2, C = 200pF (Figure 3)

L

SDA, R = 1.1kΩ, C = 200pF (Figure 3)

L

SCL2, C = 200pF (Figure 1)

L

l

t

Fall Time

SDA2, C = 200pF (Figure 3)

40

250

ns

F

L

SDA, R = 1.1kΩ, C = 200pF (Figure 3)

L

SCL2, C = 200pF (Figure 1)

L

l

Pulse Width of Spikes

Suppressed by Input Filter

0

50

ns

SP

Power Supply

Power-Up Time

l

0.6

2

2.5

ms

ON = ↑ to V

(Min)

CC2

+

ON = ↑ to V (Min)

–

ON = ↑ to V (Min)

ISOLATION CHARACTERISTICS ^T_A^{= 25°Cꢀ}

SYMBOL PARAMETER

CONDITIONS

MIN

2500

4400

30

TYP

MAX

UNITS

V

Rated Dielectric Insulation Voltage

(Notes 5, 6, 7)

1 Minute, Derived from 1 Second Test

1 Second

V

RMS

ISO

V

Common Mode Transient Immunity

LTM2883-3 V = 3.3V, LTM2883-5 V = 5V,

kV/µs

CC

V = ON = 3.3V, V = 1kV, Δt = 33ns (Note 2)

L

CM

V

Maximum Continuous Working Voltage

(Notes 2, 5)

560

400

V

PEAK

RMS

IORM

V

Partial Discharge

V

= 1050V

(Notes 2, 5)

5

pC

PD

PEAK

CTI

DTI

Comparative Tracking Index

Depth of Erosion

IEC 60112 (Note 2)

(Note 2)

600

V

RMS

0.017

0.06

mm

Distance Through Insulation

Input to Output Resistance

Input to Output Capacitance

Creepage Distance

mm

Ω

9

(Notes 2, 5)

10

(Notes 2, 5)

6

pF

(Note 2)

9.48

mm

2883fd

6

For more information www.linear.com/LTM2883

LTM2883

ISOLATION CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Continuous operation above specified maximum operating junction

temperature may result in device degradation or failure.

Note 5: Device considered a 2-terminal device. Pin group A1 through B8

shorted together and pin group K1 through L8 shorted together.

Note 2: Guaranteed by design and not subject to production test.

Note 6: The rated dielectric insulation voltage should not be interpreted as

Note 3: Maximum data rate is guaranteed by other measured parameters

and is not tested directly.

a continuous voltage rating.

Note 7: In accordance with UL1577, each device is proof tested for the

Note 4: This module includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

2500V

rating by applying the equivalent positive and negative peak

RMS

voltage multiplied by an acceleration factor of 1.2 for one second.

2883fd

7

For more information www.linear.com/LTM2883

LTM2883

T_A= 25°C, LTM2883-3 V_CC= 3ꢀ3V,

TYPICAL PERFORMANCE CHARACTERISTICS

LTM2883-5 V_CC= 5V, V_L= 3ꢀ3V, GND = GND2 = 0V, ON = V_Lunless otherwise notedꢀ

V_CCSupply Current

vs Temperature

Isolated Supplies

vs Equal Load Current

ꢔꢕ

vs Equal Load Current

3ꢍ

2ꢌ

2ꢍ

ꢓꢌ

ꢓꢍ

ꢔꢕ

ꢔ2

ꢔꢍ

8

ꢑꢖ ꢏꢖꢅꢗꢘ ꢄꢁꢙꢄꢁꢎꢚ ꢗꢅꢀꢅ ꢖꢑꢏꢐ

ꢀꢉꢘ2883ꢙ3

ꢚ 3ꢛ3ꢎ

ꢀꢉꢘ2883ꢙꢗ

ꢎ

ꢄꢄ

ꢚ ꢗꢎ

ꢄꢄ

ꢔ2

ꢔꢍ

8

ꢏꢀꢂ2883ꢛ3

ꢝ 3ꢞ3ꢜ

ꢜ

ꢉꢉ

ꢏꢀꢂ2883ꢛꢌ

ꢜ

ꢝ ꢌꢜ

ꢉꢉ

ꢖ

ꢕ

ꢎ

ꢄꢄ2

ꢐ

ꢒ

ꢄꢄ2

ꢐ

ꢒ

2

ꢍ

ꢋꢌꢍ ꢋ2ꢌ

ꢍ

2ꢌ

ꢌꢍ

ꢕꢌ ꢓꢍꢍ ꢓ2ꢌ

ꢍ

ꢗ

ꢔꢍ

ꢔꢗ

2ꢍ

2ꢗ

ꢍ

ꢗ

ꢔꢍ

ꢔꢗ

2ꢍ

2ꢗ

3ꢍ

ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

2883 ꢔꢍꢓ

2883 ꢓꢍ2

2883 ꢓꢍ3

V_CC2Line Regulation

vs Load Current

V⁺Line Regulation

vs Load Current

V^–Line Regulation

vs Load Current

ꢐꢑꢍ

ꢒꢑꢒ

ꢒꢑꢍ

ꢓꢑꢒ

ꢓꢑꢍ

3ꢑꢒ

3ꢑꢍ

2ꢑꢒ

ꢑ3ꢒꢍ

ꢑ2ꢒꢓ

ꢑ2ꢒꢍ

ꢑꢑꢒꢓ

ꢑꢑꢒꢍ

ꢑꢍꢒꢓ

ꢑꢍꢒꢍ

ꢔꢒꢓ

ꢀꢁꢂꢃ

ꢀꢁꢂꢅ

ꢀꢉꢕ2883ꢖ3

ꢀꢉꢘ2883ꢙ3

ꢄꢄ2

ꢆꢏꢗ2883ꢘ3

ꢚ

ꢘ

ꢚ

ꢛ

ꢗ

ꢙ ꢗ ꢙ ꢍꢂ

ꢚ

ꢗ ꢚ ꢗ ꢍꢂ

ꢙ

ꢖ ꢙ ꢖ ꢃꢈ

ꢊꢊ2

ꢀꢄꢃꢂꢃ

ꢀꢄꢃꢂꢅ

ꢀꢄꢄꢂꢃ

ꢀꢄꢄꢂꢅ

ꢀꢄ2ꢂꢃ

ꢀꢄ2ꢂꢅ

ꢀꢄ3ꢂꢃ

ꢓ

ꢊꢊ

ꢓ

ꢊꢊ

ꢓ

ꢊꢊ

ꢓ

ꢊꢊ

ꢖ 3ꢓ

ꢖ 3ꢂꢄꢅꢓ

ꢖ 3ꢂ3ꢓ

ꢖ 3ꢂꢕꢓ

ꢎ

ꢄꢄ

ꢎ

ꢄꢄ

ꢎ

ꢄꢄ

ꢎ

ꢄꢄ

ꢗ 3ꢎ

ꢗ 3ꢒꢑꢓꢎ

ꢗ 3ꢒ3ꢎ

ꢗ 3ꢒꢕꢎ

ꢎ

ꢙ 3ꢎ

ꢙ 3ꢑ3ꢎ

ꢙ 3ꢑꢐꢎ

ꢄꢄ

ꢔꢒꢍ

ꢍ

ꢔꢍ

2ꢍ

3ꢍ

ꢓꢍ

ꢍ

ꢑꢍ

2ꢍ

3ꢍ

ꢖꢍ

ꢓꢍ

ꢕꢍ

ꢃ

ꢄꢃ

2ꢃ

3ꢃ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

ꢆꢇꢈꢉ ꢊꢋꢌꢌꢍꢎꢏ ꢐꢑꢈꢒ

2883 ꢏꢍꢓ

2883 ꢐꢍꢓ

2883 ꢔꢃꢕ

V_CC2Line Regulation

vs Load Current

V⁺Line Regulation

vs Load Current

V^–Line Regulation

vs Load Current

ꢑ3ꢒꢍ

ꢑ2ꢒꢓ

ꢑ2ꢒꢍ

ꢑꢑꢒꢓ

ꢑꢑꢒꢍ

ꢑꢍꢒꢓ

ꢑꢍꢒꢍ

ꢔꢒꢓ

ꢀꢁꢂꢃ

ꢀꢁꢂꢅ

ꢐꢑꢍ

ꢒꢑꢒ

ꢒꢑꢍ

ꢓꢑꢒ

ꢓꢑꢍ

3ꢑꢒ

3ꢑꢍ

2ꢑꢒ

ꢀꢉꢙ2883ꢚꢓ

ꢜ

ꢆꢏꢘ2883ꢙꢅ

ꢛ

ꢀꢉꢗ2883ꢘꢒ

ꢚ

ꢛ

ꢗ ꢛ ꢗ ꢍꢂ

ꢚ

ꢖ ꢚ ꢖ ꢃꢈ

ꢙ

ꢖ ꢙ ꢖ ꢍꢂ

ꢄꢄ2

ꢊꢊ2

ꢀꢄꢃꢂꢃ

ꢀꢄꢃꢂꢅ

ꢀꢄꢄꢂꢃ

ꢀꢄꢄꢂꢅ

ꢀꢄ2ꢂꢃ

ꢀꢄ2ꢂꢅ

ꢀꢄ3ꢂꢃ

ꢓ

ꢊꢊ

ꢓ

ꢊꢊ

ꢓ

ꢊꢊ

ꢓ

ꢊꢊ

ꢖ ꢕꢂꢅꢓ

ꢖ ꢕꢂꢗꢅꢓ

ꢖ ꢅꢓ

ꢖ ꢅꢂꢅꢓ

ꢎ

ꢄꢄ

ꢎ

ꢄꢄ

ꢎ

ꢄꢄ

ꢎ

ꢄꢄ

ꢗ ꢖꢒꢓꢎ

ꢗ ꢖꢒꢘꢓꢎ

ꢗ ꢓꢎ

ꢎ

ꢖ ꢓꢑꢒꢎ

ꢖ ꢒꢎ

ꢖ ꢒꢑꢒꢎ

ꢄꢄ

ꢎ

ꢗ ꢓꢒꢓꢎ

ꢎ

ꢔꢒꢍ

ꢍ

ꢑꢍ

2ꢍ

3ꢍ

ꢖꢍ

ꢓꢍ

ꢕꢍ

ꢃ

ꢄꢃ

2ꢃ

3ꢃ

ꢕꢃ

ꢍ

ꢔꢍ

2ꢍ

3ꢍ

ꢓꢍ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

ꢆꢇꢈꢉ ꢊꢋꢌꢌꢍꢎꢏ ꢐꢑꢈꢒ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

2883 ꢐꢍ8

2883 ꢔꢃꢁ

2883 ꢏꢍꢕ

2883fd

8

For more information www.linear.com/LTM2883

LTM2883

T_A= 25°C, LTM2883-3 V_CC= 3ꢀ3V,

TYPICAL PERFORMANCE CHARACTERISTICS

LTM2883-5 V_CC= 5V, V_L= 3ꢀ3V, GND = GND2 = 0V, ON = V_Lunless otherwise notedꢀ

V⁺Load Regulation

vs Temperature

V^–Load Regulation

vs Temperature

V_CC2Load Regulation

vs Temperature

ꢓ2ꢔ8

ꢓ2ꢔꢕ

ꢓ2ꢔꢖ

ꢓ2ꢔꢌ

ꢓ2ꢔꢗ

ꢓ2ꢔ3

ꢓ2ꢔ2

ꢌꢒ2ꢍ

ꢌꢒꢓꢌ

ꢌꢒꢓꢍ

ꢌꢒꢍꢌ

ꢌꢒꢍꢍ

ꢔꢒꢕꢌ

ꢔꢒꢕꢍ

ꢋꢒ2ꢓ2

ꢋꢒ2ꢓ3

ꢋꢒ2ꢓꢔ

ꢋꢒ2ꢓꢌ

ꢋꢒ2ꢓꢕ

ꢋꢒ2ꢓꢖ

ꢋꢒ2ꢓ8

ꢏ

ꢋ

ꢚ

ꢙ ꢓꢛꢅ

ꢐꢀꢂ2883ꢗ3

ꢗ

ꢘ ꢒꢙꢅ

ꢐꢀꢂ2883ꢚ3

ꢏ

ꢙ ꢌꢛꢅ

ꢎ

ꢘ 3ꢒ3ꢎ

ꢘ ꢒꢌꢙꢅ

ꢎ

ꢘ 3ꢓ3ꢎ

ꢉꢉ

ꢉꢉ2

ꢚ

ꢋ

ꢛ

ꢙ ꢓꢍꢛꢅ

ꢙ ꢓꢌꢛꢅ

ꢙ 2ꢍꢛꢅ

ꢙ

ꢘ ꢙ ꢘ ꢍꢅ

ꢗ

ꢘ ꢗ ꢘ ꢍꢅ

ꢑꢀꢂ2883ꢘ3

ꢎ

ꢚ

ꢙ 3ꢔ3ꢎ

ꢙ

ꢘ ꢓꢛꢅ

ꢉꢉ

ꢉꢉ2

ꢋ

ꢙ ꢚ ꢙ ꢍꢅ

ꢘ 2ꢍꢛꢅ

ꢋꢌꢍ ꢋ2ꢌ

ꢍ

2ꢌ

ꢌꢍ

ꢕꢌ ꢓꢍꢍ ꢓ2ꢌ

ꢋꢌꢍ ꢋ2ꢌ

ꢍ

2ꢌ

ꢌꢍ

ꢖꢌ ꢓꢍꢍ ꢓ2ꢌ

ꢋꢌꢍ ꢋ2ꢌ

ꢍ

2ꢌ

ꢌꢍ

ꢖꢌ ꢒꢍꢍ ꢒ2ꢌ

ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ

2883 ꢒꢓ2

2883 ꢑꢓꢍ

2883 ꢑꢒꢔ

V⁺Load Regulation

vs Temperature

V_CC2Load Regulation

vs Temperature

V^–Load Regulation

vs Temperature

ꢌꢒ2ꢍ

ꢌꢒꢓꢌ

ꢌꢒꢓꢍ

ꢌꢒꢍꢌ

ꢌꢒꢍꢍ

ꢔꢒꢕꢌ

ꢔꢒꢕꢍ

ꢓ2ꢔꢕ

ꢓ2ꢔꢖ

ꢓ2ꢔꢌ

ꢓ2ꢔꢗ

ꢓ2ꢔ3

ꢓ2ꢔ2

ꢓ2ꢔꢓ

ꢋꢒ2ꢓ2

ꢋꢒ2ꢓ3

ꢋꢒ2ꢓꢔ

ꢋꢒ2ꢓꢌ

ꢋꢒ2ꢓꢕ

ꢏ

ꢋ

ꢐꢀꢂ2883ꢗꢌ

ꢘ

ꢙ ꢓꢚꢅ

ꢗ

ꢘ ꢒꢙꢅ

ꢘ 2ꢍꢙꢅ

ꢐꢀꢂ2883ꢚꢌ

ꢏ

ꢎ

ꢘ ꢌꢎ

ꢙ ꢌꢚꢅ

ꢎ

ꢉꢉ2

ꢘ ꢌꢎ

ꢉꢉ

ꢚ

ꢋ

ꢛ

ꢙ

ꢘ ꢙ ꢘ ꢍꢅ

ꢙ ꢓꢍꢚꢅ

ꢙ ꢓꢌꢚꢅ

ꢙ 2ꢍꢚꢅ

ꢗ

ꢘ ꢗ ꢘ ꢍꢅ

ꢑꢀꢂ2883ꢛꢌ

ꢙ

ꢘ ꢓꢛꢅ

ꢘ 2ꢍꢛꢅ

ꢎ

ꢘ

ꢙ ꢌꢎ

ꢉꢉ2

ꢉꢉ

ꢉꢉ2

ꢋ

ꢙ ꢘ ꢙ ꢍꢅ

ꢋꢌꢍ ꢋ2ꢌ

ꢍ

2ꢌ

ꢌꢍ

ꢖꢌ ꢓꢍꢍ ꢓ2ꢌ

ꢋꢌꢍ ꢋ2ꢌ

ꢍ

2ꢌ

ꢌꢍ

ꢕꢌ ꢓꢍꢍ ꢓ2ꢌ

ꢋꢌꢍ ꢋ2ꢌ

ꢍ

2ꢌ

ꢌꢍ

ꢖꢌ ꢒꢍꢍ ꢒ2ꢌ

ꢀꢁꢂꢃꢁꢄꢅꢀꢆꢄꢁ ꢇꢈꢉꢊ

2883 ꢑꢓꢓ

2883 ꢒꢓ3

2883 ꢑꢒꢌ

V_CC2Voltage and I_CCCurrent

vs Load Current

V_CC2Efficiency

ꢕꢍ

ꢘꢍ

ꢗꢍ

3ꢍ

2ꢍ

ꢖꢍ

ꢍ

ꢍꢙꢕ

ꢍꢙꢘ

ꢍꢙꢗ

ꢍꢙ3

ꢍꢙ2

ꢍꢙꢖ

ꢍ

ꢑ

ꢔ

ꢓ

3

2

ꢒ

ꢍ

ꢒꢔꢍ

ꢒ2ꢔ

ꢒꢍꢍ

ꢕꢔ

ꢛ

ꢜ

ꢀꢉꢛ2883ꢜ3ꢝ ꢞ ꢟ 3ꢙ3ꢞ

ꢄꢄ

ꢀꢉꢛ2883ꢜꢘꢝ ꢞ ꢟ ꢘꢞ

ꢄꢄ

ꢐ

ꢙ ꢐ ꢙ ꢍꢂ

ꢎꢁꢀꢉꢂꢏꢇ

ꢇꢎꢎꢏꢄꢏꢇꢈꢄꢐ

ꢐ

ꢄꢅꢆꢆꢇꢈꢉ

ꢄꢄ

ꢔꢍ

ꢒꢁꢓꢇꢆ ꢀꢁꢔꢔ

2ꢔ

ꢀꢉꢖ2883ꢗ3ꢘ ꢎ ꢙ 3ꢚ3ꢎ

ꢄꢄ

ꢠ

ꢡ

ꢀꢉꢖ2883ꢗꢔꢘ ꢎ ꢙ ꢔꢎ

ꢄꢄ

ꢏ

ꢟ ꢏ ꢟ ꢍꢂ

ꢗꢍ

ꢍ

ꢖꢍ

2ꢍ

3ꢍ

ꢍ

ꢒꢍ

2ꢍ

3ꢍ

ꢓꢍ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

2883 ꢚꢖꢕ

2883 ꢏꢒꢕ

2883fd

9

For more information www.linear.com/LTM2883

LTM2883

T_A= 25°C, LTM2883-3 V_CC= 3ꢀ3V,

V⁺Voltage and I_CCCurrent

TYPICAL PERFORMANCE CHARACTERISTICS

LTM2883-5 V_CC= 5V, V_L= 3ꢀ3V, GND = GND2 = 0V, ON = V_Lunless otherwise notedꢀ

V⁺Efficiency

vs Load Current

ꢕꢍ

ꢘꢍ

ꢗꢍ

3ꢍ

2ꢍ

ꢖꢍ

ꢍ

ꢖꢙ2

ꢖꢙꢍ

ꢍꢙ8

ꢍꢙꢕ

ꢍꢙꢗ

ꢍꢙ2

ꢍ

ꢁꢃ

ꢁ2

ꢁꢀ

8

3ꢂꢀ

3ꢀꢀ

2ꢂꢀ

2ꢀꢀ

ꢁꢂꢀ

ꢁꢀꢀ

ꢂꢀ

ꢜ

ꢀꢉꢛ2883ꢜ3ꢝ ꢞ ꢟ 3ꢙ3ꢞ

ꢔ

ꢚ ꢔ ꢚ ꢀꢆ

ꢄꢄ

ꢈꢈ2

ꢑꢅꢄꢍꢆꢓꢋ

ꢀꢉꢛ2883ꢜꢘꢝ ꢞ ꢟ ꢘꢞ

ꢄꢄ

ꢇꢎꢎꢏꢄꢏꢇꢈꢄꢐ

ꢔ

ꢈꢈ

ꢈꢉꢊꢊꢋꢌꢍ

ꢕ

ꢒꢁꢓꢇꢆ ꢀꢁꢔꢔ

ꢃ

2

ꢄꢍꢗ2883ꢘ3ꢙ ꢑ ꢚ 3ꢛ3ꢑ

ꢈꢈ

ꢄꢍꢗ2883ꢘꢂꢙ ꢑ ꢚ ꢂꢑ

ꢈꢈ

ꢠ

ꢏ

ꢟ ꢏ ꢟ ꢍꢂ

ꢄꢄ2

ꢀ

ꢍ

ꢖꢍ

2ꢍ

3ꢍ

ꢗꢍ

ꢘꢍ

ꢀ

ꢁꢀ

2ꢀ

3ꢀ

ꢃꢀ

ꢂꢀ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

ꢄꢅꢆꢇ ꢈꢉꢊꢊꢋꢌꢍ ꢎꢏꢆꢐ

2883 ꢚꢖ8

2883 ꢓꢁꢖ

V^–Voltage and I_CCCurrent

vs Load Current

V^–Efficiency

ꢕꢍ

ꢘꢍ

ꢗꢍ

3ꢍ

2ꢍ

ꢖꢍ

ꢍ

ꢍꢙꢕ

ꢍꢙꢘ

ꢍꢙꢗ

ꢍꢙ3

ꢍꢙ2

ꢍꢙꢖ

ꢍ

ꢏꢒꢓꢍ

ꢏꢒꢓꢕ

32ꢍ

28ꢍ

2ꢗꢍ

2ꢍꢍ

ꢔꢖꢍ

ꢔ2ꢍ

8ꢍ

ꢀꢉꢛ2883ꢜ3ꢝ ꢞ ꢟ 3ꢙ3ꢞ

ꢀꢉꢛ2883ꢜꢘꢝ ꢞ ꢟ ꢘꢞ

ꢄꢄ

ꢀꢉꢘ2883ꢙ3ꢚ ꢎ ꢛ 3ꢓ3ꢎ

ꢄꢄ

ꢀꢉꢘ2883ꢙꢕꢚ ꢎ ꢛ ꢕꢎ

ꢄꢄ

ꢏꢔꢍꢓꢍ

ꢏꢔꢍꢓꢕ

ꢏꢔꢔꢓꢍ

ꢏꢔꢔꢓꢕ

ꢏꢔ2ꢓꢍ

ꢏꢔ2ꢓꢕ

ꢏꢔ3ꢓꢍ

ꢇꢎꢎꢏꢄꢏꢇꢈꢄꢐ

ꢑ

ꢄꢅꢆꢆꢇꢈꢉ

ꢄꢄ

ꢒꢁꢓꢇꢆ ꢀꢁꢔꢔ

ꢗꢍ

ꢎꢁꢀꢉꢂꢐꢇ

2ꢍ

ꢍ

ꢖꢍ

2ꢍ

3ꢍ

ꢍ

ꢔꢍ

3ꢍ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

2883 ꢚ2ꢍ

2883 ꢐ2ꢔ

V_CC2Transient Response

20mA Load Step

V⁺Transient Response

20mA Load Step

V^–Transient Response

20mA Load Step

ꢍ

ꢆ

ꢎ ꢀꢏꢐꢉꢊ

ꢈ

ꢇ

ꢈꢈ2

ꢀꢁꢁꢉꢇꢄꢅꢆꢇ

2ꢁꢁꢉꢇꢄꢅꢆꢇ

ꢈ

ꢆ

ꢈ

ꢆ

ꢈꢈ2

ꢀꢁꢉꢊꢄꢅꢆꢇ

2883 ꢋ22

2883 ꢋ23

2883 ꢋ2ꢌ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

2883fd

10

For more information www.linear.com/LTM2883

LTM2883

T_A= 25°C, LTM2883-3 V_CC= 3ꢀ3V,

TYPICAL PERFORMANCE CHARACTERISTICS

LTM2883-5 V_CC= 5V, V_L= 3ꢀ3V, GND = GND2 = 0V, ON = V_Lunless otherwise notedꢀ

V_CC2Ripple

V⁺Ripple

V^–Ripple

ꢉ

ꢆ

ꢊ ꢋꢈꢌ

ꢆ ꢊ ꢋꢈꢌ

2ꢈꢇꢄꢅꢆꢇ

ꢀꢈꢇꢄꢅꢆꢇ

ꢉ

ꢆ

ꢊ 2ꢁꢈꢌ

ꢆ

ꢊ 2ꢁꢈꢌ

2883 ꢉ2ꢀ

2883 ꢍ2ꢎ

ꢀꢁꢁꢂꢃꢄꢅꢆꢇ

V

_CC2Noise

V⁺Noise

V^–Noise

2ꢁꢆꢃꢄꢅꢆ

2883 ꢇ28

2883 ꢇ2ꢈ

2883 ꢇ3ꢈ

ꢀꢁꢂꢃꢄꢅꢆ

V_CCSupply Current

vs Single Channel Data Rate

Logic Input Threshold

vs V_LSupply Voltage

Logic Output Voltage

vs Load Current

ꢐꢑ

ꢒꢑ

ꢔꢑ

ꢓꢑ

3ꢑ

2ꢑ

ꢉꢑ

3ꢑꢒ

3ꢑꢓ

2ꢑꢒ

2ꢑꢓ

ꢍꢑꢒ

ꢍꢑꢓ

ꢓꢑꢒ

ꢓ

ꢑꢒꢍ

ꢕꢒꢍ

ꢔꢒꢍ

3ꢒꢍ

2ꢒꢍ

ꢓꢒꢍ

ꢍ

ꢌ

ꢗ ꢉꢜꢝ

ꢋ

ꢌꢌ2

ꢗ ꢔꢋ

ꢛ

ꢌꢌ

ꢙ

ꢚ

ꢗ 33ꢑꢞꢝ

ꢗ ꢉꢑꢑꢞꢝ

ꢗ 2ꢑꢞꢝ

ꢘ

ꢗ ꢘ ꢗ ꢘ ꢗ ꢑ

ꢏ

ꢘ ꢕꢒꢕꢏ

ꢘ 3ꢒ3ꢏ

ꢘ ꢓꢒꢑ2ꢏ

ꢀ

ꢖꢗꢄꢃꢇ ꢏꢖꢂꢖꢗꢉ

ꢖꢗꢄꢃꢇ ꢘꢈꢁꢁꢖꢗꢉ

ꢉꢊ

ꢉꢑꢊ

ꢉꢑꢑꢊ

ꢉꢕ

ꢉꢑꢕ

ꢉꢑꢑꢕ

ꢍ

2

3

ꢔ

ꢒ

ꢕ

ꢍ

ꢓ

2

3

ꢔ

ꢕ

ꢑ

ꢗ

8

ꢖ

ꢓꢍ

ꢀꢁꢂꢁ ꢃꢁꢂꢄ ꢅꢆꢇꢈ

ꢀ

ꢂꢃꢄꢄꢁꢅ ꢀꢆꢁꢇꢈꢉꢊ ꢋꢀꢌ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

ꢁ

2883 ꢖ3ꢉ

2883 ꢉ32

2883 ꢐ33

2883fd

11

For more information www.linear.com/LTM2883

LTM2883

T_A= 25°C, LTM2883-3 V_CC= 3ꢀ3V,

TYPICAL PERFORMANCE CHARACTERISTICS

LTM2883-5 V_CC= 5V, V_L= 3ꢀ3V, GND = GND2 = 0V, ON = V_Lunless otherwise notedꢀ

V_CC2Cross Regulation

vs V⁺, V^–Load

Power On Sequence

ꢔꢕ2

ꢘꢖ

ꢘ3

ꢘ2

ꢘꢘ

ꢘꢍ

ꢗ

ꢀꢉꢛ2883ꢜ3

ꢉꢊ

ꢎ

ꢝ 3ꢕ3ꢎ

ꢄꢄ

ꢄꢄ2

ꢋ

ꢞ

ꢝ ꢘꢔꢋꢂ

ꢆ

ꢔꢕꢘ

ꢆ

ꢌꢌ2

ꢇꢆꢃꢄꢅꢆ

ꢔꢕꢍ

ꢖꢕꢗ

ꢖꢕ8

8

ꢈ

ꢆ

ꢎ

ꢄꢄ2

ꢐ

ꢓ

ꢙ

ꢚ

2883 ꢍ3ꢎ

2ꢀꢀꢁꢂꢃꢄꢅꢆ

ꢍ

ꢘꢍ

2ꢍ

3ꢍ

ꢖꢍ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

2883 ꢏ3ꢔ

V_CC2Cross Regulation

vs V⁺, V^–Load

Isolated Supply Efficiency with

Equal Load Current

ꢖꢗ2

ꢖꢗꢁ

ꢖꢗꢀ

ꢂꢗꢘ

ꢂꢗ8

ꢁꢂ

ꢁ3

ꢁ2

ꢁꢁ

ꢁꢀ

ꢘ

ꢕꢍ

ꢘꢍ

ꢗꢍ

3ꢍ

2ꢍ

ꢖꢍ

ꢍ

ꢖꢙꢍ

ꢍꢙꢛ

ꢍꢙ8

ꢍꢙꢚ

ꢍꢙꢕ

ꢍꢙꢘ

ꢍꢙꢗ

ꢍꢙ3

ꢍꢙ2

ꢍꢙꢖ

ꢍ

ꢃꢌꢛ2883ꢜꢖ

ꢐ

ꢞ

ꢝ ꢖꢐ

ꢇꢇ

ꢇꢇ2

ꢝ ꢁꢖꢎꢅ

ꢇꢎꢎꢏꢄꢏꢇꢈꢄꢐ

8

ꢒꢁꢓꢇꢆ ꢀꢁꢔꢔ

ꢐ

ꢇꢇ2

ꢒ

ꢙ

ꢀꢉꢝ2883ꢞ3ꢟ ꢠ ꢡ 3ꢙ3ꢠ

ꢄꢄ

ꢀꢉꢝ2883ꢞꢘꢟ ꢠ ꢡ ꢘꢠ

ꢄꢄ

ꢐ

ꢕ

ꢐ

ꢚ

ꢀ

ꢁꢀ

2ꢀ

3ꢀ

ꢂꢀ

ꢍ

ꢘ

ꢖꢍ

ꢖꢘ

2ꢍ

2ꢘ

ꢃꢄꢅꢆ ꢇꢈꢉꢉꢊꢋꢌ ꢍꢎꢅꢏ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

2883 ꢑ3ꢚ

2883 ꢜ3ꢚ

V⁺Cross Regulation vs V^–Load

ꢔꢕ

ꢔ3

ꢔ2

ꢔꢔ

ꢔꢍ

ꢗ

ꢔꢕ

ꢔ3

ꢔ2

ꢔꢔ

ꢔꢍ

ꢗ

ꢀꢉꢚ2883ꢛ3

ꢀꢉꢚ2883ꢛꢙ

ꢎ ꢜ ꢙꢎ

ꢄꢄ

ꢎ

ꢜ 3ꢝ3ꢎ

ꢄꢄ

8

ꢏ ꢏ

ꢏ

ꢒ

ꢏ

ꢎ ꢐ ꢞ ꢜ ꢔꢍꢋꢂ

ꢎ ꢐ ꢝ ꢜ ꢔꢍꢋꢂ

ꢒ ꢏ

ꢎ ꢐ ꢞ ꢜ ꢔꢍꢋꢂ

ꢎ ꢐ ꢝ ꢜ ꢔꢍꢋꢂ

ꢏ

ꢏ ꢏ

ꢖ

ꢎ ꢐ ꢞ ꢜ ꢔꢙꢋꢂ

ꢎ ꢐ ꢝ ꢜ ꢔꢙꢋꢂ

ꢒ

ꢒ ꢏ

ꢎ ꢐ ꢞ ꢜ ꢔꢙꢋꢂ

ꢔꢍ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

ꢎ ꢐ ꢝ ꢜ ꢔꢙꢋꢂ

ꢔꢍ ꢔꢙ

ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ

ꢘ

ꢍ

ꢙ

ꢔꢙ

2ꢍ

2ꢙ

ꢍ

ꢙ

2ꢍ

2ꢙ

3ꢍ

3ꢙ

2883 ꢓ38

2883 ꢓ3ꢗ

2883fd

12

For more information www.linear.com/LTM2883

LTM2883

PIN FUNCTIONS ^(LTM2883-I)

Logic Side

The logic state on I2 translates to the same logic state on

DO2. Do not float.

DO2(A1):DigitalOutput,ReferencedtoV andGND.Logic

L

DNC (L2): Do Not Connect Pin. Pin connected internally.

output connected to I2 through isolation barrier. Under

the condition of an isolation communication failure this

output is in a high impedance state.

2

SCL2 (L3): Serial I C Clock Output, Referenced to V

CC2

and GND2. Logic output connected to logic side SCL pin

through isolation barrier. Clock is unidirectional from logic

to isolated side. SCL2 has a push-pull output stage, do not

connect an external pull-up device. Under the condition of

an isolation communication failure this output defaults to

a high state.

DNC (A2): Do Not Connect Pin. Pin connected internally.

2

SCL (A3): Serial I C Clock Input, Referenced to V and

L

GND. Logic input connected to isolated side SCL2 pin

throughisolationbarrier.Clockisunidirectionalfromlogic

to isolated side. Do not float.

2

SDA2 (L4): Serial I C Data Pin, Referenced to V

and

CC2

2

SDA (A4): Serial I C Data Pin, Referenced to V and GND.

L

GND2. Bidirectional logic pin connected to logic side SDA

pin through isolation barrier. Output is biased high by a

1.8mA current source. Do not connect an external pull-

up device to SDA2. Under the condition of an isolation

communication failure this output defaults to a high state.

BidirectionallogicpinconnectedtoisolatedsideSDA2pin

through isolation barrier. Under the condition of an isola-

tion communication failure this pin is in a high impedance

state. Do not float.

DI1 (A5): Digital Input, Referenced to V and GND. Logic

L

O1 (L5): Digital Output, Referenced to V

and GND2.

CC2

input connected to O1 through isolation barrier. The logic

state on DI1 translates to the same logic state on O1. Do

not float.

Logic output connected to DI1 through isolation barrier.

Under the condition of an isolation communication failure

O1 defaults to a high state.

GND (A6, B2 to B6): Circuit Ground.

V

(L6): 5V Nominal Isolated Supply Voltage. Internally

CC2

generated from V by an isolated DC/DC converter and

CC

ON (A7): Enable. Enables power and data communica-

tion through the isolation barrier. If ON is high the part is

enabled and power and communications are functional

to the isolated side. If ON is low the logic side is held in

reset, all digital outputs are in a high impedance state, and

the isolated side is unpowered. Do not float.

regulated to 5V. Internally bypassed with 2.2µF.

–

V (L7):–12.5VNominalIsolatedSupplyVoltage.Internally

generated from V by an isolated DC/DC converter and

CC

regulated to –12.5V. Internally bypassed with 1µF.

+

V (L8):12.5VNominalIsolatedSupplyVoltage.Internally

V (A8): Logic Supply. Interface supply voltage for pins

generated from V by an isolated DC/DC converter and

L

CC

DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is

regulated to 12.5V. Internally bypassed with 1µF.

3V to 5.5V. Internally bypassed with 2.2µF.

I1 (K1): Digital Input, Referenced to V

and GND2.

CC2

DO1(B1):DigitalOutput,ReferencedtoV andGND.Logic

Logic input connected to DO1 through isolation barrier.

The logic state on I1 translates to the same logic state on

DO1. Do not float.

L

output connected to I1 through isolation barrier. Under

the condition of an isolation communication failure this

output is in a high impedance state.

GND2 (K2 to K5): Isolated Ground.

V

(B7 to B8): Supply Voltage. Operating voltage is 3V

CC

AV

(K6): 5V Nominal Isolated Supply Voltage Adjust.

CC2

to 3.6V for LTM2883-3 and 4.5V to 5.5V for LTM2883-5.

The adjust pin voltage is 600mV referenced to GND2.

Internally bypassed with 2.2µF.

–

AV (K7): –12.5V Nominal Isolated Supply Voltage Adjust.

The adjust pin voltage is –1.22V referenced to GND2.

Isolated Side

+

AV (K8): 12.5V Nominal Isolated Supply Voltage Adjust.

I2 (L1): Digital Input, Referenced to V

Logic input connected to DO2 through isolation barrier.

and GND2.

CC2

The adjust pin voltage is 1.22V referenced to GND2.

2883fd

13

For more information www.linear.com/LTM2883

LTM2883

PIN FUNCTIONS ^(LTM2883-S)

Logic Side

Isolated Side

SDO2 (L1): Serial SPI Digital Input, Referenced to V

and GND2. Logic input connected to logic side SDO pin

through isolation barrier. Do not float.

SDO (A1): Serial SPI Digital Output, Referenced to V

CC2

L

and GND. Logic output connected to isolated side SDO2

pin through isolation barrier. Under the condition of an

isolation communication failure this output is in a high

impedance state.

I2 (L2): Digital Input, Referenced to V

and GND2.

CC2

Logic input connected to DO2 through isolation barrier.

The logic state on I2 translates to the same logic state on

DO2. Do not float.

DO2(A2):DigitalOutput,ReferencedtoV andGND.Logic

L

output connected to I2 through isolation barrier. Under

the condition of an isolation communication failure this

output is in a high impedance state.

SCK2 (L3): Serial SPI Clock Output, Referenced to V

CC2

and GND2. Logic output connected to logic side SCK pin

throughisolationbarrier.Undertheconditionofanisolation

communication failure this output defaults to a low state.

SCK (A3): Serial SPI Clock Input, Referenced to V and

L

GND. Logic input connected to isolated side SCK2 pin

through isolation barrier. Do not float.

SDI2 (L4): Serial SPI Data Output, Referenced to V

CC2

and GND2. Logic output connected to logic side SDI pin

throughisolationbarrier.Undertheconditionofanisolation

communication failure this output defaults to a low state.

SDI(A4):SerialSPIDataInput,ReferencedtoV andGND.

L

Logic input connected to isolated side SDI2 pin through

isolation barrier. Do not float.

CS2 (L5): Serial SPI Chip Select, Referenced to V

and

CC2

CS(A5):SerialSPIChipSelect,ReferencedtoV andGND.

L

GND2.LogicoutputconnectedtologicsideCSpinthrough

isolation barrier. Under the condition of an isolation com-

munication failure this output defaults to a high state.

Logic input connected to isolated side CS2 pin through

isolation barrier. Do not float.

SDOE (A6): Serial SPI Data Output Enable, Referenced to

V

(L6): 5V Nominal Isolated Supply Voltage. Internally

CC2

V and GND. A logic high on SDOE places the logic side

L

generated from V by an isolated DC/DC converter and

CC

SDO pin in a high impedance state, a logic low enables

regulated to 5V. Internally bypassed with 2.2µF.

the output. Do not float.

–

V (L7):–12.5VNominalIsolatedSupplyVoltage.Internally

ON (A7): Enable. Enables power and data communica-

tion through the isolation barrier. If ON is high the part is

enabled and power and communications are functional

to the isolated side. If ON is low the logic side is held in

reset, all digital outputs are in a high impedance state, and

the isolated side is unpowered. Do not float.

generated from V by an isolated DC/DC converter and

CC

regulated to –12.5V. Internally bypassed with 1µF.

+

V (L8):12.5VNominalIsolatedSupplyVoltage.Internally

generated from V by an isolated DC/DC converter and

CC

regulated to 12.5V. Internally bypassed with 1µF.

I1 (K1): Digital Input, Referenced to V

and GND2.

V (A8): Logic Supply. Interface supply voltage for pins

CC2

L

Logic input connected to DO1 through isolation barrier.

The logic state on I1 translates to the same logic state on

DO1. Do not float.

SDI, SCK, SDO, DO1, DO2, CS, and ON. Operating voltage

is 1.62V to 5.5V. Internally bypassed with 2.2µF.

DO1(B1):DigitalOutput,ReferencedtoV andGND.Logic

L

GND2 (K2 to K5): Isolated Ground.

output connected to I1 through isolation barrier. Under

the condition of an isolation communication failure this

output is in a high impedance state.

AV

(K6): 5V Nominal Isolated Supply Voltage Adjust.

CC2

The adjust pin voltage is 600mV Referenced to GND2.

–

GND (B2 to B6): Circuit Ground.

AV (K7): –12.5V Nominal Isolated Supply Voltage Adjust.

The adjust pin voltage is –1.22V Referenced to GND2.

V

(B7 to B8): Supply Voltage. Operating voltage is 3V

CC

+

to 3.6V for LTM2883-3 and 4.5V to 5.5V for LTM2883-5.

AV (K8): 12.5V Nominal Isolated Supply Voltage Adjust.

Internally bypassed with 2.2µF.

The adjust pin voltage is 1.22V Referenced to GND2.

2883fd

14

For more information www.linear.com/LTM2883

LTM2883

BLOCK DIAGRAM

ꢔꢓꢉ

ꢆ

ꢇꢇ2

ꢇꢇ

ꢌꢌꢍꢎ

ꢌꢙꢎ

2ꢃ2ꢄꢅ

ꢆ

ꢋ

ꢈꢆ

2ꢃ2ꢄꢅ

ꢉꢊꢁ2

ꢉꢊꢁ

ꢚ

ꢆ

ꢌꢙꢍꢎ

ꢌꢛꢃ2ꢎ

ꢌꢙꢍꢎ

ꢌꢄꢅ

ꢚ

ꢈꢆ

ꢔꢓꢉ

ꢁꢇꢒꢁꢇ

ꢇꢏꢊꢆꢓꢔꢕꢓꢔ

ꢜ

ꢈꢆ

ꢌꢄꢅ

ꢏꢊ

ꢔꢓꢉ

ꢜ

ꢆ

ꢐꢑꢏꢋꢈꢕꢓꢁ

ꢇꢏꢖꢖꢗꢊꢐꢘ

ꢇꢈꢕꢐꢏꢊꢑ

ꢐꢑꢏꢋꢈꢕꢓꢁ

ꢇꢏꢖꢖꢗꢊꢐꢘ

ꢇꢈꢕꢐꢏꢊꢑ

ꢁꢐꢌ

ꢏꢌ

ꢑꢁꢈ2

ꢑꢇꢋ2

ꢐ2

ꢐꢊꢕꢓꢔꢅꢈꢇꢓ

ꢑꢁꢈ

ꢑꢇꢋ

ꢁꢏ2

ꢁꢏꢌ

ꢐꢌ

2882 ꢀꢁꢂ

LTM2883-I

ꢕꢔꢉ

ꢆ

ꢇꢇ

ꢋ

ꢇꢇ2

ꢌꢌꢍꢎ

ꢌꢚꢎ

2ꢃ2ꢄꢅ

ꢈꢆ

2ꢃ2ꢄꢅ

ꢉꢊꢁ2

ꢉꢊꢁ

ꢛ

ꢆ

ꢌꢚꢍꢎ

ꢌꢜꢃ2ꢎ

ꢌꢚꢍꢎ

ꢌꢄꢅ

ꢛ

ꢈꢆ

ꢕꢔꢉ

ꢁꢇꢓꢁꢇ

ꢇꢏꢊꢆꢔꢕꢖꢔꢕ

ꢝ

ꢈꢆ

ꢌꢄꢅ

ꢏꢊ

ꢕꢔꢉ

ꢝ

ꢆ

SDOE

CS

CS2

ꢐꢁꢑ2

ꢐꢇꢒ2

ꢑ2

ꢑꢐꢏꢋꢈꢖꢔꢁ

ꢇꢏꢗꢗꢘꢊꢑꢙ

ꢇꢈꢖꢑꢏꢊꢐ

ꢑꢐꢏꢋꢈꢖꢔꢁ

ꢇꢏꢗꢗꢘꢊꢑꢙ

ꢇꢈꢖꢑꢏꢊꢐ

ꢐꢁꢑ

ꢐꢇꢒ

ꢁꢏ2

ꢐꢁꢏ

ꢁꢏꢌ

ꢑꢊꢖꢔꢕꢅꢈꢇꢔ

ꢐꢁꢏ2

ꢑꢌ

2883 ꢀꢁꢂ

LTM2883-S

2883fd

15

For more information www.linear.com/LTM2883

LTM2883

TEST CIRCUITS

ꢑ

ꢇ

ꢀꢁꢂꢃꢄ

ꢐꢑ

ꢇ

ꢍꢑ

ꢅꢃꢄꢂꢃꢄ

ꢈ

ꢂꢉꢇ

ꢂꢇꢉ

ꢆ

ꢇ

ꢀꢁꢂꢃꢄ

ꢑ

ꢅꢉ

ꢌꢍꢎ

ꢏꢍꢎ

ꢌꢍꢎ

ꢅꢃꢄꢂꢃꢄ

ꢐꢑ

ꢆꢆ2

ꢑ

ꢅꢇ

ꢈ

ꢋ

ꢊ

ꢑ

ꢆꢆ2

ꢍꢑ

ꢀꢁꢂꢃꢄ

ꢐꢑ

ꢆꢆ2

ꢅꢃꢄꢂꢃꢄ

ꢈ

ꢂꢉꢇ

ꢂꢇꢉ

ꢆ

ꢇ

ꢀꢁꢂꢃꢄ

ꢑ

ꢅꢉ

ꢌꢍꢎ

ꢏꢍꢎ

ꢌꢍꢎ

ꢅꢃꢄꢂꢃꢄ

ꢐꢑ

ꢇ

ꢑ

ꢅꢇ

ꢈ

ꢋ

ꢊ

2883 ꢋꢍꢏ

Figure 1ꢀ Logic Timing Measurements

ꢇ

ꢆ

ꢈꢐ ꢁꢇ

ꢇ

ꢆ

SDOE

ꢎꢏꢈ

ꢍꢇ

ꢆ

ꢐ

ꢆ

ꢁꢇ

ꢂ

ꢃꢅꢄ

ꢃꢄꢅ

ꢇ

ꢈꢅ

ꢎꢏꢈ

ꢎꢏꢈ2 ꢈꢐ

ꢇ

ꢑꢑ2

ꢇ

ꢌ ꢁꢊꢋꢇ

ꢉ ꢁꢊꢋꢇ

ꢈꢅ

ꢍꢇ

ꢑ

ꢆ

ꢂ

ꢆ

ꢁꢇ

ꢂ

ꢃꢆꢄ

SDOE

ꢃꢄꢆ

ꢆ

ꢇ

ꢆ

ꢍꢇ

ꢈꢆ

ꢇ

ꢈꢆ

2883 ꢀꢁ2

Figure 2ꢀ Logic Enable/Disable Time

ꢉ

ꢃ

ꢉ

ꢃ

ꢅ

ꢃ

ꢌꢍꢎ

ꢈꢉ

ꢃ

ꢆꢉ

ꢌꢍꢎ2

ꢀ

ꢁꢃꢂ

ꢁꢂꢃ

ꢏ

ꢃ

ꢌꢍꢎ

ꢉ

ꢋꢂ

3ꢆꢇ

ꢊꢆꢇ

3ꢆꢇ

ꢌꢍꢎ2

ꢈꢉ

ꢏꢏ2

ꢊꢆꢇ

ꢉ

ꢋꢃ

ꢀ

ꢅ

ꢄ

ꢉ

ꢃ

ꢉ

ꢏꢏ2

ꢆꢉ

ꢅ

ꢃ

ꢌꢍꢎ2

ꢌꢍꢎ

ꢈꢉ

ꢏꢏ2

ꢌꢍꢎ

ꢀ

ꢁꢃꢂ

ꢁꢂꢃ

ꢏ

ꢃ

ꢌꢍꢎ2

ꢉ

ꢋꢂ

3ꢆꢇ

ꢊꢆꢇ

3ꢆꢇ

ꢈꢉ

ꢃ

ꢊꢆꢇ

ꢉ

ꢋꢃ

ꢀ

ꢅ

ꢄ

2883 ꢄꢆ3

Figure 3ꢀ I²C Timing Measurements

2883fd

16

For more information www.linear.com/LTM2883

LTM2883

APPLICATIONS INFORMATION

Overview

the 12.5V supply. A load current of 1.5mA is sufficient to

improvestaticanddynamicloadregulationcharacteristics

of the –12.5V output. The increased load allows the boost

regulatortooperatecontinuouslyandinturnimprovesthe

regulation of the inverting charge pump.

The LTM2883 digital µModule isolator provides a

galvanically-isolated robust logic interface, powered by

an integrated, regulated DC/DC converter, complete with

decoupling capacitors. The LTM2883 is ideal for use in

networks where grounds can take on different voltages.

Isolation in the LTM2883 blocks high voltage differences,

eliminates ground loops and is extremely tolerant of com-

mon mode transients between ground planes. Error-free

operation is maintained through common mode events

greater than 30kV/μs providing excellent noise isolation.

The internal power solution is sufficient to provide a mini

-

+

mum of 20mA of current from V

and V , and 15mA

CC2

–

from V . V and V

are each bypassed with 2.2µF

ceramic capacitors, and V and V are bypassed with 1µF

CC

CC2

+

–

ceramic capacitors.

V Logic Supply

L

Isolator µModule Technology

A separate logic supply pin V allows the LTM2883 to in-

L

terface with any logic signal from 1.62V to 5.5V as shown

The LTM2883 utilizes isolator µModule technology to

translate signals and power across an isolation barrier.

Signalsoneithersideofthebarrierareencodedintopulses

and translated across the isolation boundary using core-

less transformers formed in the µModule substrate. This

system, complete with data refresh, error checking, safe

shutdown on fail, and extremely high common mode im-

munity, provides a robust solution for bidirectional signal

isolation. The µModule technology provides the means to

combinetheisolatedsignalingwithmultipleregulatorsand

apowerfulisolatedDC/DCconverterinonesmallpackage.

in Figure 4. Simply connect the desired logic supply to V .

L

There is no interdependency between V and V ; they

CC

L

may simultaneously operate at any voltage within their

specified operating ranges and sequence in any order. V

is bypassed internally by a 2.2µF capacitor.

L

3ꢌ ꢆꢃ 3ꢑꢒꢌ ꢅꢆꢇ2883ꢈ3

ꢂꢑꢓꢌ ꢆꢃ ꢓꢑꢓꢌ ꢅꢆꢇ2883ꢈꢓ

ꢅꢆꢇ2883ꢈꢉ

ꢌ

ꢗꢗ2

ꢌ

ꢗꢗ

ꢅ

ꢊꢌ

ꢙ

ꢊꢄꢋ ꢌꢃꢅꢆꢊꢍꢎ ꢀꢏꢃꢇ

ꢐꢑꢒ2ꢌ ꢆꢃ ꢓꢑꢓꢌ

ꢌ

DC/DC Converter

ꢙ

ꢊꢌ

ꢌ

ꢚ

TheLTM2883containsafullyintegratedDC/DCconverter,

includingthetransformer,sothatnoexternalcomponents

are necessary. The logic side contains a full-bridge driver,

running at 2MHz, and is AC-coupled to a single trans-

former primary. A series DC blocking capacitor prevents

transformersaturationduetodriverdutycycleimbalance.

The transformer scales the primary voltage, and is recti-

fied by a full-wave voltage doubler. This topology allows

for a single diode drop, as in a center tapped full-wave

bridge, and eliminates transformer saturation caused by

secondary imbalances.

ꢊꢌ

ꢃꢄ

SDOE

CS

CS2

ꢉꢕꢖ2

ꢉꢗꢘ2

ꢉꢕꢖ

ꢉꢗꢘ

ꢎꢔꢆꢎꢏꢄꢊꢅ

ꢕꢎꢌꢖꢗꢎ

ꢕꢃ2

ꢉꢕꢃ

ꢕꢃꢐ

ꢖ2

ꢉꢕꢃ2

ꢖꢐ

ꢍꢄꢕ

ꢍꢄꢕ2

2883 ꢀꢁꢂ

TheDC/DCconverterisconnectedtoalowdropoutregula-

tor (LDO) to provide a regulated 5V output.

Figure 4ꢀ V_CCand V_LAre Independent

Hot-Plugging Safely

Caution must be exercised in applications where power is

plugged into the LTM2883’s power supplies, V or V ,

due to the integrated ceramic decoupling capacitors. The

An integrated boost converter generates a regulated 14V

supply and a charge pumped –14V supply. These rails are

regulatedto 12.5Vrespectivelybylowdropoutregulators.

Performance of the –12.5V supply is enhanced by loading

CC

L

2883fd

17

For more information www.linear.com/LTM2883

LTM2883

APPLICATIONS INFORMATION

parasitic cable inductance along with the high Q char-

acteristics of ceramic capacitors can cause substantial

ringing which could exceed the maximum voltage ratings

and damage the LTM2883. Refer to Analog Devices Ap-

plication Note 88, entitled Ceramic Input Capacitors Can

Cause Overvoltage Transients for a detailed discussion

and mitigation of this phenomenon.

Table 1ꢀ Voltage Adjustment Formula

OUTPUT

VOLTAGE

RESISTOR (Ax TO Vx) TO RESISTOR (Ax TO GND2) TO

REDUCE OUTPUT

INCREASE OUTPUT

ꢀꢀꢁ

ꢂ_ꢃꢃ2ꢄ ꢅ

ꢀꢀꢁꢂ • ꢃ ꢅ ꢁꢆꢇ

ꢈ

ꢉ

V

ꢄꢄ2

CC2

ꢊ ꢅ ꢃ_ꢄꢄ2

ꢀꢁꢂꢃ • ꢄ^ꢅꢆꢄ^ꢇꢇ ꢀꢈ22

ꢀ83ꢁ

ꢂ^ꢃꢄꢂ^ꢅꢅ ꢀ2ꢆꢇ

+

–

V , V

ꢉ

ꢊ

Isolated Supply Adjustable Operation

ꢀ2ꢈꢁ ꢇ ꢄ^ꢅꢆꢄ^ꢇ

The three isolated power rails may be adjusted by con-

nection of a single resistor from the adjust pin of each

output to its associated output voltage or to GND2. The

pre-configured voltages represent the maximums for

Channel Timing Uncertainty

Multiplechannelsaresupportedacrosstheisolationbound-

arybyencodinganddecodingoftheinputsandoutputs. Up

to three signals in each direction are assembled as a serial

packetandtransferredacrosstheisolationbarrier.Thetime

required to transfer all 3 bits is 100ns maximum, and sets

the limit for how often a signal can change on the opposite

side of the barrier. Encoding transmission is independent

for each data direction. The technique used assigns SCK

or SCL on the logic side, and SDO2 or I2 on the isolated

side, the highest priority such that there is no jitter on the

associated output channels, only delay. This preemptive

scheme will produce a certain amount of uncertainty on

the other isolation channels. The resulting pulse width

uncertainty on these low priority channels is typically 6ns,

but may vary up to 44ns if the low priority channels are

not encoded within the same high priority serial packet.

guaranteed performance. Figure 5 illustrates configura-

+

tion of the output power rails for V

= 3.3V, V = 10V,

CC2

–

and V = –10V.

ꢃꢄꢅ2883ꢆꢂꢇ

ꢈ

ꢉꢉ2

3ꢗ3ꢈ

ꢓꢁꢈ

ꢈ

ꢉꢉ

ꢃ

ꢓꢘꢙꢚ

ꢂ3ꢁꢚ

ꢐꢈ

ꢂꢈ

ꢑ

ꢈ

ꢑ

ꢐꢈ

ꢈ

ꢎꢋ

ꢒ

ꢒꢓꢁꢈ

ꢐꢈ

SDOE

CS

CS2

ꢇꢌꢍ2

ꢇꢉꢏ2

ꢇꢌꢍ

ꢇꢉꢏ

ꢌꢎ2

ꢇꢌꢎ

ꢌꢎꢓ

ꢍ2

ꢇꢌꢎ2

ꢍꢓ

Serial Peripheral Interface (SPI) Bus

ꢊꢋꢌ

ꢊꢋꢌ2

2883 ꢀꢁꢂ

The LTM2883-S provides a SPI compatible isolated inter-

face. The maximum data rate is a function of the inherent

channel propagation delays, channel to channel pulse

width uncertainty, and data direction requirements. Chan-

nel timing is detailed in Figures 5 through 8 and Tables

3 and 4. The SPI protocol supports four unique timing

configurations defined by the clock polarity (CPOL) and

clock phase (CPHA) summarized in Table 2.

Figure 5ꢀ Adjustable Voltage Rails

To decreasetheoutputvoltagearesistormustbeconnected

from the output voltage pin to the associated adjust pin.

To increase the output voltage connect a resistor to the

adjust pin to GND2. Use the equations listed in Table 1

tocalculatetheresistancesrequiredtoadjusteachoutput.

Table 2ꢀ SPI Mode

TheoutputvoltageadjustmentrangeforV is3Vto5.5V.

CC2

CPOL CPHA

DATA TO (CLOCK) RELATIONSHIP

+

–

AdjustmentrangeforV andV is 1.22Vtoapproximately

0

1

0

1

0

1

Sample (Rising)

Set-Up (Falling)

Sample (Falling)

Set-Up (Rising)

Sample (Rising)

+

–

13.5V. Operation at low output voltages for V or V may

result in thermal shutdown due to low dropout regulator

power dissipation.

Set-Up (Rising)

Sample (Falling)

Set-Up (Falling)

2883fd

18

For more information www.linear.com/LTM2883

LTM2883

APPLICATIONS INFORMATION

The maximum data rate for bidirectional communication

is 4MHz, based on a synchronous system, as detailed in

the timing waveforms. Slightly higher data rates may be

achieved by skewing the clock duty cycle and minimiz-

ing the SDO to SCK set-up time, however the clock rate

is still dominated by the system propagation delays. A

discussion of the critical timing paths relative to Figure 6

and 7 follows.

• CS to SCK (master sample SDO, 1st SDO valid)

t → t

≈50ns, CS to CS2 propagation delay

0

1

t → t

Isolated slave device propagation

(response time), asserts SDO2

1

1+

t → t

≈50ns, SDO2 to SDO propagation delay

Set-up time for master SDO to SCK

1

3

t → t

3

5

ꢆꢉꢏꢐ ꢋ ꢁ

CS ꢋ SDOE

CS2

ꢃꢄꢎ

ꢃꢄꢎ2

ꢃꢆꢇ ꢈꢆꢉꢅꢊ ꢋ ꢁꢍ

ꢃꢆꢇ2 ꢈꢆꢉꢅꢊ ꢋ ꢁꢍ

ꢃꢆꢇ ꢈꢆꢉꢅꢊ ꢋ ꢌꢍ

ꢃꢆꢇ2 ꢈꢆꢉꢅꢊ ꢋ ꢌꢍ

ꢃꢄꢅ

ꢎꢖꢗꢐꢊꢎꢄ

ꢃꢄꢅ2

ꢑ

ꢁ

ꢑ

ꢓ

ꢑ

ꢂ

ꢑ

ꢔ

ꢑ

ꢕ

ꢑ

ꢌꢁ

ꢑ

ꢌ

2

3

ꢒ

ꢌꢌ ꢌ2

ꢌ3

ꢌꢒ

ꢌꢓ

ꢌꢔ

ꢌ8

ꢑ

8

2883 ꢀꢁꢂ

Figure 6ꢀ SPI Timing, Bidirectional, CPHA = 0

ꢆꢉꢏꢐ ꢋ ꢌ

CS ꢋ SDOE

CS2

ꢃꢄꢎ

ꢃꢄꢎ2

ꢃꢆꢇ ꢈꢆꢉꢅꢊ ꢋ ꢁꢍ

ꢃꢆꢇ2 ꢈꢆꢉꢅꢊ ꢋ ꢁꢍ

ꢃꢆꢇ ꢈꢆꢉꢅꢊ ꢋ ꢌꢍ

ꢃꢆꢇ2 ꢈꢆꢉꢅꢊ ꢋ ꢌꢍ

ꢃꢄꢅ

ꢎꢖꢗꢐꢊꢎꢄ

ꢃꢄꢅ2

ꢑ

ꢁ

ꢑ

ꢓ

ꢑ

ꢔ

ꢑ

ꢂ

ꢑ

ꢕ

ꢑ

ꢌꢁ

ꢑ

ꢌ

2

3

ꢒ

ꢌꢌ ꢌ2

ꢌ3

ꢌꢒ

ꢌꢓ

ꢌꢔ ꢌꢂ

ꢌ8

ꢑ

8

2883 ꢀꢁꢂ

Figure 7ꢀ SPI Timing, Bidirectional, CPHA = 1

2883fd

19

For more information www.linear.com/LTM2883

LTM2883

APPLICATIONS INFORMATION

• SDI to SCK (master data write to slave)

• SDO to SCK (master sample SDO, subsequent

SDO valid)

t → t

≈50ns, SDI to SDI2 propagation delay

≈50ns, SCK to SCK2 propagation delay

2

4

6

5

t

set-up data transition SDI and SCK

8

t → t

5

t → t

≈50ns, SDI to SDI2 and SCK to SCK2

propagation delay

8

10

t → t

2

≥50ns, SDI to SCK, separate packet

non-zero set-up time

t

10

SDO2 data transition in response to SCK2

t → t

≥50ns, SDI2 to SCK2, separate packet

non-zero set-up time

4

6

t → t ≈50ns, SDO2 to SDO propagation delay

10

11

t → t Set-up time for master SDO to SCK

11

12

Table 3ꢀ Bidirectional SPI Timing Event Description

TIME

CPHA

EVENT DESCRIPTION

t

0

0, 1

Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output

enabled, initial data is not equivalent to slave device data output

t to t

t

to t

18

0, 1

0

Propagation delay chip select, logic to isolated side, 50ns typical

Slave device chip select output data enable

0

1, 17

t

1

t

2

Start of data transmission, data set-up

1

Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

Propagation delay of slave data, isolated to logic side, 50ns typical

Slave data output valid, logic side

t to t

0, 1

0

1

3

t

3

t to t

Propagation delay of data, logic side to isolated side

Propagation delay of data and clock, logic side to isolated side

Logic side data sample time, half clock period delay from data set-up transition

Propagation delay of clock, logic to isolated side

Isolated side data sample time

2

4

1

t

5

0, 1

0

t to t

5

6

t

6

t

8

Synchronous data and clock transition, logic side

Data to clock delay, must be ≤13ns

t to t

7

8

t to t

8

Clock to data delay, must be ≤3ns

9

t to t

8

Propagation delay clock and data, logic to isolated side

Slave device data transition

10

t

10, 14

to t

t

to t

15

Propagation delay slave data, isolated to logic side

Slave data output to sample clock set-up time

10

11

13

11, 14

12

Last data and clock transition logic side

1

Last sample clock transition logic side

t

to t

0

Propagation delay data and clock, logic to isolated side

Propagation delay clock, logic to isolated side

13

15

14

1

t

0

Last slave data output transition logic side

1

Last slave data output and data transition, logic side

Propagation delay data, logic to isolated side

t

15

t

17

t

18

1

16

0, 1

Asynchronous chip select transition, end of transmission. Disable slave data output logic side

Chip select transition isolated side, slave data output disabled

2883fd

20

For more information www.linear.com/LTM2883

LTM2883

APPLICATIONS INFORMATION

Maximum data rate for single direction communication,

master to slave, is 8MHz, limited by the systems encod-

ing/decodingschemeorpropagationdelay. Timingdetails

for both variations of clock phase are shown in Figures 8

and 9 and Table 4.

• SDI and SCK set-up data transition occur within the

same data packet. Referencing Figure 6, SDI can pre-

cede SCK by up to 13ns (t → t ) or lag SCK by 3ns

7

8

(t → t ) and not violate this requirement. Similarly in

8

9

Figure 8, SDI can precede SCK by up to 13ns (t → t )

4

5

or lag SCK by 3ns (t → t ).

5

6

Additional requirements to insure maximum data rate are:

2

• CS is transmitted prior to (asynchronous) or within the

Inter-IC Communication (I C) Bus

same (synchronous) data packet as SDI

2

The LTM2883-I provides an I C compatible isolated in-

terface, Clock (SCL) is unidirectional, supporting master

mode only, and data (SDA) is bidirectional. The maximum

ꢃꢆꢎꢏ ꢉ ꢁ

CS ꢉ SDOE

CS2

ꢂꢌꢍ

ꢂꢌꢍ2

ꢂꢃꢄ ꢅꢃꢆꢇꢈ ꢉ ꢁꢋ

ꢂꢃꢄ2 ꢅꢃꢆꢇꢈ ꢉ ꢁꢋ

ꢂꢃꢄ ꢅꢃꢆꢇꢈ ꢉ ꢊꢋ

ꢂꢃꢄ2 ꢅꢃꢆꢇꢈ ꢉ ꢊꢋ

ꢐ

ꢁ

ꢐ

3

ꢐ

ꢑ

ꢐ

ꢒ

ꢐ

ꢕ

ꢐ

ꢊ2

ꢊ

2

ꢓ

8

ꢊꢊ

ꢐ

ꢔ

2883 ꢀꢁ8

Figure 8ꢀ SPI Timing, Unidirectional, CPHA = 0

ꢄꢇꢏꢐ ꢊ ꢋ

CS ꢊ SDOE

CS2

ꢃꢍꢎ

ꢃꢍꢎ2

ꢃꢄꢅ ꢆꢄꢇꢈꢉ ꢊ ꢁꢌ

ꢃꢄꢅ2 ꢆꢄꢇꢈꢉ ꢊ ꢁꢌ

ꢃꢄꢅ ꢆꢄꢇꢈꢉ ꢊ ꢋꢌ

ꢃꢄꢅ2 ꢆꢄꢇꢈꢉ ꢊ ꢋꢌ

ꢑ

ꢁ

ꢑ

3

ꢑ

ꢒ

ꢑ

ꢓ

ꢑ

ꢂ

ꢑ

ꢋ2

ꢋ

2

ꢔ

8

ꢋꢁ ꢋꢋ

ꢑ

ꢕ

2883 ꢀꢁꢂ

Figure 9ꢀ SPI Timing, Unidirectional, CPHA = 1

2883fd

21

For more information www.linear.com/LTM2883

LTM2883

APPLICATIONS INFORMATION

Table 4ꢀ Unidirectional SPI Timing Event Description

TIME

CPHA

0, 1

0

EVENT DESCRIPTION

t

Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns

Propagation delay chip select, logic to isolated side

Start of data transmission, data set-up

0

t to t

0

1

3

t

2

1

Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

Propagation delay of data, logic side to isolated side

Propagation delay of data and clock, logic side to isolated side

Logic side data sample time, half clock period delay from data set-up transition

Clock propagation delay, clock and data transition

Data to clock delay, must be ≤13ns

t to t

2

0

1

t

3

0, 1

0

t to t

3

5

6

7

t to t

4

t to t

5

Clock to data delay, must be ≤3ns

t to t

5

Data and clock propagation delay

t

8

Last clock and data transition

1

Last clock transition

t to t

0

Clock and data propagation delay

8

9

1

Clock propagation delay

t to t

1

Data propagation delay

9

10

t

11

t

12

0, 1

Asynchronous chip select transition, end of transmission

Chip select transition isolated side

2

1.8mA current source provides a pull-up for SDA2. Do not

connect any other pull-up device to SDA2. This current

source is sufficient to satisfy the system requirements for

bus capacitances greater than 200pF in FAST mode and

greater than 400pF in STANDARD mode.

data rate is 400kHz which supports fast-mode I C. Timing

is detailed in Figure 10. The data rate is limited by the slave

2

acknowledge setup time (t

), consisting of the I C

SU;ACK

standardminimumsetuptime(t

)of100ns,maximum

SU;DAT

clock propagation delay of 225ns, glitch filter and isolated

data delay of 350ns maximum, and the combined isolated

and logic data fall time of 500ns at maximum bus load-

Additional proprietary circuitry monitors the slew rate on

the SDA and SDA2 signals to manage directional control

across the isolation barrier. Slew rates on both pins must

be greater than 1V/μs for proper operation.

2

ing. The total setup time reduces the I C data hold time

(t

) to a maximum of 125ns, guaranteeing sufficient

HD;DAT

data setup time (t

).

SU;ACK

The logic side bidirectional serial data pin, SDA, requires a

The isolated side bidirectional serial data pin, SDA2,

simplified schematic is shown in Figure 11. An internal

pull-up resistor or current source connected to V . Follow

L

ꢃꢈꢅꢒꢓ ꢅꢇꢑ

ꢃꢄꢅ

ꢃꢄꢅ2

ꢃꢇꢈ

ꢁ

8

ꢆ

ꢃꢇꢈ2

ꢃꢉꢅꢊꢉ

ꢃꢉꢍꢌ

2883 ꢀꢁꢂ

ꢋ

ꢌꢊꢍꢌ

ꢋ

ꢐꢄꢏꢄꢅꢉ

ꢋ

ꢃꢎꢏꢄꢅꢉ

ꢃꢎꢏꢅꢇꢑ

Figure 10ꢀ I²C Timing Diagram

2883fd

22

For more information www.linear.com/LTM2883

LTM2883

APPLICATIONS INFORMATION

The isolated side clock pin, SCL2, has a weak push-pull

output driver; do not connect an external pull-up device.

ꢁꢅ8ꢆꢄ

ꢋꢊꢌꢏꢍꢐ ꢀꢌꢊꢏꢎꢇ

ꢏꢈ

ꢊꢈꢋꢌꢍ

2

SCL2iscompatiblewithI Cdeviceswithoutclockstretch-

ꢂꢌꢃꢎ

ꢂꢃꢄ2

ing. On lightly loaded connections, a 100pF capacitor

from SCL2 to GND2 or RC low-pass filter (R = 500Ω C =

100pF) can be used to increase the rise and fall times and

minimize noise.

ꢀꢇꢈꢉ

ꢊꢈꢋꢌꢍ

ꢂꢌꢃꢎ

2883 ꢀꢁꢁ

Some consideration must be given to signal coupling

between SCL2 and SDA2. Separate these signals on a

printed circuit board or route with ground between. If

Figure 11ꢀ Isolated SDA2 Pin Schematic

the requirements in Figures 12 and 13 for the appropri-

ate pull-up resistor on SDA that satisfies the desired rise

these signals are wired off board, twist SCL2 with V

CC2

time specifications and V maximum limits for FAST and

and/or GND2 and SDA2 with GND2 and/or V , do not

OL

CC2

STANDARD modes. The resistance curves represent the

maximum resistance boundary; any value may be used

to the left of the appropriate curve.

twist SCL2 and SDA2 together. If coupling between SCL2

and SDA2 is unavoidable, place the aforementioned RC

filter at the SCL2 pin to reduce noise injection onto SDA2.

30

RF, Magnetic Field Immunity

V = 3V

V = 3.3V

25

20

15

10

5

V = 3.6V

V = 4.5V TO 5.5V

TheisolatorµModuletechnologyusedwithintheLTM2883

hasbeenindependentlyevaluated,andsuccessfullypassed

the RF and magnetic field immunity testing requirements

per European Standard EN 55024, in accordance with the

following test standards:

EN 61000-4-3

EN 61000-4-8

EN 61000-4-9

Radiated, Radio-Frequency,

Electromagnetic Field Immunity

0

Power Frequency Magnetic Field

Immunity

10

100

(pF)

1000

C

BUS

2883 F12

Pulsed Magnetic Field Immunity

Figure 12ꢀ Maximum Standard Speed Pull-Up Resistance on SDA

Tests were performed using an unshielded test card de-

signed per the data sheet PCB layout recommendations.

Specific limits per test are detailed in Table 5.

10

V = 3V

9

8

7

6

5

4

3

2

1

0

V = 3.3V

V = 3.6V

V = 4.5V TO 5.5V

Table 5ꢀ

TEST

FREQUENCY

80MHz to 1GHz

1.4MHz to 2GHz

2GHz to 2.7GHz

50Hz and 60Hz

60Hz

FIELD STRENGTH

10V/m

EN 61000-4-3 Annex D

3V/m

1V/m

EN 61000-4-8 Level 4

EN 61000-4-8 Level 5

EN 61000-4-9 Level 5

*non IEC method

30A/m

100A/m*

1000A/m

10

100

(pF)

1000

Pulse

C

BUS

2883 F13

Figure 13ꢀ Maximum Fast Speed Pull-Up Resistance on SDA

2883fd

23

For more information www.linear.com/LTM2883

LTM2883

APPLICATIONS INFORMATION

PCB Layout

anyhighfrequencydifferentialvoltagesandsubstantially

reducing radiated emissions. Discrete capacitance will

notbeaseffectiveduetoparasiticESL.Inaddition,volt-

age rating, leakage, and clearance must be considered

for component selection. Embedding the capacitance

withinthePCBsubstrateprovidesanearidealcapacitor

and eliminates component selection issues; however,

the PCB must be 4 layers. Care must be exercised in

applying either technique to insure the voltage rating

of the barrier is not compromised.

The high integration of the LTM2883 makes PCB layout

very simple. However, to optimize its electrical isolation

characteristics, EMI, and thermal performance, some

layout considerations are necessary.

• Under heavily loaded conditions V and GND current

CC

can exceed 300mA. Sufficient copper must be used

on the PCB to insure resistive losses do not cause the

supply voltage to drop below the minimum allowed

level. Similarly, the V

and GND2 conductors must

CC2

The PCB layout in Figures 14a and 14b shows the low

EMI demo board for the LTM2883. The demo board uses

a combination of EMI mitigation techniques, including

both embedded PCB bridge capacitance and discrete GND

to GND2 capacitors. Two safety rated type Y2 capacitors

are used in series, manufactured by MuRata, part number

GA342QR7GF471KW01L. The embedded capacitor ef-

fectively suppresses emissions above 400MHz, whereas

the discrete capacitors are more effective below 400MHz.

be sized to support any external load current. These

heavy copper traces will also help to reduce thermal

stress and improve the thermal conductivity.

• Inputandoutputdecouplingisnotrequired,sincethese

components are integrated within the package. An ad-

ditional bulk capacitor with a value of 6.8µF to 22µF is

recommended. The high ESR of this capacitor reduces

boardresonancesandminimizesvoltagespikescaused

by hot plugging of the supply voltage. For EMI sensitive

applications,anadditionallowESLceramiccapacitorof

1µF to 4.7µF, placed as close to the power and ground

terminalsaspossible, isrecommended. Alternatively, a

numberofsmallervalueparallelcapacitorsmaybeused

to reduce ESL and achieve the same net capacitance.

EMI performance is shown in Figure 15, measured using

a Gigahertz Transverse Electromagnetic (GTEM) cell and

method detailed in IEC 61000-4-20, Testing and Measure-

ment Techniques – Emission and Immunity Testing in

Transverse Electromagnetic Waveguides.

• Do not place copper on the PCB between the inner col-

umnsofpads. Thisareamustremainopentowithstand

the rated isolation voltage.

• The use of solid ground planes for GND and GND2

is recommended for non-EMI critical applications to

optimize signal fidelity, thermal performance, and to

minimize RF emissions due to uncoupled PCB trace

conduction. The drawback of using ground planes,

where EMI is of concern, is the creation of a dipole

antennastructurewhichcanradiatedifferentialvoltages

formed between GND and GND2. If ground planes are

used it is recommended to minimize their area, and

use contiguous planes as any openings or splits can

exacerbate RF emissions.

• For large ground planes a small capacitance (≤330pF)

from GND to GND2, either discrete or embedded within

the substrate, provides a low impedance current return

path for the module parasitic capacitance, minimizing

TECHNOLOGY

Figure 14aꢀ LTM2883 Low EMI Demo Board Layout

2883fd

24

For more information www.linear.com/LTM2883

LTM2883

APPLICATIONS INFORMATION

Top Layer

Inner Layer 2

Inner Layer 1

Bottom Layer

Figure 14bꢀ LTM2883 Low EMI Demo Board Layout (DC1748A)

2883fd

25

For more information www.linear.com/LTM2883

LTM2883

APPLICATIONS INFORMATION

ꢕꢍ

ꢘꢍ

ꢆꢧꢦꢢꢁ 22 ꢆꢫꢩꢦꢦ ꢏ ꢫꢧꢉꢧꢛ

ꢚꢆꢔꢖꢙ8ꢩꢪꢏ

ꢙꢍ

3ꢍ

2ꢍ

ꢔꢍ

ꢚꢆꢔꢖꢙ8ꢩꢪꢩ

ꢍ

ꢚꢂꢛꢂꢆꢛꢜꢁ ꢝ ꢃꢞꢟꢠꢡꢢꢣꢟꢤ

ꢁꢏꢥ ꢝ ꢔ2ꢍꢤꢊꢋ

ꢑꢏꢥ ꢝ 3ꢍꢍꢤꢊꢋ

ꢦꢥꢂꢂꢢ ꢛꢧꢉꢂ ꢝ ꢔꢖꢠ

ꢨ ꢜꢀ ꢢꢜꢧꢅꢛꢦ ꢝ ꢘꢍꢔ

ꢎꢔꢍ

ꢎ2ꢍ

ꢎ3ꢍ

ꢍ

ꢔꢍꢍ 2ꢍꢍ 3ꢍꢍ ꢙꢍꢍ ꢘꢍꢍ ꢕꢍꢍ ꢖꢍꢍ 8ꢍꢍ ꢗꢍꢍꢔꢍꢍꢍ

ꢀꢁꢂꢃꢄꢂꢅꢆꢇ ꢈꢉꢊꢋꢌ

2883 ꢀꢔꢘ

Figure 15ꢀ LTM2883 Low EMI Demo Board Emissions

TYPICAL APPLICATIONS

ꢗꢟꢁꢏꢀ

ꢁ2ꢟꢇꢉ

ꢍ

ꢃꢄꢅ2883ꢆꢇꢈ

ꢗꢟꢁꢏꢀ

ꢁꢏꢀ

ꢌ8

ꢊ8

ꢃ8

ꢎ8

ꢃꢍ

ꢎꢍ

ꢃꢂ

ꢎꢂ

ꢚ

ꢙ

8

ꢁ2ꢟꢇꢉ

ꢉ

ꢊꢉ

ꢉ

ꢇꢉ

ꢉ

ꢑꢑ

ꢃ

3

2

ꢚ

ꢁꢏꢀ

ꢁ

8

ꢛ

ꢁꢡ2 ꢃꢄꢑ2ꢗꢇꢇ

ꢙꢁ2ꢟꢇꢉ

ꢇꢉ

ꢁꢟꢍꢠ

ꢙ

ꢊꢉ

ꢙ

ꢁꢗ

ꢊꢍ

ꢊꢂ

ꢊꢇ

ꢊꢋ

ꢊ3

ꢊ2

ꢊꢁ

ꢌꢁ

ꢌ2

ꢋ

ꢉ

ꢝꢔ

ꢑꢑ2

ꢂ

ꢃꢄꢁꢛꢛꢁ

ꢓ ꢢ 8

ꢁꢟꢍꢠ

ꢁꢗꢉ ꢝꢞꢄ

ꢁ

2

3

ꢊꢉ

ꢓꢔꢒ

ꢒꢈꢁ

ꢑꢑ2

ꢝꢁ

ꢉ

ꢑꢑ

ꢃꢇ

ꢃꢋ

ꢃ3

ꢃ2

ꢃꢁ

ꢎꢁ

ꢎ2

ꢃꢄꢑ2ꢂ3ꢁꢊꢆꢃꢅꢁ2ꢘ ꢒꢊꢑ

ꢁꢟ2ꢇꢉ

ꢚ

ꢁ

2

3

ꢋ

8

ꢍ

ꢂ

ꢇ

ꢐꢒꢊ2

ꢐꢑꢃ2

ꢒꢔꢑ

ꢈ2

ꢑꢊꢗ

ꢐꢑꢃ

ꢐꢒꢊ

ꢓꢔꢒ

ꢕꢜꢐꢖꢃ

ꢐꢒꢊ

ꢐꢑꢃ

ꢐꢒꢊ

ꢐꢑꢃ

ꢒꢔꢑ

ꢒꢝ2

ꢒꢝꢁ

ꢓꢔꢒ

ꢇ

2ꢟꢇꢉ ꢟꢐꢟ

ꢗꢟꢁꢏꢀ

ꢋ

ꢏꢑ

ꢉ

ꢝꢞꢄ

ꢙꢁ2ꢟꢇꢉ

ꢕꢖꢀ

ꢇ

ꢂ

ꢚ

ꢉ

ꢑꢑ

ꢓꢔꢒ

ꢍ

ꢈꢁ

ꢁꢡ2 ꢃꢄꢑ2ꢗꢇꢇ

ꢓꢔꢒ2

2883 ꢀꢁꢂ

ꢙ

ꢗꢟꢁꢏꢀ

ꢁ2ꢟꢇꢉ

ꢍ

ꢗꢟꢁꢏꢀ

2ꢟꢇꢉ

ꢃꢄꢑ23ꢗꢁꢘ ꢊꢒꢑ

ꢁꢗ

ꢁꢁ

ꢁ2

ꢁ

ꢛ

8

ꢍ

ꢂ

ꢇ

ꢋ

ꢓꢔꢒ

ꢊꢒꢗ ꢕꢖꢀꢑ

ꢉ

ꢒꢒ

ꢗꢟꢁꢏꢀ

8

ꢙ ^ꢛ_ꢁꢗ

ꢊꢒꢁ

ꢓꢔꢒ

ꢐꢒꢊ

ꢐꢑꢃ

ꢉ

ꢁꢗꢏꢀ

ꢁꢏꢀ

ꢗꢟꢁꢏꢀ

ꢕꢖꢀ

ꢙ

ꢈꢔ

2

ꢂ

ꢃꢄꢁꢛꢛꢁ

ꢓ ꢢ ꢗꢟ2

ꢚ

ꢈꢔ

ꢁ

ꢋꢉ ꢟꢐꢟ

3

ꢁꢗꢉ ꢈꢔ

ꢓꢔꢒ

ꢚ ²

3

ꢇ

ꢗꢟꢁꢏꢀ

ꢋ

ꢙꢁ2ꢟꢇꢉ

Figure 16ꢀ Isolated I²C 12-Bit, 10V Analog Input and Output

2883fd

26

For more information www.linear.com/LTM2883

LTM2883

TYPICAL APPLICATIONS

ꢆꢇꢈ2883ꢉ3ꢊ

ꢖ8

ꢐ8

ꢆ8

ꢏ8

ꢆꢂ

ꢏꢂ

ꢆꢕ

ꢏꢕ

ꢑ

ꢒ

ꢋ

ꢐꢋ

ꢋ

3ꢛ3ꢋ

ꢋ

ꢌꢌ

ꢆ

ꢁꢞꢟ

ꢁꢝꢀ

ꢂꢔꢋꢌꢁꢍꢁ23

ꢐꢋ

ꢌꢘ

ꢗꢘꢙꢌꢘ

ꢌꢆꢗ

ꢐ

ꢐꢂ

ꢐꢕ

ꢐꢓ

ꢐꢔ

ꢐ3

ꢐ2

ꢐꢁ

ꢖꢁ

ꢖ2

ꢋ

CSꢁ

ꢃꢄ

ꢌꢌ2

ꢐꢋ

SDOE

CS

ꢆꢓ

ꢆꢔ

ꢆ3

ꢆ2

ꢆꢁ

ꢏꢁ

ꢏ2

ꢁꢜꢀ

CS2

ꢊꢎꢅ2

ꢊꢌꢏ2

ꢅ2

CSꢀ

ꢖ

ꢚ

ꢈꢃꢊꢅ

ꢊꢌꢏ

ꢊꢎꢅ

ꢊꢌꢏ

ꢎꢃ2

ꢊꢎꢃ

ꢎꢃꢁ

ꢍꢄꢎ

ꢋ

ꢌꢌ

CSꢀ

CSꢁ

ꢊꢎꢃ2

ꢅꢁ

ꢈꢅꢊꢃ

ꢜꢌ

ꢍꢄꢎ2

2883 ꢀꢁꢂ

ꢈꢃꢊꢅ

ꢊꢌꢏ

ꢈꢅꢊꢃ

ꢍꢄꢎ

CSꢀ

CSꢁ

ꢈꢃꢊꢅ

ꢊꢌꢏ

Figure 17ꢀ Isolated SPI Device Expansion

LTM2883-5I

B8

A8

L8

K8

L7

K7

L6

K6

+

–

V

AV

V

5V

V

CC

L

AV

10k

A7

A6

A5

A4

A3

A2

A1

B1

B2

V

ON

CC2

AV

GND

DI1

8.66k

137Ω

CC2

O1

10k

L5

L4

L3

L2

L1

K1

K2

ENABLE

SDA

1

2

3

4

5

10

SDA2

SCL2

DNC

I2

SDAOUT

SDA

SCL

DNC

DO2

DO1

GND

SDAIN

SCLIN

CONN

ADDR

GND

9

8

7

6

SCLIN

SCLOUT

LTC4302-1

V

CC

GPIO2

GPIO1

GPIO2

GPIO1

I1

GND2

2883 F18

Figure 18ꢀ Isolated I²C Buffer with Programmable Outputs

2883fd

27

For more information www.linear.com/LTM2883

LTM2883

TYPICAL APPLICATIONS

ꢆꢇꢈ2883ꢉꢊꢋ

ꢖ8

ꢑ8

ꢆ8

ꢐ8

ꢆꢗ

ꢐꢗ

ꢆꢕ

ꢐꢕ

ꢒ

ꢓ

ꢌ

ꢑꢌ

ꢌ

ꢊꢌ

ꢌ

ꢍꢍ

ꢆ

ꢁꢘꢀ

ꢑꢌ

ꢄꢇꢍ ꢇꢞꢟꢠꢈꢅꢋꢇꢃꢠꢋꢡ ꢈꢢꢠꢑꢇꢑ ꢄꢇꢋꢏꢁꢣꢏꢁꢝꢔꢡ ꢁꢝꢝꢤ

ꢓꢥꢦ ꢓꢥꢦ ꢓꢥꢦ ꢓꢥꢦ

ꢑꢗ

ꢑꢕ

ꢑꢊ

ꢑꢔ

ꢑ3

ꢑ2

ꢑꢁ

ꢖꢁ

ꢖ2

ꢌ

ꢃꢄ

ꢍꢍ2

ꢑꢌ

SDOE

CS

ꢌ

ꢍꢍ

ꢆꢊ

ꢆꢔ

ꢆ3

ꢆ2

ꢆꢁ

ꢐꢁ

ꢐ2

CS2

ꢋꢏꢅ2

ꢋꢍꢐ2

ꢅ2

ꢃꢚ

ꢃꢛ

ꢃꢙ

ꢋꢏꢅ

ꢆꢇꢍꢁꢗꢂꢂ

ꢋꢍꢐ

ꢏꢃ2

ꢋꢏꢃ

ꢏꢃꢁ

ꢎꢄꢏ

ꢘꢍ

ꢓꢥꢦ

ꢊ

ꢔ

ꢁ

2

3

ꢒ

ꢏꢎꢔꢝꢊꢁꢑ

ꢜꢝ

ꢌ

ꢁꢈ

ꢃꢢꢇ

ꢁꢕ

3

ꢁ3

ꢁꢔ

ꢁꢊ

ꢁ2

ꢁ

ꢅꢛ

ꢅꢙ

ꢋꢏꢃ2

ꢅꢁ

ꢎꢄꢏ

ꢌ

ꢜ

ꢑ

ꢖ

ꢍ

ꢍꢍ

3ꢧꢝꢁꢤ

ꢜꢁ

ꢜ2

ꢜ3

ꢜꢔ

ꢏꢅꢌ ꢋꢟꢇ

ꢎꢄꢏ

ꢁꢁ

ꢁꢝ

ꢂ

ꢎꢄꢏ2

2883 ꢀꢁꢂ

ꢕ

ꢊ

ꢟꢄꢑꢖꢆꢟ ꢜꢊ

ꢗ

2

ꢌ

ꢜꢕ

ꢜꢗ

ꢟꢟ

8

ꢔ

TEMPERATURE (°C) FREQUENCY (kHz)

ꢎꢄꢏ

ꢓꢔꢝ

ꢓ3ꢝ

ꢓ2ꢝ

ꢓꢁꢝ

ꢝ

ꢁꢧ23

ꢁꢧꢔꢕ

ꢓꢥꢦ

ꢁꢧ8ꢗ

2ꢧꢊ8

3ꢧꢗꢗ

ꢆꢇꢍꢁꢗꢂꢂ

ꢒ

ꢁꢝ

ꢊꢧꢕꢗ

ꢊ

ꢔ

ꢁ

2

3

ꢏꢎꢔꢝꢊꢁꢑ

2ꢝ

8ꢧꢕꢔ

ꢌ

ꢃꢢꢇ

ꢁꢈ

ꢁꢕ

3

ꢁ3

ꢁꢔ

ꢁꢊ

ꢁ2

ꢁ

ꢓꢥꢦ

3ꢝ

ꢁ3ꢧꢝꢂ

ꢁꢂꢧꢊ3

28ꢧꢔꢗ

ꢔꢝꢧꢕꢊ

ꢊꢊꢧ8ꢗ

ꢗꢔꢧꢔꢊ

ꢂꢕꢧꢝ8

ꢁꢁꢂꢧ83

ꢁꢔꢔꢧꢗ3

ꢁꢕꢂꢧ3ꢕ

ꢜꢝ

ꢜꢁ

ꢜ2

ꢜ3

ꢜꢔ

ꢎꢄꢏ

ꢌ

ꢜ

ꢑ

ꢖ

ꢍ

ꢍꢍ

3ꢧꢝꢁꢤ

ꢔꢝ

ꢏꢅꢌ ꢋꢟꢇ

ꢊꢝ

ꢁꢁ

ꢁꢝ

ꢂ

ꢕꢝ

ꢗꢝ

8ꢝ

ꢂꢝ

ꢁꢝꢝ

ꢁꢁꢝ

ꢁ2ꢝ

ꢕ

ꢊ

ꢟꢄꢑꢖꢆꢟ ꢜꢊ

ꢗ

2

ꢌ

ꢜꢕ

ꢜꢗ

ꢟꢟ

8

ꢔ

ꢎꢄꢏ

Figure 19ꢀ 16-Channel Isolated Temperature to Frequency Converter

2883fd

28

For more information www.linear.com/LTM2883

LTM2883

TYPICAL APPLICATIONS

ꢄꢞꢀꢜꢉꢁꢝ

ꢓꢁꢁꢡ

ꢊꢘꢄꢆꢌꢙꢖꢎ ꢓ2ꢔꢉꢋ

ꢊꢘꢄꢆꢌꢙꢖꢎ ꢒꢓ2ꢔꢉꢋ

ꢅꢆꢇ2883ꢈꢉꢊ

ꢗ8

ꢐ8

ꢅ8

ꢏ8

ꢅꢜ

ꢏꢜ

ꢅꢛ

ꢏꢛ

ꢑ

ꢒ

ꢄꢞꢀꢜꢉꢁꢝ

ꢋ

ꢐꢋ

ꢋ

ꢉꢋ

ꢋ

ꢌꢌ

ꢅ

ꢓꢁꢁꢡ

ꢐꢋ

ꢐꢜ

ꢐꢛ

ꢐꢉ

ꢐꢚ

ꢐ3

ꢐ2

ꢐꢓ

ꢗꢓ

ꢗ2

ꢋ

ꢂꢃ

ꢌꢌ2

ꢄꢞꢀꢜꢉꢁꢝ

ꢓꢁꢁꢡ

ꢐꢋ

SDOE

CS

ꢅꢉ

ꢅꢚ

ꢅ3

ꢅ2

ꢅꢓ

ꢏꢓ

ꢏ2

ꢄꢞꢅꢇꢅ2ꢚꢁ2

ꢓꢁꢁꢡ

ꢒꢓ2ꢔꢉꢋ ꢖꢃꢐꢗꢅꢖ

ꢓ2ꢔꢉꢋ ꢖꢃꢐꢗꢅꢖ

ꢉꢋ ꢖꢃꢐꢗꢅꢖ

ꢓ2ꢔꢉꢋ ꢕꢋ

CS2

ꢊꢎꢄ2

ꢊꢌꢏ2

ꢄ2

ꢊꢘꢄꢆꢌꢙꢖꢎ ꢉꢋ

ꢊꢎꢄ

ꢊꢌꢏ

ꢎꢂ2

ꢊꢎꢂ

ꢎꢂꢓ

ꢍꢃꢎ

22ꢛꢡ

ꢊꢎꢂ2

ꢄꢓ

ꢒꢓ2ꢔꢉꢋ ꢕꢋ

ꢉꢋ ꢕꢋ

ꢍꢃꢎ2

2883 ꢀ2ꢁ

ꢅꢆꢌ2ꢝꢁ2

ꢌꢂꢇꢟ2

ꢌꢂꢇꢟꢓ ꢌꢂꢇꢟꢚ

ꢓ

2

3

ꢚ

ꢉ

ꢛ

ꢜ

8

ꢓꢛ

ꢓꢉ

ꢓꢚ

ꢓ3

ꢓ2

ꢓꢓ

ꢓꢁ

ꢝ

ꢌꢂꢇꢟ3

ꢓꢝꢛꢡ

2ꢁꢡ

ꢁꢔꢓꢠꢀ

ꢋ3

ꢋ2

ꢋꢚ

ꢋꢓ

ꢌꢞꢆ

ꢀSꢂ

ꢆꢁ

ꢋ

ꢞꢖꢀ

ꢓꢁꢡ

ꢋ

ꢝ3ꢔꢓꢡ

ꢝꢔꢉ3ꢡ

ꢟꢍ

ꢍꢃꢎ

ꢆꢓ

ꢀDꢁS

Figure 20ꢀ Digitally Switched Triple Power Supply with Undervoltage Monitor

2883fd

29

For more information www.linear.com/LTM2883

LTM2883

TYPICAL APPLICATIONS

ꢜꢂꢁꢑꢅ

ꢁ2ꢂꢃꢄ

ꢏ

8

ꢛ

ꢀ

ꢞ

ꢁꢜ

ꢍ

ꢆꢇꢁꢛꢛꢁ

ꢕ ꢟ 8

ꢁꢜꢄ ꢓꢘꢇꢋ

ꢁꢜꢄ ꢓꢘꢇꢎ

ꢁꢜꢄ ꢓꢘꢇꢒ

ꢁ

2

3

ꢃ

ꢜꢂꢁꢑꢅ

ꢌ

ꢀꢁ2ꢂꢃꢄ

ꢜꢂꢁꢑꢅ

ꢃꢄ

ꢜꢂꢁꢑꢅ

ꢁꢂ2ꢃꢄ

ꢁ2ꢂꢃꢄ

ꢆꢇꢈ2883ꢉ3ꢊ

ꢃ

3

ꢌ

ꢎ8

ꢋ8

ꢆ8

ꢐ8

ꢆꢏ

ꢐꢏ

ꢆꢍ

ꢐꢍ

ꢞ

ꢀ

ꢏ

8

ꢛ

ꢞ

ꢀ

ꢁ2ꢂꢃꢄ

ꢄ

ꢋꢄ

ꢄ

3ꢂ3ꢄ

ꢄ

ꢒꢒ

ꢆ

ꢁ

ꢆꢇꢒ2ꢜꢃꢌ

2

ꢁꢑꢅ

ꢀ

ꢞ

ꢁꢜ

ꢀꢁ2ꢂꢃꢄ

ꢆꢇꢁꢛꢛꢁ

ꢕ ꢟ 8

ꢆꢇꢒ2ꢍꢃꢌꢉꢆꢁꢍ

ꢋꢄ

ꢁ

2

3

ꢋꢏ

ꢋꢍ

ꢋꢃ

ꢋꢌ

ꢋ3

ꢋ2

ꢋꢁ

ꢎꢁ

ꢎ2

ꢁꢃ

ꢍ

ꢃ

ꢄ

ꢙꢚꢅꢓꢘꢇ

ꢄ

ꢒꢒ

ꢓꢖ

ꢒꢒ2

3

ꢋꢄ

SDOE

CS

ꢀDꢂC

CS

ꢙꢚꢅꢒ

ꢄ

ꢃ

ꢒꢒ

ꢆꢃ

ꢆꢌ

ꢆ3

ꢆ2

ꢆꢁ

ꢐꢁ

ꢐ2

ꢏ

2

ꢜꢂꢁꢑꢅ

CS2

ꢊꢗꢔ2

ꢊꢒꢐ2

ꢔ2

CS

ꢄ

ꢌ

ꢓꢘꢇꢋ

ꢓꢘꢇꢎ

ꢓꢘꢇꢒ

ꢓꢘꢇꢗ

ꢛ

ꢌ

ꢈꢓꢊꢔ

ꢊꢒꢐ

ꢊꢗꢔ

ꢄ

ꢀꢁ2ꢂꢃꢄ

8

ꢁ3

ꢁꢌ

ꢁ

ꢊꢒꢐ

ꢗꢓ2

ꢊꢗꢓ

ꢗꢓꢁ

ꢕꢖꢗ

ꢊꢒꢐ

Cꢀꢁ

ꢊꢗꢓ

ꢑꢒ

ꢁꢁ

ꢁꢜ

ꢁ2

ꢄ

ꢜꢂꢁꢑꢅ

ꢈꢔꢊꢓ

ꢊꢗꢓ2

ꢔꢁ

ꢙꢚꢅꢆꢓ

ꢜꢂꢁꢑꢅ

ꢁꢍ

ꢕꢖꢗ

ꢁ2ꢂꢃꢄ

ꢝꢓꢙꢊꢚꢆ ꢕꢖꢗ

ꢕꢖꢗ2

2883 ꢅ2ꢁ

ꢏ

8

ꢛ

ꢀ

ꢞ

ꢁꢜ

ꢆꢇꢁꢛꢛꢁ

ꢕ ꢟ 8

ꢁ

2

3

ꢃ

ꢜꢂꢁꢑꢅ

ꢌ

ꢀꢁ2ꢂꢃꢄ

ꢜꢂꢁꢑꢅ

ꢁ2ꢂꢃꢄ

ꢏ

8

ꢛ

ꢀ

ꢞ

ꢁꢜ

ꢆꢇꢁꢛꢛꢁ

ꢕ ꢟ 8

ꢁꢜꢄ ꢓꢘꢇꢗ

ꢁ

2

3

ꢃ

ꢜꢂꢁꢑꢅ

ꢌ

ꢀꢁ2ꢂꢃꢄ

Figure 21. Quad 16-Bit 10V Output Range DAC

2883fd

30

For more information www.linear.com/LTM2883

LTM2883

TYPICAL APPLICATIONS

LTM2883-5I

B8

A8

L8

K8

L7

K7

L6

K6

+

–

V

AV

V

5V

V

CC

L

1µF

10k

AV

A7

A6

A5

A4

A3

A2

A1

B1

B2

V

ON

CC2

V

CC

AV

GND

DI1

CC2

O1

L5

L4

L3

L2

L1

K1

K2

Ox

SDA2

SCL2

DNC

I2

SDA

SCL

Ix

SDA

SCL

DNC

DO2

DO1

GND

µC

10k

GND

I1

GND2

V

EE

–48V RTN

1k, ×4 IN SERIES

1/4W EACH

453k

7

21

8

9

22

6

INTV

V

IN

ꢀꢁꢂꢃꢄ

SCL

UVL

UVH

ADIN2

OV

CC

16.9k

10

11

19

20

26

1

5

SDAI

SDAO

ꢅꢁEꢆꢂ

ON

4

3

SS

2

LTC4261CGN

TMR

Eꢄ

28

27

23

ꢇꢈꢃ

PGI0

ꢇꢈ

ꢇꢉꢆꢈD2

ꢇꢉꢆꢈDꢊ

25

24

ADR1

ADR0

ADIN

11.8k

V

SENSE GATE DRAIN RAMP

14 15 16 18

EE

13

+

330µF

100V

1M

1k

100nF

1µF

220nF

10Ω

47nF

V

10nF

100V

OUT

0.1µF

47nF

10k

0.1µF

–48V INPUT

IRF1310NS

0.008Ω

1%

402k

V

EE

2883 F22

Figure 22. –48V, 200W Hot Swap Controller with Isolated I²C Interface

2883fd

31

For more information www.linear.com/LTM2883

LTM2883

TYPICAL APPLICATIONS

3ꢜ3ꢈ

ꢃꢄꢅ2883ꢆ3ꢇ

ꢃꢄꢉꢓ8ꢖ3ꢆꢐ

CSO

3ꢜ3ꢞ

ꢔ8

ꢍ8

ꢃ8

ꢌ8

ꢃꢕ

ꢌꢕ

ꢃꢓ

ꢌꢓ

ꢒꢒ

ꢒ3

ꢒ2

ꢒꢐ

ꢒꢖ

3ꢙ

38

3ꢕ

3ꢓ

3ꢑ

3ꢒ

33

32

3ꢐ

3ꢖ

2ꢙ

28

2ꢕ

2ꢓ

2ꢑ

2ꢒ

23

ꢐ

ꢎ

ꢏ

3ꢜ3ꢞ

ꢈ

ꢍꢈ

ꢈ

CSꢀ

ꢇꢋꢀ

ꢇꢋꢂ

ꢇꢉꢌꢂ

ꢈ

ꢉꢉ

ꢐꢚꢛ

2

ꢇꢋꢀꢂ

ꢃ

3

ꢇꢉꢌꢀ

ꢒ

ꢎ

ꢍꢈ

ꢈ

ꢍꢕ

ꢍꢓ

ꢍꢑ

ꢍꢒ

ꢍ3

ꢍ2

ꢍꢐ

ꢔꢐ

ꢔ2

ꢑ

ꢈ

ꢉꢐ2

ꢇꢐ2

ꢉꢐꢐ

ꢇꢐꢐ

ꢉꢐꢖ

ꢇꢐꢖ

ꢉꢙ

ꢀꢁ

ꢉꢉ2

ꢅꢀꢋꢗ

ꢓ

ꢍꢈ

SDOE

CS

ꢊꢘꢂꢀ2

ꢊꢘꢂꢀꢐ

ꢁDꢂ

ꢃꢃ

ꢈ

ꢉꢉ

ꢃꢑ

ꢃꢒ

ꢃ3

ꢃ2

ꢃꢐ

ꢌꢐ

ꢌ2

ꢕ

ꢐꢚꢛ

CS2

ꢇꢋꢂ2

ꢇꢉꢌ2

ꢂ2

CS

8

ꢅꢀꢇꢂ

ꢇꢉꢌ

ꢇꢋꢂ

ꢚꢉ

ꢙ

ꢇꢉꢌ

ꢋꢀ2

ꢇꢋꢀ

ꢋꢀꢐ

ꢊꢁꢋ

ꢐꢖ

ꢐꢐ

ꢐ2

ꢐ3

ꢐꢒ

ꢐꢑ

ꢐꢓ

ꢐꢕ

ꢐ8

ꢐꢙ

2ꢖ

2ꢐ

22

ꢅꢂꢇꢀ

ꢊꢁꢋ

ꢄꢀꢇ

ꢇꢋꢀ2

ꢂꢐ

ꢈ

ꢝꢗꢊ

ꢐꢖꢖꢞ

ꢕꢒꢃꢈꢉ3ꢊꢖꢕ

ꢇꢙ

ꢝꢗꢛ

ꢊꢁꢋ2

2883 ꢛ23

ꢉ8

ꢄꢗꢅꢘ2

ꢄꢗꢅꢘꢐ

ꢇ8

ꢁꢉ

ꢉꢕ

ꢏ

ꢈ

ꢇꢕ

ꢐꢖꢖꢞ

ꢇꢐ

ꢉꢐ

ꢇ2

ꢉ2

ꢇ3

ꢉ3

ꢉꢓ

ꢇꢓ

ꢉꢑ

ꢇꢑ

ꢉꢒ

ꢇꢒ

Figure 23. 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown

LTM2883-3I

B8

A8

L8

K8

L7

K7

L6

K6

+

–

0.02Ω

V

AV

V

3.3V

V

CC

L

48V

V

OUT

1µF

10k

+

–

AV

SENSE SENSE

V

IN

A7

A6

A5

A4

A3

A2

A1

B1

B2

V

ON

SꢀDꢁ

100k AT 25°C, 1%

VISHAY 2381 6154.104

CC2

10k

V

CC

AV

GND

DI1

CC2

O1

L5

L4

L3

L2

L1

K1

K2

SDA2

SCL2

DNC

I2

SDA

SCL

SDA

SCL

DNC

DO2

DO1

GND

ADIN

LTC4151

µC

SCL

ADR0

ADR1

1.37k

1%

GND

I1

GND2

2883 F24

GND

3950

T(°C)=

− 273,−40°C< T <150°C





1000

8.965+LN

−1





N





ADIN

N

IS THE DIGITAL CODE MEASURED

ADIN

BY THE ADC AT THE ADIN PIN

Figure 24. Isolated I²C Voltage, Current and Temperature Power Supply Monitor

2883fd

32

For more information www.linear.com/LTM2883

LTM2883

TYPICAL APPLICATIONS

LTM2883-5I

B8

L8

K8

L7

K7

L6

K6

+

–

V

AV

V

5V

V

CC

A8

L

10k

0.1µF

10k

AV

A7

A6

A5

A4

A3

A2

A1

B1

B2

V

ON

SꢀꢁꢂDOꢃꢄ

174k

CC2

0.1µF

AV

GND

DI1

100k

CC2

O1

SꢀDꢄꢈ V

DD

L5

L4

L3

L2

L1

K1

K2

ENABLE

SDA

ꢆESEꢂ

SDAIN

SCL

BYP

SDA2

SCL2

DNC

I2

SDA

SCL

DNC

DO2

DO1

GND

SCLIN

SDAOUT

AUTO

ꢅꢄꢂ

DETECT

1/4 LTC4266

ꢅꢄꢂEꢆꢆꢁꢇꢂ

I1

GND2

AD0

AD1

AD2

CMPD3003

AD3

V

DGND AGND

SENSE GATE OUT

EE

Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T

FB1, FB2: TDK MPZ2012S601A

T1: PULSE H609NL OR COILCRAFT ETH1-230LD

SMAJ58A

1µF

0.25Ω

Q1

–48V

S1B

0.22µF

FB1

FB2

RJ45

CONNECTOR

T1

1

2

3

4

5

6

7

8

•

10nF

75Ω

PHY

(NETWORK

PHYSICAL

LAYER

•

CHIP)

10nF

75Ω

1nF

2883 F25

Figure 25. One Complete Isolated Powered Ethernet Port

2883fd

33

For more information www.linear.com/LTM2883

LTM2883

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTM2883#packaging for the most recent package drawings.

ꢟ

ꢶ ꢶ ꢮ ꢮ ꢮ

ꢟ

ꢒ ꢇ ꢒ ꢒ ꢓ

3 ꢇ ꢆ ꢦ ꢓ

ꢆ ꢇ ꢕ ꢘ ꢓ

ꢘ ꢇ ꢬ 3 ꢓ

ꢘ ꢇ ꢘ ꢘ ꢘ

ꢆ ꢇ ꢕ ꢘ ꢓ

3 ꢇ ꢆ ꢦ ꢓ

ꢒ ꢇ ꢒ ꢒ ꢓ

ꢥ ꢥ ꢥ

ꢟ

2883fd

34

For more information www.linear.com/LTM2883

LTM2883

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

11/12 Storage temperature range updated.

2

B

8/13

5/14

Added CTI/DTI parameters and Notes 6, 7 to Isolation Characteristics table.

6, 7

C

Removed H-grade throughout data sheet.

Changed Depth of Erosion parameter.

1-36

6

Changed overtemperature protection threshold.

7

D

11/17 Added H-Grade; removed Obsolete mark from H-Grade.

2, 3

2

Raised Maximum Internal Operating Temperature, Storage Temperature Range, and package T

Updated graphs showing performance characteristics vs temperature.

.

JMAX

8, 9

2883fd

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is graninted by implication or otherr.wise u/Lnder any patent or patent rights of Analog Devices.

For more formation www.linea com TM2883

35

LTM2883

TYPICAL APPLICATION

Precision 4mA to 20mA Sink/Source with Current Monitor

LTM2883-3S

B8

A8

L8

K8

L7

K7

L6

K6

+

–

V

AV

V

12.5V

SINK

3.3V

V

CC

L

LTC2641, DAC

1µF

1

2

3

4

8

7

6

5

7

LTC1050

4

1µF

GND

REF

CS

3

2

75k

+

–

AV

V

DD

1k

6

A7

A6

A5

A4

A3

A2

A1

B1

B2

Si1555DL_N

V

ON

SCK

DIN

V

OUT

CC2

AV

Cꢀꢁ

SDOE

CS

V

CC

L5

L4

L3

L2

L1

K1

K2

CS2

SDI2

SCK2

I2

CS

0.1µF

0.01µF

SDI

MOSI

SCK

µC

SCK

DO2

SDO

DO1

GND

5V

10

MISO

11

+

–

GND

SDO2

I1

14

3

LTC1100

G = 10

15Ω

0.1%

100k

15

3V

6

GND2

2883 TA02

LTC2452, ADC

LT6660-3

IN OUT

2

7

3

1

3

7

1

8

4

6

5

2

V

REF

CS

CC

+

IN

GND

2

–

0.1µF

SCK

IN

SOURCE

RETURN

0.1µF

SDO GND

–5V

RELATED PARTS

PART NUMBER

LTM2881

LTM2882

LTC4310

DESCRIPTION

COMMENTS

Isolated RS485/RS422 µModule Transceiver Plus Power 20Mbps 2500V

Isolation with Power in LGA/BGA Package

RMS

Dual Isolated RS232 µModule Transceiver Plus Power

20Mbps 2500V

2

Hot-Swappable I C Isolators

Bidirectional I C Communication, Low Voltage Level Shifting

LTC6803

Multistack Battery Monitor

Individual Battery Cell Monitoring of High Voltage Battery Stacks, Multiple

Devices Interconnected via SPI

2

LTC2309/

LTC2305/LTC2301

12-Bit, 8-/2-/1-Channel, 14ksps SAR ADCs with I C

5V, Internal Reference, Software Compatible Family

2

LTC2631/LTC2630 Single 12-/10-/8-Bit I C or SPI V

10ppm/°C Reference

DACs with

180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

Rail-to-Rail Output

OUT

LTC2641/LTC2642 16-/14-/12-Bit V

DACs

1LSB INL/DNL, 0.5nV • s Glitch, 1μs Settling, 3mm × 3mm DFN

OUT

2

LTC2452/LTC2453 Ultra-Tiny 16-Bit Differential 5.5V Δ∑ ADCs, SPI/I C

LTC1859/ 8-Channel 16-/14-/12-Bit, 100ksps, 10V SoftSpan™

LTC1858/LTC1857 SAR ADCs with SPI

2LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT Packages

5V Supply, Up to 10V Configurable Unipolar/Bipolar Input Range, Pin

Compatible Family in SSOP-28 package

LTC2487/LTC2486 16-Bit 2- or 4-Channel Δ∑ ADCs with Easy Drive™ Inputs 16-Bit and 24-Bit Δ∑ ADC Family, Up to 16 Input Channels and Integrated

2

and I C/SPI Interface

Temperature Sensor

2

LTC4303/LTC4304 Hot Swappable I C Bus Buffers

2.7V to 5.5V Supply, Rise Time Acceleration, Stuck Bus Protection,

15kV ESD

LTC1100

LT1991

Zero-Drift Instrumentation Amplifier

Fixed Gain of 10 or 100

Gain Range –13 to +14

3V/5V/ 5V Supply

Precision, Pin Configurable Gain Difference Amplifier

LTC2054/LTC2055 Micropower Zero-Drift Op Amps

2

LTC4151

LTC4261

High Voltage I C Current and Voltage Monitor

Wide Operating Range: 7V to 80V

2

Negative Voltage Hot Swap Controller with ADC and I C Floating Topology Allows Very High Voltage Operation

Monitoring

LTC1799

LTC6990

LTM2892

Wide Frequency Range Silicon Oscillator

TimerBlox™ Voltage Controlled Oscillator

1kHz to 30MHz

488Hz to 2MHz

2

SPI/Digital or I C Isolated µModule

3500V

Isolation, 6 Channels

RMS

2883fd

LT 1117 REV D • PRINTED IN USA

www.linear.com/LTM2883

36

 ANALOG DEVICES, INC. 2012

For more information www.linear.com/LTM2883


型号：	LTM2883CY-3I#PBF
厂家：	Linear
描述：	LTM2883 - SPI/Digital or I<sup>2</sup>C µModule Isolator with Adjustable ±12.5V and 5V Regulated Power; Package: BGA; Pins: 32; Temperature Range: 0°C to 70°C 接口集成电路
文件：	总36页 (文件大小：1533K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM2883CY-3I#PBF [Linear]

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