LTM2886IY-5I#PBF [Linear]
LTM2886 - SPI/Digital or I<sup>2</sup>C µModule Isolator with Fixed ±5V and Adjustable 5V Regulated Power; Package: BGA; Pins: 32; Temperature Range: -40°C to 85°C;
| 型号： | LTM2886IY-5I#PBF |
| 厂家： | 
Linear |
| 描述： | LTM2886 - SPI/Digital or I<sup>2</sup>C µModule Isolator with Fixed ±5V and Adjustable 5V Regulated Power; Package: BGA; Pins: 32; Temperature Range: -40°C to 85°C 接口集成电路 |
| 文件： | 总38页 (文件大小：987K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM2886
2
SPI/Digital or I C µModule
Isolator with Fixed 5V and
Adjustable 5V Regulated Power
DESCRIPTION
FEATURES
n
6-Channel Logic Isolator: 2500V
for 1 Minute
The LTM®2886 is a complete galvanic digital µModule®
(micromodule) isolator. No external components are
required. A single 3.3V or 5V supply powers both sides
of the interface through an integrated, isolated DC/DC
converter. A logic supply pin allows easy interfacing with
different logic levels from 1.62V to 5.5V, independent of
RMS
File #E151738
n
UL-CSA Recognized
n
Isolated DC Power:
n
3V to 5V Adjustable at Up to 100mA
5V Fiꢀed at Up to 100mA
n
n
n
n
n
No Eꢀternal Components Required
2
SPI/Digital (LTM2886-S) or I C (LTM2886-I) Options the main supply.
High Common Mode Transient Immunity: 30kV/μs
2
Available options are compliant with SPI and I C (master
mode only) specifications.
High Speed Operation:
n
10MHz Digital Isolation
n
n
The isolated side includes fixed 5V and 5V adjustable
power supplies, each capable of providing more than
100mA of load current. The 5V adjustable supply may be
programmed via an external voltage divider.
4MHz/8MHz SPI Isolation
2
400kHz I C Isolation
n
n
n
n
n
n
3.3V (LTM2886-3) or 5V (LTM2886-5) Operation
1.62V to 5.5V Logic Supply
10kV ꢀSD ꢁHM Across the Isolation Harrier
Coupled inductors and an isolation power transformer
Maximum Continuous Working Voltage: 560V
Low Current Shutdown Mode (<10µA)
Low Profile (15mm × 11.25mm × 3.42mm) HGA Package
PꢀAK
provide 2500V
of isolation between the input and out-
RMS
put logic interface. This device is ideal for systems where
the ground loop is broken, allowing for a large common
mode voltage range. Communication is uninterrupted for
common mode transients greater than 30kV/μs.
APPLICATIONS
2
n
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Analog Devices, Inc. All other trademarks are the property of their respective owners.
Isolated SPI or I C Interfaces
n
Industrial Systems
n
Test and Measurement ꢀquipment
Hreaking Ground Loops
n
TYPICAL APPLICATION
Isolated 4MHz SPI Interface
LTM2886 Operating Through 50kV/µs CM Transients
LTM2886-5S
V
SCK
SD0
SCK2 = SD02
CC2
5V AT 100mA
5V AT 100mA
–5V AT 100mA
V
CC
AV
5V
CC2
+
5V/DIV
V
V
L
ON
–
V
REPETITIVE
COMMON MODE
TRANSIENTS
GND2 TO GND
SDOE
CS
CS2
SDI2
SCK2
CS
SDI
CS
SDI
SDI
SCK
SCK
SCK
200V/DIV
2886 TA01b
DO2
SDO
DO1
I2
SDO2
I1
20ns/DIV
SDO
SDO
GND
GND2
2886 TA01a
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For more information www.linear.com/LTM2886
LTM2886
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V
to GND .................................................. –0.3V to 6V
Logic Outputs
CC
V to GND .................................................... –0.3V to 6V
L
DO1, DO2, SDO to GND ..............–0.3V to (V + 0.3V)
L
V
, AV
to GND2 ................................... –0.3V to 6V
O1, SCK2, SDI2, CS2,
CC2
CC2
+
V to GND2 .................................................. –0.3V to 6V
SCL2 to GND2 ........................–0.3V to (V
+ 0.3V)
CC2
–
V to GND2 .................................................. 0.3V to –6V
Operating Temperature Range (Note 4)
Logic Inputs
LTM2886C............................................... 0°C to 70°C
LTM2886I ............................................–40°C to 85°C
LTM2886ꢁ......................................... –40°C to 125°C
Maximum Internal Operating Temperature............ 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Hody Reflow Temperature ............................ 245°C
DI1, SCK, SDI, CS, SCL, SDA, SDOE,
ON to GND..................................–0.3V to (V + 0.3V)
L
I1, I2, SDA2,
SDO2 to GND2........................–0.3V to (V
+ 0.3V)
CC2
PIN CONFIGURATION
LTM2886-I
LTM2886-S
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
DO2 DNC SCL SDA DI1 GND ON
V
L
SDO DO2 SCK SDI CS SDOE ON
V
L
A
B
C
D
E
F
A
B
C
D
E
F
DO1
GND
V
CC
DO1
GND
V
CC
G
H
J
G
H
J
I1
GND2
AV
GND2
–
I1
GND2
AV
GND2
–
CC2
CC2
K
L
K
L
+
+
I2 DNC SCL2 SDA2 O1
BGA PACKAGE
V
V
V
SDO2 I2 SCK2 SDI2 CS2
V
V
V
CC2
CC2
BGA PACKAGE
32-PIN (15mm × 11.25mm × 3.42mm)
32-PIN (15mm × 11.25mm × 3.42mm)
T
= 125°C, θ = 25.5°C/W, θ = 9.2°C/W,
T
= 125°C, θ = 25.5°C/W, θ
= 9.2°C/W,
JMAX
JA
JC(HOTTOM)
= 9.9°C/W
JMAX
JA
JC(HOTTOM)
= 9.9°C/W
θ
= 16.6°C/W, θ
θ
= 16.6°C/W, θ
JC(TOP)
JHOARD
JC(TOP)
JHOARD
θ VALUꢀS DꢀTꢀRMINꢀD PꢀR JꢀSD51-9, WꢀIGꢁT = 1.2g
θ VALUꢀS DꢀTꢀRMINꢀD PꢀR JꢀSD51-9, WꢀIGꢁT = 1.2g
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For more information www.linear.com/LTM2886
LTM2886
PRODUCT SELECTION GUIDE
LTM2886 C
Y
-3
I
#PBF
LEAD FREE DESIGNATOR
PHF = Lead Free
LOGIC OPTION
2
I = Inter-IC (I C) Hus
S = Serial Peripheral Interface (SPI) Hus
INPUT VOLTAGE RANGE
3 = 3V to 3.6V
5 = 4.5V to 5.5V
PACKAGE TYPE
Y = Hall Grid Array (HGA)
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
ꢁ = Automotive Temperature Range (–40°C to 125°C)
PRODUCT PART NUMBER
http://www.linear.com/product/LTM2886#orderinfo
PART MARKING
ORDER INFORMATION
PAD OR BALL
PACKAGE
TYPE
MSL INPUT VOLTAGE
RATING RANGE
LOGIC
TEMPERATURE
PART NUMBER
FINISH
DEVICE
FINISH CODE
OPTION RANGE
LTM2886CY-3I#PHF
LTM2886IY-3I#PHF
LTM2886ꢁY-3I#PHF
LTM2886CY-3S#PHF
LTM2886IY-3S#PHF
LTM2886ꢁY-3S#PHF
LTM2886CY-5I#PHF
LTM2886IY-5I#PHF
LTM2886ꢁY-5I#PHF
LTM2886CY-5S#PHF
LTM2886IY-5S#PHF
LTM2886ꢁY-5S#PHF
0°C to 70°C
2
LTM2886Y-3I
I C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
3V to 3.6V
LTM2886Y-3S
LTM2886Y-5I
LTM2886Y-5S
SPI
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
SAC305 (RoꢁS)
e1
HGA
3
2
I C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
4.5V to 5.5V
SPI
–40°C to 85°C
–40°C to 125°C
• Device temperature grade is indicated by a label on the
shipping container.
• Recommended HGA PCH Assembly and Manufacturing Procedures: www.linear.
com/HGA-assy
• HGA Package and Tray Drawings: www.linear.com/packaging
• Pad or ball finish code is per IPC/JꢀDꢀC J-STD-609.
• Terminal Finish Part Marking: www.linear.com/leadfree
• This product is moisture sensitive. For more information, go to:
www.linear.com/HGA-assy
• This product is not recommended for second side reflow. For
more information, go to www.linear.com/HGA-assy
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For more information www.linear.com/LTM2886
LTM2886
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
Input Supplies
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Input Supply Range
Logic Supply Range
Input Supply Current
LTM2886-3
LTM2886-5
3
3.3
5
3.6
5.5
V
V
CC
4.5
l
l
V
LTM2886-S
LTM2886-I
1.62
3
5.5
5.5
V
V
L
5
l
l
l
I
I
ON = 0V
LTM2886-3, No Load
LTM2886-5, No Load
0
25
19
10
37
27
µA
mA
mA
CC
l
Logic Supply Current
ON = 0V
0
10
10
µA
µA
µA
L
LTM2886-S, ON = V
L
L
LTM2886-I, ON = V
150
Output Supplies
l
V
Regulated Output Voltage
No Load, AV
OPꢀN
CC2
4.75
3
5
5.25
5.5
V
V
CC2
Output Voltage Operating Range (Note 2)
l
l
l
Line Regulation
Load Regulation
ADJ Pin Voltage
Voltage Ripple
I
I
I
I
= 1mA, MIN ≤ V ≤ MAX
2
15
7.5
mV
mV
V
LOAD
LOAD
LOAD
LOAD
CC
= 1mA to 100mA
= 1mA to 100mA
= 100mA (Note 2)
100
1.27
1.15
1.220
1
mV
RMS
ꢀfficiency
LTM2886-5, I
= 100mA (Note 2)
61
%
LOAD
I
Output Short Circuit Current
Current Limit
V
= 0V
CC2
150
mA
mA
V
CC2
l
l
l
l
ΔV
= –5%
90
CC2
+
V
Regulated Output Voltage
Line Regulation
Load Regulation
Voltage Ripple
No Load
4.8
5
2
5.2
7.5
I
I
I
= 1mA, MIN ≤ V ≤ MAX
mV
mV
LOAD
LOAD
LOAD
CC
= 1mA to 100mA
= 100mA (Note 2)
35
1
150
mV
mV
RMS
ꢀfficiency
LTM2886-5, I
= 100mA (Note 2)
61
150
%
LOAD
+
+
I
Output Short Circuit Current
Current Limit
V = 0V
mA
mA
V
+
l
l
l
l
ΔV = –5%
90
–
V
Regulated Output Voltage
Line Regulation
Load Regulation
Voltage Ripple
No Load
–4.8
–5
5
–5.2
15
I
I
I
= –1mA, MIN ≤ V ≤ MAX
mV
mV
LOAD
LOAD
LOAD
CC
= 1mA to 100mA
= 100mA (Note 2)
35
1
150
RMS
ꢀfficiency
LTM2886-5, I
= 100mA (Note 2)
61
150
%
LOAD
–
–
I
Output Short-Circuit Current
Current Limit
V = 0V
mA
mA
–
l
ΔV = 5%
90
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For more information www.linear.com/LTM2886
LTM2886
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
Logic/SPI
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
V
ITꢁ
Input Threshold Voltage
ON, DI1, SDOE, SCK, SDI, CS: 1.62V ≤ V < 2.35V
0.25 • V
0.33 • V
0.75 • V
0.67 • V
V
V
V
L
L
L
L
L
ON, DI1, SDOE, SCK, SDI, CS: 2.35V ≤ V
L
I1, I2, SDO2
0.33 • V
0.67 • V
CC2
CC2
l
I
Input Current
1
µA
mV
V
INL
V
V
Input ꢁysteresis
Output ꢁigh Voltage
150
ꢁYS
Oꢁ
l
DO1, DO2, SDO,
V – 0.4
L
I
I
= –1mA, 1.62V ≤ V < 3V,
LOAD
LOAD
L
= –4mA, 3V ≤ V ≤ 5.5V
L
l
l
O1, SCK2, SDI2, CS2, I
= –4mA
V
– 0.4
CC2
V
V
LOAD
V
Output Low Voltage
Short-Circuit Current
DO1, DO2, SDO,
0.4
OL
I
I
= 1mA, 1.62V ≤ V < 3V,
LOAD
LOAD
L
= 4mA, 3V ≤ V ≤ 5.5V
L
l
l
O1, SCK2, SDI2, CS2, I
= 4mA
0.4
85
V
LOAD
I
0V ≤ (DO1, DO2, SDO) ≤ V
0V ≤ (O1, SCK2, SDI2, CS2) ≤ V
mA
mA
SC
L
60
CC2
2
I C
l
l
V
Low Level Input Voltage
ꢁigh Level Input Voltage
Input Current
SCL, SDA
SDA2
0.3 • V
V
V
IL
L
0.3 • V
CC2
l
l
V
SCL, SDA
SDA2
0.7 • V
V
V
Iꢁ
L
0.7 • V
CC2
l
l
I
SCL, SDA = V or 0V
1
1
µA
µA
INL
L
SDA2 = V , SDA2 = V
= 0V
CC2
CC2
V
V
V
Input ꢁysteresis
SCL, SDA
SDA2
0.05 • V
V
V
ꢁYS
Oꢁ
L
0.05 • V
CC2
l
l
Output ꢁigh Voltage
Output Low Voltage
SCL2, I
= –2mA
V
– 0.4
CC2
L
V
V
LOAD
DO2, I
= –2mA
V – 0.4
LOAD
l
l
l
l
l
SDA, I
DO2, I
= 3mA
= 2mA
= 2mA
0.4
0.4
0.4
0.45
0.55
V
V
V
V
V
OL
LOAD
LOAD
LOAD
SCL2, I
SDA2, No Load, SDA = 0V, 4.5V ≤ V
SDA2, No Load, SDA = 0V, 3V ≤ V
< 5.5V
CC2
CC2
< 4.5V
0.3
l
C
C
Input Pin Capacitance
Hus Capacitive Load
SCL, SDA, SDA2 (Note 2)
10
pF
IN
H
l
l
l
l
SCL2, Standard Speed (Note 2)
SCL2, Fast Speed
SDA, SDA2, SR ≥ 1V/µs, Standard Speed (Note 2)
SDA, SDA2, SR ≥ 1V/µs, Fast Speed
400
200
400
200
pF
pF
pF
pF
l
l
Minimum Hus Slew Rate
Short-Circuit Current
SDA, SDA2
1
V/µs
I
SDA2 = 0, SDA = V
100
mA
mA
mA
mA
mA
SC
L
0V ≤ SCL2 ≤ V
30
30
CC2
L
0V ≤ DO2 ≤ V
SDA = 0, SDA2 = V
6
CC2
SDA = V , SDA2 = 0
–1.8
L
ESD (HBM) (Note 2)
Isolation Houndary
+
–
(V , V , V , GND2) to (V , V , GND)
10
kV
CC2
CC
L
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For more information www.linear.com/LTM2886
LTM2886
SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
Logic
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Maximum Data Rate
10
35
Mꢁz
ns
DI1 → O1, Ix → DOx, C = 15pF (Note 3)
L
t
t
, t
Propagation Delay
Rise Time
C = 15pF (Figure 1)
L
60
100
PꢁL PLꢁ
l
l
C = 15pF (Figure 1)
3
20
12.5
35
ns
ns
R
L
LTM2886-I, DO2, C = 15pF (Figure 1)
L
l
l
t
F
Fall Time
C = 15pF (Figure 1)
3
20
12.5
35
ns
ns
L
LTM2886-I, DO2, C = 15pF (Figure 1)
L
SPI
l
l
Maximum Data Rate
Hidirectional Communication (Note 3)
Unidirectional Communication (Note 3)
4
8
Mꢁz
Mꢁz
l
t
t
t
t
t
t
, t
Propagation Delay
Output Pulse Width Uncertainty
Rise Time
C = 15pF (Figure 1)
35
60
100
50
ns
ns
ns
ns
ns
ns
PꢁL PLꢁ
L
SDO, SDI2, CS2 (Note 2)
PWU
l
l
l
l
C = 15pF (Figure 1)
L
3
3
12.5
12.5
50
R
F
Fall Time
C = 15pF (Figure 1)
L
t
Output ꢀnable Time
Output Disable Time
SDOE = ↓, R = 1kΩ, C = 15pF (Figure 2)
PZꢁ, PZL
L
L
t
50
SDOE = ↑, R = 1kΩ, C = 15pF (Figure 2)
PꢁZ, PLZ
L
L
2
I C
l
Maximum Data Rate
Propagation Delay
(Note 3)
SCL → SCL2, C = 15pF (Figure 1)
400
kꢁz
l
l
l
t
, t
150
150
300
225
250
500
ns
ns
ns
PꢁL PLꢁ
L
SDA → SDA2, R = Open, C = 15pF (Figure 3)
L
L
SDA2 → SDA, R = 1.1kΩ, C = 15pF (Figure 3)
L
L
t
t
t
Output Pulse Width Uncertainty
Data ꢁold Time
SDA, SDA2 (Note 2)
50
ns
ns
PWU
ꢁD;DAT
R
(Note 2)
600
l
l
l
Rise Time
SDA2, C = 200pF (Figure 3)
40
40
300
250
250
ns
ns
ns
L
SDA, R = 1.1kΩ C = 200pF (Figure 3)
L
L
SCL2, C = 200pF (Figure 1)
L
l
l
l
t
F
Fall Time
SDA2, C = 200pF (Figure 3)
40
40
250
250
250
ns
ns
ns
L
SDA, R = 1.1kΩ C = 200pF (Figure 3)
L
L
SCL2, C = 200pF (Figure 1)
L
l
t
SP
Pulse Width of Spikes Suppressed
by Input Filter
0
50
ns
Power Supply
Power-Up Time
l
l
l
0.6
0.6
0.6
5
5
5
ms
ms
ms
ON = ↑ to V
(Min)
CC2
+
ON = ↑ to V (Min)
–
ON = ↑ to V (Min)
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For more information www.linear.com/LTM2886
LTM2886
ISOLATION CHARACTERISTICS TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Rated Dielectric Insulation Voltage
Common Mode Transient Immunity
Maximum Continuous Working Voltage
1 Minute, Derived from 1 Second Test
1 Second (Notes 5, 6)
2500
3000
V
V
ISO
RMS
RMS
LTM2886-3 V = 3.3V, LTM2885-5 V = 5V,
30
kV/µs
CC
CC
V = ON = 3.3V, V = 1kV, Δt = 33ns (Note 2)
L
CM
V
(Notes 2, 5)
560
400
V
PꢀAK
,
IORM
V
DC
V
RMS
Partial Discharge
V
= 750V
(Note 5)
5
pC
PD
RMS
CTI
DTI
Comparative Tracking Index
Depth of ꢀrosion
IꢀC 60112 (Note 2)
IꢀC 60112 (Note 2)
(Note 2)
600
V
RMS
0.017
0.06
mm
Distance Through Insulation
Input to Output Resistance
Input to Output Capacitance
Creepage Distance
mm
Ω
9
(Notes 2, 5)
10
(Notes 2, 5)
6
pF
(Note 2)
9.5
mm
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. ꢀxposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: This Module includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above specified maximum operating junction
temperature may result in device degradation or failure.
Note 2: Guaranteed by design and not subject to production test.
Note 5: Device considered a 2-terminal device. Pin group A1 through H8
shorted together and pin group K1 through L8 shorted together.
Note 3: Maximum Data rate is guaranteed by other measured parameters
and is not tested directly.
Note 6: The rated dielectric insulation voltage should not be interpreted as
a continuous voltage rating.
TA = 25°C, LTM2886-3 VCC = 3.3V,
TYPICAL PERFORMANCE CHARACTERISTICS
LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
VCC Supply Current
vs Temperature
Isolated Supplies
Isolated Supplies
vs Equal Load Current
vs Equal Load Current
30
25
20
15
10
5.50
5.25
5.00
4.75
4.50
4.25
4.00
5.50
5.25
5.00
4.75
4.50
4.25
4.00
NO LOAD, REFRESH DATA ONLY
LTM2886-3
LTM2886-5
V
= 3.3V
V
CC
= 5V
CC
LTM2886-3
= 3.3V
V
CC
LTM2886-5
V
CC
= 5V
V
V
CC2
CC2
+
+
V
V
–
–
|V |
10
|V |
–50 –25
0
25
50
75 100 125
0
20
30
40
50
60
0
20
40
60
80
100
TEMPERATURE (°C)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2886 G01
2886 G02
2886 G03
2886fb
7
For more information www.linear.com/LTM2886
LTM2886
TA = 25°C, LTM2886-3 VCC = 3.3V,
TYPICAL PERFORMANCE CHARACTERISTICS
LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
VCC2 Line Regulation
vs Load Current
V+ Line Regulation
vs Load Current
V– Line Regulation
vs Load Current
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
6.0
LTM2886-3
LTM2886-3
LTM2886-3
5.5
5.0
4.5
4.0
3.5
V
CC
V
CC
V
CC
= 3V
= 3.3V
= 3.6V
V
CC
V
CC
V
CC
= 3V
= 3.3V
= 3.6V
V
CC
V
CC
V
CC
= 3V
= 3.3V
= 3.6V
3.0
2.5
0
25 50 75 100 125 150 175 200
0
25 50 75 100 125 150 175 200
0
25 50 75 100 125 150 175 200
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2886 G04
2886 G05
2886 G06
VCC2 Line Regulation
vs Load Current
V+ Line Regulation
vs Load Current
V– Line Regulation
vs Load Current
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
LTM2886-5
LTM2886-5
LTM2886-5
V
CC
V
CC
V
CC
= 4.5V
= 5V
= 5.5V
V
CC
V
CC
V
CC
= 4.5V
= 5V
= 5.5V
V
CC
V
CC
V
CC
= 4.5V
= 5V
= 5.5V
0
50
100
150
200
250
300
0
50
100
150
200
250
300
0
50
100
150
200
250
300
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2886 G08
2886 G07
2886 G09
V+ Load Regulation
vs Temperature
V– Load Regulation
vs Temperature
VCC2 Load Regulation
vs Temperature
5.15
5.10
5.05
5.00
4.95
4.90
4.85
5.15
5.10
5.05
5.00
4.95
4.90
4.85
5.15
5.10
5.05
5.00
4.95
4.90
4.85
LTM2886-3
LTM2886-3
LTM2886-3
V
CC
= 3.3V
V
CC
= 3.3V
V = 3.3V
CC
+
+
–
I
I
= 1mA
= 100mA
I
I
= 1mA
= 1mA
= 100mA
CC2
–
I
I
= 100mA
25
TEMPERATURE (°C)
CC2
–50 –25
0
25
50
75 100 125
–50 –25
0
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
2886 G10
2886 G11
2886 G12
2886fb
8
For more information www.linear.com/LTM2886
LTM2886
TA = 25°C, LTM2886-3 VCC = 3.3V,
TYPICAL PERFORMANCE CHARACTERISTICS
LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
V
CC2 Load Regulation
V+ Load Regulation
vs Temperature
V– Load Regulation
vs Temperature
vs Temperature
5.15
5.10
5.05
5.00
4.95
4.90
4.85
5.15
5.10
5.05
5.00
4.95
4.90
4.85
5.15
5.10
5.05
5.00
4.95
4.90
4.85
LTM2886-5
CC
LTM2886-5
CC
LTM2886-5
CC
V
= 5V
V
= 5V
V
= 5V
+
+
–
–
I
I
= 1mA
= 100mA
I
I
= 1mA
= 100mA
I
I
= 1mA
CC2
CC2
= 100mA
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2886 G14
2886 G15
2886 G13
VCC2 Voltage and ICC Current
vs Load Current
VCC2 Efficiency
70
1.4
1.2
1.0
0.8
0.6
0.4
0.2
6
5
4
3
2
1
0
600
500
400
300
200
100
60
EFFICIENCY
VOLTAGE
50
40
30
20
10
0
POWER LOSS
I
CC
CURRENT
LTM2886-3, V = 3.3V
CC
LTM2886-5, V = 5V
CC
LTM2886-3, V = 3.3V
CC
LTM2886-5, V = 5V
CC
0.0
300
0
0
50
100
150
200
250
0
50
100
150
200
250
300
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2886 G16
2886 G17
V+ Voltage and ICC Current
vs Load Current
V+ Efficiency
70
60
50
40
30
20
10
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
6
5
4
3
2
1
0
600
500
400
300
200
100
0
EFFICIENCY
VOLTAGE
POWER LOSS
I
CC
CURRENT
LTM2886-3, V = 3.3V
LTM2886-3, V = 3.3V
CC
LTM2886-5, V = 5V
CC
CC
LTM2886-5, V = 5V
CC
0
50
100
150
200
250
300
0
50
100
150
200
250
300
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2886 G18
2886 G19
2886fb
9
For more information www.linear.com/LTM2886
LTM2886
TA = 25°C, LTM2886-3 VCC = 3.3V,
TYPICAL PERFORMANCE CHARACTERISTICS
LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
V– Voltage and ICC Current
vs Load Current
V– Efficiency
70
60
50
40
30
20
10
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
6
5
4
3
2
1
0
600
500
400
300
200
100
0
EFFICIENCY
VOLTAGE
POWER LOSS
I
CURRENT
CC
LTM2886-3, V = 3.3V
LTM2886-3, V = 3.3V
CC
LTM2886-5, V = 5V
CC
CC
LTM2886-5, V = 5V
CC
0
50
100
150
200
250 300
0
50
100
150
200
250
300
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2886 G20
2886 G21
VCC2 Transient Response
100mA Load Step
V+ Transient Response
100mA Load Step
V– Transient Response
100mA Load Step
0.5V/DIV
0.5V/DIV
0.5V/DIV
50mA/DIV
50mA/DIV
50mA/DIV
2886 G22
2886 G23
2886 G24
100µs/DIV
100µs/DIV
100µs/DIV
VCC2 Ripple
V+ Ripple
V– Ripple
LOAD = 1mA
LOAD = 1mA
LOAD = 1mA
LOAD = 100mA
LOAD = 100mA
LOAD = 100mA
400ns/DIV
2886 G27
2886 G25
2886 G26
400ns/DIV
400ns/DIV
2886fb
10
For more information www.linear.com/LTM2886
LTM2886
TA = 25°C, LTM2886-3 VCC = 3.3V,
TYPICAL PERFORMANCE CHARACTERISTICS
LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
V+ Noise
V– Noise
V
CC2 Noise
LOAD = 100mA
LOAD = 100mA
LOAD = 100mA
2mV/DIV
2mV/DIV
2mV/DIV
2886 G28
2886 G29
2886 G30
1ms/DIV
1ms/DIV
1ms/DIV
VCC Supply Current
vs Single Channel Data Rate
Logic Input Threshold
vs VL Supply Voltage
Logic Output Voltage
vs Load Current
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
70
60
50
40
30
20
10
6
5
4
3
2
1
0
C
C
C
C
= 1nF
V
= 5V
L
L
L
L
CC
= 330pF
= 100pF
= 20pF
V
V
V
= 5.5V
= 3.3V
= 1.62V
L
L
L
INPUT RISING
INPUT FALLING
1
2
3
4
5
6
1k
10k
100k
1M
10M
100M
0
1
2
3
4
5
6
7
8
9
10
V
L
SUPPLY VOLTAGE (V)
DATA RATE (Hz)
|LOAD CURRENT| (mA)
2886 G32
2886 G31
2886 G33
Isolated Supply Efficiency with
Equal Load Current
Derating for 125°C Maꢀimum
Internal Operating Temperature
Power On Sequence
600
500
400
300
200
100
0
70
60
1.4
LTM2886-5, V = 5V
L
ON
1.2
1.0
0.8
0.6
0.4
0.2
0.0
EFFICIENCY
V
CC2
2.5V/DIV
1V/DIV
50
40
30
20
10
0
+
V
LTM2886-3, V = 3.3V
CC
LTM2886-5, V = 5V
CC
POWER LOSS
BASED ON THERMAL IMAGING
OF DEMO CIRCUIT 1790A
LTM2886-3, V = 3.3V
CC
LTM2886-5, V = 5V
CC
–
+
–
V
V
CC2
, V , V EQUALLY LOADED
2886 G34
0
25
50
75
100
125
0
10 20 30 40 50 60 70 80 90 100
100µs/DIV
LOAD CURRENT (mA)
TEMPERATURE (°C)
2886 G36
2886 G35
2886fb
11
For more information www.linear.com/LTM2886
LTM2886
PIN FUNCTIONS (LTM2886-I)
Logic Side
The logic state on I2 translates to the same logic state on
DO2. Do not float.
DO2(A1):DigitalOutput,ReferencedtoV andGND.Logic
L
DNC (L2): Do Not Connect. Pin connected internally.
output connected to I2 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
2
SCL2 (L3): Serial I C Clock Output, Referenced to V
CC2
and GND2. Logic output connected to logic side SCL pin
throughisolationbarrier. Clockisunidirectionalfromlogic
to isolated side. SCL2 has a push-pull output stage, do not
connect an external pull-up device. Under the condition
of an isolation communication failure this output defaults
to a high state.
DNC (A2): Do Not Connect. Pin connected internally.
2
SCL (A3): Serial I C Clock Input, Referenced to V and
L
GND. Logic input connected to isolated side SCL2 pin
throughisolationbarrier. Clockisunidirectionalfromlogic
to isolated side. Do not float.
2
SDA2 (L4): Serial I C Data Pin, Referenced to V
and
CC2
2
SDA (A4): Serial I C Data Pin, Referenced to V and GND.
L
GND2. Hidirectional logic pin connected to logic side SDA
pin through isolation barrier. Output is biased high by a
1.8mA current source. Do not connect an external pull-
up device to SDA2. Under the condition of an isolation
communication failure this output defaults to a high state.
HidirectionallogicpinconnectedtoisolatedsideSDA2pin
through isolation barrier. Under the condition of an isola-
tion communication failure this pin is in a high impedance
state. Do not float.
DI1(A5):DigitalInput,ReferencedtoV andGND.Logicinput
L
O1 (L5): Digital Output, Referenced to V
and GND2.
CC2
connected to O1 through isolation barrier. The logic state on
Logic output connected to DI1 through isolation barrier.
Under the condition of an isolation communication failure
O1 defaults to a high state.
DI1 translates to the same logic state on O1. Do not float.
GND (A6, B2 to B6): Circuit Ground.
V
(L6): 3V to 5.5V Adjustable Isolated Supply Voltage.
CC2
ON (A7): ꢀnable, Referenced to V and GND. ꢀnables
L
Internally generated from V by an isolated DC/DC con-
CC
power and data communication through the isolation
barrier. If ON is high the part is enabled and power and
communications are functional to the isolated side. If ON
is low the logic side is held in reset, all digital outputs
are in a high impedance state, and the isolated side is
unpowered. Do not float.
verter and regulated to 5V with no external components.
Internally bypassed with 2.2µF.
–
V (L7): –5V Nominal Isolated Supply Voltage. Internally
generated from V by an isolated DC/DC converter and
CC
regulated to –5V with no external components. Internally
bypassed with 2.2µF.
V (A8): Logic Supply. Interface supply voltage for pins
L
+
DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is
V (L8): 5V Nominal Isolated Supply Voltage. Internally
1.62V to 5.5V. Internally bypassed with 1µF.
generated from V by an isolated DC/DC converter and
CC
regulated to 5V with no external components. Internally
DO1(B1):DigitalOutput,ReferencedtoV andGND.Logic
L
bypassed with 2.2µF.
output connected to I1 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
I1 (K1): Digital Input, Referenced to V
and GND2.
CC2
Logic input connected to DO1 through isolation barrier.
The logic state on I1 translates to the same logic state on
DO1. Do not float.
V
(B7 to B8): Supply Voltage. Operating voltage is 3V
CC
to 3.6V for LTM2886-3 and 4.5V to 5.5V for LTM2886-5.
GND2 (K2 to K5, K7, K8): Isolated Ground.
Internally bypassed with 2.2µF.
AV
(K6): 5V Nominal Isolated Supply Voltage Adjust.
CC2
Isolated Side
The adjust pin voltage is 1.22V referenced to GND2. See
Applications Information section for details.
I2 (L1): Digital Input, Referenced to V
Logic input connected to DO2 through isolation barrier.
and GND2.
CC2
2886fb
12
For more information www.linear.com/LTM2886
LTM2886
PIN FUNCTIONS (LTM2886-S)
Logic Side
Isolated Side
SDO2 (L1): Serial SPI Digital Input, Referenced to V
SDO (A1): Serial SPI Digital Output, Referenced to V
CC2
L
and GND2. Logic input connected to logic side SDO pin
through isolation barrier. Do not float.
and GND. Logic output connected to isolated side SDO2
pin through isolation barrier. Under the condition of an
isolation communication failure this output is in a high
impedance state.
I2 (L2): Digital Input, Referenced to V
and GND2.
CC2
Logic input connected to DO2 through isolation barrier.
The logic state on I2 translates to the same logic state on
DO2. Do not float.
DO2(A2):DigitalOutput,ReferencedtoV andGND.Logic
L
output connected to I2 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
SCK2 (L3): Serial SPI Clock Output, Referenced to V
CC2
and GND2. Logic output connected to logic side SCK pin
throughisolationbarrier.Undertheconditionofanisolation
communication failure this output defaults to a low state.
SCK (A3): Serial SPI Clock Input, Referenced to V and
L
GND. Logic input connected to isolated side SCK2 pin
through isolation barrier. Do not float.
SDI2 (L4): Serial SPI Data Output, Referenced to V
CC2
and GND2. Logic output connected to logic side SDI pin
throughisolationbarrier.Undertheconditionofanisolation
communication failure this output defaults to a low state.
SDI(A4):SerialSPIDataInput,ReferencedtoV andGND.
L
Logic input connected to isolated side SDI2 pin through
isolation barrier. Do not float.
CS2 (L5): Serial SPI Chip Select, Referenced to V
and
CC2
CS(A5):SerialSPIChipSelect,ReferencedtoV andGND.
L
GND2.LogicoutputconnectedtologicsideCSpinthrough
isolation barrier. Under the condition of an isolation com-
munication failure this output defaults to a high state.
Logic input connected to isolated side CS2 pin through
isolation barrier. Do not float.
SDOE (A6): Serial SPI Data Output ꢀnable, Referenced to
V
(L6): 3V to 5.5V Adjustable Isolated Supply Voltage.
CC2
V and GND. A logic high on SDOE places the logic side
L
Internally generated from V by an isolated DC/DC con-
CC
SDO pin in a high impedance state, a logic low enables
verter and regulated to 5V with no external components.
Internally bypassed with 2.2µF.
the output. Do not float.
ON(A7):ꢀnable,ReferencedtoV andGND.ꢀnablespower
L
–
V (L7): –5V Nominal Isolated Supply Voltage. Internally
anddatacommunicationthroughtheisolationbarrier.IfON
is high the part is enabled and power and communications
arefunctionaltotheisolatedside. IfONislowthelogicside
is held in reset, all digital outputs are in a high impedance
state, and the isolated side is unpowered. Do not float.
generated from V by an isolated DC/DC converter and
CC
regulated to –5V with no external components. Internally
bypassed with 2.2µF.
+
V (L8): 5V Nominal Isolated Supply Voltage. Internally
generated from V by an isolated DC/DC converter and
CC
V (A8): Logic Supply. Interface supply voltage for pins
L
regulated to 5V with no external components. Internally
SDI, SCK, SDO, SDOE, DO1, DO2, CS, and ON. Operating
bypassed with 2.2µF.
voltage is 1.62V to 5.5V. Internally bypassed with 1µF.
I1 (K1): Digital Input, Referenced to V
and GND2.
CC2
DO1(B1):DigitalOutput,ReferencedtoV andGND.Logic
L
Logic input connected to DO1 through isolation barrier.
The logic state on I1 translates to the same logic state on
DO1. Do not float.
output connected to I1 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
GND2 (K2 to K5, K7, K8): Isolated Ground.
GND (B2 to B6): Circuit Ground.
AV
(K6): 5V Nominal Isolated Supply Voltage Adjust.
CC2
V
(B7 to B8): Supply Voltage. Operating voltage is 3V
CC
The adjust pin voltage is 1.22V Referenced to GND2. See
Applications Information section for details.
to 3.6V for LTM2886-3 and 4.5V to 5.5V for LTM2886-5.
Internally bypassed with 2.2µF.
2886fb
13
For more information www.linear.com/LTM2886
LTM2886
BLOCK DIAGRAMS
(LTM2886-I)
V
REG
CC2
2.2µF
AV
CC2
+
V
REG
REG
CC
V
2.2µF
2.2µF
V
L
2.2µF
GND2
1µF
–
V
GND
DC/DC
CONVERTER
ON
DI1
O1
SDA
SCL
SDA2
SCL2
ISOLATED
COMMUNI-
CATIONS
ISOLATED
COMMUNI-
CATIONS
INTERFACE
INTERFACE
DO2
DO1
I2
I1
2886 BD
2886fb
14
For more information www.linear.com/LTM2886
LTM2886
(LTM2886-S)
V
REG
CC2
2.2µF
AV
CC2
+
V
REG
REG
CC
V
2.2µF
2.2µF
V
L
2.2µF
GND2
1µF
DC/DC
CONVERTER
–
V
GND
ON
SDOE
CS
CS2
SDI2
SCK2
I2
SDI
ISOLATED
COMMUNI-
CATIONS
ISOLATED
COMMUNI-
CATIONS
SCK
DO2
INTERFACE
INTERFACE
SDO
DO1
SDO2
I1
2886 BDa
2886fb
15
For more information www.linear.com/LTM2886
LTM2886
TEST CIRCUITS
V
L
INPUT
½V
L
0V
OUTPUT
t
t
PHL
PLH
C
L
INPUT
V
OH
90%
10%
10%
90%
OUTPUT
½V
CC2
V
OL
t
t
F
R
V
CC2
INPUT
½V
CC2
0V
OUTPUT
t
t
PHL
PLH
C
L
INPUT
V
OH
90%
10%
10%
90%
OUTPUT
½V
L
V
OL
t
t
F
R
2886 F01
Figure 1. Logic Timing Measurements
V
L
OR 0V
V
L
SDOE
SDO
SDO
½V
L
R
L
0V
0V
t
t
PHZ
PZH
V
OH
SDO
SDO2 OR
V
CC2
V
V
– 0.5V
+ 0.5V
OH
½V
C
L
t
L
0V
t
PLZ
SDOE
PZL
L
V
L
½V
OL
V
OL
2886 F02
Figure 2. Logic Enable/Disable Time
V
L
V
L
R
L
SDA
½V
L
0V
SDA2
t
t
PLH
PHL
C
L
SDA
V
OH
30%
70%
30%
SDA2
½V
CC2
70%
V
OL
t
t
R
F
V
L
V
CC2
R
L
SDA2
SDA
½V
CC2
0V
SDA
t
t
PLH
PHL
C
L
SDA2
V
OH
30%
70%
30%
½V
L
70%
V
OL
t
t
R
F
2886 F03
Figure 3. I2C Timing Measurements
2886fb
16
For more information www.linear.com/LTM2886
LTM2886
APPLICATIONS INFORMATION
Overview
V Logic Supply
L
The LTM2886 digital µModule isolator provides a
galvanically-isolated robust logic interface, powered by
an integrated, regulated DC/DC converter, complete with
decoupling capacitors. The LTM2886 is ideal for use in
networks where grounds can take on different voltages.
Isolation in the LTM2886 blocks high voltage differences,
eliminates ground loops and is extremely tolerant of com-
mon mode transients between ground planes. ꢀrror-free
operation is maintained through common mode events
greater than 30kV/μs providing excellent noise isolation.
A separate logic supply pin V allows the LTM2886 to in-
L
terface with any logic signal from 1.62V to 5.5V as shown
in Figure 4. Simply connect the desired logic supply to V
.
L
There is no interdependency between V and V ; they
CC
L
may simultaneously operate at any voltage within their
specified operating ranges and sequence in any order. V
is bypassed internally by a 1µF capacitor.
L
3V TO 3.6V LTM2886-3
4.5V TO 5.5V LTM2886-5
LTM2886-I
V
CC2
CC2
V
V
CC
L
Isolator µModule Technology
AV
+
ANY VOLTAGE FROM
1.62V TO 5.5V
V
The LTM2886 utilizes isolator µModule technology to
translate signals and power across an isolation barrier.
Signals on either side of the barrier are encoded into
pulses and translated across the isolation boundary using
coreless transformers formed in the µModule substrate.
This system, complete with data refresh, error checking,
safe shutdown on fail, and extremely high common mode
immunity,providesarobustsolutionforbidirectionalsignal
isolation. The µModule technology provides the means to
combinetheisolatedsignalingwithmultipleregulatorsand
apowerfulisolatedDC/DCconverterinonesmallpackage.
–
V
ON
DI1
O1
SDA
SCL
SDA2
SCL2
EXTERNAL
DEVICE
DO2
DO1
I2
I1
GND
GND2
2886 F04
DC/DC Converter
Figure 4. VCC and VL Are Independent
The LTM2886 contains a fully integrated DC/DC converter,
including the transformer, so that no external components
are necessary. The logic side contains a full-bridge driver,
running at 1.6Mꢁz, and is AC-coupled to a single trans-
former primary. A series DC blocking capacitor prevents
transformer saturation due to driver duty cycle imbal-
ance. The transformer scales the primary voltage, and is
rectified by a voltage quadrupler. This topology eliminates
transformer saturation caused by secondary imbalances.
Hot-Plugging Safely
Caution must be exercised in applications where power is
plugged into the LTM2886’s power supplies, V or V ,
due to the integrated ceramic decoupling capacitors. The
parasitic cable inductance along with the high Q char-
acteristics of ceramic capacitors can cause substantial
ringing which could exceed the maximum voltage ratings
anddamagetheLTM2886. RefertoLinearTechnologyAp-
plication Note 88, entitled Ceramic Input Capacitors Can
Cause Overvoltage Transients for a detailed discussion
and mitigation of this phenomenon.
CC
L
The quadrupler is grounded in the middle producing sym-
metrical positive and negative voltage rails. The positive
rail is post regulated with two low dropout regulators
+
(LDOs) producing V
and V , the negative rail also has
CC2
–
an LDO producing V .
ꢀach voltage rail is capable of producing 100mA of output
current,totaloutputpowercapabilityisapproximately1W.
Allvoltagerailsarebypassedwith2.2µFceramiccapacitors.
2886fb
17
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LTM2886
APPLICATIONS INFORMATION
Isolated Supply Adjustable Operation
Channel Timing Uncertainty
The V
isolated power rail is nominally 5V, but may be
Multiplechannelsaresupportedacrosstheisolationbound-
ary by encoding and decoding of the inputs and outputs.
Up to three signals in each direction are assembled as a
packet and transferred across the isolation barrier. The
time required to transfer all 3 bits is 100ns maximum,
and sets the limit for how often a signal can change on
the opposite side of the barrier. ꢀncoding transmission is
independent for each data direction. The technique used
assigns SCK or SCL on the logic side, and SDO2 or I2 on
the isolated side, the highest priority such that there is
no jitter on the associated output channels, only delay.
This preemptive scheme will produce a certain amount of
uncertainty on the other isolation channels. The resulting
pulse width uncertainty on these low priority channels is
typically 6ns, but may vary up to 50ns if the low priority
channels are not encoded within the same high priority
serial packet.
CC2
overdrivenbyaddingtwoexternalresistors.Theunadjusted
output voltage represents the maximum for guaranteed
performance. Figure 5 illustrates configuration for V
CC2
+
–
= 3.3V, V and V are fixed at 5V and –5V respectively.
LTM2886-5S
V
CC2
3.3V
V
V
CC
L
AV
5V
CC2
R2
42.2k
+
V
5V
ON
R1
–
V
–5V
24.9k
SDOE
CS
CS2
SDI2
SCK2
SDI
SCK
I2
SDO2
I1
DO2
SDO
DO1
Serial Peripheral Interface (SPI) Bus
The LTM2886-S provides a SPI compatible isolated inter-
face. The maximum data rate is a function of the inherent
channel propagation delays, channel to channel pulse
width uncertainty, and data direction requirements. Chan-
nel timing is detailed in Figures 6 through 9 and Tables
2 and 3. The SPI protocol supports four unique timing
configurations defined by the clock polarity (CPOL) and
clock phase (CPꢁA) summarized in Table 1.
GND
GND2
2886 F05
Figure 5. Adjustable Voltage Rails
The output adjustment range for V
output voltage is calculated by:
is 3V to 5.5V. V
CC2
CC2
V
CC2
= 1.22V(1 + R2/R1)
Table 1. SPI Mode
CPOL CPHA
DATA TO (CLOCK) RELATIONSHIP
The value of R1 should be no greater than 24.9k to mini-
0
0
1
1
0
1
0
1
Sample (Rising)
Set-Up (Falling)
Sample (Falling)
Set-Up (Rising)
Sample (Rising)
mize errors in the output voltage caused by the AV pin
CC2
Set-Up (Rising)
Sample (Falling)
Set-Up (Falling)
bias current.
Operation at low output voltages may result in thermal
shutdownduetolowdropoutregulatorpowerdissipation.
The maximum data rate for bidirectional communication
is 4Mꢁz, based on a synchronous system, as detailed in
the timing waveforms. Slightly higher data rates may be
achieved by skewing the clock duty cycle and minimiz-
ing the SDO to SCK set-up time, however the clock rate
is still dominated by the system propagation delays. A
discussion of the critical timing paths relative to Figures 6
and 7 follows.
2886fb
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For more information www.linear.com/LTM2886
LTM2886
APPLICATIONS INFORMATION
• CS to SCK (master sample SDO, 1st SDO valid)
t
10
SDO2 data transition in response to SCK2
t → t
0
≈50ns, CS to CS2 propagation delay
t → t ≈50ns, SDO2 to SDO propagation delay
10 11
1
t → t
Isolated slave device propagation
(response time), asserts SDO2
t → t Set-up time for master SDO to SCK
11 12
1
1+
Maximum data rate for single direction communication,
master to slave, is 8Mꢁz, limited by the systems encod-
ing/decodingschemeorpropagationdelay. Timingdetails
for both variations of clock phase are shown in Figures 8
and 9 and Table 3.
t → t
1
≈50ns, SDO2 to SDO propagation delay
Set-up time for master SDO to SCK
3
5
t → t
3
• SDI to SCK (master data write to slave)
t → t
≈50ns, SDI to SDI2 propagation delay
≈50ns, SCK to SCK2 propagation delay
Additional requirements to insure maximum data rate are:
2
4
6
5
t → t
5
•
CS is transmitted prior to (asynchronous) or within
the same (synchronous) data packet as SDI
t → t
2
≥50ns, SDI to SCK, separate packet
non-zero set-up time
•
SDI and SCK set-up data transition occur within the
same data packet. Referencing Figure 6, SDI can pre-
t → t
4
≥50ns, SDI2 to SCK2, separate packet
non-zero set-up time
6
cede SCK by up to 13ns (t → t ) or lag SCK by 3ns
7
8
(t → t ) and not violate this requirement. Similarly in
8
9
• SDO to SCK (master sample SDO, subsequent
SDO valid)
Figure 8, SDI can precede SCK by up to 13ns (t → t )
4
5
or lag SCK by 3ns (t → t ).
5
6
t
8
set-up data transition SDI and SCK
t → t
8
≈50ns, SDI to SDI2 and SCK to SCK2
propagation delay
10
2886fb
19
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APPLICATIONS INFORMATION
CPHA = 0
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
SDO
INVALID
SDO2
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
t
10
t
t
t
t
t
15
t
t
9
11 12
13
14
17
18
t
8
2886 F06
Figure 6. SPI Timing, Bidirectional, CPHA = 0
CPHA = 1
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
SDO
INVALID
SDO2
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
t
10
t
t
t
t
t
15
t
t
t
9
11 12
13
14
16 17
18
t
8
2886 F07
Figure 7. SPI Timing, Bidirectional, CPHA = 1
2886fb
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For more information www.linear.com/LTM2886
LTM2886
APPLICATIONS INFORMATION
CPHA = 0
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
t
0
t
1
t
2
t
3
t
4
t
5
t
t
t
9
t
t
12
7
8
11
t
6
2886 F08
Figure 8. SPI Timing, Unidirectional, CPHA = 0
CPHA = 1
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
t
0
t
1
t
2
t
3
t
4
t
5
t
7
t
8
t
9
t
t
t
12
10 11
t
6
2886 F09
Figure 9. SPI Timing, Unidirectional, CPHA = 1
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APPLICATIONS INFORMATION
Table 2. Bidirectional SPI Timing Event Description
TIME
CPHA
EVENT DESCRIPTION
t
0
0, 1
Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output
enabled, initial data is not equivalent to slave device data output
t to t
t
to t
18
0, 1
0, 1
0
Propagation delay chip select, logic to isolated side, 50ns typical
Slave device chip select output data enable
0
1, 17
t
1
t
2
Start of data transmission, data set-up
1
Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge
Propagation delay of slave data, isolated to logic side, 50ns typical
Slave data output valid, logic side
t to t
0, 1
0, 1
0
1
3
t
3
t to t
Propagation delay of data, logic side to isolated side
Propagation delay of data and clock, logic side to isolated side
Logic side data sample time, half clock period delay from data set-up transition
Propagation delay of clock, logic to isolated side
Isolated side data sample time
2
4
1
t
5
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0
t to t
5
6
t
6
t
8
Synchronous data and clock transition, logic side
Data to clock delay, must be ≤13ns
t to t
7
8
t to t
Clock to data delay, must be ≤3ns
8
9
t to t
8
Propagation delay clock and data, logic to isolated side
Slave device data transition
10
t
t
t
t
t
10, 14
to t
to t
t
to t
15
Propagation delay slave data, isolated to logic side
Slave data output to sample clock set-up time
10
11
13
11, 14
12
Last data and clock transition logic side
1
Last sample clock transition logic side
t
to t
0
Propagation delay data and clock, logic to isolated side
Propagation delay clock, logic to isolated side
13
15
14
1
t
0
Last slave data output transition logic side
1
Last slave data output and data transition, logic side
Propagation delay data, logic to isolated side
t
15
t
17
t
18
to t
1
16
0, 1
0, 1
Asynchronous chip select transition, end of transmission. Disable slave data output logic side
Chip select transition isolated side, slave data output disabled
2
Inter-IC Communication (I C) Bus
2
2
The LTM2886-I provides an I C compatible isolated in-
ThetotalsetuptimereducestheI Cdataholdtime(t
)
HD;DAT
terface. Clock (SCL) is unidirectional, supporting master
mode only, and data (SDA) is bidirectional. The maximum
toamaximumof175ns,guaranteeingsufficientdatasetup
time (t ).
SU;ACK
2
data rate is 400kHz which supports fast-mode I C. Timing
The isolated side bidirectional serial data pin, SDA2,
simplified schematic is shown in Figure 11. An internal
1.8mA current source provides a pull-up for SDA2. Do not
connect any other pull-up device to SDA2. This current
source is sufficient to satisfy the system requirements for
bus capacitances greater than 200pF in FAST mode and
greater than 400pF in STANDARD mode.
is detailed in Figure 10. The data rate is limited by the slave
2
acknowledge setup time (t
), consisting of the I C
SU;DAT
SU;ACK
standardminimumsetuptime(t
)of100ns,maximum
clock propagation delay of 225ns, glitch filter and isolated
data delay of 500ns maximum, and the combined isolated
and logic data fall time of 300ns at maximum bus loading.
2886fb
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APPLICATIONS INFORMATION
Table 3. Unidirectional SPI Timing Event Description
TIME
CPHA
0, 1
0, 1
0
EVENT DESCRIPTION
t
0
Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns
Propagation delay chip select, logic to isolated side
Start of data transmission, data set-up
t to t
0
1
3
t
2
1
Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge
Propagation delay of data, logic side to isolated side
Propagation delay of data and clock, logic side to isolated side
Logic side data sample time, half clock period delay from data set-up transition
Clock propagation delay, clock and data transition
Data to clock delay, must be ≤13ns
t to t
2
0
1
t
3
0, 1
0, 1
0, 1
0, 1
0, 1
0
t to t
3
5
5
6
7
t to t
4
t to t
5
Clock to data delay, must be ≤3ns
t to t
5
Data and clock propagation delay
t
8
Last clock and data transition
1
Last clock transition
t to t
8
0
Clock and data propagation delay
9
1
Clock propagation delay
t to t
9
1
Data propagation delay
10
t
11
t
12
0, 1
0, 1
Asynchronous chip select transition, end of transmission
Chip select transition isolated side
SLAVE ACK
SDA
SDA2
SCL
1
8
9
SCL2
START
STOP
2886 F10
t
PROP
t
t
HD;DAT
t
SU;DAT
SU;ACK
Figure 10. I2C Timing Diagram
Additional proprietary circuitry monitors the slew rate on
the SDA and SDA2 signals to manage directional control
across the isolation barrier. Slew rates on both pins must
be greater than 1V/µs for proper operation.
1.8mA
GLITCH FILTER
TO
LOGIC
SIDE
SDA2
The logic side bidirectional serial data pin, SDA, requires a
FROM
LOGIC
SIDE
pull-up resistor or current source connected to V . Follow
L
2886 F11
the requirements in Figures 12 and 13 for the appropri-
ate pull-up resistor on SDA that satisfies the desired rise
Figure 11. Isolated SDA2 Pin Schematic
time specifications and V maximum limits for FAST and
OL
STANDARD modes. The resistance curves represent the
maximum resistance boundary; any value may be used
to the left of the appropriate curve.
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LTM2886
APPLICATIONS INFORMATION
30
If these signals are wired off board, twist SCL2 with V
CC2
V
V
V
V
= 3V
L
L
L
L
= 3.3V
and/or GND2 and SDA2 with GND2 and/or V , do not
CC2
25
20
15
10
5
= 3.6V
= 4.5V TO 5.5V
twist SCL2 and SDA2 together. If coupling between SCL2
and SDA2 is unavoidable, place the aforementioned RC
filter at the SCL2 pin to reduce noise injection onto SDA2.
Low Noise Applications
+
–
For precision analog applications the V and V power
rails may be filtered to improve the noise performance.
Figure 14 shows the recommended component values to
reduce noise at high frequencies. The selected inductor
should be chosen such that the parasitic capacitance is
low enough to keep the self resonant frequency greater
than 10MHz. The plots of Figures 15 and 16 show the high
0
10
100
(pF)
1000
C
BUS
2886 F12
Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA
+
frequency noise improvement for the V rail, the improve-
10
–
V
V
V
V
= 3V
L
L
L
L
ment on the V rail will be nearly equivalent.
9
8
7
6
5
4
3
2
1
0
= 3.3V
= 3.6V
Some applications may require the noise performance be
improved in the 100Hz to 10kHz region. An additional LC
filter stage may be added between the LTM2886 and the
high frequency filter to lower the noise corner frequency.
Using an inductance of 330µH and capacitance of 680µF
reduces the noise corner to approximately 340Hz. The
RMSnoiseatabandwidthof340Hzisapproximately22µV.
= 4.5V TO 5.5V
22µH
LTM2886-5S
10
100
(pF)
1000
B8
A8
L8
L7
+
–
+
–
V
V
FILTERED V
FILTERED V
5V
V
V
C
CC
L
BUS
2886 F13
22µH
Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA
A7
A6
A5
A4
A3
A2
A1
B1
B2
L6
K6
L5
L4
L3
L2
L1
K1
K2
V
ON
CC2
AV
SDOE
CS
CC2
The isolated side clock pin, SCL2, has a weak push-pull
output driver; do not connect an external pull-up device.
CS2
SDI2
SCK2
I2
10µF
10µF
SDI
2
SCL2iscompatiblewithI Cdeviceswithoutclockstretch-
SCK
DO2
SDO
DO1
GND
ing. On lightly loaded connections, a 100pF capacitor
from SCL2 to GND2 or RC lowpass filter (R = 500Ω,
C = 100pF) can be used to increase the rise and fall times
and minimize noise.
SDO2
I1
GND2
2886 F15
Some consideration must be given to signal coupling
between SCL2 and SDA2. Separate these signals on
a printed circuit board or route with ground between.
Figure 14. Filtered Voltage Rails for Low Noise Applications
2886fb
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LTM2886
APPLICATIONS INFORMATION
10
Table 4. EMC Immunity Tests
TEST
LTM2886-5
FREQUENCY
FIELD STRENGTH
10V/m
LOAD = 50Ω
EN 61000-4-3 Annex D
80MHz to 1GHz
1.4MHz to 2GHz
2GHz to 2.7GHz
50Hz and 60Hz
60Hz
1
3V/m
1V/m
EN 61000-4-8 Level 4
EN 61000-4-8 Level 5
EN 61000-4-9 Level 5
*non IEC method
30A/m
NO LOAD
0.1
100A/m*
1000A/m
Pulse
0.01
0.01
0.1
1
10
100 1000 10000
FREQUENCY (kHz)
PCB Layout
2886 F15
The high integration of the LTM2886 makes PCB layout
very simple. However, to optimize its electrical isolation
characteristics, EMI, and thermal performance, some
layout considerations are necessary.
Figure 15. V+ Output Noise Spectral Density Without Filter
10
LTM2886-5
•
Under heavily loaded conditions V and GND current
CC
1
can exceed 300mA. Sufficient copper must be used
on the PCB to insure resistive losses do not cause the
supply voltage to drop below the minimum allowed
LOAD = 50Ω
NO LOAD
0.1
level. Similarly, the V
and GND2 conductors must
CC2
be sized to support any external load current. These
heavy copper traces will also help to reduce thermal
stress and improve the thermal conductivity.
0.01
0.01
0.1
1
10
100 1000 10000
FREQUENCY (kHz)
•
Input and output supply decoupling is not required,
since these components are integrated within the
package. An additional bulk capacitor with a value of
6.8µF to 22µF is recommended. The high ESR of this
capacitor reduces board resonances and minimizes
voltage spikes caused by hot plugging of the supply
voltage. For EMI sensitive applications, an additional
low ESL ceramic capacitor of 1µF to 4.7µF, placed as
close to the power and ground terminals as possible,
is recommended. Alternatively, a number of smaller
value parallel capacitors may be used to reduce ESL
and achieve the same net capacitance.
2886 F16
Figure 16. V+ Output Noise Spectral Density With Filter
RF, Magnetic Field Immunity
TheisolatorµModuletechnologyusedwithintheLTM2886
hasbeenindependentlyevaluated,andsuccessfullypassed
the RF and magnetic field immunity testing requirements
per European Standard EN 55024, in accordance with the
following test standards:
EN 61000-4-3
EN 61000-4-8
EN 61000-4-9
Radiated, Radio-Frequency,
Electromagnetic Field Immunity
•
•
Do not place copper on the PCB between the inner
columns of pads. This area must remain open to
withstand the rated isolation voltage.
Power Frequency Magnetic Field
Immunity
Pulsed Magnetic Field Immunity
The use of solid ground planes for GND and GND2
is recommended for non-EMI critical applications to
optimize signal fidelity, thermal performance, and to
Tests were performed using an unshielded test card de-
signed per the data sheet PCB layout recommendations.
Specific limits per test are detailed in Table 5.
minimize RF emissions due to uncoupled PCB trace
2886fb
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For more information www.linear.com/LTM2886
LTM2886
APPLICATIONS INFORMATION
conduction. The drawback of using ground planes,
where EMI is of concern, is the creation of a dipole
antenna structure which can radiate differential volt-
agesformedbetweenGNDandGND2.Ifgroundplanes
are used it is recommended to minimize their area,
and use contiguous planes as any openings or splits
can exacerbate RF emissions.
The PCB layout in Figures 17 and 18 shows the low EMI
demo board for the LTM2886. The demo board uses a
combination of EMI mitigation techniques, including both
embedded PCB bridge capacitance and discrete GND to
GND2 capacitors. Two safety rated type Y2 capacitors are
used in series, manufactured by MuRata, part number
GA342QR7GF471KW01L. The embedded capacitor ef-
fectively suppresses emissions above 400MHz, whereas
the discrete capacitors are more effective below 400MHz.
•
For large ground planes a small capacitance (≤330pF)
from GND to GND2, either discrete or embedded
within the substrate, provides a low impedance cur-
rent return path for the module parasitic capacitance,
minimizinganyhighfrequencydifferentialvoltagesand
substantially reducing radiated emissions. Discrete
capacitance will not be as effective due to parasitic
ESL. In addition, voltage rating, leakage, and clear-
ance must be considered for component selection.
Embedding the capacitance within the PCB substrate
provides a near ideal capacitor and eliminates com-
ponent selection issues; however, the PCB must be
four layers. Care must be exercised in applying either
technique to ensure the voltage rating of the barrier
is not compromised.
EMI performance is shown in Figure 19, measured using
a Gigahertz Transverse Electromagnetic (GTEM) cell and
method detailed in IEC 61000-4-20, Testing and Measure-
ment Techniques – Emission and Immunity Testing in
Transverse Electromagnetic Waveguides.
•
In applications without an embedded PCB substrate
capacitance a slot may be added between the logic
side and isolated side device pins. The slot extends
the creepage path between terminals on the PCB side,
andmayreduceleakagecausedbyPCBcontamination.
The slot should be placed in the middle of the device
and extend beyond the package perimeter.
Figure 17. LTM2886 Low EMI Demo Board Layout
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LTM2886
APPLICATIONS INFORMATION
Top Layer
Inner Layer 2
Inner Layer 1
Bottom Layer
Figure 18. LTM2886 Low EMI Demo Board Layout (DC1790A)
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LTM2886
APPLICATIONS INFORMATION
60
50
CISPR 22 CLASS B LIMIT
40
30
20
DC1790A-B
10
DC1790A-A
0
DETECTOR = QuasiPeak
RBW = 120kHz
VBW = 300kHz
SWEEP TIME = 17s
# OF POINTS = 501
–10
–20
–30
0
100 200 300 400 500 600 700 800 9001000
FREQUENCY (MHz)
2886 F19
Figure 19. LTM2886 Low EMI Demo Board Emissions
TYPICAL APPLICATIONS
5V
5V
0.1µF
0.1µF
5V
LTM2886-5I
1µF
B8
A8
L8
L7
+
–
8
5V
V
V
V
V
CC
L
3
2
7
8
9
+
–5V
1µF
1
1/2 LTC2055
–
+
10
–
6
5V
OUT
LT1991
G = 4
1.7k 1.7k
A7
A6
A5
A4
A3
A2
A1
B1
B3
L6
K6
L5
L4
L3
L2
L1
K1
K4
1
2
3
4
V
ON
CC2
AV
GND
DI1
CC2
O1
V
CC
LTC2631A-LM12, DAC
1.25V
5
0.1µF
1
2
3
4
8
7
6
5
4
SDA2
SCL2
DNC
I2
CA0
SCL
SDA
GND
R_SEL
SDA
SCL
SDA
SCL
DNC
DO2
DO1
GND
2.5V F.S.
–5V
µC
V
OUT
REF
5
6
+
V
CC
GND
7
I1
1/2 LTC2055
DAC
GND2
–
0.1µF
RA1, 10k
VISHAY, OSOPTA1002AT1
5V
0.1µF
2.5V
LTC2301, ADC
10
11
12
1
9
8
7
6
5
4
GND
AD0 REFC
V
DD
0.1µF
5
7
AD1
GND
SDA
SCL
V
REF
3
2
5V
IN
–
+
–
IN
2
4V F.S.
0.1µF
6
+
IN
LT1218L
3
1µF
GND
10µF
ADC
0.1µF
4
–5V
2886 F20
Figure 20. Isolated I2C 12-Bit, 5V Analog Input and Output
2886fb
28
For more information www.linear.com/LTM2886
LTM2886
TYPICAL APPLICATIONS
LTM2886-3S
B8
A8
L8
L7
+
–
V
V
3.3V
V
V
CC
L
10k
1nF
74LVC1G123
Cx
Rx/Cx
CLR
A
A7
A6
A5
A4
A3
A2
A1
B1
B2
L6
K6
L5
L4
L3
L2
L1
K1
K2
V
CSB
ON
CC2
CC2
AV
SDOE
CS
1µF
CS2
SDI2
SCK2
I2
CSA
B
Q
MOSI
SCK
SDI
SCK
DO2
SDO
DO1
GND
V
CC
CSA
CSB
SDO2
I1
MISO
µC
GND2
MOSI
SCK
MISO
GND
CSA
CSB
MOSI
SCK
2886 F21
Figure 21. Isolated SPI Device Expansion
LTM2886-5I
B8
A8
L8
+
–
10k 10k
10k 10k 10k 10k 10k 10k
V
V
5V
V
V
CC
L
0.01µF
L7
L6
ALERT2
10k 10k
A7
A6
A5
A4
A3
A2
A1
B1
B3
V
1
16
ON
CC2
ALERT2
ALERT
SDAIN
GND
SCLIN
ENABLE
SCL2
SDA2
ALERT1
SDA1
SCL2
K6
L5
L4
L3
L2
L1
K1
K4
2
3
4
5
15
14
13
12
AV
GND
DI1
CC2
O1
SDA2
ALERT1
SDA1
SCL1
ENABLE
SDA
SDA2
SCL2
DNC
I2
SDA
SCL
DNC
DO2
DO1
GND
LTC4305
SCLIN
SCL1
6
7
8
11
10
9
READY
ADR2
V
CC
ALERT
READY
ADR0
ADR1
I1
GND2
2886 F22
Figure 22. Isolated I2C Buffer with Dual Outputs
2886fb
29
For more information www.linear.com/LTM2886
LTM2886
TYPICAL APPLICATIONS
LTM2886-5S
B8
A8
L8
+
V
V
5V
V
V
CC
L
1µF
L7
–
NTC THERMISTORS, MURATA NTSD1WD104, 100k
–t° –t° –t° –t°
A7
A6
A5
A4
A3
A2
A1
B1
B2
L6
K6
L5
L4
L3
L2
L1
K1
K2
V
ON
CC2
AV
SDOE
CS
CC2
V
CC
CS2
SDI2
SCK2
I2
Oz
Oy
Ox
SDI
LTC1799
SCK
DO2
SDO
DO1
GND
µC
–t°
–t°
–t°
–t°
5
4
1
2
3
+
DG4051A
X0
V
1M
OUT
16
3
13
14
15
12
1
Iy
Ix
SDO2
I1
GND
V
X
A
B
C
CC
3.01k
X1
X2
X3
X4
DIV SET
GND
11
10
9
GND2
6
5
ENABLE X5
7
2
V
X6
X7
EE
8
4
TEMPERATURE (°C) FREQUENCY (kHz)
GND
–40
–30
–20
–10
0
1.23
1.46
–t°
–t°
–t°
–t°
1.87
2.58
3.77
LTC1799
+
10
5.67
5
4
1
2
3
DG4051A
20
8.64
V
OUT
1M
16
3
13
14
15
12
1
–t°
–t°
–t°
–t°
30
13.09
19.53
28.47
40.65
55.87
74.45
96.08
119.83
144.73
169.36
X0
X1
X2
X3
X4
GND
V
X
A
B
C
CC
3.01k
40
DIV SET
50
11
10
9
60
70
80
90
100
110
120
6
5
ENABLE X5
7
2
V
X6
X7
EE
8
4
GND
2886 F23
Figure 23. 16-Channel Isolated Temperature to Frequency Converter
2886fb
30
For more information www.linear.com/LTM2886
LTM2886
TYPICAL APPLICATIONS
IRF7509
100k
SWITCHED 5V
SWITCHED –5V
LTM2886-5S
B8
A8
L8
L7
+
–
IRF7509
V
V
5V
V
V
CC
L
100k
A7
A6
A5
A4
A3
A2
A1
B1
B2
L6
K6
L5
L4
L3
L2
L1
K1
K2
V
ON
CC2
IRF7509
100k
AV
SDOE
CS
CC2
IRLML2402
100k
–5V ENABLE
5V ENABLE
5V ENABLE
5V UV
CS2
SDI2
SCK2
I2
SWITCHED 5V
SDI
SCK
DO2
SDO
DO1
GND
84.5k
SDO2
I1
–5V UV
5V UV
GND2
LTC2902
COMP2
COMP1 COMP4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMP3
76.8k
20k
0.1µF
V3
V2
V4
V1
CRT
RST
T0
V
REF
10k
V
PG
93.1k
GND
T1
RDIS
9.53k
2886 F24
Figure 24. Digitally Switched Triple Power Supply with Undervoltage Monitor
2886fb
31
For more information www.linear.com/LTM2886
LTM2886
TYPICAL APPLICATIONS
0.1µF
5V
8
7
9
–
+
10
6
6
6
6
LT1991
G = 4
5V OUTA
5V OUTB
5V OUTC
1
2
3
5
0.1µF
4
–5V
5V
0.1µF
0.1µF
0.1µF
1.25V
5V
8
LTM2886-3S
5
3
4
B8
A8
L8
L7
+
–
7
+
–
5V
V
V
3.3V
V
V
CC
L
1
9
LTC2054
2
1µF
–
+
10
–5V
LT1991
G = 4
LTC2654-L16
1
2
3
A7
A6
A5
A4
A3
A2
A1
B1
B2
L6
K6
L5
L4
L3
L2
L1
K1
K2
15
6
5
V
REFOUT
V
CC
ON
CC2
CC2
3
AV
SDOE
CS
LDAC
CS
REFC
V
5
CC
7
2
0.1µF
CS2
SDI2
SCK2
I2
CS
V
4
OUTA
OUTB
OUTC
OUTD
9
4
MOSI
SCK
SDI
SDI
V
V
–5V
8
13
14
1
SCK
DO2
SDO
DO1
GND
SCK
CLR
SDO
µC
11
10
12
V
0.1µF
MISO
SDO2
I1
REFLO
0.1µF
16
GND
5V
8
PORSEL GND
GND2
7
9
–
+
10
LT1991
G = 4
1
2
3
5
0.1µF
4
–5V
0.1µF
5V
8
7
9
–
+
10
LT1991
G = 4
5V OUTD
1
2
3
5
0.1µF
4
–5V
2886 F25
Figure 25. Quad 16-Bit 5V Output Range DAC
2886fb
32
For more information www.linear.com/LTM2886
LTM2886
TYPICAL APPLICATIONS
LTM2886-5I
B8
A8
L8
L7
+
–
V
V
5V
V
V
CC
L
1µF
10k
10k
A7
A6
A5
A4
A3
A2
A1
B1
B2
L6
K6
L5
L4
L3
L2
L1
K1
K2
V
ON
CC2
V
CC
AV
GND
DI1
CC2
O1
Ox
SDA2
SCL2
DNC
I2
SDA
SCL
1x
SDA
SCL
DNC
DO2
DO1
GND
µC
10k
GND
I1
GND2
V
EE
–48V RTN
1k, ×4 IN SERIES
1/4W EACH
453k
7
21
8
9
22
6
INTV
V
IN
FLTIN
SCL
UVL
UVH
ADIN2
OV
CC
16.9k
10
11
19
20
26
1
5
SDAI
SDAO
ALERT
ON
4
3
SS
2
LTC4261CGN
TMR
EN
28
27
23
PGI
PGI0
PG
PWRGD2
PWRGD1
25
24
ADR1
ADR0
ADIN
11.8k
V
EE
SENSE GATE DRAIN RAMP
14 15 16 18
13
+
330µF
100V
1M
1k
100nF
1µF
220nF
10Ω
47nF
V
OUT
10nF
100V
0.1µF
47nF
10k
0.1µF
–48V INPUT
IRF1310NS
0.008Ω
1%
402k
V
EE
2886 F26
Figure 26. –48V, 200W Hot Swap Controller with Isolated I2C Interface
2886fb
33
For more information www.linear.com/LTM2886
LTM2886
TYPICAL APPLICATIONS
3.3V
LTM2886-3S
LTC6803-1
CSO
3.3k
3.3k
3.3k
B8
A8
L8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
+
3.3k
V
V
CSI
SDO
SDI
SCKI
V
V
V
CC
L
1µF
2
SDOI
L7
3
–
SCKO
4
+
V
A7
A6
A5
A4
A3
A2
A1
B1
B2
L6
K6
L5
L4
L3
L2
L1
K1
K2
5
V
C12
S12
C11
S11
C10
S10
C9
ON
CC2
MODE
6
AV
SDOE
CS
GPIO2
GPIO1
WDT
NC
V
CC2
CC
7
1µF
1µF
CS2
SDI2
SCK2
I2
CS
8
SDI
MOSI
SCK
µC
9
SCK
DO2
SDO
DO1
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
MISO
GND
TOS
SDO2
I1
V
V
V
V
REG
100k
100k
74LVC3G07
S9
REF
GND2
C8
TEMP2
TEMP1
S8
NC
C7
–
V
S7
100k
100k
S1
C1
S2
C2
S3
C3
C6
S6
C5
S5
C4
S4
2886 F27
Figure 27. 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown
LTM2886-3I
B8
A8
L8
L7
+
–
0.02Ω
V
V
3.3V
V
V
CC
48V
V
OUT
L
1µF
10k
+
–
SENSE SENSE
V
IN
A7
A6
A5
A4
A3
A2
A1
B1
B2
L6
K6
L5
L4
L3
L2
L1
K1
K2
V
ON
SHDN
100k AT 25°C, 1%
CC2
10k
V
VISHAY 2381 6154.104
CC
AV
GND
DI1
CC2
O1
SDA2
SCL2
DNC
I2
SDA
SDA
SCL
SDA
SCL
DNC
DO2
DO1
GND
ADIN
LTC4151
µC
SCL
ADR0
ADR1
1.37k
1%
GND
I1
GND2
GND
3950
T(°C)=
− 273,−40°C< T <150°C
1000
8.965+LN
−1
N
ADIN
N
IS THE DIGITAL CODE MEASURED
ADIN
BY THE ADC AT THE ADIN PIN
2886 F28
Figure 28. Isolated I2C Voltage, Current and Temperature Power Supply Monitor
2886fb
34
For more information www.linear.com/LTM2886
LTM2886
TYPICAL APPLICATIONS
LTM2886-5I
B8
L8
L7
+
–
V
V
5V
V
V
CC
A8
L
10k
0.1µF
10k
A7
A6
A5
A4
A3
A2
A1
B1
B2
L6
K6
L5
L4
L3
L2
L1
K1
K2
V
ON
SHUTDOWN
42.2k
CC2
0.1µF
AV
GND
DI1
CC2
O1
100k
SHDN1 V
DD
ENABLE
SDA
RESET
SDAIN
SCL
BYP
SDA2
SCL2
DNC
I2
SDA
SCL
DNC
DO2
DO1
GND
SCLIN
SDAOUT
AUTO
INT
DETECT
1/4 LTC4266
INTERRUPT
I1
GND2
AD0
AD1
24.9k
AD2
CMPD3003
AD3
V
EE
DGND AGND
SENSE GATE OUT
Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T
FB1, FB2: TDK MPZ2012S601A
T1: PULSE H609NL OR COILCRAFT ETH1-230LD
SMAJ58A
1µF
0.25Ω
Q1
–48V
S1B
S1B
0.22µF
FB1
FB2
RJ45
CONNECTOR
1
T1
•
•
•
•
2
3
4
5
6
7
8
10nF
10nF
75Ω
75Ω
PHY
(NETWORK
PHYSICAL
LAYER
•
•
•
•
CHIP)
10nF
10nF
75Ω
75Ω
1nF
2886 F29
Figure 29. One Complete Isolated Powered Ethernet Port
2886fb
35
For more information www.linear.com/LTM2886
LTM2886
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM2886#packaging for the most recent package drawings.
/ / b b b
Z
4 . 4 4 5
3 . 1 7 5
1 . 9 0 5
0 . 6 3 5
0 . 6 3 5
0 . 0 0 0
1 . 9 0 5
3 . 1 7 5
4 . 4 4 5
a a a
Z
2886fb
36
For more information www.linear.com/LTM2886
LTM2886
REVISION HISTORY
REV
DATE
03/17 Added UL-CSA File Number
07/17 Changed MIN limits for t
DESCRIPTION
PAGE NUMBER
A
1
2
B
(SPI and I C)
6
6
PWU
Changed MAX limits for Power-Up Time
2886fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
37
LTM2886
TYPICAL APPLICATION
14-Bit Isolated High Speed Bipolar ADC
LTM2886-3S
B8
L8
L7
+
–
V
3.3V
V
V
CC
A8
L
LTC1417, ADC
1µF
V
2.048V INꢀPT ꢁANGꢂ
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
+
–
AIN
V
V
DD
SS
10µF
0.1µF
10µF
0.1µF
+
+
A7
A6
A5
A4
A3
A2
A1
B1
B2
L6
K6
L5
L4
L3
L2
L1
K1
K4
V
AIN
V
ON
CC2
AV
BUSY
CONVST
RD
SDOE
CS
V
CC
CC2
ꢁꢂF
ꢁꢂFC
CS2
SDI2
SCK2
I2
OX
OY
AGND
ꢂCLK
SCLK
CLKO
SDI
µC
10µF 0.1µF
1µF
+
SHDN
DGND
DOPT
SCK
DO2
SDO
DO1
GND
SCK
MISO
IX
SDO2
I1
GND
GND2
2886 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM2881
Isolated RS485/RS422 µModule Transceiver with 20Mbps 2500V
Integrated DC/DC Converter
Isolation with Power in LGA/BGA Package
RMS
LTM2882
LTM2883
Dual Isolated RS232 µModule Transceiver with
Integrated DC/DC Converter
2500V
Isolation with Power in LGA/BGA Package
RMS
RMS
RMS
2
SPI/Digital or I C µModule Isolator with Integrated 2500V
DC/DC Converter
Isolation with Adjustable 12.5V and 5V Power in BGA Package
LTM2884
LTM2889
LTM2892
LTC®1535
LTC4310
Isolated USB Transceiver with Power
2500V
, Auto Speed Selection, 1 to 2.5W Isolated Power
Isolated CAN FD µModule Transceiver with Power 4Mbps 2500V
Isolation with Power in BGA Package
RMS
2
SPI/Digital or I C µModule Isolator
Isolated RS485 Transceiver
3500V
2500V
Isolation without Power in 9mm × 6.25mm BGA Package
RMS
RMS
Isolation with External Transformer Drive
2
2
Hot-Swappable I C Isolators
Bidirectional I C Communication, Low Voltage Level Shifting, 100kHz or
400kHz Operation
LTC6803-1, LTC6803-3, Multicell Battery Stack Monitor
LTC6803-2, LTC6803-4
LTC6803-1 Allows for Multiple Devices to be Daisy Chained, the LTC6803-2
Allows for Parallel Communication Battery Stack Topologies
2886fb
LT 0717 REV B • PRINTED IN USA
www.linear.com/LTM2886
38
LINEAR TECHNOLOGY CORPORATION 2016
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SI9122E
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