LTM2887CY-3I#PBF [Linear]
LTM2887 - SPI/Digital or I<sup>2</sup>C µModule Isolator with Dual Adjustable 5V Regulators; Package: BGA; Pins: 32; Temperature Range: 0°C to 70°C;
| 型号： | LTM2887CY-3I#PBF |
| 厂家： | 
Linear |
| 描述： | LTM2887 - SPI/Digital or I<sup>2</sup>C µModule Isolator with Dual Adjustable 5V Regulators; Package: BGA; Pins: 32; Temperature Range: 0°C to 70°C 接口集成电路 |
| 文件： | 总38页 (文件大小：578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM2887
2
SPI/Digital or I C µModule
Isolator with Dual Adjustable
5V Regulators
FEATURES
DESCRIPTION
6-Channel Logic Isolator: 2500V
for 1 Minute
The LTM®2887 is a complete galvanic digital µModule®
(micromodule) isolator. No external components are
required. A single 3.3V or 5V supply powers both sides
of the interface through an integrated, isolated DC/DC
converter. A logic supply pin allows easy interfacing with
different logic levels from 1.62V to 5.5V, independent of
the main supply.
n
RMS
File #E151738
n
UL-CSA Recognized
n
Isolated DC Power:
n
1.8V to 5V Logic Supply at Up to 100mA
0.6V to 5V Auxiliary Supply at Up to 100mA
n
n
n
n
n
No External Components Required
2
SPI/Digital (LTM2887-S) or I C (LTM2887-I) Options
High Common Mode Transient Immunity: 30kV/μs
High Speed Operation:
2
Available options are compliant with SPI and I C (master
mode only) specifications.
n
10MHz Digital Isolation
n
n
Theisolatedsideincludestwo5Vnominalpowersupplies,
including programmable current limit, each capable of
providing more than 100mA of load current. The supplies
may be adjusted from their nominal value using a single
external resistor.
4MHz/8MHz SPI Isolation
2
400kHz I C Isolation
n
n
n
n
n
n
3.3V (LTM2887-3) or 5V (LTM2887-5) Operation
1.62V to 5.5V Logic Supply
10kV ꢀSD ꢁHM Across the Isolation Harrier
Maximum Continuous Working Voltage: 560V
Low Current Shutdown Mode (<10µA)
PꢀAK
Coupled inductors and an isolation power transformer
provide 2500V
of isolation between the input and out-
RMS
Low Profile 15mm × 11.25mm × 3.42mm HGA Package
put logic interface. This device is ideal for systems where
the ground loop is broken, allowing for a large common
mode voltage range. Communication is uninterrupted for
common mode transients greater than 30kV/μs.
APPLICATIONS
2
n
Isolated SPI or I C Interfaces
n
Industrial Systems
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Analog Devices, Inc. All other trademarks are the property of their respective owners.
n
Test and Measurement ꢀquipment
n
Hreaking Ground Loops
TYPICAL APPLICATION
Isolated 4MHz SPI Interface
LTM2887 Operating Through 50kV/µs CM Transients
LTM2887-5S
SCK
SD0
SCK2 = SD02
V
AV
IV
CC2
CC2
CC2
5V AT 100mA
V
CC
5V
5V/DIV
1.15k
V
L
V
L2
L2
L2
ON
3.3V AT 100mA
AV
IV
27.4k
REPETITIVE
COMMON MODE
TRANSIENTS
GND2 TO GND
1.15k
SDOE
CS
CS2
SDI2
SCK2
6.04k
CS
SDI
CS
SDI
SDI
SCK
SCK
SCK
200V/DIV
2887 TA01b
20ns/DIV
DO2
SDO
DO1
I2
SDO2
I1
SDO
SDO
GND
GND2
2887 TA01a
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For more information www.linear.com/LTM2887
LTM2887
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V
to GND .................................................. –0.3V to 6V
Logic Outputs
CC
V to GND .................................................... –0.3V to 6V
L
DO1, DO2, SDO to GND ..............–0.3V to (V + 0.3V)
L
V
CC2
, AV , IV to GND2......................... –0.3V to 6V
O1, SCK2, SDI2, CS2,
CC2
CC2
V , AV , IV to GND2 .............................. –0.3V to 6V
SCL2 to GND2 ..........................–0.3V to (V + 0.3V)
L2
L2
L2
L2
Logic Inputs
DI1, SCK, SDI, CS, SCL, SDA, SDOE,
Operating Temperature Range (Note 4)
LTM2887C ............................................... 0°C to 70°C
LTM2887I ............................................–40°C to 85°C
LTM2887ꢁ......................................... –40°C to 125°C
Maximum Internal Operating Temperature............ 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Hody Reflow Temperature ............................ 245°C
ON to GND..................................–0.3V to (V + 0.3V)
L
I1, I2, SDA2,
SDO2 to GND2..........................–0.3V to (V + 0.3V)
L2
PIN CONFIGURATION
LTM2887-I
LTM2887-S
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
DO2 DNC SCL SDA DI1 GND ON
V
L
SDO DO2 SCK SDI CS SDOE ON
V
L
A
B
C
D
E
F
A
B
C
D
E
F
DO1
GND
V
DO1
GND
V
CC
CC
G
H
J
G
H
J
I1
GND2
AV
L2
IV AV
L2
I1
GND2
AV IV AV
L2 L2 CC2
CC2
K
L
K
L
I2 DNC SCL2 SDA2 O1
BGA PACKAGE
V
IV
V
SDO2 I2 SCK2 SDI2 CS2
V
IV V
CC2 CC2
L2
CC2 CC2
L2
BGA PACKAGE
32-PIN (15mm × 11.25mm × 3.42mm)
32-PIN (15mm × 11.25mm × 3.42mm)
T
= 125°C, θ = 23.9°C/W, θ = 8.1°C/W,
T
= 125°C, θ = 23.9°C/W, θ
= 8.1°C/W,
JMAX
JA
JCbottom
JMAX
JA
JCbottom
θ
= 18.1°C/W, θ = 9.3°C/W
θ
= 18.1°C/W, θ = 9.3°C/W
JCtop
JH
JCtop JH
θ VALUꢀS DꢀTꢀRMINꢀD PꢀR JꢀSD51-9, WꢀIGꢁT = 1.2g
θ VALUꢀS DꢀTꢀRMINꢀD PꢀR JꢀSD51-9, WꢀIGꢁT = 1.2g
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For more information www.linear.com/LTM2887
LTM2887
PRODUCT SELECTION GUIDE
LTM2887 C
Y
-3
I
#PBF
LEAD FREE DESIGNATOR
PHF = Lead Free
LOGIC OPTION
2
I = Inter-IC (I C) Hus
S = Serial Peripheral Interface (SPI) Hus
INPUT VOLTAGE RANGE
3 = 3V to 3.6V
5 = 4.5V to 5.5V
PACKAGE TYPE
Y = Hall Grid Array (HGA)
TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)
ꢁ = Automotive Temperature Range (–40°C to 125°C)
PRODUCT PART NUMBER
http://www.linear.com/product/LTM2887#orderinfo
PART MARKING
ORDER INFORMATION
PAD OR BALL
PACKAGE
TYPE
MSL INPUT VOLTAGE
RATING RANGE
LOGIC
OPTION RANGE
TEMPERATURE
PART NUMBER
FINISH
DEVICE
FINISH CODE
LTM2887CY-3I#PHF
LTM2887IY-3I#PHF
LTM2887ꢁY-3I#PHF
LTM2887CY-3S#PHF
LTM2887IY-3S#PHF
LTM2887ꢁY-3S#PHF
LTM2887CY-5I#PHF
LTM2887IY-5I#PHF
LTM2887ꢁY-5I#PHF
LTM2887CY-5S#PHF
LTM2887IY-5S#PHF
LTM2887ꢁY-5S#PHF
0°C to 70°C
2
LTM2887Y-3I
I C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
3V to 3.6V
LTM2887Y-3S
LTM2887Y-5I
LTM2887Y-5S
SPI
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
SAC305 (RoꢁS)
e1
HGA
3
2
I C
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
4.5V to 5.5V
SPI
–40°C to 85°C
–40°C to 125°C
• Device temperature grade is indicated by a label on the
shipping container.
• Recommended HGA PCH Assembly and Manufacturing Procedures:
www.linear.com/HGA-assy
• Pad or ball finish code is per IPC/JꢀDꢀC J-STD-609.
• Terminal Finish Part Marking: www.linear.com/leadfree
• HGA Package and Tray Drawings: www.linear.com/packaging
• This product is moisture sensitive. For more information, go to:
www.linear.com/HGA-assy
• This product is not recommended for second side reflow. For
more information, go to www.linear.com/HGA-assy
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For more information www.linear.com/LTM2887
LTM2887
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
Input Supplies
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Input Supply Range
Logic Supply Range
Input Supply Current
LTM2887-3
LTM2887-5
3
4.5
3.3
5
3.6
5.5
V
V
CC
l
l
V
L
LTM2887-S
LTM2887-I
1.62
3
5.5
5.5
V
V
5
l
l
l
I
I
ON = 0V
LTM2887-3, ON = V , No Load
LTM2887-5, ON = V , No Load
0
25
19
10
30
25
µA
mA
mA
CC
L
L
l
Logic Supply Current
ON = 0V
LTM2887-S, ON = V
LTM2887-I, ON = V
0
10
10
µA
µA
µA
L
L
150
L
Output Supplies
l
V
CC2
Regulated Output Voltage
Output Voltage Operating Range
Line Regulation
No Load, AV
Open
CC2
4.75
0.6
5
5.25
5.5
6
V
V
(Note 2)
l
l
l
I
I
I
I
= 1mA, MIN ≤ V ≤ MAX
1
45
580
1
mV
mV
mV
LOAD
LOAD
LOAD
LOAD
CC
Load Regulation
= 1mA to 100mA
= 1mA to 100mA
= 100mA (Note 2)
150
620
ADJ Pin Voltage
540
Voltage Ripple
mV
RMS
ꢀfficiency
LTM2887-5, I
= 100mA (Note 2)
62
200
%
LOAD
I
Output Short Circuit Current
Internal Current Limit
V
CC2
= 0V, IV = 0V
CC2
mA
mA
CC2
l
ΔV
CC2
= –5%, IV
= 0V
100
CC2
l
l
l
ꢀxternal Programmed Current
Limit
V
CC2
V
CC2
V
CC2
= 5V, R(IV
= 5V, R(IV
= 5V, R(IV
to GND2) = 2.26k
to GND2) = 1.5k
to GND2) = 1.15k
49
71
91
53
79
103
57
87
115
mA
mA
mA
CC2
CC2
CC2
l
V
L2
Regulated Output Voltage
No Load, AV Open
4.75
5
5.25
V
L2
Output Voltage Operating Range
LTM2887-I (Note 2)
LTM2887-S (Note 2)
3
1.8
5.5
5.5
V
V
l
l
l
Line Regulation
Load Regulation
ADJ Pin Voltage
Voltage Ripple
I
I
I
I
= 1mA, MIN ≤ V ≤ MAX
0.25
25
3
mV
mV
mV
LOAD
LOAD
LOAD
LOAD
CC
= 1mA to 100mA
= 1mA to 100mA
= 100mA (Note 2)
100
620
540
580
1
mV
RMS
ꢀfficiency
LTM2887-5, I
= 100mA (Note 2)
62
%
LOAD
I
L2
Output Short Circuit Current
Current Limit
V
= 0V, IV = 0V
200
mA
mA
L2
L2
l
ΔV = –5%, IV = 0V
100
L2
L2
l
l
l
ꢀxternal Programmed Current
Limit
V
V
V
= 5V, R(IV to GND2) = 2.26k
49
71
91
53
79
103
57
87
115
mA
mA
mA
L2
L2
L2
L2
= 5V, R(IV to GND2) = 1.5k
L2
= 5V, R(IV to GND2) = 1.15k
L2
Logic/SPI
l
l
l
V
Input Threshold Voltage
Input Current
ON, DI1, SDOE, SCK, SDI, CS 1.62V ≤ V < 2.35V
0.25 • V
0.33 • V
0.75 • V
0.67 • V
V
V
V
ITꢁ
L
L
L
L
L
ON, DI1, SDOE, SCK, SDI, CS 2.35V ≤ V
L
I1, I2, SDO2
0.33 • V
0.67 • V
L2
L2
l
I
1
µA
INL
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For more information www.linear.com/LTM2887
LTM2887
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
mV
V
ꢁYS
V
Oꢁ
Input ꢁysteresis
150
l
Output ꢁigh Voltage
DO1, DO2, SDO
V – 0.4
L
V
I
I
= –1mA, 1.62V ≤ V < 3V
LOAD
LOAD
L
= –4mA, 3V ≤ V ≤ 5.5V
L
l
l
O1, SCK2, SDI2, CS2, I
= –4mA
V
– 0.4
L2
V
V
LOAD
V
Output Low Voltage
Short-Circuit Current
DO1, DO2, SDO
0.4
OL
I
I
= 1mA, 1.62V ≤ V < 3V
LOAD
LOAD
L
= 4mA, 3V ≤ V ≤ 5.5V
L
l
l
O1, SCK2, SDI2, CS2, I
= 4mA
0.4
85
V
LOAD
I
0V ≤ (DO1, DO2, SDO) ≤ V
0V ≤ (O1, SCK2, SDI2, CS2) ≤ V
mA
mA
SC
L
60
L2
2
I C
l
l
V
Low Level Input Voltage
ꢁigh Level Input Voltage
Input Current
SCL, SDA
SDA2
0.3 • V
V
V
IL
L
0.3 • V
L2
l
l
V
SCL, SDA
SDA2
0.7 • V
V
V
Iꢁ
L
0.7 • V
L2
l
l
I
SCL, SDA = V or 0V
1
1
µA
µA
INL
L
SDA2 = V , SDA2 = V = 0V
L2
L2
V
V
V
Input ꢁysteresis
SCL, SDA
SDA2
0.05 • V
mV
mV
ꢁYS
Oꢁ
L
0.05 • V
L2
l
Output ꢁigh Voltage
Output Low Voltage
SCL2, I
= –2mA
= –2mA
V
– 0.4
L2
L
V
V
LOAD
DO2, I
V – 0.4
LOAD
l
l
l
l
l
SDA, I
DO2, I
= 3mA
= 2mA
= 2mA
0.4
0.4
0.4
0.45
0.55
V
V
V
V
V
OL
LOAD
LOAD
SCL2, I
LOAD
SDA2, No Load, SDA = 0V, 4.5V ≤ V < 5.5V
SDA2, No Load, SDA = 0V, 3V < V < 4.5V
L2
0.3
L2
l
C
C
Input Pin Capacitance
Hus Capacitive Load
SCL, SDA, SDA2 (Note 2)
10
pF
IN
H
l
l
l
l
SCL2, Standard Speed (Note 2)
SCL2, Fast Speed
SDA, SDA2, SR ≥ 1V/µs, Standard Speed (Note 2)
SDA, SDA2, SR ≥ 1V/µs, Fast Speed
400
200
400
200
pF
pF
pF
pF
l
l
Minimum Hus Slew Rate
Short-Circuit Current
SDA, SDA2
1
V/µs
I
SDA2 = 0, SDA = V
0V ≤ SCL2 ≤ V
0V ≤ DO2 ≤ V
SDA = 0, SDA2 = V
100
mA
mA
mA
mA
mA
SC
L
30
30
6
L2
L
L2
SDA = V , SDA2 = 0
–1.8
L
ESD (HBM) (Note 2)
Isolation Houndary
(V , V , GND2) to (V , V , GND)
10
kV
CC2 L2
CC
L
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For more information www.linear.com/LTM2887
LTM2887
SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, and GND =
GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.
SYMBOL PARAMETER
Logic
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Maximum Data Rate
10
35
Mꢁz
ns
DI1 → O1, Ix → DOx, C = 15pF (Note 3)
L
t
t
, t
Propagation Delay
Rise Time
C = 15pF (Figure 1)
L
60
100
PꢁL PLꢁ
l
l
C = 15pF (Figure 1)
3
20
12.5
35
ns
ns
R
L
LTM2887-I, DO2, C = 15pF (Figure 1)
L
l
l
t
F
Fall Time
C = 15pF (Figure 1)
3
20
12.5
35
ns
ns
L
LTM2887-I, DO2, C = 15pF (Figure 1)
L
SPI
l
l
Maximum Data Rate
Hidirectional Communication (Note 3)
Unidirectional Communication (Note 3)
4
8
Mꢁz
Mꢁz
l
t
t
t
t
t
t
, t
Propagation Delay
Output Pulse Width Uncertainty
Rise Time
C = 15pF (Figure 1)
35
60
100
50
ns
ns
ns
ns
ns
ns
PꢁL PLꢁ
L
SDO, SDI2, CS2 (Note 2)
PWU
l
l
l
l
C = 15pF (Figure 1)
L
3
3
12.5
12.5
50
R
F
Fall Time
C = 15pF (Figure 1)
L
, t
Output ꢀnable Time
Output Disable Time
SDOE = ↓, R = 1kΩ, C = 15pF (Figure 2)
PZꢁ PZL
L
L
, t
50
SDOE = ↑, R = 1kΩ, C = 15pF (Figure 2)
PꢁZ PLZ
L
L
2
I C
l
Maximum Data Rate
Propagation Delay
(Note 3)
SCL → SCL2, C = 15pF (Figure 1)
400
kꢁz
l
l
l
t
, t
150
150
300
225
250
500
ns
ns
ns
PꢁL PLꢁ
L
SDA → SDA2, R = Open, C = 15pF (Figure 3)
L
L
SDA2 → SDA, R = 1.1kΩ, C = 15pF (Figure 3)
L
L
t
t
t
Output Pulse Width Uncertainty
Data ꢁold Time
SDA, SDA2 (Note 2)
50
ns
ns
PWU
ꢁD;DAT
R
(Note 2)
600
l
l
l
Rise Time
SDA2, C = 200pF (Figure 3)
40
40
300
250
250
ns
ns
ns
L
SDA, R = 1.1kΩ, C = 200pF (Figure 3)
L
L
SCL2, C = 200pF (Figure 1)
L
l
l
l
t
F
Fall Time
SDA2, C = 200pF (Figure 3)
40
40
250
250
250
ns
ns
ns
L
SDA, R = 1.1kΩ, C = 200pF (Figure 3)
L
L
SCL2, C = 200pF (Figure 1)
L
l
t
SP
Pulse Width of Spikes
0
50
ns
Suppressed by Input Filter
Power Supply
Power-Up Time
l
l
3
3
5
5
ms
ms
ON = ↑ to V
(Min)
ON = ↑ to V (Min)
CC2
L2
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For more information www.linear.com/LTM2887
LTM2887
ISOLATION CHARACTERISTICS TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Rated Dielectric Insulation Voltage
Common Mode Transient Immunity
Maximum Continuous Working Voltage
1 Minute, Derived from 1 Second Test
1 Second (Notes 5, 6)
2500
3000
V
V
ISO
RMS
RMS
LTM2887-3 V = 3.3V, LTM2887-5 V = 5V,
30
kV/µs
CC
CC
V = ON = 3.3V, V = 1kV, Δt = 33ns (Note 2)
L
CM
V
(Notes 2, 5)
560
400
V
,
DC
IORM
PꢀAK
V
V
RMS
Partial Discharge
V
= 750V
(Note 5)
5
pC
PD
RMS
9
Input to Output Resistance
Comparative Tracking Index
Depth of ꢀrosion
(Notes 2, 5)
10
Ω
CTI
DTI
IꢀC 60112 (Note 2)
IꢀC 60112 (Note 2)
(Note 2)
600
V
RMS
0.017
0.06
6
mm
Distance Through Insulation
Input to Output Capacitance
Creepage Distance
mm
pF
(Notes 2, 5)
(Note 2)
9.5
mm
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. ꢀxposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: This Module includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above specified maximum operating junction
temperature may result in device degradation or failure.
Note 2: Guaranteed by design and not subject to production test.
Note 5: Device considered a 2-terminal device. Pin group A1 through H8
shorted together and pin group K1 through L8 shorted together.
Note 3: Maximum Data rate is guaranteed by other measured parameters
and is not tested directly.
Note 6: The rated dielectric insulation voltage should not be interpreted as
a continuous voltage rating.
2887fb
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For more information www.linear.com/LTM2887
LTM2887
TA = 25°C, LTM2887-3 VCC = 3.3V,
TYPICAL PERFORMANCE CHARACTERISTICS
LTM2887-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
VCC Supply Current
vs Temperature
VCC2 and VL2 Voltage
vs Equal Load Current
VCC2 or VL2 Output Voltage
vs Input Voltage and Load Current
30
25
20
15
10
5
5.25
5.00
4.75
4.50
4.25
4.00
5.25
5.00
4.75
4.50
4.25
4.00
NO LOAD, REFRESH DATA ONLY
LTM2887-3
= 3.3V
V
CC
LTM2887-5
V
= 5V
CC
LTM2887-3, V = 3V
CC
LTM2887-3, V = 3.3V
CC
LTM2887-3, V = 3.3V
CC
LTM2887-5, V = 5V
CC
LTM2887-3, V = 3.6V
CC
–50 –25
0
25
50
75 100 125
0
25
50
75
100
125
0
50
100
150
200
TEMPERATURE (°C)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2887 G01
2887 G02
2887 G03
V
CC2 or VL2 Output Voltage
VCC2 or VL2 Load Regulation
vs Temperature
V
CC2 or VL2 Load Regulation
vs Input Voltage and Load Current
vs Temperature
5.25
5.00
4.75
4.50
4.25
4.00
5.10
5.05
5.00
4.95
4.90
5.10
5.05
5.00
4.95
4.90
LTM2887-3
= 3.3V
LTM2887-5
CC
V
V
= 5V
CC
I
I
I
= 1mA
= 10mA
= 100mA
I
= 1mA
= 10mA
= 100mA
LOAD
LOAD
LOAD
LTM2887-5, V = 4.5V
LOAD
CC
I
I
LTM2887-5, V = 5V
LOAD
LOAD
CC
LTM2887-5, V = 5.5V
CC
0
50
100
150
200
250
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
LOAD CURRENT (mA)
TEMPERATURE (°C)
TEMERATURE (°C)
2887 G04
2887 G05
2887 G06
V
CC2 or VL2 Voltage and VCC Input
VCC2 or VL2 Efficiency
Current vs Load Current
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
800
700
600
500
400
300
200
100
0.0
70
60
50
40
30
20
10
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VOLTAGE
EFFICIENCY
CURRENT
POWER LOSS
LTM2887-3, V = 3.3V
LTM2887-3, V = 3.3V
CC
LTM2887-5, V = 5V
CC
CC
LTM2887-5, V = 5V
CC
0
25 50 75 100 125 150 175 200 225
0
25 50 75 100 125 150 175 200 225
LOAD CURRENT (mA)
LOAD CURRENT (mA)
2887 G08
2887 G07
2887fb
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For more information www.linear.com/LTM2887
LTM2887
TA = 25°C, LTM2887-3 VCC = 3.3V,
TYPICAL PERFORMANCE CHARACTERISTICS
LTM2887-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.
V
CC2 or VL2 Transient Response
100mA Load Step
VCC2 or VL2 Ripple
VCC2 or VL2 Noise
LOAD = 1mA
LOAD = 1mA
0.2V/
DIV
5mV/
DIV
2mV/
DIV
LOAD = 100mA
400ns/DIV
LOAD = 100mA
10ms/DIV
50mA/
DIV
200µs/DIV
2887 G09
2887 G10
2887 G11
VCC Supply Current
vs Single Channel Data Rate
Logic Input Threshold
vs VL Supply Voltage
Logic Output Voltage
vs Load Current
6
5
4
3
2
1
0
70
60
50
40
30
20
10
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
C
C
C
C
= 1nF
LTM2887-5
L
L
L
L
= 330pF
= 100pF
= 20pF
V
V
V
= 5.5V
= 3.3V
= 1.62V
L
L
L
INPUT RISING
INPUT FALLING
0
1
2
3
4
5
6
7
8
9
10
1k
10k
100k
1M
10M
100M
1
2
3
4
5
6
|LOAD CURRENT| (mA)
DATA RATE (Hz)
V
SUPPLY VOLTAGE (V)
L
2887 G14
2887 G12
2887 G13
V
CC2 and VL2 Efficiency with
Derating for 125°C Maximum
Internal Operating Temperature
Power On Sequence
Equal Load Current
70
60
50
40
30
20
10
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
600
500
400
300
200
100
0
ON
EFFICIENCY
V
CC2
5V/DIV
or V
L2
LTM2887-3, V = 3.3V
CC
LTM2887-5, V = 5V
CC
POWER LOSS
BASED ON THERMAL IMAGING
1V/DIV
OF DEMO CIRCUIT 1791A
LTM2887-3, V = 3.3V
CC
LTM2887-5, V = 5V
CC
V
CC2
and V EQUALLY LOADED
V
L
= 5V
L2
1ms/DIV
0
25
50
75
100
125
0
25
50
75
100
125
LOAD CURRENT (mA)
TEMPERATURE (°C)
2887 G15
2887 G16
2887 G17
2887fb
9
For more information www.linear.com/LTM2887
LTM2887
PIN FUNCTIONS
LTM2887-I Logic Side
LTM2887-I Isolated Side
I2 (L1): Digital Input, Referenced to V and GND2. Logic
DO2(A1):DigitalOutput,ReferencedtoV andGND.Logic
L2
L
inputconnectedtoDO2throughisolationbarrier.Thelogic
state on I2 translates to the same logic state on DO2. Do
not float.
output connected to I2 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
DNC (L2): Do Not Connect. Pin connected internally.
DNC (A2): Do Not Connect. Pin connected internally.
2
2
SCL2 (L3): Serial I C Clock Output, Referenced to V and
SCL (A3): Serial I C Clock Input, Referenced to V and
L2
L
GND2.LogicoutputconnectedtologicsideSCLpinthrough
isolationbarrier.Clockisunidirectionalfromlogictoisolated
side. SCL2 has a push-pull output stage, do not connect an
external pull-up device. Under the condition of an isolation
communication failure this output defaults to a high state.
GND. Logic input connected to isolated side SCL2 pin
throughisolationbarrier.Clockisunidirectionalfromlogic
to isolated side. Do not float.
2
SDA (A4): Serial I C Data Pin, Referenced to V and GND.
L
HidirectionallogicpinconnectedtoisolatedsideSDA2pin
through isolation barrier. Under the condition of an isola-
tion communication failure this pin is in a high impedance
state. Do not float.
2
SDA2 (L4): Serial I C Data Pin, Referenced to V and
L2
GND2. Hidirectional logic pin connected to logic side SDA
pin through isolation barrier. Output is biased high by a
1.8mA current source. Do not connect an external pull-
up device to SDA2. Under the condition of an isolation
communication failure this output defaults to a high state.
DI1 (A5): Digital Input, Referenced to V and GND. Logic
L
input connected to O1 through isolation barrier. The logic
state on DI1 translates to the same logic state on O1. Do
not float.
O1 (L5): Digital Output, Referenced to V and GND2.
L2
Logic output connected to DI1 through isolation barrier.
Under the condition of an isolation communication failure
O1 defaults to a high state.
GND (A6, B2 to B6): Circuit Ground.
ON (A7): ꢀnable, Referenced to V and GND. ꢀnables
L
power and data communication through the isolation
barrier. If ON is high the part is enabled and power and
communications are functional to the isolated side. If ON
is low the logic side is held in reset, all digital outputs
are in a high impedance state, and the isolated side is
unpowered. Do not float.
V
(L6): 3V to 5.5V Adjustable Isolated Supply Voltage.
L2
Internally generated from V by an isolated DC/DC con-
CC
verter and regulated to 5V with no external components.
Internally bypassed with 4.7µF.
IV (L7): V precision current limit adjust pin. Current
limit threshold is set by connecting a resistor between
IV and GND2. For detailed information on how to set
the current limit resistor value, see the Application Infor-
mation section. If not used, tie IV
bypassed with 10nF.
CC2
CC2
V (A8): Logic Supply. Interface supply voltage for pins
CC2
L
DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is
to GND2. Internally
1.62V to 5.5V. Internally bypassed with 1µF.
CC2
DO1(B1):DigitalOutput,ReferencedtoV andGND.Logic
L
V
(L8): 0.6V to 5.5V Adjustable Isolated Supply Volt-
output connected to I1 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
CC2
age. Internally generated from V by an isolated DC/DC
CC
converterandregulatedto5Vwithnoexternalcomponents.
Internally bypassed with 4.7µF.
V
(B7 to B8): Supply Voltage. Operating voltage is 3V
CC
I1 (K1): Digital Input, Referenced to V and GND2. Logic
L2
to 3.6V for LTM2887-3 and 4.5V to 5.5V for LTM2887-5.
inputconnectedtoDO1throughisolationbarrier.Thelogic
state on I1 translates to the same logic state on DO1. Do
not float.
Internally bypassed with 2.2µF.
GND2 (K2 to K5): Isolated Ground.
2887fb
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For more information www.linear.com/LTM2887
LTM2887
PIN FUNCTIONS
LTM2887-I Isolated Side
communications are functional to the isolated side. If ON
is low the logic side is held in reset, all digital outputs
are in a high impedance state, and the isolated side is
unpowered. Do not float.
AV (K6): 5V Nominal Isolated Supply Voltage Adjust.
L2
The adjust pin voltage is 600mV referenced to GND2. See
Applications Information section for details.
V (A8): Logic Supply. Interface supply voltage for pins
L
IV (K7): V precision current limit adjust pin. Current
L2
L2
SDI, SCK, SDO, SDOE, DO1, DO2, CS, and ON. Operating
limit threshold is set by connecting a resistor between
voltage is 1.62V to 5.5V. Internally bypassed with 1µF.
IV and GND2. For detailed information on how to set
L2
the current limit resistor value, see the Application Infor-
DO1(B1):DigitalOutput,ReferencedtoV andGND.Logic
L
mation section. If not used, tie IV to GND2. Internally
L2
output connected to I1 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
bypassed with 10nF.
AV
(K8): 5V Nominal Isolated Supply Voltage Adjust.
CC2
The adjust pin voltage is 600mV referenced to GND2. See
Applications Information section for details.
GND (B2 to B6): Circuit Ground.
V
(B7 to B8): Supply Voltage. Operating voltage is 3V
CC
to 3.6V for LTM2887-3 and 4.5V to 5.5V for LTM2887-5.
LTM2887-S Logic Side
Internally bypassed with 2.2µF.
SDO (A1): Serial SPI Digital Output, Referenced to V
L
and GND. Logic output connected to isolated side SDO2
pin through isolation barrier. Under the condition of an
isolation communication failure this output is in a high
impedance state.
LTM2887-S Isolated Side
SDO2 (L1): Serial SPI Digital Input, Referenced to V
and GND2. Logic input connected to logic side SDO pin
through isolation barrier. Do not float.
L2
DO2(A2):DigitalOutput,ReferencedtoV andGND.Logic
L
I2 (L2): Digital Input, Referenced to V and GND2. Logic
L2
output connected to I2 through isolation barrier. Under
the condition of an isolation communication failure this
output is in a high impedance state.
inputconnectedtoDO2throughisolationbarrier.Thelogic
state on I2 translates to the same logic state on DO2. Do
not float.
SCK (A3): Serial SPI Clock Input, Referenced to V and
L
SCK2 (L3): Serial SPI Clock Output, Referenced to V
L2
GND. Logic input connected to isolated side SCK2 pin
and GND2. Logic output connected to logic side SCK pin
throughisolationbarrier.Undertheconditionofanisolation
communication failure this output defaults to a low state.
through isolation barrier. Do not float.
SDI(A4):SerialSPIDataInput,ReferencedtoV andGND.
L
Logic input connected to isolated side SDI2 pin through
SDI2 (L4): Serial SPI Data Output, Referenced to V
L2
isolation barrier. Do not float.
and GND2. Logic output connected to logic side SDI pin
throughisolationbarrier.Undertheconditionofanisolation
communication failure this output defaults to a low state.
CS(A5):SerialSPIChipSelect,ReferencedtoV andGND.
L
Logic input connected to isolated side CS2 pin through
isolation barrier. Do not float.
CS2 (L5): Serial SPI Chip Select, Referenced to V and
L2
GND2.LogicoutputconnectedtologicsideCSpinthrough
isolation barrier. Under the condition of an isolation com-
munication failure this output defaults to a high state.
SDOE (A6): Serial SPI Data Output ꢀnable, Referenced to
L
SDO pin in a high impedance state, a logic low enables
the output. Do not float.
V and GND. A logic high on SDOE places the logic side
V (L6): 1.8V to 5.5V Adjustable Isolated Supply Voltage.
L2
Internally generated from V by an isolated DC/DC con-
CC
ON (A7): ꢀnable, Referenced to V and GND. ꢀnables
L
verter and regulated to 5V with no external components.
power and data communication through the isolation
Internally bypassed with 4.7µF.
barrier. If ON is high the part is enabled and power and
2887fb
11
For more information www.linear.com/LTM2887
LTM2887
PIN FUNCTIONS
LTM2887-S Isolated Side
GND2 (K2 to K5): Isolated Ground.
IV (L7): V precision current limit adjust pin. Current
AV (K6): 5V Nominal Isolated Supply Voltage Adjust.
The adjust pin voltage is 600mV Referenced to GND2. See
Applications Information section for details..
CC2
CC2
L2
limit threshold is set by connecting a resistor between
IV and GND2. For detailed information on how to set
CC2
the current limit resistor value, please see the Applica-
IV (K7): V precision current limit adjust pin. Current
L2
L2
tion Information section. If not used, tie IV
Internally bypassed with 10nF.
to GND2.
CC2
limit threshold is set by connecting a resistor between
IV and GND2. For detailed information on how to set
L2
V
(L8): 0.6V to 5.5V Adjustable Isolated Supply Volt-
the current limit resistor value, please see the Applica-
CC2
age. Internally generated from V by an isolated DC/DC
tion Information section. If not used, tie IV to GND2.
CC
L2
Internally bypassed with 10nF.
converterandregulatedto5Vwithnoexternalcomponents.
Internally bypassed with 4.7µF.
AV
(K8): 5V Nominal Isolated Supply Voltage Adjust.
CC2
Theadjustpinvoltageis600mVReferencedtoGND2. See
Applications Information section for details.
I1 (K1): Digital Input, Referenced to V and GND2. Logic
L2
inputconnectedtoDO1throughisolationbarrier.Thelogic
state on I1 translates to the same logic state on DO1. Do
not float.
2887fb
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For more information www.linear.com/LTM2887
LTM2887
BLOCK DIAGRAMS
LTM2887-I
IV
CC2
REG
V
CC2
4.7µF
10nF
AV
CC2
V
CC
GND2
IV
V
L
2.2µF
L2
1µF
REG
V
L2
GND
ON
4.7µF
10nF
DC/DC
CONVERTER
AV
L2
REG
O1
DI1
SDA
SCL
SDA2
SCL2
ISOLATED
COMMUNI-
CATIONS
ISOLATED
COMMUNI-
CATIONS
INTERFACE
INTERFACE
DO2
DO1
I2
I1
2887 BDa
2887fb
13
For more information www.linear.com/LTM2887
LTM2887
BLOCK DIAGRAMS
LTM2887-S
IV
CC2
REG
V
CC2
4.7µF
10nF
AV
CC2
V
CC
GND2
IV
V
L
2.2µF
L2
1µF
REG
V
L2
GND
4.7µF
10nF
DC/DC
CONVERTER
AV
L2
ON
SDOE
CS
REG
CS2
SDI2
SCK2
I2
SDI
ISOLATED
COMMUNI-
CATIONS
ISOLATED
SCK
DO2
SDO
DO1
COMMUNI-
CATIONS
INTERFACE
INTERFACE
SDO2
I1
2887 BDb
2887fb
14
For more information www.linear.com/LTM2887
LTM2887
TEST CIRCUITS
V
L
INPUT
½V
L
0V
OUTPUT
t
t
PHL
PLH
C
L
INPUT
V
OH
90%
10%
10%
90%
OUTPUT
½V
L2
V
OL
t
t
F
R
V
L2
INPUT
½V
L2
0V
OUTPUT
t
t
PHL
PLH
C
L
INPUT
V
OH
90%
10%
10%
90%
OUTPUT
½V
L
V
OL
t
t
F
R
2887 F01
Figure 1. Logic Timing Measurements
V
L
OR 0V
V
L
SDOE
SDO
SDO
½V
L
R
L
0V
0V
t
t
PHZ
PZH
V
OH
SDO
SDO2 OR
V
L2
V
V
– 0.5V
+ 0.5V
OH
½V
C
L
t
L
0V
t
PLZ
SDOE
PZL
L
V
L
½V
OL
V
OL
2887 F02
Figure 2. Logic Enable/Disable Time
V
L
V
L
R
L
SDA
½V
L
0V
SDA2
t
t
PLH
PHL
C
L
SDA
V
OH
30%
70%
30%
SDA2
½V
L2
70%
V
OL
t
t
R
F
V
L
V
L2
R
L
SDA2
SDA
½V
L2
0V
SDA
t
t
PLH
PHL
C
L
SDA2
V
OH
30%
70%
30%
½V
L
70%
V
OL
t
t
R
F
2887 F03
Figure 3. I2C Timing Measurements
2887fb
15
For more information www.linear.com/LTM2887
LTM2887
APPLICATIONS INFORMATION
Overview
The internal power solution is sufficient to provide a
minimum of 100mA of current from V and V . V
CC2
L2 CC
The LTM2887 digital µModule isolator provides a
galvanically-isolated robust logic interface, powered by
an integrated, regulated DC/DC converter, complete with
decoupling capacitors. The LTM2887 is ideal for use in
networks where grounds can take on different voltages.
Isolation in the LTM2887 blocks high voltage differences,
eliminates ground loops and is extremely tolerant of com-
mon mode transients between ground planes. ꢀrror-free
operation is maintained through common mode events
greater than 30kV/μs providing excellent noise isolation.
is bypassed with 2.2µF, V
with 4.7µF.
and V are each bypassed
CC2
L2
V Logic Supply
L
A separate logic supply pin V allows the LTM2887 to in-
L
terface with any logic signal from 1.62V to 5.5V as shown
in Figure 4. Simply connect the desired logic supply to V .
L
There is no interdependency between V and V ; they
CC
L
may simultaneously operate at any voltage within their
specified operating ranges and sequence in any order. V
is bypassed internally by a 1µF capacitor.
L
Isolator µModule Technology
The LTM2887 utilizes isolator µModule technology to
translate signals and power across an isolation barrier.
Signalsoneithersideofthebarrierareencodedintopulses
and translated across the isolation boundary using core-
less transformers formed in the µModule substrate. This
system, complete with data refresh, error checking, safe
shutdown on fail, and extremely high common mode im-
munity, provides a robust solution for bidirectional signal
isolation. The µModule technology provides the means to
combinetheisolatedsignalingwithmultipleregulatorsand
apowerfulisolatedDC/DCconverterinonesmallpackage.
3V TO 3.6V LTM2887-3
4.5V TO 5.5V LTM2887-5
LTM2887-I
V
AV
IV
CC2
CC2
CC2
V
V
CC
L
ANY VOLTAGE FROM
1.62V TO 5.5V
V
L2
L2
L2
AV
IV
ON
DI1
O1
SDA2
SCL2
SDA
SCL
EXTERNAL
DEVICE
DC/DC Converter
DO2
DO1
I2
I1
TheLTM2887containsafullyintegratedDC/DCconverter,
includingthetransformer,sothatnoexternalcomponents
are necessary. The logic side contains a full-bridge driver,
running at 1.6Mꢁz, and is AC-coupled to a single trans-
former primary. A series DC blocking capacitor prevents
transformersaturationduetodriverdutycycleimbalance.
The transformer scales the primary voltage, and is recti-
fied by a full-wave voltage doubler. This topology allows
for a single diode drop, as in a center tapped full-wave
bridge, and eliminates transformer saturation caused by
secondary imbalances.
GND
GND2
2887 F04
Figure 4. VCC and VL Are Independent
Hot-Plugging Safely
Caution must be exercised in applications where power is
plugged into the LTM2887’s power supplies, V or V ,
CC
L
due to the integrated ceramic decoupling capacitors. The
parasitic cable inductance along with the high Q char-
acteristics of ceramic capacitors can cause substantial
ringing which could exceed the maximum voltage ratings
anddamagetheLTM2887. RefertoLinearTechnologyAp-
plication Note 88, entitled Ceramic Input Capacitors Can
Cause Overvoltage Transients for a detailed discussion
Three low dropout regulators (LDOs) are connected to
the output of the voltage doubler. One LDO powers the
internal circuitry and is not available externally. The other
two LDOs provide regulated 5V nominally for the V and
CC2
V
outputs. V corresponds to the voltage levels on the
L2
L2
isolated logic pins.
and mitigation of this phenomenon.
2887fb
16
For more information www.linear.com/LTM2887
LTM2887
APPLICATIONS INFORMATION
Isolated Supply Adjustable Operation
maximum output power, insuring that either voltage rail
does not collapse if the opposing rail is loaded beyond
Thetwoisolatedpowerrailsmaybeadjustedbyconnection
of external resistive dividers. The unadjusted output volt-
agesrepresentthemaximumsforguaranteedperformance.
Figure 5 illustrates configuration of the output power rails
its capability. The current limit threshold (I
) is set by
to GND2:
LIMIT
or I
CC2 VL2
attaching a resistor (R
) from IV
IMAX
R
IMAX
= [119.22-(0.894 • (V , V ))]/I
CC2 L2 LIMIT
for V
= 3.3V, and V = 2.5V.
CC2
L2
The output adjustment range for V
Output voltage is calculated by:
is 0.6V to 5.5V.
The accuracy of this equation for setting the resistor value
is approximately 1%. Unit values are amps, volts, and
ohms. Figure 5 shows the current limit programmed for
CC2
V
CC2
= 0.6V(1 + R2/R1)
75mA on V and 25mA on V . If the external program-
CC2
L2
Adjustment range for V is 3V to 5.5V for the LTM2887-I,
L2
mable current limit is not needed, the IV
must be connected to GND2. The current limit pins are
pin or IV
CC2
L2
and 1.8V to 5.5V for the LTM2887-S. Output voltage is
calculated by:
internally decoupled with 10nF capacitors.
V
= 0.6V(1 + R5/R4)
L2
Channel Timing Uncertainty
The value of R1 or R4 should be no greater than 6.04k to
minimize errors in the output voltage caused by the adjust
pin bias currents and internal voltage dividers.
Multiplechannelsaresupportedacrosstheisolationbound-
ary by encoding and decoding of the inputs and outputs.
Up to three signals in each direction are assembled as a
packet and transferred across the isolation barrier. The
time required to transfer all 3 bits is 100ns maximum,
and sets the limit for how often a signal can change on
the opposite side of the barrier. ꢀncoding transmission is
independent for each data direction. The technique used
assigns SCK or SCL on the logic side, and SDO2 or I2 on
the isolated side, the highest priority such that there is
Operation at low output voltages may result in thermal
shutdownduetolowdropoutregulatorpowerdissipation.
Isolated Supply Programmable Current Limit
The IV
pin and IV pin allow programming of the
L2
CC2
maximum current available from V
and V respec-
CC2
L2
tively. The current adjustments may be used to limit the
2.5V AT 25mA
3.3V AT 75mA
LTM2887-5S
V
AV
IV
CC2
CC2
CC2
V
V
CC
L
5V
R2
27.4k
V
L2
L2
L2
ON
AV
IV
R5
19.1k
R3
1.54k
R1
6.04k
R6
4.64k
SDOE
CS
R4
6.04k
CS2
SDI2
SCK2
SDI
SCK
DO2
SDO
DO1
I2
SDO2
I1
GND
GND2
2887 F05
Figure 5. Adjustable Voltage Rails
2887fb
17
For more information www.linear.com/LTM2887
LTM2887
APPLICATIONS INFORMATION
no jitter on the associated output channels, only delay.
This preemptive scheme will produce a certain amount of
uncertainty on the other isolation channels. The resulting
pulse width uncertainty on these low priority channels is
typically 6ns, but may vary up to 50ns if the low priority
channels are not encoded within the same high priority
serial packet.
• SDI to SCK (master data write to slave)
t → t
≈50ns, SDI to SDI2 propagation delay
≈50ns, SCK to SCK2 propagation delay
2
4
6
5
t → t
5
t → t
2
≥50ns, SDI to SCK, separate packet
non-zero set-up time
t → t
4
≥50ns, SDI2 to SCK2, separate packet
non-zero set-up time
6
Serial Peripheral Interface (SPI) Bus
• SDO to SCK (master sample SDO, subsequent
SDO valid)
The LTM2887-S provides a SPI compatible isolated inter-
face. The maximum data rate is a function of the inherent
channel propagation delays, channel to channel pulse
width uncertainty, and data direction requirements. Chan-
nel timing is detailed in Figures 6 through 9 and Tables
2 and 3. The SPI protocol supports four unique timing
configurations defined by the clock polarity (CPOL) and
clock phase (CPꢁA) summarized in Table 1.
t
set-up data transition SDI and SCK
8
t → t
8
≈50ns, SDI to SDI2 and SCK to SCK2
propagation delay
10
t
10
SDO2 data transition in response to SCK2
t → t ≈50ns, SDO2 to SDO propagation delay
10
11
Table 1. SPI Mode
t → t Set-up time for master SDO to SCK
11
12
CPOL CPHA
DATA TO (CLOCK) RELATIONSHIP
Maximum data rate for single direction communication,
master to slave, is 8Mꢁz, limited by the systems encod-
ing/decodingschemeorpropagationdelay. Timingdetails
for both variations of clock phase are shown in Figures 8
and 9 and Table 3.
0
0
1
1
0
1
0
1
Sample (Rising)
Set-Up (Falling)
Sample (Falling)
Set-Up (Rising)
Sample (Rising)
Set-Up (Rising)
Sample (Falling)
Set-Up (Falling)
The maximum data rate for bidirectional communication
is 4Mꢁz, based on a synchronous system, as detailed in
the timing waveforms. Slightly higher data rates may be
achieved by skewing the clock duty cycle and minimiz-
ing the SDO to SCK set-up time, however the clock rate
is still dominated by the system propagation delays. A
discussion of the critical timing paths relative to Figure 6
and 7 follows.
Additional requirements to insure maximum data rate are:
• CS is transmitted prior to (asynchronous) or within the
same (synchronous) data packet as SDI
• SDI and SCK set-up data transition occur within the
same data packet. Referencing Figure 6, SDI can pre-
cede SCK by up to 13ns (t → t ) or lag SCK by 3ns
7
8
(t → t ) and not violate this requirement. Similarly in
8
9
Figure 8, SDI can precede SCK by up to 13ns (t → t )
4
5
• CS to SCK (master sample SDO, 1st SDO valid)
or lag SCK by 3ns (t → t ).
5
6
t → t
≈50ns, CS to CS2 propagation delay
0
1
t → t
Isolated slave device propagation
(response time), asserts SDO2
1
1+
t → t
≈50ns, SDO2 to SDO propagation delay
Set-up time for master SDO to SCK
1
3
t → t
3
5
2887fb
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APPLICATIONS INFORMATION
CPHA = 0
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
SDO
INVALID
SDO2
t
0
t
1
t
t
t
t
t
t
t
t
10
t
t
t
t
t
t
t
2
3
4
5
6
7
9
11 12
13
14
15
17
18
t
8
2887 F06
Figure 6. SPI Timing, Bidirectional, CPHA = 0
CPHA = 1
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
SDO
INVALID
SDO2
t
0
t
1
t
t
t
t
t
t
t
t
10
t
t
t
t
t
t
t
t
2
3
4
5
6
7
9
11 12
13
14
15
16 17
18
t
8
2887 F07
Figure 7. SPI Timing, Bidirectional, CPHA = 1
2887fb
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LTM2887
APPLICATIONS INFORMATION
CPHA = 0
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
t
0
t
t
t
3
t
4
t
5
t
t
t
9
t
t
12
1
2
7
8
11
t
6
2887 F08
Figure 8. SPI Timing, Unidirectional, CPHA = 0
CPHA = 1
CS = SDOE
CS2
SDI
SDI2
SCK (CPOL = 0)
SCK2 (CPOL = 0)
SCK (CPOL = 1)
SCK2 (CPOL = 1)
t
0
t
t
t
3
t
4
t
5
t
t
t
9
t
t
t
12
1
2
7
8
10 11
t
6
2887 F09
Figure 9. SPI Timing, Unidirectional, CPHA = 1
2887fb
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APPLICATIONS INFORMATION
Table 2. Bidirectional SPI Timing Event Description
TIME
CPHA
EVENT DESCRIPTION
t
0, 1
Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output
enabled, initial data is not equivalent to slave device data output
0
t to t
t
to t
18
0, 1
0, 1
0
Propagation delay chip select, logic to isolated side, 50ns typical
Slave device chip select output data enable
0
1, 17
t
1
t
2
Start of data transmission, data set-up
1
Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge
Propagation delay of slave data, isolated to logic side, 50ns typical
Slave data output valid, logic side
t to t
0, 1
0, 1
0
1
3
4
t
3
t to t
2
Propagation delay of data, logic side to isolated side
Propagation delay of data and clock, logic side to isolated side
Logic side data sample time, half clock period delay from data set-up transition
Propagation delay of clock, logic to isolated side
Isolated side data sample time
1
t
5
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0, 1
0
t to t
5
6
t
6
t
8
Synchronous data and clock transition, logic side
Data to clock delay, must be ≤13ns
t to t
7
8
t to t
8
Clock to data delay, must be ≤3ns
9
t to t
8
Propagation delay clock and data, logic to isolated side
Slave device data transition
10
t
t
t
t
t
10, 14
to t
to t
t
to t
15
Propagation delay slave data, isolated to logic side
Slave data output to sample clock set-up time
10
11
13
11, 14
12
Last data and clock transition logic side
1
Last sample clock transition logic side
t
to t
to t
0
Propagation delay data and clock, logic to isolated side
Propagation delay clock, logic to isolated side
13
15
14
1
t
0
Last slave data output transition logic side
1
Last slave data output and data transition, logic side
Propagation delay data, logic to isolated side
t
15
t
17
t
18
1
16
0, 1
0, 1
Asynchronous chip select transition, end of transmission. Disable slave data output logic side
Chip select transition isolated side, slave data output disabled
2887fb
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APPLICATIONS INFORMATION
Table 3. Unidirectional SPI Timing Event Description
TIME
CPHA
0, 1
0, 1
0
EVENT DESCRIPTION
t
Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns
Propagation delay chip select, logic to isolated side
Start of data transmission, data set-up
0
t to t
0
1
3
t
2
1
Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge
Propagation delay of data, logic side to isolated side
Propagation delay of data and clock, logic side to isolated side
Logic side data sample time, half clock period delay from data set-up transition
Clock propagation delay, clock and data transition
Data to clock delay, must be ≤13ns
t to t
2
0
1
t
3
0, 1
0, 1
0, 1
0, 1
0, 1
0
t to t
3
5
5
6
7
t to t
4
t to t
5
Clock to data delay, must be ≤3ns
t to t
5
Data and clock propagation delay
t
8
Last clock and data transition
1
Last clock transition
t to t
8
0
Clock and data propagation delay
9
1
Clock propagation delay
t to t
9
1
Data propagation delay
10
t
11
t
12
0, 1
0, 1
Asynchronous chip select transition, end of transmission
Chip select transition isolated side
2
Inter-IC Communication (I C) Bus
standardminimumsetuptime(t )of100ns,maximum
SU;DAT
clock propagation delay of 225ns, glitch filter and isolated
data delay of 500ns maximum, and the combined isolated
and logic data fall time of 300ns at maximum bus load-
2
The LTM2887-I provides an I C compatible isolated in-
terface. Clock (SCL) is unidirectional, supporting master
mode only, and data (SDA) is bidirectional. The maximum
data rate is 400kꢁz which supports fast-mode I C. Timing
is detailed in Figure 10. The data rate is limited by the slave
2
ing. The total setup time reduces the I C data hold time
2
(t
) to a maximum of 175ns, guaranteeing sufficient
ꢁD;DAT
data setup time (t
).
2
SU;ACK
acknowledge setup time (t
), consisting of the I C
SU;ACK
SLAVE ACK
SDA
SDA2
SCL
1
8
9
SCL2
START
STOP
2887 F10
t
PROP
t
t
t
SU;DAT
HD;DAT
SU;ACK
Figure 10. I2C Timing Diagram
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APPLICATIONS INFORMATION
The isolated side bidirectional serial data pin, SDA2,
simplified schematic is shown in Figure 11. An internal
1.8mA current source provides a pull-up for SDA2. Do not
connect any other pull-up device to SDA2. This current
source is sufficient to satisfy the system requirements for
bus capacitances greater than 200pF in FAST mode and
greater than 400pF in STANDARD mode.
Some consideration must be given to signal coupling
between SCL2 and SDA2. Separate these signals on a
printed circuit board or route with ground between. If
these signals are wired off board, twist SCL2 with V
CC2
and/or GND2 and SDA2 with GND2 and/or V , do not
CC2
twist SCL2 and SDA2 together. If coupling between SCL2
and SDA2 is unavoidable, place the aforementioned RC
filter at the SCL2 pin to reduce noise injection onto SDA2.
1.8mA
GLITCH FILTER
30
TO
V = 3V
LOGIC
V = 3.3V
SIDE
SDA2
25
20
15
10
5
V = 3.6V
V = 4.5V TO 5.5V
FROM
LOGIC
SIDE
2887 F11
Figure 11. Isolated SDA2 Pin Schematic
Additional proprietary circuitry monitors the slew rate on
the SDA and SDA2 signals to manage directional control
across the isolation barrier. Slew rates on both pins must
be greater than 1V/µs for proper operation.
0
10
100
(pF)
1000
C
BUS
2887 F12
Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA
The logic side bidirectional serial data pin, SDA, requires a
pull-up resistor or current source connected to V . Follow
L
10
V = 3V
the requirements in Figures 12 and 13 for the appropri-
9
8
7
6
5
4
3
2
1
0
V = 3.3V
ate pull-up resistor on SDA that satisfies the desired rise
V = 3.6V
V = 4.5V TO 5.5V
time specifications and V maximum limits for FAST and
OL
STANDARD modes. The resistance curves represent the
maximum resistance boundary; any value may be used
to the left of the appropriate curve.
The isolated side clock pin, SCL2, has a weak push-pull
output driver; do not connect an external pull-up device.
2
SCL2iscompatiblewithI Cdeviceswithoutclockstretch-
10
100
(pF)
1000
ing. On lightly loaded connections, a 100pF capacitor
form SCL2 to GND2 or RC lowpass filter (R = 500Ω,
C = 100pF) can be used to increase the rise and fall times
and minimize noise.
C
BUS
2887 F13
Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA
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APPLICATIONS INFORMATION
RF, Magnetic Field Immunity
• Inputandoutputdecouplingisnotrequired,sincethese
components are integrated within the package. An ad-
ditional bulk capacitor with a value of 6.8µF to 22µF is
recommended. The high ꢀSR of this capacitor reduces
boardresonancesandminimizesvoltagespikescaused
by hot plugging of the supply voltage. For ꢀMI sensitive
applications,anadditionallowꢀSLceramiccapacitorof
1µF to 4.7µF, placed as close to the power and ground
terminalsaspossible, isrecommended. Alternatively, a
numberofsmallervalueparallelcapacitorsmaybeused
to reduce ꢀSL and achieve the same net capacitance.
TheisolatorµModuletechnologyusedwithintheLTM2887
hasbeenindependentlyevaluated,andsuccessfullypassed
the RF and magnetic field immunity testing requirements
per ꢀuropean Standard ꢀN 55024, in accordance with the
following test standards:
ꢀN 61000-4-3
ꢀN 61000-4-8
ꢀN 61000-4-9
Radiated, Radio-Frequency,
ꢀlectromagnetic Field Immunity
Power Frequency Magnetic Field
Immunity
• Do not place copper on the PCH between the inner col-
umnsofpads. Thisareamustremainopentowithstand
the rated isolation voltage.
Pulsed Magnetic Field Immunity
Tests were performed using an unshielded test card de-
signed per the data sheet PCH layout recommendations.
Specific limits per test are detailed in Table 4.
• The use of solid ground planes for GND and GND2
is recommended for non-ꢀMI critical applications to
optimize signal fidelity, thermal performance, and to
minimize RF emissions due to uncoupled PCH trace
conduction. The drawback of using ground planes,
where ꢀMI is of concern, is the creation of a dipole
antennastructurewhichcanradiatedifferentialvoltages
formed between GND and GND2. If ground planes are
used it is recommended to minimize their area, and
use contiguous planes as any openings or splits can
exacerbate RF emissions.
Table 4. EMC Immunity Tests
TEST
FREQUENCY
80Mꢁz to 1Gꢁz
1.4Mꢁz to 2Gꢁz
2Gꢁz to 2.7Gꢁz
50ꢁz and 60ꢁz
60ꢁz
FIELD STRENGTH
10V/m
ꢀN 61000-4-3 Annex D
3V/m
1V/m
ꢀN 61000-4-8 Level 4
ꢀN 61000-4-8 Level 5
ꢀN 61000-4-9 Level 5
*non IꢀC method
30A/m
100A/m*
1000A/m
Pulse
• For large ground planes a small capacitance (≤330pF)
from GND to GND2, either discrete or embedded within
the substrate, provides a low impedance current return
path for the module parasitic capacitance, minimizing
anyhighfrequencydifferentialvoltagesandsubstantially
reducing radiated emissions. Discrete capacitance will
notbeaseffectiveduetoparasiticꢀSL.Inaddition,volt-
age rating, leakage, and clearance must be considered
for component selection. ꢀmbedding the capacitance
withinthePCHsubstrateprovidesanearidealcapacitor
and eliminates component selection issues; however,
the PCH must be 4 layers. Care must be exercised in
applying either technique to ensure the voltage rating
of the barrier is not compromised.
PCB Layout
The high integration of the LTM2887 makes PCH layout
very simple. ꢁowever, to optimize its electrical isolation
characteristics, ꢀMI, and thermal performance, some
layout considerations are necessary.
• Under heavily loaded conditions V and GND current
CC
can exceed 300mA. Sufficient copper must be used
on the PCH to insure resistive losses do not cause the
supply voltage to drop below the minimum allowed
level. Similarly, the V
and GND2 conductors must
CC2
be sized to support any external load current. These
heavy copper traces will also help to reduce thermal
stress and improve the thermal conductivity.
2887fb
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APPLICATIONS INFORMATION
• In applications without an embedded PCH substrate
capacitance a slot may be added between the logic
side and isolated side device pins. The slot extends
the creepage path between terminals on the PCH side,
and may reduce leakage caused by PCH contamination.
The slot should be placed in the middle of the device
and extend beyond the package perimeter.
The PCH layout in Figures 14 and 15 shows the low ꢀMI
demo board for the LTM2887. The demo board uses a
combination of ꢀMI mitigation techniques, including both
embedded PCH bridge capacitance and discrete GND to
GND2 capacitors. Two safety rated type Y2 capacitors are
used in series, manufactured by MuRata, part number
GA342QR7GF471KW01L. The embedded capacitor ef-
fectively suppresses emissions above 400Mꢁz, whereas
the discrete capacitors are more effective below 400Mꢁz.
ꢀMI performance is shown in Figure 16, measured using
a Gigahertz Transverse ꢀlectromagnetic (GTꢀM) cell and
method detailed in IꢀC 61000-4-20, Testing and Measure-
ment Techniques – ꢀmission and Immunity Testing in
Transverse ꢀlectromagnetic Waveguides.
Figure 14. LTM2887 Low EMI Demo Board Layout
2887fb
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LTM2887
APPLICATIONS INFORMATION
Top Layer
Inner Layer 2
Inner Layer 1
Bottom Layer
Figure 15. LTM2887 Low EMI Demo Board Layout (DC1791A)
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26
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LTM2887
APPLICATIONS INFORMATION
60
50
CISPR 22 CLASS B LIMIT
DC1791A-B
40
30
20
10
DC1791A-A
0
DETECTOR=QUASIPEAK
RBW=120kHz
VBW=300kHz
SWEEP TIME=17s
# of POINTS=501
–10
–20
–30
0
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
2887 F16
Figure 16. LTM2887 Low EMI Demo Board Emissions
TYPICAL APPLICATIONS
LTM2887-5I
B8
A8
L8
K8
L7
K7
L6
K6
V
AV
IV
5V
V
V
CC2
CC2
CC2
CC
L
1µF
1.7k
IV
L2
L2
A7
A6
A5
A4
A3
A2
A1
B1
B3
V
ON
1.7k
AV
GND
DI1
L2
V
CC
L5
L4
L3
L2
L1
K1
K2
LTC2631A-HZ12, DAC
O1
SDA2
SCL2
DNC
I2
1
2
3
4
8
7
6
5
CA1
SDA
SCL
SDA
SCL
DNC
DO2
DO1
GND
CA0
SCL
SDA
GND
µC
0V TO 4.096V OUT
V
OUT
REF
V
CC
GND
I1
0.1µF
1µF
GND2
LTC2301, ADC
10
11
12
1
9
8
7
6
5
4
GND
AD0 REFC
V
DD
0.1µF
AD1
GND
SDA
SCL
V
REF
–
IN
2
+
IN
0V TO 4.096V IN
0.1µF
3
10µF
1µF
GND
2887 F17
Figure 17. Isolated I2C 12-Bit, 0V to 4.096V Analog Input and Output
2887fb
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LTM2887
TYPICAL APPLICATIONS
LTM2887-3S
B8
A8
L8
K8
L7
K7
L6
K6
V
3.3V
V
V
CC2
CC2
CC2
CC
L
AV
IV
10k
1nF
74LVC1G123
IV
L2
L2
Cx
Rx/Cx
CLR
A
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
CSB
ON
AV
SDOE
CS
L2
L5
L4
L3
L2
L1
K1
K2
1µF
CS2
SDI2
SCK2
I2
CSA
B
Q
MOSI
SCK
SDI
SCK
DO2
SDO
DO1
GND
V
CC
CSA
CSB
SDO2
I1
MISO
µC
GND2
MOSI
SCK
MISO
GND
CSA
CSB
MOSI
SCK
2887 F18
Figure 18. Isolated SPI Device Expansion
LTM2887-5I
B8
A8
L8
K8
V
AV
IV
5V
V
V
CC2
CC2
CC2
CC
10k 10k
0.01µF
1
10k 10k 10k 10k 10k 10k
ALERT2
L
L7
K7
L6
K6
IV
L2
L2
10k
10k
A7
A6
A5
A4
A3
A2
A1
B1
B3
16
15
14
13
12
11
10
9
V
ALERT2
SCL2
SDA2
SCL2
ON
2
3
4
5
6
7
8
AV
ALERT
SDAIN
GND
SDA2
ALERT1
SDA1
SCL1
GND
DI1
L2
L5
L4
L3
L2
L1
K1
K2
O1
SDA2
SCL2
DNC
I2
ENABLE
SDA
ALERT1
SDA1
SDA
SCL
DNC
DO2
DO1
GND
LTC4305
SCLIN
ENABLE
SCL1
SCLIN
READY
ADR2
ALERT
V
CC
ADR0
ADR1
READY
I1
GND2
2887 F19
Figure 19. Isolated I2C Buffer with Dual Outputs
2887fb
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LTM2887
TYPICAL APPLICATIONS
LTM2887-5S
B8
A8
L8
K8
L7
K7
L6
K6
V
AV
IV
5V
V
V
CC2
CC2
CC2
CC
L
1µF
IV
NTC THERMISTORS, MURATA NTSD1WD104, 100k
L2
L2
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
–t°
–t°
–t°
–t°
AV
SDOE
CS
L2
V
CC
L5
L4
L3
L2
L1
K1
K2
CS2
SDI2
SCK2
I2
Oz
Oy
Ox
SDI
LTC1799
SCK
DO2
SDO
DO1
GND
µC
–t°
–t°
–t°
–t°
5
4
1
2
3
+
DG4051A
X0
V
1M
OUT
16
3
13
14
15
12
1
Iy
Ix
SDO2
I1
GND
V
X
A
B
C
CC
3.01k
X1
X2
X3
X4
DIV SET
GND
11
10
9
GND2
6
5
ENABLE X5
7
2
V
X6
X7
EE
8
4
TEMPERATURE (°C) FREQUENCY (kHz)
GND
–40
–30
–20
–10
0
1.23
1.46
–t°
–t°
–t°
–t°
1.87
2.58
3.77
LTC1799
+
10
5.67
5
4
1
2
3
DG4051A
20
8.64
V
OUT
1M
16
3
13
14
15
12
1
–t°
–t°
–t°
–t°
30
13.09
19.53
28.47
40.65
55.87
74.45
96.08
119.83
144.73
169.36
X0
X1
X2
X3
X4
GND
V
X
A
B
C
CC
3.01k
40
DIV SET
50
11
10
9
60
70
80
90
100
110
120
6
5
ENABLE X5
7
2
V
X6
X7
EE
8
4
GND
2887 F20
Figure 20. 16-Channel Isolated Temperature to Frequency Converter
2887fb
29
For more information www.linear.com/LTM2887
LTM2887
TYPICAL APPLICATIONS
IRF7509
LTM2887-5S
B8
100k
L8
K8
L7
K7
L6
K6
SWITCHED 3.3V
V
AV
IV
5V
V
V
CC2
CC2
CC2
CC
A8
L
1.15k
1.15k
27.4k
IV
L2
L2
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
6.04k
ON
AV
SDOE
CS
L2
L5
L4
L3
L2
L1
K1
K2
CS2
SDI2
SCK2
I2
SDI
3.3V ENABLE
5V ENABLE
IRF7509
SCK
DO2
SDO
DO1
GND
100k
SDO2
I1
SWITCHED 5V
3.3V UV
5V UV
GND2
51.1k
LTC2902
COMP2
COMP1 COMP4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
COMP3
0.1µF
V3
V2
V4
V1
10k
CRT
RST
T0
V
REF
V
93.1k
PG
GND
T1
RDIS
9.53k
2887 F21
Figure 21. Digitally Switched Dual Power Supply with Undervoltage Monitor
2887fb
30
For more information www.linear.com/LTM2887
LTM2887
TYPICAL APPLICATIONS
LTM2887-3S
B8
A8
L8
K8
L7
K7
L6
K6
V
AV
IV
3.3V
V
V
CC2
CC2
CC2
CC
L
1µF
LTC2654-H16
IV
L2
L2
A7
A6
A5
A4
A3
A2
A1
B1
B2
15
6
5
V
REFOUT
V
CC
ON
3
AV
SDOE
CS
LDAC
CS
REFC
L2
V
CC
L5
L4
L3
L2
L1
K1
K2
7
2
CS2
SDI2
SCK2
I2
0V TO 4.096V OUTA
CS
V
OUTA
OUTB
OUTC
OUTD
9
4
MOSI
SCK
SDI
SDI
V
V
0V TO 4.096V OUTB
0V TO 4.096V OUTC
0V TO 4.096V OUTD
8
13
14
1
SCK
DO2
SDO
DO1
GND
SCK
CLR
SDO
µC
11
10
12
V
MISO
SDO2
I1
REFLO
0.1µF
0.1µF
4
GND
PORSEL GND
GND2
2887 F22
Figure 22. Quad 16-Bit 0 to 4.096V Output Range DAC
LTM2887-5S
B8
A8
L8
K8
L7
K7
L6
K6
5V
V
AV
IV
5V@200mA
V
V
CC2
CC2
CC2
CC
L
IV
L2
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
L2
AV
SDOE
CS
L2
L5
L4
L3
L2
L1
K1
K2
CS2
SDI2
SCK2
I2
CS
SDI
CS
SDI
SDI
SCK
SCK
SCK
DO2
SDO
DO1
GND
SDO
SDO2
I1
SDO
GND2
2887 F23
Figure 23. Parallel Output Supplies for Higher Current
2887fb
31
For more information www.linear.com/LTM2887
LTM2887
TYPICAL APPLICATIONS
LTM2887-5I
B8
A8
L8
K8
L7
K7
L6
K6
L5
L4
L3
L2
L1
K1
K2
V
AV
IV
5V
V
V
CC2
CC2
CC2
CC
L
1µF
10k
10k
IV
L2
L2
L2
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
V
CC
AV
GND
DI1
O1
SDA2
SCL2
DNC
I2
Ox
SDA
SCL
1x
SDA
SCL
DNC
DO2
DO1
GND
µC
10k
GND
I1
GND2
V
EE
–48V RTN
1k, ×4 IN SERIES
1/4W EACH
453k
7
21
8
9
22
6
INTV
V
IN
FLTIN
SCL
UVL
UVH
ADIN2
OV
CC
16.9k
10
11
19
20
26
1
5
SDAI
SDAO
ALERT
ON
4
3
SS
2
LTC4261CGN
TMR
EN
28
27
23
PGI
PGI0
PG
PWRGD2
PWRGD1
25
24
ADR1
ADR0
ADIN
11.8k
V
SENSE GATE DRAIN RAMP
14 15 16 18
EE
13
+
330µF
100V
1M
1k
100nF
1µF
220nF
10Ω
47nF
V
10nF
100V
OUT
0.1µF
47nF
10k
0.1µF
–48V INPUT
IRF1310NS
0.008Ω
1%
402k
V
EE
2887 F24
Figure 24. –48V, 200W Hot Swap Controller with Isolated I2C Interface
2887fb
32
For more information www.linear.com/LTM2887
LTM2887
TYPICAL APPLICATIONS
3.3V
LTM2887-3S
LTC6803-1
3.3k
3.3k
3.3k
B8
A8
L8
K8
L7
K7
L6
K6
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
3.3k
V
CSO
SDOI
SCKO
CSI
SDO
SDI
SCKI
V
V
V
CC2
CC2
CC2
CC
L
1µF
2
AV
IV
3
4
+
IV
V
L2
L2
A7
A6
A5
A4
A3
A2
A1
B1
B2
5
V
C12
S12
C11
S11
C10
S10
C9
ON
MODE
6
AV
SDOE
CS
GPIO2
GPIO1
WDT
NC
V
L2
CC
L5
L4
L3
L2
L1
K1
K2
7
1µF
1µF
CS2
SDI2
SCK2
I2
CS
8
SDI
MOSI
SCK
µC
9
SCK
DO2
SDO
DO1
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
MISO
GND
TOS
SDO2
I1
V
V
V
V
REG
100k
100k
74LVC3G07
S9
REF
GND2
C8
TEMP2
TEMP1
S8
NC
C7
–
V
S7
100k
100k
S1
C1
S2
C2
S3
C3
C6
S6
C5
S5
C4
S4
2887 F25
Figure 25. 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown
2887fb
33
For more information www.linear.com/LTM2887
LTM2887
TYPICAL APPLICATIONS
LTM2887-3I
B8
L8
K8
L7
K7
L6
K6
0.02Ω
V
AV
IV
3.3V
V
V
CC2
CC2
CC2
CC
L
48V
V
OUT
A8
1µF
10k
+
–
IV
SENSE SENSE
V
L2
L2
IN
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
SHDN
100k AT 25°C, 1%
VISHAY 2381 6154.104
10k
V
CC
AV
GND
DI1
L2
L5
L4
L3
L2
L1
K1
K2
O1
SDA2
SCL2
DNC
I2
SDA
SCL
SDA
SCL
DNC
DO2
DO1
GND
SDA
ADIN
LTC4151
µC
SCL
ADR0
ADR1
1.37k
1%
GND
I1
GND2
GND
3950
T(°C)=
−273,−40°C < T < 150°C
1000
8.965+LN
−1
N
ADIN
N
IS THE DIGITAL CODE MEASURED
ADIN
2887 F26
BY THE ADC AT THE ADIN PIN
Figure 26. Isolated I2C Voltage, Current and Temperature Power Supply Monitor
2887fb
34
For more information www.linear.com/LTM2887
LTM2887
TYPICAL APPLICATIONS
LTM2887-5I
B8
L8
K8
L7
K7
L6
K6
V
5V
V
V
CC2
CC2
CC2
CC
A8
AV
IV
L
10k
0.1µF
10k
IV
L2
L2
A7
A6
A5
A4
A3
A2
A1
B1
B2
27.4k
V
ON
SHUTDOWN
0.1µF
AV
GND
DI1
100k
L2
SHDN1 V
DD
L5
L4
L3
L2
L1
K1
K2
ENABLE
SDA
O1
SDA2
SCL2
DNC
I2
RESET
SDAIN
SCL
BYP
SDA
SCL
DNC
DO2
DO1
GND
SCLIN
SDAOUT
AUTO
INT
DETECT
1/4 LTC4266
INTERRUPT
I1
GND2
AD0
AD1
AD2
6.04k
CMPD3003
AD3
V
DGND AGND
SENSE GATE OUT
EE
Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T
FB1, FB2: TDK MPZ2012S601A
T1: PULSE H609NL OR COILCRAFT ETH1-230LD
SMAJ58A
1µF
0.25Ω
Q1
–48V
S1B
S1B
0.22µF
FB1
FB2
RJ45
CONNECTOR
T1
1
2
3
4
5
6
7
8
•
•
•
•
10nF
10nF
75Ω
75Ω
PHY
(NETWORK
PHYSICAL
LAYER
•
•
•
•
CHIP)
10nF
10nF
75Ω
75Ω
1nF
2887 F27
Figure 27. One Complete Isolated Powered Ethernet Port
2887fb
35
For more information www.linear.com/LTM2887
LTM2887
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM2887#packaging for the most recent package drawings.
/ / b b b
Z
4 . 4 4 5
3 . 1 7 5
1 . 9 0 5
0 . 6 3 5
0 . 6 3 5
0 . 0 0 0
1 . 9 0 5
3 . 1 7 5
4 . 4 4 5
a a a
Z
2887fb
36
For more information www.linear.com/LTM2887
LTM2887
REVISION HISTORY
REV
DATE
03/17 Added UL-CSA File Number
07/17 Changed MIN limit for t
DESCRIPTION
PAGE NUMBER
A
1
6
2
B
(SPI and I C)
PWU
2887fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
37
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTM2887
TYPICAL APPLICATION
Isolated Dual Channel Simultaneous Sampling Analog to Digital Converter, Input Range 0V to 2.5V
LTM2887-3S
B8
A8
L8
K8
L7
K7
L6
K6
V
3.3V
V
V
CC2
CC2
CC2
CC
L
AV
IV
1µF
1.15k
IV
L2
L2
A7
A6
A5
A4
A3
A2
A1
B1
B2
V
ON
V
CC
AV
SDOE
CS
L2
19.1k
6.04k
L5
L4
L3
L2
L1
K1
K2
LTC1407A
CS2
SDI2
SCK2
I2
Ox
10
9
1
2
3
4
5
+
–
+
–
SDI
CONV
SCK
CH0
CH0
CH0
CH0
µC
SCK
DO2
SDO
DO1
GND
SCK
8
SDO
V
REF
+
7
+
–
SDO2
I1
V
CH1
CH1
CH1
CH1
MISO
GND
DD
6
–
GND
10µF
10µF
GND2
2887 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM2881
Isolated RS485/RS422 µModule Transceiver with 20Mbps 2500V
Integrated DC/DC Converter
Isolation with Power in LGA/BGA Package
RMS
LTM2882
LTM2883
Dual Isolated RS232 µModule Transceiver with
Integrated DC/DC Converter
2500V
Isolation with Power in LGA/BGA Package
RMS
2
SPI/Digital or I C µModule Isolator with Integrated 2500V
DC/DC Converter
Isolation with Adjustable 12.5V and 5V Power in BGA Package
RMS
LTM2884
LTM2886
Isolated USB Transceiver with Power
2500V
Auto Speed Selection, 1 to 2.5W Isolated Power
RMS
2
SPI/Digital or I C µModule Isolator with Integrated 2500V
Isolation with Fixed 5V and Adjustable 5V Power in BGA
RMS
DC/DC Converter
Package
LTM2889
LTM2892
LTC®1535
LTC4310
Isolated CAN FD µModule Transceiver with Power 4Mbps 2500V
Isolation with Power in BGA Package
RMS
2
SPI/Digital or I C µModule Isolator
Isolated RS485 Transceiver
3500V
2500V
Isolation without Power in 9mm × 6.25mm BGA Package
RMS
RMS
Isolation with External Transformer Drive
2
2
Hot-Swappable I C Isolators
Bidirectional I C Communication, Low Voltage Level Shifting, 100kHz or
400kHz Operation
LTC6803-1, LTC6803-3, Multicell Battery Stack Monitor
LTC6803-2, LTC6803-4
LTC6803-1 Allows for Multiple Devices to be Daisy Chained, the LTC6803-2
Allows for Parallel Communication Battery Stack Topologies
2887fb
LT 0717 REV B • PRINTED IN USA
www.linear.com/LTM2887
38
LINEAR TECHNOLOGY CORPORATION 2016
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