LTM4601A-1_技术文档

LTM4601A/LTM4601A-1

12A DC/DC µModules

with PLL, Output Tracking

and Margining

FEATURES

DESCRIPTION

TheLTM^®4601Aisacomplete12Astep-downswitchmode

DC/DC power supply with onboard switching controller,

MOSFETs, inductor and all support components. The

μModule™ is housed in a small surface mount 15mm

× 15mm × 2.8mm LGA package. The LTM4601A LGA

package is designed with redundant mounting pads to

enhance solder-joint strength for extended temperature

cycling endurance. Operating over an input voltage range

of 4.5 to 20V, the LTM4601A supports an output voltage

range of 0.6V to 5V as well as output voltage tracking

and margining. The high efﬁciency design delivers 12A

continuouscurrent(14Apeak). Onlybulkinputandoutput

capacitors are needed to complete the design.

n

Complete Switch Mode Power Supply

n

Wide Input Voltage Range: 4.5V to 20V

n

12A DC Typical, 14A Peak Output Current

n

0.6V to 5V Output Voltage

Output Voltage Tracking and Margining

n

Redundant Mounting Pads for Enhanced Solder-

Joint Strength

n

Parallel Multiple μModules for Current Sharing

n

Differential Remote Sensing for Precision

Regulation (LTM4601A Only)

n

PLL Frequency Synchronization

n

1.5ꢀ Total DC Error

n

Current Foldback Protection (Disabled at Start-Up)

n

Pb-Free (e4) RoHS Compliant Package with Gold

The low proﬁle (2.8mm) and light weight (1.7g) package

easilymountsonthebacksideofPCboards. TheμModule

can be synchronized with an external clock for reducing

undesirable frequency harmonics and allows PolyPhase^®

operation for high load currents.

Finish Pads

n

UltraFast™ Transient Response

n

Current Mode Control

n

Up to 95% Efﬁciency at 5V , 3.3V

IN

OUT

n

Programmable Soft-Start

Anonboarddifferentialremotesenseampliﬁercanbeused

to accurately regulate an output voltage independent of

load current. The onboard remote sense ampliﬁer is not

available in the LTM4601A-1.

Output Overvoltage Protection

Enhanced (15mm × 15mm × 2.8mm) Surface Mount

LGA Package

L, LT, LTC, LTM and PolyPhase are registered trademarks of Linear Technology Corporation.

μModule and UltraFast are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners. Protected by U.S. Patents including 5481178,

5847554, 6304066, 6476589, 6580258, 6677210, 6774611.

APPLICATIONS

n

Telecom and Networking Equipment

n

Servers

TYPICAL APPLICATION

Efﬁciency and Power Loss

vs Load Current

1.5V/12A Power Supply with 4.5V to 20V Input

95

90

85

80

75

70

65

60

55

50

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

CLOCK SYNC

EFFICIENCY

5V

IN

V

IN

4.5V TO 20V

TRACK/SS CONTROL

V

PLLIN TRACK/SS

V

1.5V

12A

IN

OUT

12V

IN

PGOOD

V

OUT

100pF

V

FB

ON/OFF

RUN

COMP

INTV

DRV

MARG0

MARG1

MARGIN

CONTROL

12V

IN

C

OUT

LTM4601A

C

IN

5V

IN

V

CC

OUT_LCL

DIFFV

CC

OUT

+

MPGM

SGND PGND

V

OSNS

–

POWER LOSS

OSNS

R1

392k

f

SET

R

SET

40.2k

5% MARGIN

0

2

4

6

8

10

12

14

4601A TA01a

LOAD CURRENT (A)

4601A TA01b

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1

LTM4601A/LTM4601A-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

(See Table 5. Pin Assignment)

INTV , DRV , V

, V

(V

≤ 3.3V with

CC

CC OUT_LCL OUT OUT

TOP VIEW

DIFFV ).....................................................–0.3V to 6V

OUT

PLLIN, TRACK/SS, MPGM, MARG0, MARG1,

PGOOD, f ..............................–0.3V to INTV + 0.3V

SET

CC

V

f

SET

MARG0

RUN .............................................................–0.3V to 5V

IN

MTP1

V , COMP................................................–0.3V to 2.7V

FB

MARG1

DRV

CC

INTV

CC

MTP2

MTP3

V .............................................................–0.3V to 20V

IN

OSNS

+

–

V

FB

V

, V

..........................–0.3V to INTV + 0.3V

OSNS CC

PGND

PGOOD

Operating Temperature Range (Note 2)....–40°C to 85°C

Junction Temperature ........................................... 125°C

Storage Temperature Range...................–55°C to 125°C

SGND

+

V

/NC2*

OSNS

DIFFV /NC3*

OUT

V

OUT

V

OUT_LCL

–

/NC1*

OSNS

LGA PACKAGE

133-LEAD (15mm × 15mm × 2.8mm)

= 125°C, θ = 15°C/W, θ = 6°C/W,

T

JMAX

JA

JC

θ

DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS

JA

WEIGHT = 1.7g

*LTM4601A-1 ONLY

ORDER INFORMATION

LEAD FREE FINISH

LTM4601AEV#PBF

LTM4601AIV#PBF

TRAY

PART MARKING*

LTM4601AV

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 85°C

LTM4601AEV#PBF

LTM4601AIV#PBF

133-Lead (15mm × 15mm × 2.8mm) LGA

LTM4601AV

–40°C to 85°C

LTM4601AEV-1#PBF LTM4601AEV-1#PBF

LTM4601AIV-1#PBF LTM4601AIV-1#PBF

LTM4601AV-1

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

ELECTRICAL CHARACTERISTICS

The ^ldenotes the speciﬁcations which apply over the –40°C to 85°C

temperature range, otherwise speciﬁcations are at T_A= 25°C, V_IN= 12V. Per typical application (front page) conﬁguration.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Input DC Voltage

4.5

20

V

IN(DC)

Output Voltage, Total Variation with

Line and Load

C

= 10μF ×3, C

IN

= 200μF, R = 40.2k

OUT SET

OUT(DC)

IN

1.478

1.5

3.2

1.522

4

V

= 5V to 20V, I

= 0A to 12A (Note 5)

OUT

Input Speciﬁcations

V

Undervoltage Lockout Threshold

Input Inrush Current at Startup

I

= 0A

IN(UVLO)

OUT

I

= 0A. V

= 1.5V

OUT

INRUSH(VIN)

OUT

V

= 5V

0.6

0.7

A

IN

V

= 12V

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2

LTM4601A/LTM4601A-1

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the –40°C to 85°C

temperature range, otherwise speciﬁcations are at T_A= 25°C, V_IN= 12V. Per typical application (front page) conﬁguration.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Input Supply Bias Current

V

= 12V, No Switching

3.8

38

mA

μA

Q(VIN,NOLOAD)

IN

= 12V, V

= 1.5V, Switching Continuous

OUT

= 5V, No Switching

= 5V, V = 1.5V, Switching Continuous

2.5

42

OUT

Shutdown, RUN = 0, V = 12V

22

IN

I

Input Supply Current

V

= 12V, V

= 1.5V, I

= 3.3V, I

= 12A

1.81

3.63

4.29

A

S(VIN)

IN

OUT

= 5V, V

= 1.5V, I

= 12A

OUT

INTV

V

= 12V, RUN > 2V

IN

No Load

4.7

0

5

5.3

V

CC

Output Speciﬁcations

I

Output Continuous Current Range

Line Regulation Accuracy

V

= 12V, V = 1.5V (Note 5)

OUT

12

A

OUTDC

IN

l

= 1.5V, I

= 0A, V from 4.5V to 20V

0.3

%

ΔV

OUT(LINE)

OUT

IN

V

OUT

OUT(LOAD)

Load Regulation Accuracy

Output Ripple Voltage

V

= 1.5V, 0A to 12A (Note 5)

IN

ΔV

OUT

V

= 12V, with Remote Sense Ampliﬁer

= 12V (LTM4601A-1)

l

0.25

1

%

V

OUT

V

I

= 0A, C

= 2×, 100μF X5R Ceramic

OUT

OUT(AC)

OUT

20

18

mV

V

= 12V, V

= 1.5V

OUT

P-P

IN

= 5V, V

= 1.5V

OUT

f

Output Ripple Voltage Frequency

I

= 5A, V = 12V, V = 1.5V

OUT

850

kHz

S

OUT

IN

Turn-On Overshoot,

TRACK/SS = 10nF

C

= 200μF, V

= 12V

= 1.5V, I

= 0A

ΔV

OUT

OUT(START)

V

IN

V

IN

20

mV

= 5V

t

Turn-On Time, TRACK/SS = Open

C

Load

= 200μF, V

OUT

= 1A Resisitive

START

OUT

V

IN

V

IN

= 12V

= 5V

0.5

ms

ΔV

OUTLS

Peak Deviation for Dynamic Load

Load: 0% to 50% to 0% of Full Load,

= 2 × 22μF Ceramic, 470μF4V Sanyo

C

OUT

POSCAP

V

IN

V

IN

= 12V

= 5V

35

mV

t

I

Settling Time for Dynamic Load Step Load: 0% to 50%, or 50% to 0% of Full Load

SETTLE

V

= 12V

25

μs

IN

Output Current Limit

C

= 200μF, Table 2

OUTPK

OUT

V

IN

V

IN

= 12V, V

= 1.5V

17

A

OUT

= 5V, V

= 1.5V

OUT

Remote Sense Amp (Note 3) (LTM4601A Only, Not Supported in the LTM4601A-1)

+

–

V

, V

Common Mode Input Voltage Range

V

= 12V, RUN > 2V

0

INTV – 1

V

OSNS

IN

CC

CM Range

DIFFV Range Output Voltage Range

V

= 12V, DIFF OUT Load = 100k

INTV

V

mV

OUT

IN

CC

V

Input Offset Voltage Magnitude

1.25

OS

A

Differential Gain

1

3

V/V

V

GBP

Gain-Bandwidth Product

MHz

4601afb

3

LTM4601A/LTM4601A-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the –40°C to 85°C

temperature range, otherwise speciﬁcations are at T_A= 25°C, V_IN= 12V. Per typical application (front page) conﬁguration.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

2

MAX

UNITS

V/μs

kΩ

SR

Slew Rate

+

R

IN

Input Resistance

Common Mode Rejection Mode

V

to GND

20

OSNS

CMRR

100

dB

Control Stage

l

V

Error Ampliﬁer Input Voltage

Accuracy

I

= 0A, V

= 1.5V

0.594

0.6

0.606

V

FB

OUT

V

RUN Pin On/Off Threshold

Soft-Start Charging Current

Minimum On-Time

1

1.5

–1.5

50

1.9

–2

V

μA

ns

kΩ

mA

kΩ

V

RUN

I

t

V

= 0V

–1

SS/TRACK

ON(MIN)

OFF(MIN)

SS/TRACK

(Note 4)

100

400

Minimum Off-Time

250

50

R

PLLIN Input Resistance

PLLIN

I

Current into DRV Pin

V

= 1.5V, I

= 1A, DRV = 5V

18

25

DRVCC

CC

OUT

CC

R

Resistor Between V

and V

FB

60.098

60.4

1.18

1.4

60.702

FBHI

OUT_LCL

V

Margin Reference Voltage

MPGM

, V

MARG0, MARG1 Voltage Thresholds

V

MARG0 MARG1

PGOOD Output

PGOOD Upper Threshold

PGOOD Lower Threshold

PGOOD Hysteresis

V

Rising

7

10

–10

1.5

13

%

V

ΔV

FB

FBH

Falling

–7

–13

ΔV

FBL

FB

Returning

ΔV

FB(HYS)

FB

V

PGL

PGOOD Low Voltage

I

= 5mA

0.15

0.4

PGOOD

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTM4601AE/LTM4601AE-1 are guaranteed to meet

performance speciﬁcations from 0°C to 85°C. Speciﬁcations over the

–40°C to 85°C operating temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTM4601AI/LTM4601AI-1 are guaranteed and tested over the –40°C to

85°C temperature range.

Note 3: Remote sense ampliﬁer recommended for ≤3.3V output.

Note 4: 100% tested at wafer level only.

Note 5: See Output Current Derating curves for different V , V

and T .

IN OUT

A

4601afb

4

LTM4601A/LTM4601A-1

TYPICAL PERFORMANCE CHARACTERISTICS

(See Figure 18 for all curves)

Efﬁciency vs Load Current

with 20V_IN

Efﬁciency vs Load Current

with 5V_IN

Efﬁciency vs Load Current

with 12V_IN

100

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

0.6V

1.2V

1.5V

2.5V

3.3V

5V

OUT

0.6V

1.2V

1.5V

2.5V

3.3V

65

60

55

50

1.2V

1.5V

2.5V

3.3V

5.0V

OUT

5

10

LOAD CURRENT (A)

15

0

5

15

10

5

LOAD CURRENT (A)

15

0

LOAD CURRENT (A)

4601A G01

4601A G02

4601A G03

1.2V Transient Response

1.5V Transient Response

1.8V Transient Response

V

OUT

50mV/DIV

V

OUT

50mV/DIV

I

OUT

I

OUT

5A/DIV

4601A G05

4601A G04

4601A G06

20μs/DIV

1.5V AT 6A/μs LOAD STEP

1.2V AT 6A/μs LOAD STEP

1.8V AT 6A/μs LOAD STEP

C

OUT

= 3 • 22μF 6.3V CERAMICS

C

OUT

= 3 • 22μF 6.3V CERAMICS

C

OUT

= 3 • 22μF 6.3V CERAMICS

470μF 4V SANYO POSCAP

C3 = 100pF

470μF 4V SANYO POSCAP

C3 = 100pF

470μF 4V SANYO POSCAP

C3 = 100pF

2.5V Transient Response

3.3V Transient Response

V

OUT

V

OUT

50mV/DIV

I

OUT

5A/DIV

4601A G08

4601A G07

20μs/DIV

3.3V AT 6A/μs LOAD STEP

2.5V AT 6A/μs LOAD STEP

C

OUT

= 3 • 22μF 6.3V CERAMICS

C

OUT

= 3 • 22μF 6.3V CERAMICS

470μF 4V SANYO POSCAP

C3 = 100pF

470μF 4V SANYO POSCAP

C3 = 100pF

4601afb

5

LTM4601A/LTM4601A-1

TYPICAL PERFORMANCE CHARACTERISTICS _{(See Figure 18 for all curves)}

Start-Up, I_OUT= 12A

(Resistive Load)

Start-Up, I_OUT= 0A

V

OUT

0.5V/DIV

I

IN

I

IN

1A/DIV

0.5A/DIV

4601A G09

4601A G10

5ms/DIV

2ms/DIV

V

C

= 12V

V

C

= 12V

IN

= 1.5V

OUT

= 470μF

3 s 22μF

SOFT-START = 10nF

V_INto V_OUTStep-Down Ratio

Track, I_OUT= 12A

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.3V OUTPUT WITH

130k ADDED FROM

TRACK/SS

0.5V/DIV

V

TO f

OUT

SET

V

5V OUTPUT WITH

100k RESISTOR

FB

0.5V/DIV

ADDED FROM f

TO GND

SET

V

OUT

1V/DIV

5V OUTPUT WITH

NO RESISTOR ADDED

FROM f

TO GND

SET

4601A G12

2ms/DIV

2.5V OUTPUT

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

V

C

= 12V

IN

= 1.5V

OUT

= 470μF

3 s 22μF

SOFT-START = 10nF

0

2

4

6

8

10 12 14 16 18 20

INPUT VOLTAGE (V)

4601A G11

Short-Circuit Protection, I_OUT= 0A

Short-Circuit Protection, I_OUT= 12A

V

OUT

0.5V/DIV

I

IN

1A/DIV

4601A G13

4601A G14

50μs/DIV

V

C

= 12V

V

C

= 12V

IN

= 1.5V

OUT

= 470μF

3 s 22μF

SOFT-START = 10nF

4601afb

6

LTM4601A/LTM4601A-1

PIN FUNCTIONS

(See Package Description for Pin Assignment)

V (Bank 1): Power Input Pins. Apply input voltage be- INTV (Pin A7, D9): This pin is for additional decoupling

IN

CC

tween these pins and PGND pins. Recommend placing of the 5V internal regulator. These pins are internally

input decoupling capacitance directly between V pins connected. Pin A7 is a test pin.

IN

and PGND pins.

PLLIN (Pin A8): External Clock Synchronization Input to

V

(Bank 3): Power Output Pins. Apply output load the Phase Detector. This pin is internally terminated to

OUT

between these pins and PGND pins. Recommend placing SGND with a 50k resistor. Apply a clock above 2V and

outputdecouplingcapacitancedirectlybetweenthesepins below INTV . See Applications Information.

CC

and PGND pins. Review the ﬁgure below.

TRACK/SS (Pin A9): Output Voltage Tracking and Soft-

PGND (Bank 2): Power ground pins for both input and Start Pin. When the module is conﬁgured as a master

output returns.

output, then a soft-start capacitor is placed on this pin

to ground to control the master ramp rate. A soft-start

capacitor can be used for soft-start turn on as a stand

alone regulator. Slave operation is performed by putting

a resistor divider from the master output to the ground,

and connecting the center point of the divider to this pin.

See Applications Information.

–

V

(PinM12):(–)InputtotheRemoteSenseAmpliﬁer.

OSNS

This pin connects to the ground remote sense point. The

remote sense ampliﬁer is used for V ≤3.3V.

OUT

NC1 (Pin M12): No Connect On the LTM4601A-1.

+

V

(PinJ12):(+)InputtotheRemoteSenseAmpliﬁer.

OSNS

This pin connects to the output remote sense point. The

MPGM (Pins A12, B11): Programmable Margining Input.

A resistor from this pin to ground sets a current that is

equal to 1.18V/R. This current multiplied by 10kΩ will

equal a value in millivolts that is a percentage of the 0.6V

referencevoltage.SeeApplicationsInformation.Toparallel

LTM4601As, each requires an individual MPGM resistor.

Do not tie MPGM pins together. Both pins are internally

connected. Pin A12 is a test pin.

remote sense ampliﬁer is used for V ≤3.3V.

OUT

NC2 (Pin J12): No Connect On the LTM4601A-1.

DIFFV (Pin K12): Output of the Remote Sense Ampli-

ﬁer. This pin connects to the V

OUT

pin.

OUT_LCL

NC3 (Pin K12): No Connect On the LTM4601A-1.

DRV (Pin E12): This pin normally connects to INTV

CC

for powering the internal MOSFET drivers. This pin can

be biased up to 6V from an external supply with about

50mA capability, or an external circuit shown in Figure 16.

This improves efﬁciency at the higher input voltages by

reducing power dissipation in the module.

f

(Pins B12, C11): Frequency Set Internally to 850kHz.

SET

An external resistor can be placed from this pin to ground

to increase frequency. This pin can be decoupled with a

1000pF capacitor. See Applications Information for fre-

quency adjustment. Both pins are internally connected.

Pin B12 is a test pin.

TOP VIEW

V

(Pin F12): The Negative Input of the Error Ampliﬁer.

FB

Internally, this pin is connected to V

pin with a

OUT_LCL

A

60.4k precision resistor. Different output voltages can be

V

B

C

D

E

f

SET

MARG0

IN

MTP1

BANK 1

programmed with an additional resistor between V and

FB

MARG1

DRV

CC

V

FB

PGOOD

SGND pins. See Applications Information.

INTV

CC

MTP2

MTP3

F

MARG0 (Pin C12): This pin is the LSB logic input for the

margining function. Together with the MARG1 pin will

determine if margin high, margin low or no margin state

is applied. The pin has an internal pull-down resistor of

50k. See Applications Information.

PGND

BANK 2

G

H

J

SGND

+

V

OSNS

/NC2*

DIFFV /NC3*

OUT

K

L

M

V

OUT

V

OUT_LCL

BANK 3

–

V

/NC1*

OSNS

1

2

3

4

5

6

7

8 9 10 11 12

*LTM4601A-1 ONLY

4601afb

7

LTM4601A/LTM4601A-1

PIN FUNCTIONS

(See Package Description for Pin Assignment)

MARG1 (Pin D12): This pin is the MSB logic input for the

margining function. Together with the MARG0 pin will

determine if margin high, margin low or no margin state

is applied. The pin has an internal pull-down resistor of

50k. See Applications Information.

RUN (Pin A10): Run Control Pin. A voltage above 1.9V

will turn on the module, and when below 1V, will turn off

the module. A programmable UVLO function can be ac-

complished with a resistor from V to this pin that has a

IN

5.1V zener to ground. Maximum pin voltage is 5V. Limit

current into the RUN pin to less than 1mA.

SGND (Pins H12, H11, G11): Signal Ground. These pins

connect to PGND at output capacitor point. See Figure 15.

V

(Pin L12): V

connects directly to this pin

OUT_LCL

OUT

to bypass the remote sense ampliﬁer, or DIFFV

con-

OUT

COMP (Pin A11): Current Control Threshold and Error

Ampliﬁer Compensation Point. The current comparator

threshold increases with this control voltage. The voltage

ranges from 0V to 2.4V with 0.7V corresponding to zero

sense voltage (zero current).

nects to this pin when remote sense ampliﬁer is used.

V

can be connected to V

is internally connected to V

on the LTM4601A-1,

OUT_LCL

OUT

with 50Ω in the

LTM4601A-1.

MTP1,MTP2,MPT3(PinsC10,D10,D11):ExtraMounting

Pads used for increased solder integrity strength. These

pads must remain ﬂoating (electrical open circuit).

PGOOD (Pins G12, F11): Output Voltage Power Good

Indicator. Open-drain logic output that is pulled to ground

when the output voltage is not within 10% of the regula-

tion point, after a 25μs power bad mask timer expires.

SIMPLIFIED BLOCK DIAGRAM

V

IN

V

OUT_LCL

V

OUT

1M

R1

>1.9V = ON

<1V = OFF

MAX = 5V

(50Ω, LTM4601A-1)

RUN

PGOOD

COMP

V

UVLO

FUNCTION

IN

4.5V TO 20V

+

5.1V

ZENER

1.5μF

C

IN

R2

60.4k

INTERNAL

COMP

POWER CONTROL

Q1

Q2

SGND

V

1.5V

12A

OUT

MARG1

MARG0

22μF

V

FB

50k 50k

+

f

SET

R

SET

40.2k

C

OUT

39.2k

PGND

MPGM

TRACK/SS

PLLIN

INTV

CC

10k

–

10k

C

V

SS

OSNS

NOT INCLUDED

–

+

IN THE LTM4601A-1

+

10k

50k

4.7μF

OSNS

–

+

V

= NC1

= NC2

= NC3

OSNS

INTV

DRV

CC

10k

DIFFV

OUT

CC

DIFFV

OUT

4601A F01

Figure 1. Simpliﬁed LTM4601A/LTM4601A-1 Block Diagram

4601afb

8

LTM4601A/LTM4601A-1

DECOUPLING REQUIREMENTS

T_A= 25°C, V_IN= 12V. Use Figure 1 conﬁguration.

SYMBOL

PARAMETER

CONDITIONS MIN

TYP

MAX

UNITS

C

External Input Capacitor Requirement

20

30

μF

I

= 12A, 3× 10μF Ceramics

IN

OUT

(V = 4.5V to 20V, V

= 1.5V)

IN

OUT

C

External Output Capacitor Requirement

(V = 4.5V to 20V, V = 1.5V)

I

= 12A

100

200

μF

OUT

IN

OUT

OPERATION

Power Module Description

and bottom FET Q2 is turned on and held on until the

overvoltage condition clears.

TheLTM4601Aisastandalonenonisolatedswitchingmode

DC/DC power supply. It can deliver up to 12A of DC output

current with few external input and output capacitors.

This module provides precisely regulated output voltage

Pulling the RUN pin below 1V forces the controller into its

shutdown state, turning off both Q1 and Q2. At low load

current, the module works in continuous current mode by

default to achieve minimum output voltage ripple.

programmable via one external resistor from 0.6V to

DC

5.0V over a 4.5V to 20V wide input voltage. The typical

DC

When DRV pin is connected to INTV an integrated

CC

application schematic is shown in Figure 18.

5V linear regulator powers the internal gate drivers. If a

TheLTM4601Ahasanintegratedconstanton-timecurrent

5V external bias supply is applied on the DRV pin, then

CC

mode regulator, ultralow R

FETs with fast switch-

an efﬁciency improvement will occur due to the reduced

powerlossintheinternallinearregulator.Thisisespecially

true at the higher input voltage range.

DS(ON)

ing speed and integrated Schottky diodes. The typical

switching frequency is 850kHz at full load. With current

mode control and internal feedback loop compensation,

theLTM4601Amodulehassufﬁcientstabilitymarginsand

good transient performance under a wide range of operat-

ing conditions and with a wide range of output capacitors,

even all ceramic output capacitors.

The LTM4601A has a very accurate differential remote

sense ampliﬁer with very low offset. This provides for

very accurate remote sense voltage measurement. The

MPGM pin, MARG0 pin and MARG1 pin are used to sup-

port voltage margining, where the percentage of margin

is programmed by the MPGM pin, and the MARG0 and

MARG1 select margining.

Currentmodecontrolprovidescycle-by-cyclefastcurrent

limit. Besides, foldback current limiting is provided in an

overcurrentconditionwhileV drops.Internalovervoltage

andundervoltagecomparatorspulltheopen-drainPGOOD

output low if the output feedback voltage exits a 10%

window around the regulation point. Furthermore, in an

overvoltage condition, internal top FET Q1 is turned off

FB

The PLLIN pin provides frequency synchronization of the

device to an external clock. The TRACK/SS pin is used for

power supply tracking and soft-start programming.

4601afb

9

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

The typical LTM4601A application circuit is shown in

Figure 18. External component selection is primarily

determined by the maximum load current and output

voltage. Refer to Table 2 for speciﬁc external capacitor

requirements for a particular application.

The MPGM pin programs a current that when multiplied

by an internal 10k resistor sets up the 0.6V reference

offset for margining. A 1.18V reference divided by the

RPGM resistor on the MPGM pin programs the current.

Calculate V

:

OUT(MARGIN)

V to V

Step-Down Ratios

IN

OUT

%V_OUT

100

V_OUT(MARGIN)

=

• V_OUT

There are restrictions in the maximum V and V

step

IN

OUT

down ratio that can be achieved for a given input voltage.

where%V isthepercentageofV youwanttomargin,

OUT

These constraints are shown in the Typical Performance

and V

is the margin quantity in volts:

OUT(MARGIN)

Characteristics curves labeled “V to V

Step-Down

OUT

IN

Ratio”.Notethatadditionalthermalderatingmayapply.See

the Thermal Considerations and Output Current Derating

section of this data sheet.

V_OUT

1.18V

•10k

R_PGM

=

•

0.6V V_OUT(MARGIN)

where R

is the resistor value to place on the MPGM

PGM

Output Voltage Programming and Margining

pin to ground.

ThePWMcontrollerhasaninternal0.6Vreferencevoltage.

As shown in the Block Diagram, a 1M and a 60.4k 0.5%

The output margining will be margining of the value.

This is controlled by the MARG0 and MARG1 pins. See

the truth table below:

internal feedback resistor connects V

and V pins

OUT

FB

together. The V

pin is connected between the 1M

OUT_LCL

MARG1

LOW

MARG0

LOW

MODE

and the 60.4k resistor. The 1M resistor is used to protect

against an output overvoltage condition if the V

NO MARGIN

MARGIN UP

MARGIN DOWN

NO MARGIN

OUT_LCL

LOW

HIGH

LOW

pin is not connected to the output, or if the remote sense

HIGH

ampliﬁer output is not connected to V . The output

OUT_LCL

HIGH

voltagewilldefaultto0.6V. AddingaresistorR fromthe

SET

V

FB

pin to SGND pin programs the output voltage:

Input Capacitors

60.4k +R_SET

LTM4601A module should be connected to a low AC

impedance DC source. Input capacitors are required to

be placed adjacent to the module. In Figure 18, the 10μF

ceramic input capacitors are selected for their ability to

handle the large RMS current into the converter. An input

bulkcapacitorof100μFisoptional.This100μFcapacitoris

onlyneedediftheinputsourceimpedanceiscompromised

by long inductive leads or traces.

V

_OUT= 0.6V

R_SET

Table 1. R_SETStandard 1ꢀ Resistor Values vs V_OUT

R

SET

(kΩ)

Open 60.4

0.6 1.2

40.2

1.5

30.1

1.8

25.5

2

19.1

2.5

13.3

3.3

8.25

5

V

OUT

(V)

4601afb

10

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

For a buck converter, the switching duty-cycle can be

estimated as:

the corresponding duty cycle and the number of phases to

arrive at the correct ripple current value. For example, the

2-phase parallel LTM4601A design provides 24A at 2.5V

output from a 12V input. The duty cycle is DC = 2.5V/12V

= 0.21. The 2-phase curve has a ratio of ~0.25 for a duty

cycle of 0.21. This 0.25 ratio of RMS ripple current to a

DC load current of 24A equals ~6A of input RMS ripple

current for the external input capacitors.

V_OUT

D=

V

IN

Without considering the inductor current ripple, the RMS

current of the input capacitor can be estimated as:

I_OUT(MAX)

I_CIN(RMS)

=

• D• 1–D

(

)

Output Capacitors

ꢀ%

The LTM4601A is designed for low output voltage ripple.

In the above equation, η% is the estimated efﬁciency of

The bulk output capacitors deﬁned as C

are chosen

OUT

the power module. C can be a switcher-rated electrolytic

IN

with low enough effective series resistance (ESR) to meet

theoutputvoltagerippleandtransientrequirements. C

aluminum capacitor, OS-CON capacitor or high volume

ceramic capacitor. Note the capacitor ripple current rat-

ings are often based on temperature and hours of life. This

makes it advisable to properly derate the input capacitor,

or choose a capacitor rated at a higher temperature than

required. Always contact the capacitor manufacturer for

derating requirements.

OUT

can be a low ESR tantalum capacitor, a low ESR polymer

capacitororaceramiccapacitor. Thetypicalcapacitanceis

200μF if all ceramic output capacitors are used. Additional

output ﬁltering may be required by the system designer,

if further reduction of output ripple or dynamic transient

spikeisrequired.Table2showsamatrixofdifferentoutput

voltages and output capacitors to minimize the voltage

droop and overshoot during a 5A/μs transient. The table

optimizes total equivalent ESR and total bulk capacitance

to maximize transient performance.

In Figure 18, the 10μF ceramic capacitors are together

used as a high frequency input decoupling capacitor. In a

typical 12A output application, three very low ESR, X5R or

X7R, 10μF ceramic capacitors are recommended. These

decoupling capacitors should be placed directly adjacent

to the module input pins in the PCB layout to minimize

the trace inductance and high frequency AC noise. Each

10μF ceramic is typically good for 2A to 3A of RMS ripple

current. Refer to your ceramics capacitor catalog for the

RMS current ratings.

0.6

0.5

1-PHASE

2-PHASE

0.4

3-PHASE

4-PHASE

6-PHASE

0.3

12-PHASE

Multiphase operation with multiple LTM4601A devices in

parallelwilllowertheeffectiveinputRMSripplecurrentdue

to the interleaving operation of the regulators. Application

Note 77 provides a detailed explanation. Refer to Figure 2

for the input capacitor ripple current requirement as a

function of the number of phases. The ﬁgure provides a

ratio of RMS ripple current to DC load current as function

of duty cycle and the number of paralleled phases. Pick

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

4601A F02

Figure 2. Normalized Input RMS Ripple Current

vs Duty Factor for One to Six Modules (Phases)

4601afb

11

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

Multiphase operation with multiple LTM4601A devices

in parallel will lower the effective output ripple current

due to the interleaving operation of the regulators. For

example, each LTM4601A’s inductor current of a 12V to

2.5V multiphase design can be read from the Inductor

Ripple Current vs Duty Cycle graph (Figure 3). The large

ripple current at low duty cycle and high output voltage

can be reduced by adding an external resistor from f to

SET

ground which increases the frequency. If the duty cycle is

DC = 2.5V/12V = 0.21, the inductor ripple current for 2.5V

output at 21% duty cycle is ~6A in Figure 3.

Figure 4 provides a ratio of peak-to-peak output ripple cur-

rent to the inductor current as a function of duty cycle and

the number of paralleled phases. Pick the corresponding

dutycycleandthenumberofphasestoarriveatthecorrect

output ripple current ratio value. If a 2-phase operation is

chosen at a duty cycle of 21%, then 0.6 is the ratio. This

0.6 ratio of output ripple current to inductor ripple of 6A

equals 3.6A of effective output ripple current. Refer to Ap-

plicationNote77foradetailedexplanationofoutputripple

current reduction as a function of paralleled phases.

12

2.5V OUTPUT

10

5V OUTPUT

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

8

6

3.3V OUTPUT WITH

130k ADDED FROM

V

TO f

OUT

SET

4

2

0

5V OUTPUT WITH

100k ADDED FROM

The output voltage ripple has two components that are

related to the amount of bulk capacitance and effective

series resistance (ESR) of the output bulk capacitance.

Therefore, the output voltage ripple can be calculated with

the known effective output ripple current. The equation:

f

TO GND

SET

0

20

40

60

80

DUTY CYCLE (V /V

)

OUT IN

4601A F03

Figure 3. Inductor Ripple Current vs Duty Cycle

ΔV

≈ (ΔI /(8 • f • m • C ) + ESR • ΔI ), where f

OUT(P-P)

L OUT L

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY CYCLE (V /V

)

IN

O

4601A F04

Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = V_OT/L_I, Dlr = Each Phase’s Inductor Current

4601afb

12

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

is frequency and m is the number of parallel phases. This

calculation process can be easily fulﬁlled using our Linear

Technology μModule Design Tool.

downwithanotherregulator.Themasterregulator’soutput

is divided down with an external resistor divider that is the

same as the slave regulator’s feedback divider. Figure 5

shows an example of coincident tracking. Ratiometric

modes of tracking can be achieved by selecting different

resistor values to change the output tracking ratio. The

master output must be greater than the slave output for

the tracking to work. Figure 6 shows the coincident output

tracking characteristics.

Fault Conditions: Current Limit and Overcurrent

Foldback

LTM4601A has a current mode controller, which inher-

ently limits the cycle-by-cycle inductor current not only

in steady-state operation, but also in transient.

MASTER

OUTPUT

Tofurtherlimitcurrentintheeventofanoverloadcondition,

the LTM4601A provides foldback current limiting. If the

output voltage falls by more than 50%, then the maximum

output current is progressively lowered to about one sixth

of its full current limit value.

R2

60.4k

TRACK CONTROL

V

IN

R1

40.2k

100k

V

PLLIN TRACK/SS

IN

SLAVE OUTPUT

PGOOD

V

OUT

Soft-Start and Tracking

MPGM

RUN

COMP

V

C

OUT

FB

MARG0

MARG1

V

OUT_LCL

The TRACK/SS pin provides a means to either soft-start

the regulator or track it to a different power supply. A

capacitor on this pin will program the ramp rate of the

output voltage. A 1.5μA current source will charge up the

external soft-start capacitor to 80% of the 0.6V internal

voltagereferenceminusanymargindelta.Thiswillcontrol

the ramp of the internal reference and the output voltage.

The total soft-start time can be calculated as:

LTM4601A

C

IN

INTV

CC

DRV

DIFFV

V

CC

OUT

+

OSNS

–

OSNS

f

SGND PGND

SET

R

SET

40.2k

4601A F05

Figure 5. Coincident Tracking

C_SS

1.5μA

t_SOFTSTARTꢀ0.8 • 0.6V – V

•

ꢁ

_OUT(MARGIN)ꢂ

WhentheRUNpinfallsbelow1.5V, thentheSSpinisreset

to allow for proper soft-start control when the regulator

is enabled again. Current foldback and force continuous

mode are disabled during the soft-start process. The

soft-start function can also be used to control the output

ramp up time, so that another regulator can be easily

tracked to it.

MASTER OUTPUT

SLAVE OUTPUT

OUTPUT

VOLTAGE

Output Voltage Tracking

4601A F06

TIME

Output voltage tracking can be programmed externally

usingtheTRACK/SSpin. Theoutputcanbetrackedupand

Figure 6. Coincident Output Tracking Characteristics

4601afb

13

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

Run Enable

through the LDO is about 20mA. The internal LDO power

dissipation can be calculated as:

The RUN pin is used to enable the power module. The

pin has an internal 5.1V zener to ground. The pin can be

driven with a logic input not to exceed 5V.

P

= 20mA • (V – 5V)

IN

LDO_LOSS

The LTM4601A also provides the external gate driver

The RUN pin can also be used as an undervoltage lockout

(UVLO) function by connecting a resistor divider from the

input supply to the RUN pin:

voltage pin DRV . If there is a 5V rail in the system, it is

CC

recommended to connect DRV pin to the external 5V

CC

rail. This is especially true for higher input voltages. Do

not apply more than 6V to the DRV pin. A 5V output can

CC

R1+R2

be used to power the DRV pin with an external circuit

CC

V_UVLO

=

•1.5V

R2

as shown in Figure 16.

See Figure 1, Simpliﬁed Block Diagram.

Parallel Operation of the Module

The LTM4601A device is an inherently current mode

controlled device. Parallel modules will have very good

current sharing. This will balance the thermals on the de-

sign. Figure 19 shows a schematic of the parallel design.

The voltage feedback equation changes with the variable

N as modules are paralleled:

Power Good

The PGOOD pin is an open-drain pin that can be used to

monitor valid output voltage regulation. This pin monitors

a 10% window around the regulation point and tracks

with margining.

COMP Pin

60.4k

+R_SET

N

This pin is the external compensation pin. The module

has already been internally compensated for most output

voltages. Table 2 is provided for most application require-

ments. A spice model will be provided for other control

loop optimization.

V

_OUT= 0.6V

R_SET

N is the number of paralleled modules.

Figure 19 shows an LTM4601A and an LTM4601A-1 used

in a parallel design. The 2nd LTM4601A device does

not require the remote sense ampliﬁer, therefore, the

PLLIN

LTM4601A-1 device is used. An LTM4601A device can be

The power module has a phase-locked loop comprised

of an internal voltage controlled oscillator and a phase

detector. This allows the internal top MOSFET turn-on

to be locked to the rising edge of the external clock. The

frequency range is 30% around the operating frequency

of 850kHz. A pulse detection circuit is used to detect a

clock on the PLLIN pin to turn on the phase-lock loop.

The pulse width of the clock has to be at least 400ns and

2V in amplitude. During the start-up of the regulator, the

phase-lock loop function is disabled.

+

used without the diff amp. V

can be tied to ground

OSNS

–

and the V

can be tied to INTV . DIFFV

can ﬂoat.

OSNS

CC

OUT

When using multiple LTM4601A-1 devices in parallel with

an LTM4601A, limit the number to ﬁve for a total of six

modules in parallel.

Thermal Considerations and Output Current Derating

The power loss curves in Figures 7 and 8 can be used

in coordination with the load current derating curves in

Figures 9 to 14 for calculating an approximate θ for the

modulewithvariousheatsinkingmethods.Thermalmodels

are derived from several temperature measurements at

the bench and thermal modeling analysis. Thermal Ap-

plication Note 103 provides a detailed explanation of the

analysis for the thermal models and the derating curves.

JA

INTV and DRV Connection

CC

An internal low dropout regulator produces an internal

5V supply that powers the control circuitry and DRV

for driving the internal power MOSFETs. Therefore, if the

system does not have a 5V power rail, the LTM4601A

can be directly powered by V . The gate driver current

CC

IN

4601afb

14

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

6

5

4

5.0

4.5

4.0

3.5

20V LOSS

3.0

12V LOSS

2.5

20V LOSS

3

2.0

12V LOSS

2

1.5

5V LOSS

1.0

1

0

0.5

0

4

6

8

10

12

2

0

2

6

8

10

12

4

LOAD CURRENT (A)

4601A F08

4601A F07

Figure 7. 1.5V Power Loss

Figure 8. 3.3V Power Loss

12

10

12

10

8

6

8

6

4

2

0

4

2

0

5V , 1.5V

IN

0LFM

200LFM

400LFM

5V , 1.5V

IN

0LFM

200LFM

400LFM

OUT

5V , 1.5V

IN

5V , 1.5V

IN

5V , 1.5V

IN

5V , 1.5V

IN

50

60

70

80

90

100

50

60

70

80

90

100

AMBIENT TEMPERATURE (°C)

4601A F09

4601A F10

Figure 10. BGA Heat Sink 5V_IN

Figure 9. No Heat Sink 5V_IN

4601afb

15

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

12

10

12

10

8

6

8

6

4

2

0

4

12V , 1.5V

IN

0LFM

200LFM

400LFM

12V , 1.5V

IN

0LFM

200LFM

400LFM

OUT

2

0

12V , 1.5V

IN

12V , 1.5V

IN

12V , 1.5V

IN

12V , 1.5V

IN

50

60

70

80

90

100

50

60

70

80

90

100

AMBIENT TEMPERATURE (°C)

4601A F12

4601A F11

Figure 11. No Heat Sink 12V_IN

Figure 12. BGA Heat Sink 12V_IN

12

10

12

10

8

6

8

6

4

2

0

4

2

0

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

40

60

80

100

40

60

80

100

AMBIENT TEMPERATURE (°C)

4601A F13

4601A F14

Figure 14. 12V_IN, 3.3V_OUT, BGA Heat Sink

Figure 13. 12V_IN, 3.3V_OUT, No Heat Sink

4601afb

16

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 18), 0A to 6A Load Step

TYPICAL MEASURED VALUES

C

VENDORS

PART NUMBER

C

OUT2

VENDORS

PART NUMBER

OUT1

TDK

C4532X5R0J107MZ (100μF, 6.3V)

JMK432BJ107MU-T ( 100μF, 6.3V)

JMK316BJ226ML-T501 ( 22μF, 6.3V)

SANYO POSCAP

6TPE330MIL (330μF, 6.3V)

2R5TPE470M9 (470μF, 2.5V)

4TPE470MCL (470μF, 4V)

TAIYO YUDEN

V

C

V

(V)

DROOP

(mV)

PEAK TO

RECOVERY

TIME (μs)

LOAD STEP

R

SET

OUT

IN

OUT1

OUT2

IN

(V)

1.2

1.5

1.8

2.5

3.3

5

(CERAMIC)

2 × 10μF 25V

(BULK)

(CERAMIC)

(BULK)

470μF 4V

470μF 2.5V

330μF 6.3V

NONE

C

C3

PEAK (mV)

140

70

(A/μs)

6

(kΩ)

60.4

40.2

30.1

19.1

13.3

8.25

COMP

150μF 35V

NONE

47pF

5

70

35

30

20

30

20

35

30

35

30

25

30

20

30

20

30

25

30

25

30

35

30

25

3 × 22μF 6.3V

1 × 100μF 6.3V

2 × 100μF 6.3V

4 × 100μF 6.3V

3 × 22μF 6.3V

1 × 100μF 6.3V

2 × 100μF 6.3V

4 × 100μF 6.3V

3 × 22μF 6.3V

1 × 100μF 6.3V

2 × 100μF 6.3V

4 × 100μF 6.3V

3 × 22μF 6.3V

1 × 100μF 6.3V

2 × 100μF 6.3V

4 × 100μF 6.3V

3 × 22μF 6.3V

1 × 100μF 6.3V

2 × 100μF 6.3V

4 × 100μF 6.3V

3 × 22μF 6.3V

1 × 100μF 6.3V

2 × 100μF 6.3V

4 × 100μF 6.3V

1 × 100μF 6.3V

2 × 100μF 6.3V

3 × 22μF 6.3V

4 × 100μF 6.3V

1 × 100μF 6.3V

3 × 22μF 6.3V

2 × 100μF 6.3V

4 × 100μF 6.3V

2 × 100μF 6.3V

1 × 100μF 6.3V

3 × 22μF 6.3V

4 × 100μF 6.3V

1 × 100μF 6.3V

3 × 22μF 6.3V

2 × 100μF 6.3V

4 × 100μF 6.3V

NONE 100pF

NONE 22pF

5

70

140

93

NONE 100pF

5

40

470μF 4V

470μF 2.5V

330μF 6.3V

NONE

12

5

70

140

70

35

NONE

22pF

70

140

98

NONE 100pF

49

470μF 4V

470μF 2.5V

330μF 6.3V

NONE

48

100

109

84

NONE

33pF

5

54

NONE 100pF

5

44

5

61

118

100

109

89

470μF 4V

470μF 2.5V

330μF 6.3V

NONE

12

5

48

NONE

33pF

54

NONE 100pF

44

54

108

100

90

470μF 4V

470μF 2.5V

330μF 6.3V

NONE

47pF

48

NONE 100pF

NONE 220pF

NONE NONE

NONE 100pF

NONE NONE

NONE 220pF

NONE 100pF

NONE 150pF

NONE 100pF

5

44

5

68

140

130

120

140

130

103

113

116

115

103

102

113

140

240

214

230

214

230

375

320

5

65

470μF 4V

470μF 2.5V

330μF 6.3V

NONE

12

5

60

68

65

470μF 4V

330μF 6.3V

470μF 4V

NONE

48

5

56

5

57

5

60

470μF 4V

330μF 6.3V

NONE

12

7

48

51

56

70

330μF 6.3V

470μF 4V

NONE

120

110

114

110

114

188

159

7

470μF 4V

330μF 6.3V

NONE

12

15

20

NONE

22pF

5

NONE

4601afb

17

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

Table 3. 1.5V Output at 12A

DERATING CURVE

Figures 9, 11

Figures 10, 12

V

(V)

POWER LOSS CURVE

Figure 7

AIR FLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

IN

5, 12

0

15.2

14

Figure 7

200

400

0

None

Figure 7

None

12

Figure 7

BGA Heat Sink

13.9

11.3

10.25

Figure 7

200

400

Figure 7

Table 4. 3.3V Output at 12A

DERATING CURVE

Figure 13

V

IN

(V)

POWER LOSS CURVE

Figure 8

AIR FLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

12

0

15.2

14.6

13.4

13.9

11.1

10.5

Figure 13

12

Figure 8

200

400

0

None

Figure 13

Figure 8

None

Figure 14

Figure 8

BGA Heat Sink

Figure 14

Figure 8

200

400

Figure 14

Figure 8

Heat Sink Manufacturer

Wakeﬁeld Engineering

Aavid Thermalloy

Part No: LTN20069

Phone: 603-635-2800

Phone: 603-224-9988

Part No: 375424B00034G

4601afb

18

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

• Use large PCB copper areas for high current path, in-

cluding V , PGND and V . It helps to minimize the

Tables 3 and 4 provide a summary of the equivalent θ

JA

for the noted conditions. These equivalent θ parameters

IN

OUT

JA

PCB conduction loss and thermal stress.

are correlated to the measured values, and are improved

withairﬂow. Thecasetemperatureismaintainedat100°C

or below for the derating curves. The maximum case

temperature of 100°C is to allow for a rise of about 13°C

• Place high frequency ceramic input and output capaci-

tors next to the V , PGND and V

pins to minimize

IN

OUT

high frequency noise.

to 25°C inside the μModule with a thermal resistance θ

JC

• Place a dedicated power ground layer underneath the

unit. Refer frequency synchronization source to power

ground.

from junction to case between 6°C/W to 9°C/W. This will

maintain the maximum junction temperature inside the

μModule below 125°C.

• Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

Safety Considerations

The LTM4601A modules do not provide isolation from

V

to V . There is no internal fuse. If required, a

IN

OUT

• Do not put vias directly on pads unless they are capped.

slow blow fuse with a rating twice the maximum input

current needs to be provided to protect each unit from

catastrophic failure.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to PGND underneath the unit.

Layout Checklist/Example

Figure 15 gives a good example of the recommended

layout.

The high integration of LTM4601A makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

V

IN

C

IN

CONTROL

IN

•

• • • • • •

• •

•

CONTROL

PGND

•

• •

•

• • • • • • • •

SIGNAL

GND

•

CONTROL

•_C• • • •_C• • •

OUT

V

OUT

4601A F15

Figure 15. Recommended Layout

4601afb

19

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

Frequency Adjustment

14A peak speciﬁed value. A 100k resistor is placed from

to ground, and the parallel combination of 100k and

f

SET

The LTM4601A is designed to typically operate at 850kHz

39.2k equates to 28k. The I

calculation with 28k and

fSET

across most input conditions. The f pin is normally left

SET

20V input voltage equals 238μA. This equates to a t of

ON

open or decoupled with an optional 1000pF capacitor. The

switching frequency has been optimized for maintaining

constant output ripple noise over most operating ranges.

The 850kHz switching frequency and the 400ns minimum

off time can limit operation at higher duty cycles like 5V to

3.3V, and produce excessive inductor ripple currents for

lower duty cycle applications like 20V to 5V. The 5V and

3.3V drop out curves are modiﬁed by adding an external

200ns. This will increase the switching frequency from

~886kHz to ~1.25MHz for the 20V to 5V conversion. The

minimum on time is above 100ns at 20V input. Since

the switching frequency is approximately constant over

input and output conditions, then the lower input voltage

range is limited to 10V for the 1.25MHz operation due to

the 400ns minimum off time. Equation: t = (V /V )

ON

OUT IN

• (1/Frequency) equates to a 400ns on time, and a 400ns

resistor on the f

pin to allow for lower input voltage

SET

offtime. The“V toV Step-DownRatio”curvereﬂects

IN

OUT

operation, or higher input voltage operation.

an operating range of 10V to 20V for 1.25MHz operation

with a 100k resistor to ground, and an 8V to 16V operation

Example for 5V Output

for f ﬂoating. These modiﬁcations are made to provide

SET

LTM4601A minimum on time = 100ns;

wider input voltage ranges for the 5V output designs while

limiting the inductor ripple current, and maintaining the

400ns minimum off time.

t

= ((4.8 • 10pf)/I

)

ON

fSET

LTM4601A minimum off time = 400ns; t = t – t ,

OFF

ON

where t = 1/Frequency

Example for 3.3V Output

Duty Cycle = t /t or V /V

ON

OUT IN

LTM4601A minimum on time = 100ns;

Equations for setting frequency:

t

= ((3.3 • 10pF)/I

)

ON

fSET

I

t

= (V /(3 • R )), for 20V operation, I = 170μA,

fSET

IN

fSET

LTM4601A minimum off time = 400ns;

= t – t , where t = 1/Frequency

= ((4.8 • 10pF)/I ), t = 282ns, where the internal

ON

R

fSET ON

t

OFF

ON

is 39.2k. Frequency = (V /(V • t )) = (5V/(20

fSET

OUT IN ON

Duty Cycle (DC) = t /t or V /V

ON

OUT IN

• 282ns)) ≈ 886kHz. The inductor ripple current begins

to get high at the higher input voltages due to a larger

voltage across the inductor. This is noted in the “Induc-

tor Ripple Current vs Duty Cycle” graph (Figure 3) where

Equations for setting frequency:

I

t

R

= (V /(3 • R )), for 20V operation, I

= 170μA,

fSET

IN

fSET

= ((3.3 • 10pf)/I ), t = 195ns, where the internal

ON

fSET ON

I ≈ 10A at 25% duty cycle. The inductor ripple current

L

is 39.2k. Frequency = (V /(V • t )) = (3.3V/(20

fSET

OUT IN ON

can be lowered at the higher input voltages by adding an

• 195ns)) ≈ 846kHz. The minimum on time and minimum

off time are within speciﬁcation at 195ns and 980ns. The

4.5V minimum input for converting 3.3V output will not

externalresistorfromf togroundtoincreasetheswitch-

SET

ing frequency. An 8A ripple current is chosen, and the total

peak current is equal to 1/2 of the 8A ripple current plus

the output current. The 5V output current is limited to 8A,

so the total peak current is less than 12A. This is below the

meet the minimum off-time speciﬁcation of 400ns. t

=

ON

868ns, Frequency = 850kHz, t = 315ns.

OFF

4601afb

20

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

Solution

The I

current needs to be 24μA for 540kHz operation.

fSET

A resistor can be placed from V

to f

to lower the

OUT

SET

Lower the switching frequency at lower input voltages

to allow for higher duty cycles, and meet the 400ns

minimum off time at 4.5V input voltage. The off time

should be about 500ns with 100ns guard band. The duty

effective I

current out of the f pin to 24μA. The f

fSET

SET SET

= 3.3V, therefore 130k will

pin is 4.5V/3 =1.5V and V

OUT

source 14μA into the f

node and lower the I

cur-

SET

fSET

rent to 24μA. This enables the 540kHz operation and the

4.5V to 20V input operation for down converting to 3.3V

output. The frequency will scale from 540kHz to 1.1MHz

over this input range. This provides for an effective output

current of 8A over the input range.

cycle for (3.3V/4.5) ≈ 73%. Frequency = (1 – DC)/t , or

OFF

(1–0.73)/500ns=540kHz.Theswitchingfrequencyneeds

tobeloweredto540kHzat4.5Vinput. t =DC/frequency,

ON

or1.35μs.Thef pinvoltagecomplianceis1/3ofV ,and

SET

IN

the I

current equates to 38μA with the internal 39.2k.

fSET

V

OUT

TRACK/SS CONTROL

V

IN

10V TO 20V

REVIEW TEMPERATURE

R2

R4

V

PLLIN TRACK/SS

DERATING CURVE

V

5V

8A

IN

100k 100k

OUT

PGOOD

V

OUT

C3

C6 100pF

+

MPGM

RUN

V

100μF

6.3V

SANYO POSCAP

FB

REFER TO

TABLE 2

MARG0

MARG1

COMP

INTV

DRV

LTM4601A-1

V

CC

OUT_LCL

NC3

5% MARGIN

NC1

NC2

R1

392k

1%

C1

10μF

25V

C2

10μF

25V

f

SGND PGND

SET

R

SET

8.25k

fSET

100k

MARGIN CONTROL

IMPROVE

EFFICIENCY

SOT-323

FOR r12V INPUT

CMSSH-3C

4601A F16

Figure 16. 5V at 8A Design Without Differential Ampliﬁer

4601afb

21

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

V

OUT

TRACK/SS CONTROL

V

IN

4.5V TO 16V

REVIEW TEMPERATURE

DERATING CURVE

R2

R4

V

PLLIN TRACK/SS

V

3.3V

10A

IN

100k 100k

OUT

PGOOD

V

OUT

C6 100pF

PGOOD

MPGM

RUN

V

FB

C3

MARG0

MARG1

V

OUT_LCL

+

100μF

COMP

INTV

DRV

LTM4601A

6.3V

CC

SANYO POSCAP

DIFFV

OUT

+

C2

V

OSNS

10μF

25V

s3

R1

392k

–

OSNS

R

f

fSET

SGND PGND

SET

R

SET

130k

13.3k

5% MARGIN

MARGIN CONTROL

4601A F17

Figure 17. 3.3V at 10A Design

CLOCK SYNC

C5

0.01μF

V

OUT

V

IN

4.5V TO 20V

REVIEW TEMPERATURE

DERATING CURVE

R2

100k

R4

V

PLLIN TRACK/SS

V

1.5V

12A

IN

100k

OUT

PGOOD

V

OUT

C3 100pF

+

C

OUT2

470μF

6.3V

PGOOD

MPGM

RUN

V

OUT1

FB

100μF

MARG0

MARG1

V

OUT_LCL

MARGIN

CONTROL

6.3V

ON/OFF

COMP

INTV

DRV

LTM4601A

CC

DIFFV

OUT

+

C

IN

R1

392k

V

OSNS

BULK

OPT

–

REFER TO

TABLE 2 FOR

DIFFERENT

OUTPUT

OSNS

C

IN

f

10μF

SGND PGND

SET

R

SET

25V

40.2k

s3 CER

VOLTAGE

4601A F18

5% MARGIN

Figure 18. Typical 4.5V-20V_IN, 1.5V at 12A Design

4601afb

22

LTM4601A/LTM4601A-1

APPLICATIONS INFORMATION

60.4k

+ R

SET

V

OUT

N

V

= 0.6V

OUT

R

SET

CLOCK SYNC

0o PHASE

N = NUMBER OF PHASES

TRACK/SS CONTROL

V

IN

4.5V TO 20V

R2

100k

R4

100k

V

PLLIN TRACK/SS

IN

V

OUT

1.5V

PGOOD

V

OUT

C6 220pF

24A

C3

22μF

6.3V

^C4+

470μF

6.3V

MPGM

RUN

V

FB

MARG0

MARG1

V

OUT_LCL

COMP

INTV

DRV

LTM4601A

CC

+

C5*

100μF

25V

DIFFV

V

OUT

+

C1

0.1μF

OSNS

LTC6908-1

+

REFER TO

TABLE 2

–

V

OSNS

C2

10μF

25V

s2

1

2

3

6

5

4

118k

1%

V

OUT1

R1

392k

f

SGND PGND

SET

R

SET

20k

100pF

GND OUT2

SET

MOD

5%

MARGIN

MARGIN CONTROL

2-PHASE

OSCILLATOR

CLOCK SYNC

180o PHASE

TRACK/SS CONTROL

4.5V TO 20V

C7

0.033μF

V

IN

PLLIN TRACK/SS

PGOOD

V

OUT

+

C4

470μF

6.3V

C3

22μF

6.3V

MPGM

RUN

COMP

INTV

CC

DRV

CC

V

FB

MARG0

MARG1

C8

10μF

25V

s2

LTM4601A-1

REFER TO

TABLE 2

V

OUT_LCL

NC3

NC2

NC1

392k

f

SGND PGND

SET

4601A F19

*C5 OPTIONAL TO REDUCE ANY LC RINGING.

NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTION

Figure 19. 2-Phase Parallel, 1.5V at 24A Design

4601afb

23

LTM4601A/LTM4601A-1

TYPICAL APPLICATIONS

4601afb

24

LTM4601A/LTM4601A-1

PACKAGE DESCRIPTION

Z

b b b

Z

6 . 9 8 5 0

5 . 7 1 5 0

4 . 4 4 5 0

3 . 1 7 5 0

1 . 9 0 5 0

0 . 6 3 5 0

0 . 0 0 0 0

0 . 6 3 5 0

1 . 9 0 5 0

3 . 1 7 5 0

4 . 4 4 5 0

5 . 7 1 5 0

6 . 9 8 5 0

4601afb

25

LTM4601A/LTM4601A-1

PACKAGE DESCRIPTION

Pin Assignment Table 5

(Arranged by Pin Number)

PIN NAME

E1 PGND

E2 PGND

E3 PGND

E4 PGND

E5 PGND

E6 PGND

E7 PGND

PIN NAME

F1 PGND

F2 PGND

F3 PGND

F4 PGND

F5 PGND

F6 PGND

F7 PGND

F8 PGND

F9 PGND

A1

A2

A3

A4

A5

A6

V

B1

B2

B3

B4

B5

B6

V

C1

C2

C3

C4

C5

C6

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

D1 PGND

D2 PGND

D3 PGND

D4 PGND

D5 PGND

D6 PGND

IN

A7 INTV

B7 PGND

B8

A9 TRACK/SS B9 PGND

C7 PGND

C8

D7

D8 PGND

D9 INTV

-

CC

A8 PLLIN

-

E8

-

C9 PGND

C10 MTP1

E9 PGND

CC

A10 RUN

B10

B11 MPGM

B12

-

D10 MPT2

D11 MPT3

D12 MARG1

E10

E11

-

F10

F11 PGOOD

F12

-

A11 COMP

A12 MPGM

C11 f

SET

f

C12 MARG0

E12 DRV

V

FB

SET

CC

PIN NAME

G1 PGND

G2 PGND

G3 PGND

G4 PGND

G5 PGND

G6 PGND

G7 PGND

G8 PGND

G9 PGND

PIN NAME

H1 PGND

H2 PGND

H3 PGND

H4 PGND

H5 PGND

H6 PGND

H7 PGND

H8 PGND

H9 PGND

PIN NAME

J1

V

-

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

L1

V

M1

M2

M3

M4

M5

M6

M7

M8

M9

V

OUT

OUT_LCL

OUT

OSNS

J2

L2

J3

L3

J4

L4

J5

L5

J6

L6

J7

L7

J8

L8

J9

L9

G10

-

H10

-

J10

J11

J12

L10

L11

L12

M10 V

M11 V

M12 V

G11 SGND

H11 SGND

H12 SGND

+

–

G12 PGOOD

V

K12 DIFFV

OUT

OSNS

4601afb

26

LTM4601A/LTM4601A-1

PACKAGE DESCRIPTION

Pin Assignment Table 6

(Arranged by Pin Function)

PIN NAME

PGND

PIN NAME

A1

A2

A3

A4

A5

A6

V

D1

D2

D3

D4

D5

D6

D8

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

V

A7

INTVCC

PLLIN

B7

PGND

IN

OUT

PGND

A8

B8

-

A9

TRACK/SS

RUN

B9

B10

B11

PGND

-

A10

A11

A12

COMP

MPGM

C7

PGND

-

B1

B2

B3

B4

B5

B6

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

B12

C12

D12

E12

F12

G12

H12

J12

K12

L12

M12

f

C8

SET

E1

E2

E3

E4

E5

E6

E7

PGND

C9

PGND

MTP1

MARG0

MARG1

C10

C11

f

SET

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

V

OUT

DRV

D7

-

CC

D8

PGND

INTVCC

MTP2

MTP3

V

FB

C1

C2

C3

C4

C5

C6

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

D9

PGOOD

D10

D11

F1

F2

F3

F4

F5

F6

F7

F8

F9

PGND

SGND

+

E8

E9

E10

E11

-

V

OSNS

PGND

DIFFV

OUT

-

V

OUT_LCL

–

F10

F11

-

OSNS

PGOOD

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

V

OUT

G10

G11

-

SGND

G1

G2

G3

G4

G5

G6

G7

G8

G9

PGND

H10

H11

-

SGND

J11

-

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

V

OUT

H1

H2

H3

H4

H5

H6

H7

H8

H9

PGND

4601afb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTM4601A/LTM4601A-1

RELATED PARTS

PART NUMBER

LTC2900

DESCRIPTION

COMMENTS

Quad Supply Monitor with Adjustable Reset Timer

Power Supply Tracking Controller

Synchronous Isolated Flyback Controllers

10A DC/DC μModule

Monitors Four Supplies; Adjustable Reset Timer

Tracks Both Up and Down; Power Supply Sequencing

No Optocoupler Required; 3.3V, 12A Output; Simple Design

Basic 10A DC/DC μModule

LTC2923

LT3825/LT3837

LTM4600

LTM4601

12A DC/DC μModule with PLL, Output Tracking/

Margining and Remote Sensing

Synchronizable, PolyPhase Operation to 48A, LTM4601-1 Version has no

Remote Sensing

LTM4602

LTM4603

6A DC/DC μModule

Pin Compatible with the LTM4600

6A DC/DC μModule with PLL and Output Tracking/

Margining and Remote Sensing

Synchronizable, PolyPhase Operation, LTM4603-1 Version has no

Remote Sensing, Pin Compatible with the LTM4601

LTM4604A

LTM4608A

4A Low Voltage DC/DC μModule

2.7V ≤ V ≤ 5.5V; 0.8V ≤ V

≤ 5V,

IN

OUT

9mm × 15mm × 2.3mm (Ultra-thin) LGA Package

8A Low Voltage DC/DC μModule

2.7V ≤ V ≤ 5.5V; 0.6V ≤ V ≤ 5V;

IN

OUT

9mm × 15mm × 2.8mm LGA Package

®

This product contains technology licensed from Silicon Semiconductor Corporation.

4601afb

LT 1108 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTM4601A-1
厂家：	Linear
描述：	12A DC/DC μModules with PLL, Output Tracking and Margining 12A DC / DC与PLL ，输出跟踪和裕度μModules
文件：	总28页 (文件大小：366K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4601A-1 [Linear]

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