LTM4601_技术文档

LTM4601/LTM4601-1

12A DC/DC µModules

with PLL, Output Tracking

and Margining

U

DESCRIPTIO

FEATURES

The LTM^®4601 is a complete 12A step-down switch mode

DC/DC power supply with onboard switching controller,

MOSFETs, inductor and all support components. The

µModule^TMis housed in a small surface mount 15mm

×15mm × 2.8mm LGA package. Operating over an input

voltage range of 4.5 to 20V, the LTM4601 supports an

outputvoltagerangeof0.6Vto5Vaswellasoutputvoltage

trackingandmargining.Thehighefﬁciencydesigndelivers

12A continuous current (14A peak). Only bulk input and

output capacitors are needed to complete the design.

■

Complete Switch Mode Power Supply

■

Wide Input Voltage Range: 4.5V to 20V

■

12A DC Typical, 14A Peak Output Current

■

0.6V to 5V Output Voltage

■

Output Voltage Tracking and Margining

■

Parallel Multiple µModules for Current Sharing

■

Differential Remote Sensing for Precision

Regulation (LTM4601 Only)

■

PLL Frequency Synchronization

■

1.5ꢀ Regulation

■

Current Foldback Protection (Disabled at Start-Up)

The low proﬁle (2.8mm) and light weight (1.7g) pack-

age easily mounts in unused space on the back side of

PC boards for high density point of load regulation. The

µModule can be synchronized with an external clock for

reducing undesirable frequency harmonics and allows

PolyPhase^®operation for high load currents.

■

Pb-Free (e4) RoHS Compliant Package with Gold

Finish Pads

■

Ultrafast Transient Response

■

Current Mode Control

■

Up to 95% Efﬁciency at 5V , 3.3V

IN

OUT

■

Programmable Soft-Start

A high switching frequency and adaptive on-time current

mode architecture deliver a very fast transient response

to line and load changes without sacriﬁcing stability. An

onboard differential remote sense ampliﬁer can be used

to accurately regulate an output voltage independent of

load current. The onboard remote sense ampliﬁer is not

available in the LTM4601-1.

, LTC, LT and PolyPhase are registered trademarks of Linear Technology Corporation.

µModule is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589,

6774611, 6677210

Output Overvoltage Protection

Small Footprint, Low Proﬁle (15mm × 15mm ×

^{2.8mm) Surface}U^{Mount LGA Package}

APPLICATIO S

■

Telecom and Networking Equipment

■

Servers

■

Industrial Equipment

Point of Load Regulation

■

U

Efﬁciency and Power Loss

vs Load Current

TYPICAL APPLICATIO

1.5V/12A Power Supply with 4.5V to 20V Input

95

90

85

80

75

70

65

60

55

50

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

EFFICIENCY

5V

IN

CLOCK SYNC

V

IN

4.5V TO 20V

TRACK/SS CONTROL

V

PLLIN TRACK/SS

12V

V

1.5V

12A

IN

OUT

PGOOD

V

OUT

100pF

V

FB

12V

IN

ON/OFF

RUN

COMP

INTV

DRV

MARG0

MARG1

V

OUT_LCL

MARGIN

CONTROL

C

OUT

5V

IN

LTM4601

C

IN

CC

DIFFV

CC

OUT

+

MPGM

SGND PGND

V

OSNS

POWER LOSS

–

OSNS

R1

392k

f

SET

R

SET

40.2k

0

2

4

6

8

10

12

14

5% MARGIN

OUTPUT CURRENT (A)

4601 TA01a

4601 TA01b

4601f

1

LTM4601/LTM4601-1

W W U W

U

W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

INTV , DRV , V

, V

(V

≤ 3.3V with

CC

CC OUT_LCL OUT OUT

DIFFV ) .................................................... –0.3V to 6V

OUT

PLLIN, TRACK/SS, MPGM, MARG0, MARG1,

PGOOD, f ..............................–0.3V to INTV + 0.3V

SET

CC

V

f

IN

SET

RUN ............................................................. –0.3V to 5V

MARG0

MARG1

V , COMP................................................ –0.3V to 2.7V

FB

DRV

CC

V ............................................................. –0.3V to 20V

IN

OSNS

V

FB

+

–

PGND

V

, V

.............................–0.3V to INTV – 1V

OSNS CC

PGOOD

SGND

+

Operating Temperature Range (Note 2) ... –40°C to 85°C

Junction Temperature ........................................... 125°C

Storage Temperature Range................... –55°C to 125°C

V

/NC2*

OSNS

DIFFV /NC3*

OUT

V

OUT

OUT_LCL

–

V

/NC1*

OSNS

LGA PACKAGE

118-LEAD (15mm 15mm 2.8mm)

T

= 125°C, θ = 15°C/W, θ = 6°C/W,

JA JC

JMAX

θ

DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS

JA

WEIGHT = 1.7g

*LTM4601-1 ONLY

ORDER PART NUMBER

LGA PART MARKING*

LTM4601EV#PBF

LTM4601IV#PBF

LTM4601EV-1#PBF

LTM4601IV-1#PBF

LTM4601V

LTM4601V-1

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

*The temperature grade is identiﬁed by a label on the shipping container.

ELECTRICAL CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the –40°C to 85°C

temperature range, otherwise speciﬁcations are at T_A= 25°C, V_IN= 12V. Per typical application (front page) conﬁguration.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

●

V

Input DC Voltage

Output Voltage

4.5

20

V

IN(DC)

C

IN

= 10µF ×3, C

= 200µF

OUT(DC)

OUT

●

V

= 5V, V

= 1.5V, I = 0A

OUT

1.478

1.5

1.522

V

IN

OUT

= 12V, V

= 1.5V, I

= 0A

OUT

Input Speciﬁcations

V

Undervoltage Lockout Threshold

Input Inrush Current at Startup

I

= 0A

3.2

4

V

IN(UVLO)

OUT

I

= 0A. V

= 1.5V

INRUSH(VIN)

OUT

V

= 5V

= 12V

0.6

0.7

A

IN

I

Input Supply Bias Current

V

= 12V, V

= 1.5V, No Switching

= 1.5V, Switching

3.8

38

mA

Q(VIN,NOLOAD)

IN

OUT

Continuous

V

= 5V, V

= 1.5V, No Switching

= 1.5V, Switching Continuous

2.5

42

22

mA

µA

IN

OUT

Shutdown, RUN = 0, VIN = 12V

I

Input Supply Current

V

IN

V

IN

V

IN

= 12V, V

= 1.5V, I

= 3.3V, I

= 12A

1.81

3.63

4.29

A

S(VIN)

OUT

= 5V, V

= 1.5V, I

= 12A

OUT

4601f

2

LTM4601/LTM4601-1

ELECTRICAL CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the –40°C to 85°C

temperature range, otherwise speciﬁcations are at T_A= 25°C, V_IN= 12V. Per typical application (front page) conﬁguration.

SYMBOL

INTV

PARAMETER

= 12V, RUN > 2V

CONDITIONS

MIN

TYP

MAX

UNITS

V

No Load

4.7

5

5.3

V

CC

IN

Output Speciﬁcations

I

Output Continuous Current Range

(See Output Current Derating Curves

V

= 12V, V = 1.5V

OUT

0

12

A

OUTDC

IN

for Different V , V

and T )

A

IN OUT

●

ΔV

Line Regulation Accuracy

V

= 1.5V, I

= 0A, V from 4.5V to 20V

0.3

%

OUT(LINE)

OUT

IN

V

OUT(MIN)

ΔV

Load Regulation Accuracy

= 1.5V, 0A to 12A

OUT(0A-12A)

OUT

V

= 12V, Remote Sense Ampliﬁer

= 12V (LTM4601-1)

●

0.25

1

%

IN

V

OUT(MIN)

V

Output Ripple Voltage

I

= 0A, C

= 2×, 100µF/X5R/Ceramic

OUT(AC)

OUT

V

OUT

= 12V, V

= 1.5V

20

18

mV

IN

OUT

P-P

= 5V, V

= 1.5V

OUT

f

Output Ripple Voltage Frequency

= 5A, V = 12V, V = 1.5V

OUT

850

kHz

S

OUT

IN

ΔV

Turn-On Overshoot,

TRACK/SS = 10nF

C

= 200µF, V

= 12V

= 1.5V, I

= 0A

OUT(START)

OUT

V

20

mV

IN

= 5V

t

Turn-On Time, TRACK/SS = Open

C

= 200µF, V

OUT

= 1.5V, I

= 1A

START

OUT

Resisitive Load

V

= 12V

= 5V

0.5

0.7

ms

IN

ΔV

Peak Deviation for Dynamic Load

Load: 0% to 50% to 0% of Full Load,

= 2 × 22µF/Ceramic, 470µF, 4V Sanyo

OUTLS

C

OUT

POSCAP

V

IN

V

IN

= 12V

= 5V

35

mV

t

I

Settling Time for Dynamic Load Step Load: 0% to 50%, or 50% to 0% of Full Load

SETTLE

V

= 12V

25

µs

IN

Output Current Limit

C

= 200µF, Table 2

OUTPK

OUT

V

IN

V

IN

= 12V, V

= 1.5V

17

A

OUT

= 5V, V

= 1.5V

OUT

Remote Sense Amp (Note 3) (LTM4601 Only, Not Supported in the LTM4601-1)

+

–

V

, V

Common Mode Input Voltage Range

V

= 12V, RUN > 2V

0

INTV – 1

V

OSNS

IN

CC

CM Range

DIFFV

Range

Output Voltage Range

Input Offset Voltage Magnitude

Differential Gain

V

IN

= 12V, DIFF OUT Load = 100k

INTV

V

mV

OUT

CC

V

1.25

OS

A

V

1

3

V/V

MHz

V/µs

kΩ

GBP

Gain Bandwidth Product

Slew Rate

SR

2

+

R

Input Resistance

V

OSNS

to GND

20

100

IN

CMRR

Control Stage

Common Mode Rejection Mode

dB

●

V

Error Ampliﬁer Input Voltage

Accuracy

I

= 0A, V

= 1.5V

0.594

0.6

0.606

V

FB

OUT

V

RUN Pin On/Off Threshold

Soft-Start Charging Current

Minimum On Time

1

1.5

–1.5

50

1.9

–2.0

100

V

µA

RUN

I

t

V

= 0V

–1.0

SS/TRACK

ON(MIN)

SS/TRACK

(Note 4)

ns

4601f

3

LTM4601/LTM4601-1

ELECTRICAL CHARACTERISTICS ^The● denotes the speciﬁcations which apply over the –40°C to 85°C

temperature range, otherwise speciﬁcations are at T_A= 25°C, V_IN= 12V. Per typical application (front page) conﬁguration.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

250

50

MAX

UNITS

ns

t

Minimum Off Time

PLLIN Input Resistance

(Note 4)

400

OFF(MIN)

R

kΩ

PLLIN

I

Current into DRV Pin

V

= 1.5V, I = 1A, Frequency = 850kHz,

OUT

CC

18

25

mA

DRVCC

CC

OUT

DRV = 5V

R

Resistor Between V

and V

FB

60.098

60.4

1.18

1.4

60.702

kΩ

V

FBHI

OUT

V

Margin Reference Voltage

MPGM

, V

MARG0, MARG1 Voltage Thresholds

V

MARG0 MARG1

PGOOD Output

ΔV

PGOOD Upper Threshold

PGOOD Lower Threshold

PGOOD Hysteresis

V

FB

V

FB

V

FB

Rising

7

10

–10

1.5

13

%

FBH

Falling

–7

–13

FBL

Returning

FB(HYS)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTM4601E/LTM4601E-1 are guaranteed to meet performance

speciﬁcations from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C

operating temperature range are assured by design, characterization and

correlation with statistical process controls. The LTM4601I/LTM4601I-1

are guaranteed and tested over the –40°C to 85°C temperature range.

Note 3: Remote sense ampliﬁer recommended for ≤3.3V output.

Note 4: 100% tested at wafer level only.

4601f

4

LTM4601/LTM4601-1

U W

TYPICAL PERFOR A CE CHARACTERISTICS ^{(See Figure 18 for all curves)}

Efﬁciency vs Load Current

with 20V_IN

Efﬁciency vs Load Current

with 5V_IN

Efﬁciency vs Load Current

with 12V_IN

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

0.6V

1.2V

1.5V

2.5V

3.3V

5V

OUT

0.6V

OUT

1.2V

1.5V

2.5V

3.3V

5.0V

OUT

70

65

60

1.2V

OUT

1.5V

OUT

2.5V

OUT

3.3V

OUT

0

5

10

15

5

10

0

15

0

10

15

5

OUTPUT CURRENT (A)

4601 G02

4601 G01

4601 G03

1.2V Transient Response

1.5V Transient Response

1.8V Transient Response

V

OUT

50mV/DIV

I

OUT

I

OUT

5A/DIV

4601 G05

4601 G04

4601 G06

20 s/DIV

1.5V AT 6A/ s LOAD STEP

1.2V AT 6A/ s LOAD STEP

1.8V AT 6A/ s LOAD STEP

C

OUT

= 3 • 22 F 6.3V CERAMICS

C

OUT

= 3 • 22 F 6.3V CERAMICS

C

OUT

= 3 • 22 F 6.3V CERAMICS

470 F 4V SANYO POSCAP

C3 = 100pF

470 F 4V SANYO POSCAP

C3 = 100pF

470 F 4V SANYO POSCAP

C3 = 100pF

2.5V Transient Response

3.3V Transient Response

V

OUT

V

OUT

50mV/DIV

I

OUT

5A/DIV

4601 G08

4601 G07

20 s/DIV

3.3V AT 6A/ s LOAD STEP

C = 3 • 22 F 6.3V CERAMICS

470 F 4V SANYO POSCAP

C3 = 100pF

20 s/DIV

2.5V AT 6A/ s LOAD STEP

C

OUT

= 3 • 22 F 6.3V CERAMICS

OUT

470 F 4V SANYO POSCAP

C3 = 100pF

4601f

5

LTM4601/LTM4601-1

U W

TYPICAL PERFOR A CE CHARACTERISTICS ^{(See Figure 18 for all curves)}

Start-Up, I_OUT= 12A

(Resistive Load)

Start-Up, I_OUT= 0A

V

OUT

0.5V/DIV

I

IN

I

IN

1A/DIV

0.5A/DIV

4601 G09

4601 G10

5ms/DIV

2ms/DIV

V

C

= 12V

V

C

= 12V

IN

= 1.5V

OUT

= 470µF

3 × 22µF

SOFT-START = 10nF

V_INto V_OUTStep-Down Ratio

Track, I_OUT= 12A

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3.3V OUTPUT WITH

130k FROM V

TRACK/SS

0.5V/DIV

OUT

TO I

ON

V

5V OUTPUT WITH

100k RESISTOR

FB

0.5V/DIV

ADDED FROM f

TO GND

SET

V

OUT

1V/DIV

5V OUTPUT WITH

NO RESISTOR ADDED

FROM f

TO GND

4601 G12

SET

2ms/DIV

2.5V OUTPUT

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

V

C

3

= 12V

IN

OUT

= 1.5V

= 470 F

22 F

SOFT-START = 10nF

0

2

4

6

8

10 12 14 16 18 20

INPUT VOLTAGE (V)

4601 G11

Short-Circuit Protection, I_OUT= 0A

Short-Circuit Protection, I_OUT= 12A

V

OUT

0.5V/DIV

I

IN

1A/DIV

IN

1A/DIV

4601 G13

4601 G14

50µs/DIV

V

C

= 12V

V

C

= 12V

IN

= 1.5V

OUT

= 470µF

3 × 22µF

SOFT-START = 10nF

4601f

6

LTM4601/LTM4601-1

U

PI FU CTIO S

(See Package Description for Pin Assignment)

V (Bank 1): Power Input Pins. Apply input voltage be-

PLLIN (Pin A8): External Clock Synchronization Input to

the Phase Detector. This pin is internally terminated to

SGND with a 50k resistor. Apply a clock above 2V and

IN

tween these pins and PGND pins. Recommend placing

input decoupling capacitance directly between V pins

IN

and PGND pins.

below INTV . See Applications Information.

CC

V

(Bank 3): Power Output Pins. Apply output load

TRACK/SS (Pin A9): Output Voltage Tracking and Soft-

Start Pin. When the module is conﬁgured as a master

output, then a soft-start capacitor is placed on this pin

to ground to control the master ramp rate. A soft-start

capacitor can be used for soft-start turn on as a stand

alone regulator. Slave operation is performed by putting

a resistor divider from the master output to the ground,

and connecting the center point of the divider to this pin.

See Applications Information.

OUT

between these pins and PGND pins. Recommend placing

outputdecouplingcapacitancedirectlybetweenthesepins

and PGND pins. Review the ﬁgure below.

PGND (Bank 2): Power ground pins for both input and

output returns.

–

V

(PinM12):(–)InputtotheRemoteSenseAmpliﬁer.

OSNS

This pin connects to the ground remote sense point. The

remote sense ampliﬁer is used for V ≤3.3V.

OUT

MPGM (Pin A12): Programmable Margining Input. A re-

sistor from this pin to ground sets a current that is equal

to 1.18V/R. This current multiplied by 10kΩ will equal a

value in millivolts that is a percentage of the 0.6V refer-

ence voltage. See Applications Information. To parallel

LTM4601s, each requires an individual MPGM resistor.

Do not tie MPGM pins together.

NC1 (Pin M12): No Connect On the LTM4601-1.

+

V

(PinJ12):(+)InputtotheRemoteSenseAmpliﬁer.

OSNS

This pin connects to the output remote sense point. The

remote sense ampliﬁer is used for V ≤3.3V.

OUT

NC2 (Pin J12): No Connect On the LTM4601-1.

DIFFV (Pin K12): Output of the Remote Sense Ampli-

ﬁer. This pin connects to the V

OUT

f

(Pin B12): Frequency Set Internally to 850kHz. An

SET

pin.

OUT_LCL

external resistor can be placed from this pin to ground

to increase frequency. This pin can be decoupled with a

1000pF capacitor. See Applications Information for fre-

quency adjustment.

NC3 (Pin K12): No Connect On the LTM4601-1.

DRV (Pin E12): This pin normally connects to INTV

for powering the internal MOSFET drivers. This pin can

be biased up to 6V from an external supply with about

50mA capability, or an external circuit shown in Figure 16.

This improves efﬁciency at the higher input voltages by

reducing power dissipation in the module.

CC

V

(Pin F12): The Negative Input of the Error Ampliﬁer.

FB

Internally, this pin is connected to V

pin with a

OUT_LCL

60.4k precision resistor. Different output voltages can be

programmed with an additional resistor between V and

FB

SGND pins. See Applications Information.

INTV (Pin A7): This pin is for additional decoupling of

the 5V internal regulator.

CC

TOP VIEW

A

B

C

D

E

V

IN

f

SET

BANK 1

MARG0

MARG1

DRV

CC

PGND

BANK 2

F

V

FB

G

H

J

PGOOD

SGND

+

V

/NC2*

OSNS

K

L

M

DIFFV /NC3*

OUT

V

OUT

BANK 3

V

OUT_LCL

–

/NC1*

OSNS

1

2 3 4 5 6 7 8 9 10 11 12

*LTM4601-1 ONLY

4601f

7

LTM4601/LTM4601-1

U

PI FU CTIO S

(See Package Description for Pin Assignment)

MARG0 (Pin C12): This pin is the LSB logic input for the

margining function. Together with the MARG1 pin will

determine if margin high, margin low or no margin state

is applied. The pin has an internal pull-down resistor of

50k. See Applications Information.

PGOOD (Pin G12): Output Voltage Power Good Indicator.

Open-drain logic output that is pulled to ground when the

output voltage is not within 10% of the regulation point,

after a 25µs power bad mask timer expires.

RUN (Pin A10): Run Control Pin. A voltage above 1.9V

will turn on the module, and when below 1.9V, will turn

off the module. A programmable UVLO function can be

MARG1 (Pin D12): This pin is the MSB logic input for the

margining function. Together with the MARG0 pin will

determine if margin high, margin low or no margin state

is applied. The pin has an internal pull-down resistor of

50k. See Applications Information.

accomplished with a resistor from V to this pin that has

IN

a 5.1V zener to ground. Maximum pin voltage is 5V. Limit

current into the RUN pin to less than 1mA.

SGND (Pin H12): Signal Ground. This pin connects to

V

(Pin L12): V

connects directly to this pin

OUT_LCL

OUT

PGND at output capacitor point.

to bypass the remote sense ampliﬁer, or DIFFV

con-

OUT

nects to this pin when remote sense ampliﬁer is used.

COMP (Pin A11): Current Control Threshold and Error

Ampliﬁer Compensation Point. The current comparator

threshold increases with this control voltage. The voltage

ranges from 0V to 2.4V with 0.7V corresponding to zero

sense voltage (zero current).

V

can be connected to V

is internally connected to V

on the LTM4601-1,

OUT_LCL

OUT

with 50Ω in the

LTM4601-1.

W

SI PLIFIED BLOCK DIAGRA

V

OUT_LCL

V

OUT

1M

>2V = ON

<0.9V = OFF

MAX = 5V

(50Ω, LTM4601-1)

RUN

PGOOD

COMP

V

IN

4.5V TO 20V

+

5.1V

ZENER

1.5µF

C

IN

60.4k

INTERNAL

COMP

POWER CONTROL

Q1

Q2

SGND

V

1.5V

12A

OUT

MARG1

MARG0

22µF

V

FB

50k 50k

+

f

SET

R

SET

40.2k

C

OUT

39.2k

PGND

MPGM

TRACK/SS

PLLIN

INTV

CC

10k

–

10k

C

SS

V

NOT INCLUDED

OSNS

–

+

IN THE LTM4601-1

+

10k

50k

4.7µF

OSNS

–

+

V

= NC1

= NC2

= NC3

OSNS

INTV

DRV

CC

10k

DIFFV

OUT

DIFFV

OUT

4601 F01

Figure 1. Simpliﬁed LTM4601/LTM4601-1 Block Diagram

4601f

8

LTM4601/LTM4601-1

U

W U

DECOUPLI G REQUIRE E TS

T_A= 25°C, V_IN= 12V. Use Figure 1 conﬁguration.

CONDITIONS MIN

20

SYMBOL

PARAMETER

TYP

MAX

UNITS

C

External Input Capacitor Requirement

I

= 12A, 3× 10µF Ceramics

30

µF

IN

OUT

(V = 4.5V to 20V, V

= 1.5V)

IN

OUT

C

External Output Capacitor Requirement

= 12A

100

200

µF

OUT

(V = 4.5V to 20V, V

= 1.5V)

IN

OUT

U

OPERATIO

Power Module Description

and bottom FET Q2 is turned on and held on until the

overvoltage condition clears.

TheLTM4601isastandalonenonisolatedswitchingmode

DC/DC power supply. It can deliver up to 12A of DC output

current with some external input and output capacitors.

This module provides precisely regulated output voltage

Pulling the RUN pin below 1V forces the controller into its

shutdown state, turning off both Q1 and Q2. At low load

current, the module works in continuous current mode by

default to achieve minimum output voltage ripple.

programmable via one external resistor from 0.6V to

DC

5.0V over a 4.5V to 20V wide input voltage. The typical

DC

When DRV pin is connected to INTV an integrated

CC

application schematic is shown in Figure 18.

5V linear regulator powers the internal gate drivers. If a

The LTM4601 has an integrated constant on-time current

5V external bias supply is applied on the DRV pin, then

CC

mode regulator, ultralow R

FETs with fast switch-

an efﬁciency improvement will occur due to the reduced

powerlossintheinternallinearregulator.Thisisespecially

true at the higher input voltage range.

DS(ON)

ing speed and integrated Schottky diodes. The typical

switching frequency is 850kHz at full load. With current

mode control and internal feedback loop compensation,

the LTM4601 module has sufﬁcient stability margins and

good transient performance under a wide range of operat-

ing conditions and with a wide range of output capacitors,

even all ceramic output capacitors.

The LTM4601 has a very accurate differential remote

sense ampliﬁer with very low offset. This provides for

very accurate remote sense voltage measurement. The

MPGM pin, MARG0 pin and MARG1 pin are used to sup-

port voltage margining, where the percentage of margin

is programmed by the MPGM pin, and the MARG0 and

MARG1 select margining.

Currentmodecontrolprovidescycle-by-cyclefastcurrent

limit. Besides, foldback current limiting is provided in an

overcurrentconditionwhileV drops.Internalovervoltage

andundervoltagecomparatorspulltheopen-drainPGOOD

output low if the output feedback voltage exits a 10%

window around the regulation point. Furthermore, in an

overvoltage condition, internal top FET Q1 is turned off

FB

The PLLIN pin provides frequency synchronization of the

device to an external clock. The TRACK/SS pin is used for

power supply tracking and soft-start programming.

4601f

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The typical LTM4601 application circuit is shown in

Figure 18. External component selection is primarily

determined by the maximum load current and output

voltage. Refer to Table 2 for speciﬁc external capacitor

requirements for a particular application.

The MPGM pin programs a current that when multiplied

by an internal 10k resistor sets up the 0.6V reference

offset for margining. A 1.18V reference divided by the

RPGM resistor on the MPGM pin programs the current.

Calculate V

:

OUT(MARGIN)

V to V

Step-Down Ratios

IN

OUT

%V_OUT

100

V_OUT(MARGIN)

=

• V_OUT

There are restrictions in the maximum V and V

step

IN

OUT

down ratio that can be achieved for a given input voltage.

where%V isthepercentageofV youwanttomargin,

OUT

These constraints are shown in the Typical Performance

and V

is the margin quantity in volts:

OUT(MARGIN)

Characteristics curves labeled V to V

Step-Down

IN

OUT

Ratio.Notethatadditionalthermalderatingmayapply.See

the Thermal Considerations and Output Current Derating

section of this data sheet.

V_OUT

1.18V

•10k

R_PGM

=

•

0.6V V_OUT(MARGIN)

where RPGM is the resistor value to place on the MPGM

pin to ground.

Output Voltage Programming and Margining

ThePWMcontrollerhasaninternal0.6Vreferencevoltage.

As shown in the Block Diagram, a 1M and a 60.4k 0.5%

The output margining will be margining of the value.

This is controlled by the MARG0 and MARG1 pins. See

the truth table below:

internal feedback resistor connects V

and V pins

OUT

FB

together. The V

pin is connected between the 1M

OUT_LCL

MARG0

LOW

MARG1

LOW

MODE

and the 60.4k resistor. The 1M resistor is used to protect

against an output overvoltage condition if the V

NO MARGIN

MARGIN UP

MARGIN DOWN

NO MARGIN

OUT_LCL

LOW

HIGH

LOW

pin is not connected to the output, or if the remote sense

HIGH

ampliﬁer output is not connected to V . The output

OUT_LCL

HIGH

voltage will default to 0.6V. Adding a resistor R

the V pin to SGND pin programs the output voltage:

from

SET

FB

Input Capacitors

60.4k +R_SET

V_OUT= 0.6V

LTM4601moduleshouldbeconnectedtoalowACimped-

anceDCsource. Inputcapacitorsarerequiredtobeplaced

adjacent to the module. In Figure 18, the 10µF ceramic

input capacitors are selected for their ability to handle

the large RMS current into the converter. An input bulk

capacitorof100µFisoptional.This100µFcapacitorisonly

needed if the input source impedance is compromised by

long inductive leads or traces.

R_SET

Table 1. Standard 1ꢀ Resistor Values

R

SET

Open 60.4

0.6 1.2

40.2

1.5

30.1

1.8

25.5

2

19.1

2.5

13.3

3.3

8.25

5

(kΩ)

V

OUT

(V)

4601f

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For a buck converter, the switching duty-cycle can be

the corresponding duty cycle and the number of phases

to arrive at the correct ripple current value. For example,

the2-phaseparallelLTM4601designprovides24Aat2.5V

output from a 12V input. The duty cycle is DC = 2.5V/12V

= 0.21. The 2-phase curve has a ratio of ~0.25 for a duty

cycle of 0.21. This 0.25 ratio of RMS ripple current to a

DC load current of 24A equals ~6A of input RMS ripple

current for the external input capacitors.

estimated as:

V_OUT

D=

V

IN

Without considering the inductor current ripple, the RMS

current of the input capacitor can be estimated as:

I_OUT(MAX)

I_CIN(RMS)

=

• D• 1–D

(

)

Output Capacitors

η%

The LTM4601 is designed for low output voltage ripple.

In the above equation, η% is the estimated efﬁciency of

The bulk output capacitors deﬁned as C

are chosen

OUT

the power module. C can be a switcher-rated electrolytic

IN

with low enough effective series resistance (ESR) to meet

theoutputvoltagerippleandtransientrequirements. C

aluminum capacitor, OS-CON capacitor or high volume

ceramic capacitor. Note the capacitor ripple current rat-

ings are often based on temperature and hours of life. This

makes it advisable to properly derate the input capacitor,

or choose a capacitor rated at a higher temperature than

required. Always contact the capacitor manufacturer for

derating requirements.

OUT

can be a low ESR tantalum capacitor, a low ESR polymer

capacitororaceramiccapacitor.Thetypicalcapacitanceis

200µF if all ceramic output capacitors are used. Additional

output ﬁltering may be required by the system designer,

if further reduction of output ripple or dynamic transient

spikeisrequired.Table2showsamatrixofdifferentoutput

voltages and output capacitors to minimize the voltage

droop and overshoot during a 5A/µs transient. The table

optimizes total equivalent ESR and total bulk capacitance

to maximize transient performance.

In Figure 18, the 10µF ceramic capacitors are together

used as a high frequency input decoupling capacitor. In a

typical 12A output application, three very low ESR, X5R or

X7R, 10µF ceramic capacitors are recommended. These

decoupling capacitors should be placed directly adjacent

to the module input pins in the PCB layout to minimize

the trace inductance and high frequency AC noise. Each

10µF ceramic is typically good for 2A to 3A of RMS ripple

current. Refer to your ceramics capacitor catalog for the

RMS current ratings.

0.6

0.5

1-PHASE

2-PHASE

0.4

3-PHASE

4-PHASE

6-PHASE

0.3

12-PHASE

Multiphase operation with multiple LTM4601 devices in

parallelwilllowertheeffectiveinputRMSripplecurrentdue

to the interleaving operation of the regulators. Application

Note 77 provides a detailed explanation. Refer to Figure 2

for the input capacitor ripple current requirement as a

function of the number of phases. The ﬁgure provides a

ratio of RMS ripple current to DC load current as function

of duty cycle and the number of paralleled phases. Pick

0.2

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

4601 F02

Figure 2. Normalized Input RMS Ripple Current

vs Duty Factor for One to Six Modules (Phases)

4601f

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Multiphase operation with multiple LTM4601 devices in

parallel will lower the effective output ripple current due to

the interleaving operation of the regulators. For example,

each LTM4601’s inductor current of a 12V to 2.5V multi-

phasedesigncanbereadfromtheInductorRippleCurrent

versesDutyCyclegraph(Figure3).Thelargeripplecurrent

at low duty cycle and high output voltage can be reduced

by adding an external resistor from f to ground which

SET

increases the frequency. If the duty cycle is DC = 2.5V/12V

= 0.21, the inductor ripple current for 2.5V output at 21%

duty cycle is ~6A in Figure 3.

Figure4providesaratioofpeak-to-peakoutputripplecur-

rent to the inductor current as a function of duty cycle and

the number of paralleled phases. Pick the corresponding

dutycycleandthenumberofphasestoarriveatthecorrect

output ripple current ratio value. If a 2-phase operation is

chosen at a duty cycle of 21%, then 0.6 is the ratio. This

0.6 ratio of output ripple current to inductor ripple of 6A

equals 3.6A of effective output ripple current. Refer to Ap-

plicationNote77foradetailedexplanationofoutputripple

current reduction as a function of paralleled phases.

12

2.5V OUTPUT

10

5V OUTPUT

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

8

6

3.3V OUTPUT WITH

130k ADDED FROM

V

OUT

TO f

SET

4

2

0

5V OUTPUT WITH

100k ADDED FROM

The output voltage ripple has two components that are

related to the amount of bulk capacitance and effective

series resistance (ESR) of the output bulk capacitance.

Therefore, the output voltage ripple can be calculated with

the known effective output ripple current. The equation:

f

TO GND

SET

0

20

40

60

80

DUTY CYCLE (V /V

)

OUT IN

4601 F03

Figure 3. Inductor Ripple Current vs Duty Cycle

ΔV

≈ (ΔI /(8 • f • m • C ) + ESR • ΔI ), where f

OUT(P-P)

L OUT L

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY CYCLE (V /V

)

IN

O

4601 F04

Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = V_OT/L_I, Dlr = Each Phase’s Inductor Current

4601f

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LTM4601/LTM4601-1

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is frequency and m is the number of parallel phases. This

calculation process can be easily fulﬁlled using our Linear

Technology µModule Design Tool.

downwithanotherregulator.Themasterregulator’soutput

is divided down with an external resistor divider that is the

same as the slave regulator’s feedback divider. Figure 5

shows an example of coincident tracking. Ratiometric

modes of tracking can be achieved by selecting different

resistor values to change the output tracking ratio. The

master output must be greater than the slave output for

the tracking to work. Figure 6 shows the coincident output

tracking characteristics.

Fault Conditions: Current Limit and Overcurrent

Foldback

LTM4601 has a current mode controller, which inher-

ently limits the cycle-by-cycle inductor current not only

in steady-state operation, but also in transient.

MASTER

OUTPUT

To further limit current in the event of an overload condi-

tion,theLTM4601providesfoldbackcurrentlimiting.Ifthe

output voltage falls by more than 50%, then the maximum

output current is progressively lowered to about one sixth

of its full current limit value.

R2

60.4k

TRACK CONTROL

V

IN

R1

40.2k

60.4k FROM

TO V

100k

V

PLLIN TRACK/SS

V

IN

OUT

FB

SLAVE OUTPUT

PGOOD

V

OUT

Soft-Start and Tracking

MPGM

RUN

COMP

V

C

FB

OUT

MARG0

MARG1

V

OUT_LCL

The TRACK/SS pin provides a means to either soft-start

the regulator or track it to a different power supply. A

capacitor on this pin will program the ramp rate of the

output voltage. A 1.5µA current source will charge up the

external soft-start capacitor to 80% of the 0.6V internal

voltagereferenceminusanymargindelta.Thiswillcontrol

the ramp of the internal reference and the output voltage.

The total soft-start time can be calculated as:

LTM4601

C

IN

INTV

CC

DRV

DIFFV

V

OUT

+

OSNS

–

OSNS

f

SGND PGND

SET

R

SET

40.2k

4601 F05

Figure 5

C_SS

1.5µA

t_SOFTSTART= 0.8V • 0.6V – V

•

(

)

OUT(MARGIN)

WhentheRUNpinfallsbelow1.5V, thentheSSpinisreset

to allow for proper soft-start control when the regulator

is enabled again. Current foldback and force continuous

mode are disabled during the soft-start process. The

soft-start function can also be used to control the output

ramp up time, so that another regulator can be easily

tracked to it.

MASTER OUTPUT

SLAVE OUTPUT

OUTPUT

VOLTAGE

Output Voltage Tracking

4601 F06

TIME

Output voltage tracking can be programmed externally

usingtheTRACK/SSpin. Theoutputcanbetrackedupand

Figure 6

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Run Enable

through the LDO is about 20mA. The internal LDO power

dissipation can be calculated as:

The RUN pin is used to enable the power module. The

pin has an internal 5.1V zener to ground. The pin can be

driven with a logic input not to exceed 5V.

P

= 20mA • (V – 5V)

IN

LDO_LOSS

The LTM4601 also provides the external gate driver volt-

The RUN pin can also be used as an undervoltage lock out

(UVLO) function by connecting a resistor divider from the

input supply to the RUN pin:

age pin DRV . If there is a 5V rail in the system, it is

CC

recommended to connect DRV pin to the external 5V

CC

rail. This is especially true for higher input voltages. Do

not apply more than 6V to the DRV pin. A 5V output can

CC

R1+R2

be used to power the DRV pin with an external circuit

V_UVLO

=

•1.5V

CC

R2

as shown in Figure 16.

Power Good

Parallel Operation of the Module

The PGOOD pin is an open-drain pin that can be used to

monitor valid output voltage regulation. This pin monitors

a 10% window around the regulation point and tracks

with margining.

The LTM4601 device is an inherently current mode con-

trolleddevice.Parallelmoduleswillhaveverygoodcurrent

sharing. This will balance the thermals on the design.

Figure 19 shows a schematic of the parallel design. The

voltage feedback equation changes with the variable n as

modules are paralleled:

COMP Pin

This pin is the external compensation pin. The module

has already been internally compensated for most output

voltages. Table 2 is provided for most application require-

ments. A spice model will be provided for other control

loop optimization.

60.4k

+R_FB

n

V_OUT= 0.6V

R_FB

η is the number of paralleled modules.

Figure19showsanLTM4601andanLTM4601-1usedina

parallel design. The 2nd LTM4601 device does not require

the remote sense ampliﬁer, therefore, the LTM4601-1 de-

vice is used. An LTM4601 device can be used without the

PLLIN

The power module has a phase-locked loop comprised

of an internal voltage controlled oscillator and a phase

detector. This allows the internal top MOSFET turn-on

to be locked to the rising edge of the external clock. The

frequency range is 30% around the operating frequency

of 850kHz. A pulse detection circuit is used to detect a

clock on the PLLIN pin to turn on the phase lock loop.

The pulse width of the clock has to be at least 400ns and

2V in amplitude. During the start-up of the regulator, the

phase-lock loop function is disabled.

+

–

diff amp. V

can be tied to ground and the V

can

OSNS

betiedtoINTV .DIFFV

canﬂoat.Whenusingmultiple

CC

OUT

LTM4601-1 devices in parallel with an LTM4601, limit the

number to ﬁve for a total of six modules in parallel.

Thermal Considerations and Output Current Derating

The power loss curves in Figures 7 and 8 can be used

in coordination with the load current derating curves in

Figures 9 to 14 for calculating an approximate θ for the

JA

INTV and DRV Connection

CC

modulewithvariousheatsinkingmethods.Thermalmodels

are derived from several temperature measurements at

the bench and thermal modeling analysis. Thermal Ap-

plication Note 103 provides a detailed explanation of the

analysis for the thermal models and the derating curves.

An internal low dropout regulator produces an internal

5V supply that powers the control circuitry and DRV

CC

for driving the internal power MOSFETs. Therefore, if

the system does not have a 5V power rail, the LTM4601

can be directly powered by V . The gate driver current

IN

Tables 3 and 4 provide a summary of the equivalent θ

JA

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6

5

4

3

2

1

0

5.0

4.5

4.0

3.5

20V LOSS

3.0

12V LOSS

2.5

20V LOSS

12V LOSS

2.0

1.5

5V LOSS

1.0

0.5

0

2

6

8

10

12

0

2

4

6

8

10

12

4

OUTPUT CURRENT (A)

4601 F07

4601 F08

Figure 7. 1.5V Power Loss

Figure 8. 3.3V Power Loss

12

10

12

10

8

6

8

6

4

2

0

4

2

0

5V , 1.5V

IN

0LFM

200LFM

400LFM

5V , 1.5V

IN

0LFM

200LFM

400LFM

OUT

5V , 1.5V

IN

5V , 1.5V

IN

5V , 1.5V

IN

5V , 1.5V

IN

50

60

70

80

90

100

50

60

70

80

90

100

AMBIENT TEMPERATURE (°C)

4601 F10

4600 F09

Figure 10. BGA Heat Sink 5V_IN

Figure 9. No Heat Sink 5V_IN

4601f

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12

10

12

10

8

6

8

6

4

2

0

4

5V , 1.5V

IN

0LFM

200LFM

400LFM

5V , 1.5V

IN

0LFM

200LFM

400LFM

OUT

2

0

5V , 1.5V

IN

5V , 1.5V

IN

5V , 1.5V

IN

5V , 1.5V

IN

50

60

70

80

90

100

50

60

70

80

90

100

AMBIENT TEMPERATURE (°C)

4601 F12

4601 F11

Figure 11. No Heat Sink 12V_IN

Figure 12. BGA Heat Sink 12V_IN

12

10

12

10

8

6

8

6

4

2

0

4

2

0

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

40

60

80

100

40

60

80

100

AMBIENT TEMPERATURE (°C)

4601 F13

4601 F14

Figure 14. 12V_IN, 3.3V_OUT, BGA Heat Sink

Figure 13. 12V_IN, 3.3V_OUT, No Heat Sink

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Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 18), 0A to 6A Load Step

TYPICAL MEASURED VALUES

C

VENDORS

PART NUMBER

C

VENDORS

OUT2

PART NUMBER

OUT1

TDK

C4532X5R0J107MZ (100UF,6.3V)

JMK432BJ107MU-T ( 100µF, 6.3V)

JMK316BJ226ML-T501 ( 22µF, 6.3V)

SANYO POS CAP

6TPE330MIL (330µF, 6.3V)

2R5TPE470M9 (470µF, 2.5V)

4TPE470MCL (470µF, 4V)

TAIYO YUDEN

V

C

V

(V)

DROOP

(mV)

PEAK TO

RECOVERY

TIME (µs)

LOAD STEP

R

SET

OUT

IN

OUT1

OUT2

IN

(V)

1.2

1.5

1.8

2.5

3.3

5

(CERAMIC)

2 × 10µF 25V

(BULK)

(CERAMIC)

(BULK)

470µF 4V

470µF 2.5V

330µF 6.3V

NONE

C

C3

PEAK (mV)

140

70

(A/µs)

6

(kΩ)

60.4

40.2

30.1

19.1

13.3

8.25

COMP

150µF 35V

3 × 22µF 6.3V

1 × 100µF 6.3V

2 × 100µF 6.3V

4 × 100µF 6.3V

3 × 22µF 6.3V

1 × 100µF 6.3V

2 × 100µF 6.3V

4 × 100µF 6.3V

3 × 22µF 6.3V

1 × 100µF 6.3V

2 × 100µF 6.3V

4 × 100µF 6.3V

3 × 22µF 6.3V

1 × 100µF 6.3V

2 × 100µF 6.3V

4 × 100µF 6.3V

3 × 22µF 6.3V

1 × 100µF 6.3V

2 × 100µF 6.3V

4 × 100µF 6.3V

3 × 22µF 6.3V

1 × 100µF 6.3V

2 × 100µF 6.3V

4 × 100µF 6.3V

1 × 100µF 6.3V

2 × 100µF 6.3V

3 × 22µF 6.3V

4 × 100µF 6.3V

1 × 100µF 6.3V

3 × 22µF 6.3V

2 × 100µF 6.3V

4 × 100µF 6.3V

2 × 100µF 6.3V

1 × 100µF 6.3V

3 × 22µF 6.3V

4 × 100µF 6.3V

1 × 100µF 6.3V

3 × 22µF 6.3V

2 × 100µF 6.3V

4 × 100µF 6.3V

NONE

47pF

5

70

35

30

20

30

20

35

30

35

30

25

30

20

30

20

30

25

30

25

30

35

30

25

NONE 100pF

NONE 22pF

5

70

140

93

NONE 100pF

5

40

470µF 4V

470µF 2.5V

330µF 6.3V

NONE

12

5

70

140

70

35

NONE

22pF

70

140

98

NONE 100pF

49

470µF 4V

470µF 2.5V

330µF 6.3V

NONE

48

100

109

84

NONE

33pF

5

54

NONE 100pF

5

44

5

61

118

100

109

89

470µF 4V

470µF 2.5V

330µF 6.3V

NONE

12

5

48

NONE

33pF

54

NONE 100pF

44

54

108

100

90

470µF 4V

470µF 2.5V

330µF 6.3V

NONE

47pF

48

NONE 100pF

NONE 220pF

NONE NONE

NONE 100pF

NONE NONE

NONE 220pF

NONE 100pF

NONE 150pF

NONE 100pF

5

44

5

68

140

130

120

140

130

103

113

116

115

103

102

113

140

240

214

230

214

230

375

320

5

65

470µF 4V

470µF 2.5V

330µF 6.3V

NONE

12

5

60

68

65

470µF 4V

330µF 6.3V

470µF 4V

NONE

48

5

56

5

57

5

60

470µF 4V

330µF 6.3V

NONE

12

7

48

51

56

70

330µF 6.3V

470µF 4V

NONE

120

110

114

110

114

188

159

7

470µF 4V

330µF 6.3V

NONE

12

15

20

NONE

22pF

5

NONE

4601f

17

LTM4601/LTM4601-1

U

W U U

APPLICATIO S I FOR ATIO

Table 3. 1.5V Output at 12A

DERATING CURVE

Figures 9, 11

V

(V)

POWER LOSS CURVE

Figure 7

AIR FLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

IN

5, 12

0

15.2

14

Figures 9, 11

Figure 7

200

400

0

None

Figures 9, 11

Figure 7

None

12

Figures 10, 12

Figure 7

BGA Heat Sink

13.9

11.3

10.25

Figure 7

200

400

Figure 7

Table 4. 3.3V Output at 12A

DERATING CURVE

Figure 13

V

(V)

POWER LOSS CURVE

Figure 8

AIR FLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

IN

12

0

15.2

14.6

13.4

13.9

11.1

10.5

Figure 13

12

Figure 8

200

400

0

None

Figure 13

Figure 8

None

Figure 14

Figure 8

BGA Heat Sink

Figure 14

Figure 8

200

400

Figure 14

Figure 8

Heat Sink Manufacturer

Wakeﬁeld Engineering

Part No: 20069

Phone: 603-635-2800

4601f

18

LTM4601/LTM4601-1

U

W U U

APPLICATIO S I FOR ATIO

for the noted conditions. These equivalent θ parameters

• Use large PCB copper areas for high current path, in-

JA

are correlated to the measured values, and are improved

with air ﬂow. The case temperature is maintained at 100°C

or below for the derating curves. The maximum case

temperature of 100°C is to allow for a rise of about 13°C

cluding V , PGND and V . It helps to minimize the

IN OUT

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-

tors next to the V , PGND and V

pins to minimize

IN

OUT

to 25°C inside the µModule with a thermal resistance θ

JC

high frequency noise.

from junction to case between 6°C/W to 9°C/W. This will

maintain the maximum junction temperature inside the

µModule below 125°C.

• Place a dedicated power ground layer underneath the

unit. Refer frequency synchronization source to power

ground.

Safety Considerations

• Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

The LTM4601 modules do not provide isolation from

V

IN

to V . There is no internal fuse. If required, a

OUT

slow blow fuse with a rating twice the maximum input

current needs to be provided to protect each unit from

catastrophic failure.

• Do not put vias directly on pads.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to PGND underneath the unit.

Layout Checklist/Example

The high integration of LTM4601 makes the PCB board

layoutverysimpleandeasy.However,tooptimizeitselectri-

cal and thermal performance, some layout considerations

are still necessary.

Figure 15 gives a good example of the recommended

layout.

V

IN

C

IN

GND

SIGNAL

GND

C

OUT

V

OUT

4601 F15

Figure 15. Recommended Layout

4601f

19

LTM4601/LTM4601-1

U

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APPLICATIO S I FOR ATIO

Frequency Adjustment

14A peak speciﬁed value. A 100k resistor is placed from

to ground, and the parallel combination of 100k and

f

SET

The LTM4601 is designed to typically operate at 850kHz

across most input conditions. The f pin is normally left

39.2k equates to 28k. The I

calculation with 28k and

fSET

SET

20V input voltage equals 238µA. This equates to a t of

ON

open or decoupled with an optional 1000pF capacitor. The

switching frequency has been optimized for maintaining

constant output ripple noise over most operating ranges.

The 850kHz switching frequency and the 400ns minimum

off time can limit operation at higher duty cycles like 5V to

3.3V, and produce excessive inductor ripple currents for

lower duty cycle applications like 20V to 5V. The 5V and

3.3V drop out curves are modiﬁed by adding an external

200ns. This will increase the switching frequency from

~886kHz to ~1.25MHz for the 20V to 5V conversion. The

minimum on time is above 100ns at 20V input. Since

the switching frequency is approximately constant over

input and output conditions, then the lower input voltage

range is limited to 10V for the 1.25MHz operation due to

the 400ns minimum off time. Equation: t = (V /V )

ON

OUT IN

• (1/Frequency) equates to a 400ns on time, and a 400ns

resistor on the f

pin to allow for lower input voltage

SET

off time. The “V to V Step Ratio Curve” reﬂects an

IN

OUT

operation, or higher input voltage operation.

operating range of 10V to 20V for 1.25MHz operation with

a 100k resistor to ground, and an 8V to 16V operation for

Example for 5V Output

f

ﬂoating. These modiﬁcations are made to provide

SET

LTM4601 minimum on-time = 100ns;

wider input voltage ranges for the 5V output designs while

limiting the inductor ripple current, and maintaining the

400ns minimum off time.

t

= ((4.8 • 10pf)/I

)

ON

fSET

LTM4601 minimum off-time = 400ns; t = t – t ,

where t = 1/Frequency

OFF

ON

Example for 3.3V Output

Duty Cycle = t /t or V /V

ON

OUT IN

LTM4601 minimum on-time = 100ns;

Equations for setting frequency:

t

= ((3.3 • 10pF)/I

)

ON

fSET

I

t

= (V /(3 • R )), for 20V operation, I = 170µA,

IN fSET SET

fSET

LTM4601 minimum off-time = 400ns;

= t – t , where t = 1/Frequency

= ((4.8 • 10pF)/I ), t = 282ns, where the internal

ON

R

fSET ON

t

OFF

ON

is 39.2k. Frequency = (V /(V • t )) = (5V/(20 •

fSET

OUT IN ON

Duty Cycle (DC) = t /t or V /V

ON

OUT IN

282ns)) ~ 886kHz. The inductor ripple current begins to

get high at the higher input voltages due to a larger voltage

across the inductor. This is noted in the Typical Inductor

Ripple Current verses Duty Cycle graph (Figure 3) where

Equations for setting frequency:

I

t

R

= (V /(3 • R )), for 20V operation, I

= 170µA,

fSET

IN

fSET

= ((3.3 • 10pf)/I ), t = 195ns, where the internal

ON

fSET ON

I ≈ 10A at 25% duty cycle. The inductor ripple current

L

is 39.2k. Frequency = (V /(V • t )) = (3.3V/(20

fSET

OUT IN ON

can be lowered at the higher input voltages by adding an

•195ns))~846kHz. Theminimumon-timeandminimum-

off time are within speciﬁcation at 195ns and 980ns. The

4.5V minimum input for converting 3.3V output will not

externalresistorfromf togroundtoincreasetheswitch-

SET

ing frequency. An 8A ripple current is chosen, and the total

peak current is equal to 1/2 of the 8A ripple current plus

the output current. The 5V output current is limited to 8A,

so the total peak current is less than 12A. This is below the

meet the minimum off-time speciﬁcation of 400ns. t

=

ON

868ns, Frequency = 850kHz, t = 315ns.

OFF

4601f

20

LTM4601/LTM4601-1

U

W U U

APPLICATIO S I FOR ATIO

Solution

The I

current needs to be 24µA for 540kHz operation.

fSET

A resistor can be placed from V

to f

SET

to lower the

OUT

SET

Lower the switching frequency at lower input voltages to

allow for higher duty cycles, and meet the 400ns mini-

mum off-time at 4.5V input voltage. The off-time should

be about 500ns with 100ns guard band. The duty cycle

effective I

current out of the f

pin to 24µA. The

fSET

f

pin is 4.5V/3 =1.5V and V

= 3.3V, therefore 130k

SET

OUT

will source 14µA into the f

node and lower the I

fSET

SET

current to 24µA. This enables the 540kHz operation and

the 4.5V to 20V input operation for down converting to

3.3V output. The frequency will scale from 540kHz to 1.1

MHz over this input range. This provides for an effective

output current of 8A over the input range.

for (3.3V/4.5) = ~73%. Frequency = (1 – DC)/t , or

OFF

(1–0.73)/500ns=540kHz.Theswitchingfrequencyneeds

tobeloweredto540kHzat4.5Vinput. t =DC/frequency,

ON

or1.35µs.Thef pinvoltagecomplianceis1/3ofV ,and

SET

IN

the I

current equates to 38µA with the internal 39.2k.

fSET

V

OUT

TRACK/SS CONTROL

V

IN

10V TO 20V

REVIEW TEMPERATURE

R2

R4

V

PLLIN TRACK/SS

DERATING CURVE

V

5V

8A

IN

100k 100k

OUT

PGOOD

V

OUT

C3

C6 100pF

+

MPGM

RUN

V

100µF

6.3V

SANYO POSCAP

FB

REFER TO

TABLE 2

MARG0

MARG1

COMP

INTV

DRV

LTM4601-1

V

CC

OUT_LCL

NC3

5% MARGIN

NC1

NC2

R1

392k

1%

C2

10µF

f

SGND PGND

SET

25V

C1

R

SET

8.25k

10µF

fSET

100k

25V

MARGIN CONTROL

IMPROVE

EFFICIENCY

SOT-323

FOR ≥12V INPUT

DUAL

CMSSH-3C3

4601 F16

Figure 16. 5V at 8A Design Without Differential Ampliﬁer

4601f

21

LTM4601/LTM4601-1

U

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APPLICATIO S I FOR ATIO

V

OUT

TRACK/SS CONTROL

V

IN

4.5V TO 16V

REVIEW TEMPERATURE

DERATING CURVE

R2

R4

V

PLLIN TRACK/SS

V

3.3V

10A

IN

100k 100k

OUT

PGOOD

V

OUT

C6 100pF

PGOOD

MPGM

RUN

COMP

V

FB

MARG0

MARG1

C3

+

100µF

LTM4601

6.3V

INTV

V

OUT_LCL

CC

SANYO POSCAP

DRV

DIFFV

V

OUT

+

C2

OSNS

10µF

25V

×3

R1

392k

–

OSNS

R

f

fSET

SGND PGND

SET

R

SET

130k

13.3k

5% MARGIN

MARGIN CONTROL

4601 F17

Figure 17. 3.3V at 10A Design

CLOCK SYNC

C5

0.01µF

V

OUT

V

IN

4.5V TO 20V

REVIEW TEMPERATURE

DERATING CURVE

R2

R4

V

PLLIN TRACK/SS

V

1.5V

12A

IN

100k

OUT

PGOOD

V

OUT

C3 100pF

+

C

OUT2

PGOOD

MPGM

RUN

V

OUT1

FB

100µF

470µF

MARG0

MARG1

V

OUT_LCL

MARGIN

CONTROL

6.3V

ON/OFF

COMP

INTV

DRV

LTM4601

CC

DIFFV

OUT

+

C

IN

R1

392k

V

OSNS

BULK

OPT

–

REFER TO

TABLE 2 FOR

DIFFERENT

OUTPUT

OSNS

C

IN

f

10µF

25V

SGND PGND

SET

R

SET

40.2k

×3 CER

VOLTAGE

4601 F18

5% MARGIN

Figure 18. Typical 4.5V-20V_IN, 1.5V at 12A Design

4601f

22

LTM4601/LTM4601-1

U

W U U

APPLICATIO S I FOR ATIO

60.4k

+ R

SET

V

OUT

N

V

= 0.6V

OUT

R

SET

CLOCK SYNC

0° PHASE

N = NUMBER OF PHASES

TRACK/SS CONTROL

V

IN

4.5V TO 20V

R2

100k

R4

100k

V

PLLIN TRACK/SS

IN

V

OUT

1.5V

PGOOD

V

OUT

C6 220pF

24A

C3

MPGM

RUN

V

FB

MARG0

MARG1

22µF

6.3V

COMP

INTV

DRV

+

LTM4601

C4

V

OUT_LCL

CC

470µF

6.3V

+

C5*

100µF

25V

DIFFV

V

OUT

+

C1

0.1µF

OSNS

LTC6908-1

+

REFER TO

TABLE 2

–

V

OSNS

C2

10µF

25V

×2

1

2

3

6

5

4

118k

1%

V

OUT1

R1

392k

f

SGND PGND

SET

R

SET

20k

100pF

GND OUT2

SET

MOD

5%

MARGIN

MARGIN CONTROL

2-PHASE

OSCILLATOR

CLOCK SYNC

180° PHASE

TRACK/SS CONTROL

4.5V TO 20V

C7

0.033µF

V

PLLIN TRACK/SS

IN

PGOOD

V

OUT

+

C4

470µF

6.3V

C3

22µF

6.3V

MPGM

RUN

COMP

INTV

CC

DRV

CC

V

FB

MARG0

MARG1

C8

10µF

25V

×2

LTM4601-1

REFER TO

TABLE 2

V

OUT_LCL

NC3

NC2

NC1

392k

f

SGND PGND

SET

4601 F19

*C5 OPTIONAL TO REDUCE ANY LC RINGING.

NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTION

Figure 19. 2-Phase Parallel, 1.5V at 24A Design

4601f

23

LTM4601/LTM4601-1

U

TYPICAL APPLICATIO S

4601f

24

LTM4601/LTM4601-1

U

PACKAGE DESCRIPTIO

Z

b b b

Z

6 . 9 8 5 0

5 . 7 1 5 0

4 . 4 4 5 0

3 . 1 7 5 0

1 . 9 0 5 0

0 . 6 3 5 0

0 . 0 0 0 0

0 . 6 3 5 0

1 . 9 0 5 0

3 . 1 7 5 0

4 . 4 4 5 0

5 . 7 1 5 0

6 . 9 8 5 0

4601f

25

LTM4601/LTM4601-1

U

PACKAGE DESCRIPTIO

Pin Assignment Tables

(Arranged by Pin Number)

PIN NAME

E1 PGND

E2 PGND

E3 PGND

E4 PGND

E5 PGND

E6 PGND

E7 PGND

PIN NAME

F1 PGND

F2 PGND

F3 PGND

F4 PGND

F5 PGND

F6 PGND

F7 PGND

F8 PGND

F9 PGND

A1

A2

A3

A4

A5

A6

V

B1

B2

B3

B4

B5

B6

B7

B8

V

-

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

V

-

D1 PGND

D2 PGND

D3 PGND

D4 PGND

D5 PGND

D6 PGND

IN

A7 INTV

D7

-

CC

A8 PLLIN

-

D8

E8

-

A9 TRACK/SS B9

-

D9

E9

A10 RUN

B10

-

D10

D11

E10

E11

F10

F11

F12

-

A11 COMP

A12 MPGM

B11

B12

-

f

C12 MARG0

D12 MARG1

E12 DRV

V

SET

CC

FB

PIN NAME

G1 PGND

G2 PGND

G3 PGND

G4 PGND

G5 PGND

G6 PGND

G7 PGND

G8 PGND

G9 PGND

PIN NAME

H1 PGND

H2 PGND

H3 PGND

H4 PGND

H5 PGND

H6 PGND

H7 PGND

H8 PGND

H9 PGND

PIN NAME

J1

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

-

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

L1

V

M1

M2

M3

M4

M5

M6

M7

M8

M9

V

OUT

OUT_LCL

OUT

OSNS

J2

L2

J3

L3

J4

L4

J5

L5

J6

L6

J7

L7

J8

L8

J9

L9

G10

G11

-

H10

H11

-

J10

J11

J12

L10

L11

L12

M10 V

M11 V

M12 V

+

–

G12 PGOOD

H12 SGND

V

K12 DIFFV

OUT

OSNS

4601f

26

LTM4601/LTM4601-1

U

PACKAGE DESCRIPTIO

Pin Assignment Tables

(Arranged by Pin Function)

PIN NAME

PGND

PIN NAME

A1

A2

A3

A4

A5

A6

V

D1

D2

D3

D4

D5

D6

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

A7

INTVCC

PLLIN

B7

-

IN

PGND

A8

B8

A9

TRACK/SS

RUN

B9

B10

B11

A10

A11

A12

COMP

MPGM

C7

-

B1

B2

B3

B4

B5

B6

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

E1

E2

E3

E4

E5

E6

E7

PGND

B12

C12

D12

E12

F12

G12

H12

J12

K12

L12

M12

f

C8

SET

C9

MARG0

MARG1

C10

C11

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

V

OUT

DRV

D7

-

CC

D8

V

FB

C1

C2

C3

C4

C5

C6

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

D9

PGOOD

F1

F2

F3

F4

F5

F6

F7

F8

F9

PGND

D10

D11

SGND

+

E8

E9

E10

E11

-

V

OSNS

DIFFV

OUT

V

OUT_LCL

–

F10

F11

-

OSNS

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

V

OUT

G10

G11

-

G1

G2

G3

G4

G5

G6

G7

G8

G9

PGND

H10

H11

-

J11

-

H1

H2

H3

H4

H5

H6

H7

H8

H9

PGND

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

V

OUT

4601f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTM4601/LTM4601-1

RELATED PARTS

PART NUMBER

LTC2900

DESCRIPTION

COMMENTS

Quad Supply Monitor with Adjustable Reset Timer

Power Supply Tracking Controller

Synchronous Isolated Flyback Controllers

10A DC/DC µModule

Monitors Four Supplies; Adjustable Reset Timer

Tracks Both Up and Down; Power Supply Sequencing

No Optocoupler Required; 3.3V, 12A Output; Simple Design

Basic 10A DC/DC µModule

LTC2923

LT3825/LT3837

LTM4600

LTM4601

12A DC/DC µModule with PLL, Output Tracking/

Margining and Remote Sensing

Synchronizable, PolyPhase Operation to 48A, LTM4601-1 Version has no

Remote Sensing

LTM4602

LTM4603

6A DC/DC µModule

Pin Compatible with the LTM4600

6A DC/DC µModule with PLL and Outpupt Tracking/ Synchronizable, PolyPhase Operation to 48A, LTM4601-1 Version has no

Margining and Remote Sensing

Remote Sensing, Pin Compatible with the LTM4601

®

This product contains technology licensed from Silicon Semiconductor Corporation.

4601f

LT 0107 • PRINTED IN USA

LinearTechnology Corporation

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●


型号：	LTM4601
厂家：	Linear
描述：	12A DC/DC μModules with PLL, Output Tracking and Margining 12A DC / DC与PLL ，输出跟踪和裕度μModules
文件：	总28页 (文件大小：385K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4601 [Linear]

相关型号：

LTM4601-1

LTM4601-1_15

LTM4601/

LTM4601A

LTM4601A-1

LTM4601A-1_15

LTM4601AEV#PBF

LTM4601AEV-1-PBF

LTM4601AEV-PBF

LTM4601AHV

LTM4601AHVEV-PBF

LTM4601AHVIV-PBF