LTM4613MPV#PBF [Linear]
LTM4613 - EN55022B Compliant 36VIN, 15VOUT, 8A, DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 133; Temperature Range: -55°C to 125°C;
| 型号： | LTM4613MPV#PBF |
| 厂家： | 
Linear |
| 描述： | LTM4613 - EN55022B Compliant 36VIN, 15VOUT, 8A, DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 133; Temperature Range: -55°C to 125°C 开关 |
| 文件： | 总28页 (文件大小：502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4613
EN55022B Compliant
36V , 15V , 8A,
IN
OUT
DC/DC µModule Regulator
DESCRIPTION
The LTM®4613 is a complete, ultralow noise, 8A switch
modeDC/DCpowersupply.Includedinthepackagearethe
switching controller, power FETs, inductor and all support
components. Operating over an input voltage range of 5V
to 36V, the LTM4613 supports an output voltage range of
3.3V to 15V, set by a single external resistor. Only bulk
inputandoutputcapacitorsareneededtofinishthedesign.
FEATURES
n
Complete Low EMI Switch Mode Power Supply
n
EN55022 Class B Compliant
n
Wide Input Voltage Range: 5V to 36V
n
8A Output Current
n
3.3V to 15V Output Voltage Range
n
Low Input and Output Referred Noise
n
Output Voltage Tracking and Margining
n
PLL Frequency Synchronization
High switching frequency and an adaptive on-time current
mode architecture enables a very fast transient response
to line and load changes without sacrificing stability.
n
2% Maximum Total DC Error
n
Power Good Tracks with Margining
n
Current Foldback Protection
n
The onboard input filter and noise cancellation circuits
achieve low noise coupling, thus effectively reducing
the electromagnetic interference (EMI)—see Figure 7.
Furthermore, the DC/DC µModule® regulator can be syn-
chronized with an external clock to reduce undesirable
frequency harmonics and allow PolyPhase® operation for
high load currents.
Parallel/Current Sharing
n
Ultrafast Transient Response
n
Current Mode Control
n
Programmable Soft-Start
n
Output Overvoltage Protection
n
–55°C to 125°C Operating Temperature Range
(LTM4613MPV)
n
Small Surface Mount Footprint, Low Profile
The LTM4613 is offered in a space saving and thermally
enhanced 15mm × 15mm × 4.32mm LGA package, which
enables utilization of unused space on the bottom of PC
boards for high density point-of-load regulation. The
LTM4613 is Pb-free and RoHS compliant.
(15mm × 15mm × 4.32mm) LGA Package
APPLICATIONS
n
Telecom and Networking Equipment
n
Industrial and Avionic Equipment
L, LT, LTC, LTM, µModule, PolyPhase, Linear Technology, and the Linear logo are registered
trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
n
RF Systems
TYPICAL APPLICATION
Radiated Emission Scan with 24VIN to 12VOUT at 8A
12V/8A Ultralow Noise µModule with 24V to 36V Input
70
60
CLOCK SYNC
V
IN
24V
TO 36V
51k
V
PLLIN
V
12V
8A
50
40
30
20
10
0
IN
OUT
V
OUT
PGOOD
RUN
EN55022B LIMIT
LTM4613
22pF
C
OUT
COMP
V
FB
5.23k
INTV
DRV
CC
CC
C
IN
FCB
f
SET
MARG0
MARG1
MPGM
MARGIN
TRACK/SS
V
D
CONTROL
0.1µF
10µF
× 3
392k
5% MARGIN
SGND PGND
–10
30
226.2
422.4
613.6
814.3 1010.0
4613 TA01
FREQUENCY (MHz)
4613 TA01b
4613f
1
LTM4613
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
INTV DRV ............................................. –0.3V to 6V
OUT
CC,
CC
V
........................................................... –0.3V to 16V
PLLIN, FCB, TRACK/SS, MPGM, MARG0,
A
B
C
D
E
V
IN
MARG1, PGOOD ....................–0.3V to INTV + 0.3V
CC
f
BANK 1
SET
V
D
MARG0
MARG1
RUN .............................................................–0.3V to 5V
SGND
V , COMP................................................ –0.3V to 2.7V
FB
DRV
CC
PGND
BANK 2
V , V ....................................................... –0.3V to 36V
F
V
IN
D
FB
G
H
J
K
L
PGOOD
SGND
NC
NC
NC
Internal Operating Temperature Range (Note 2)
E- and I-Grades..................................–40°C to 125°C
MP-Grade .......................................... –55°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Package Body Temperature.......................... 245°C
V
OUT
BANK 3
FCB
M
1
2 3 4 5 6 7 8 9 10 11 12
LGA PACKAGE
133-LEAD (15mm × 15mm × 4.32mm)
T
JMAX
= 125°C, θ
= 17°C/w, θ
= 2.3°C/W, θ = 11°C/W to 14°C/W,
JCtop
JCbottom JA
θ
DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS
JA
WEIGHT = 1.7g
ORDER INFORMATION
LEAD FREE FINISH
LTM4613EV#PBF
LTM4613IV#PBF
LTM4613MPV#PBF
TRAY
PART MARKING*
LTM4613V
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LTM4613EV#PBF
LTM4613IV#PBF
LTM4613MPV#PBF
133-Lead (15mm × 15mm × 4.32mm) LGA
133-Lead (15mm × 15mm × 4.32mm) LGA
133-Lead (15mm × 15mm × 4.32mm) LGA
LTM4613V
–40°C to 125°C
LTM4613V
–55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
4613f
2
LTM4613
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 24V, unless otherwise noted. Per Typical
Application (front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
V
Input DC Voltage
5
36
V
V
IN(DC)
Output Voltage, Total Variation
with Line and Load
11.83 12.07 12.31
C
V
= 10µF × 3, C
= 47µF × 4; FCB = 0,
OUT
OUT(DC)
IN
IN
OUT
= 24V to 36V, V
= 12V
Input Specifications
V
Undervoltage Lockout Threshold
Input Inrush Current at Start-Up
I
I
= 0A
3.2
4.8
V
IN(UVLO)
OUT
OUT
I
= 0A; C = 10µF × 3, C
= 47µF × 4; C = 22nF
SS
INRUSH(VIN)
IN
OUT
V
= 12V
OUT
150
120
mA
mA
V
V
= 24V
= 36V
IN
IN
I
I
Input Supply Bias Current
Input Supply Current
V
V
= 36V, V
= 24V, V
= 12V, Switching Continuous, I
= 12V, Switching Continuous, I
= 0A
= 0A
78
60
50
mA
mA
µA
Q(VIN)
S(VIN)
IN
IN
OUT
OUT
OUT
OUT
Shutdown, RUN = 0, V = 36V
IN
V
IN
V
IN
= 36V, V
= 24V, V
= 12V, I
= 12V, I
= 8A
= 8A
2.90
4.26
A
A
OUT
OUT
OUT
OUT
V
Internal V Voltage
V
= 36V, RUN > 2V, I = 0A
OUT
4.7
0
5
5.3
V
INTVCC
CC
IN
Output Specifications
I
Output Continuous Current Range
Line Regulation Accuracy
V
V
= 24V, V
= 12V (Note 4)
OUT
8
A
OUT(DC)
IN
∆V
= 12V, FCB = 0V, V = 24V to 36V,
OUT(LINE)
OUT
OUT
IN
l
I
= 0A
0.05
0.3
%
V
OUT
∆V
Load Regulation Accuracy
Input Ripple Voltage
V
= 12V, FCB = 0V, I
IN
IN
= 0A to 8A (Note 4)
OUT(LOAD)
OUT
V
V
OUT
l
l
= 36V
= 24V
0.5
0.5
0.75
0.75
%
%
V
OUT
V
IN(AC)
I
= 0A,
OUT
C
= 1 × 10µF X5R Ceramic and 1 × 100µF Electrolytic,
IN
3 × 10µF X5R Ceramic on V Pins
D
V
= 24V, V
= 12V (Note 5)
10
mV
mV
IN
OUT
P-P
P-P
V
Output Ripple Voltage
I
= 0A,
OUT(AC)
OUT
C
= 1 × 10µF, 4 × 47µF X5R Ceramic
OUT
V
= 24V, V
= 12V
OUT
19
IN
f
Output Ripple Voltage Frequency
Turn-On Overshoot
V
C
= 24V, V
= 12V, I = 0A
OUT
600
kHz
S
IN
OUT
∆V
= 47µF × 4, V
IN
IN
= 12V, I
= 12V, I
= 0A, C = 22nF
OUT(START)
OUT
V
V
OUT
OUT
SS
20
20
mV
mV
= 36V
= 24V
t
Turn-On Time
C
= 47µF × 4, V
IN
IN
= 0A, C = Open
START
OUT
V
V
OUT
OUT
SS
0.3
0.3
ms
ms
= 36V
= 24V
∆V
Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load
= 1 × 10µF, 3 × 47µF X5R Ceramic, 1 × 47µF POSCAP
OUT(LS)
C
250
100
mV
µs
OUT
V
= 24V, V
= 12V
OUT
IN
t
I
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load
SETTLE
C
= 1 × 10µF, 3 × 47µF X5R Ceramic, 1 × 47µF POSCAP
OUT
V
IN
= 24V, V
= 12V
OUT
Output Current Limit
C
= 47µF × 4
OUT(PK)
OUT
V
V
12
12
A
A
= 36V, V
= 24V, V
= 12V
= 12V
IN
IN
OUT
OUT
4613f
3
LTM4613
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 24V, unless otherwise noted. Per Typical
Application (front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Control Section
l
V
V
Voltage at V Pin
I
= 0A, V = 12V
OUT
0.591
1
0.6
1.5
–1.5
0.6
–1
0.609
1.9
V
V
FB
FB
OUT
RUN Pin On/Off Threshold
Soft-Start Charging Current
Forced Continuous Threshold
Forced Continuous Pin Current
Minimum On-Time
RUN
I
V
V
= 0V
SS/TRACK
–1
–2
µA
V
SS/TRACK
V
FCB
0.57
0.63
–2
I
t
t
= 0V
FCB
µA
ns
ns
kΩ
mA
kΩ
FCB
(Note 3)
(Note 3)
50
100
400
ON(MIN)
OFF(MIN)
Minimum Off-Time
250
50
R
PLLIN Input Resistor
PLLIN
I
Current into DRV Pin
V
= 12V, I
= 0A, DRV = 5V
22
30
DRVCC
CC
OUT
OUT
CC
R
Resistor Between V
Pins
and V
FB
99.5
100
100.5
FBHI
OUT
V
Margin Reference Voltage
1.18
1.4
V
V
MPGM
V
V
,
MARG0, MARG1 Voltage
Thresholds
MARG0
MARG1
PGOOD
∆V
∆V
∆V
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
V
V
V
Rising
Falling
7
10
–10
1.5
0.2
13
%
%
%
V
FBH
FBL
FB
–7
–13
FB
Returning
FB(HYS)
FB
V
PGOOD Low Voltage
I
= 5mA
0.4
PGL
PGOOD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
is guaranteed and tested over the full –55°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 2: The LTM4613 is tested under pulsed load conditions such that
T ≈ T . The LTM4613E is guaranteed to meet performance specifications
Note 3: 100% tested at die level only.
J
A
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4613I is guaranteed to meet specifications over the
–40°C to 125°C internal operating temperature range. The LTM4613MP
Note 4: See the Output Current Derating curves for different V , V
IN OUT
and T .
A
Note 5: Guaranteed by design.
4613f
4
LTM4613
TYPICAL PERFORMANCE CHARACTERISTICS (Refer to Figure 18)
Efficiency vs Load Current with
3.3VOUT (FCB = 0)
Efficiency vs Load Current with
5VOUT (FCB = 0)
Efficiency vs Load Current with
12VOUT (FCB = 0)
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
5V , 3.3V
20V , 12V
IN
IN
OUT
OUT
OUT
OUT
OUT
12V , 5V
IN
12V , 3.3V
IN
24V , 12V
IN
OUT
OUT
OUT
OUT
OUT
OUT
24V , 5V
IN
24V , 3.3V
IN
36V , 3.3V
IN
28V , 12V
IN
36V , 12V
IN
36V , 5V
IN
4
5
4
5
4
5
0
1
2
3
6
7
8
0
1
2
3
6
7
8
0
1
2
3
6
7
8
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4613 G01
4613 G02
4613 G03
Efficiency vs Load Current with
15VOUT (FCB = 0)
Transient Response from 12VIN
to 3.3VOUT
Transient Response from 12VIN
to 5VOUT
100
95
90
85
80
75
70
65
60
I
I
OUT
OUT
5A/DIV
5A/DIV
V
OUT
V
OUT
100mV/DIV
AC
100mV/DIV
AC
4613 G06
4613 G05
100µs/DIV
LOAD STEP: 0A TO 4A
= 1 × 47µF POSCAP
100µs/DIV
LOAD STEP: 0A TO 4A
= 1 × 47µF POSCAP
24V , 15V
IN
OUT
OUT
OUT
OUT
C
C
28V , 15V
OUT
OUT
IN
1 × 10µF CERAMIC CAPACITOR AND
3 × 47µF CERAMIC CAPACITORS
1 × 10µF CERAMIC CAPACITOR AND
3 × 47µF CERAMIC CAPACITORS
32V , 15V
IN
36V , 15V
IN
4
5
0
1
2
3
6
7
8
LOAD CURRENT (A)
4613 G04
Transient Response from 24VIN
to 12VOUT
Start-Up with 24VIN to 12VOUT
at IOUT = 0A
Start-Up with 24VIN to 12VOUT at
IOUT = 8A
I
OUT
I
IN
I
IN
5A/DIV
1A/DIV
200mA/DIV
V
V
OUT
5V/DIV
OUT
V
OUT
200mV/DIV
AC
5V/DIV
4613 G08
4613 G09
4613 G07
10ms/DIV
10ms/DIV
100µs/DIV
LOAD STEP: 0A TO 4A
= 1 × 47µF POSCAP
SOFT-START CAPACITOR: 0.1µF
SOFT-START CAPACITOR: 0.1µF
C
= 2 × 10µF CERAMIC CAPACITORS AND
C
= 2 × 10µF CERAMIC CAPACITORS AND
C
IN
IN
OUT
1 × 100µF OS-CON CAPACITOR
1 × 100µF OS-CON CAPACITOR
1 × 10µF CERAMIC CAPACITOR AND
3 × 47µF CERAMIC CAPACITORS
4613f
5
LTM4613
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up with 24VIN to 12VOUT at
IOUT = 8A, TA = –55°C
Short-Circuit with 24VIN to 12VOUT
at IOUT = 0A
Short-Circuit with 24VIN to 12VOUT
at IOUT = 8A
I
I
IN
2A/DIV
IN
I
500mA/DIV
OUT
2A/DIV
V
OUT
V
V
OUT
OUT
5V/DIV
5V/DIV
5V/DIV
4613 G10
4613 G11
4613 G12
20ms/DIV
SOFT-START CAPACITOR: 0.1µF
20µs/DIV
20µs/DIV
C
= 1 × 47µF POSCAP,
C
= 1 × 47µF POSCAP,
OUT
OUT
C
= 2 × 10µF CERAMIC CAPACITORS AND
IN
1 × 10µF CERAMIC CAPACITORS
1 × 10µF CERAMIC CAPACITORS
1 × 100µF OS-CON CAPACITOR
AND 3 × 47µF CERAMIC CAPACITORS
AND 3 × 47µF CERAMIC CAPACITORS
VIN to VOUT Step-Down Ratio
Input Ripple
Output Ripple
36
30
24
18
12
6
V
V
IN
OUT
100mV/DIV
AC
10mV/DIV
AC
4613 G14
4613 G15
1µs/DIV
1µs/DIV
V
V
C
= 24V
V
V
C
= 24V
IN
OUT
IN
IN
= 12V AT 8A RESISTIVE LOAD
= 2 × 10µF CERAMIC CAPACITORS AND
= 12V AT 8A RESISTIVE LOAD
OUT
OUT
= 1 × 47µF POSCAP
1 × 100µF OS-CON CAPACITOR
1 × 10µF CERAMIC CAPACITOR AND
3 × 47µF CERAMIC CAPACITORS
0
3.3
7
9
11
13
15
5
OUTPUT VOLTAGE (V)
4613 G13
4613f
6
LTM4613
PIN FUNCTIONS (See Package Description for Pin Assignments)
V (Bank 1): Power Input Pins. Apply input voltage be-
FCB(PinM12):ForcedContinuousInput.Connectthispin
IN
tween these pins and PGND pins. Recommend placing
to SGND to force continuous synchronization operation
input decoupling capacitance directly between V pins
at light load or to INTV to enable discontinuous mode
IN
CC
and PGND pins.
operation at light load.
PGND (Bank 2): Power Ground Pins for Both Input and
TRACK/SS(PinA9):OutputVoltageTrackingandSoft-Start
Pin. When the module is configured as a master output,
then a soft-start capacitor is placed on this pin to ground
to control the master ramp rate. A soft-start capacitor can
be used for soft-start turn-on as a standalone regulator.
Slave operation is performed by putting a resistor divider
from the master output to the ground, and connecting the
center point of the divider to this pin. See the Applications
Information section.
Output Returns.
V
(Bank 3): Power Output Pins. Apply output load
OUT
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins (see the LTM4613 Pin Configuration below).
V (Pins C1 to C7, B6 to B7, A6): Top FET Drain Pins.
D
Add more high frequency ceramic decoupling capacitors
between V and PGND to handle the input RMS current
D
MPGM (Pins A12, B11): Programmable Margining In-
put. A resistor from these pins to ground sets a current
that is equal to 1.18V/R. This current multiplied by 10k
will equal a value in millivolts that is a percentage of the
0.6V reference voltage. Leave floating if margining is not
used. SeetheApplicationsInformationsection. Toparallel
LTM4613s, each requires an individual MPGM resistor. Do
not tie MPGM pins together.
and reduce the input ripple further.
DRV (Pins C10, E11, E12): These pins normally con-
CC
nect to INTV for powering the internal MOSFET drivers.
CC
They can be biased up to 6V from an external supply
with about 50mA capability. This improves efficiency at
the higher input voltages by reducing power dissipation
in the module. See the Applications Information section.
INTV (Pin A7): This pin is for additional decoupling of
CC
f
(Pin B12): Frequency Set Internally to 600kHz at 12V
SET
the 5V internal regulator.
Output. An external resistor can be placed from this pin
to ground to increase frequency or from this pin to V
to reduce frequency. See the Applications Information
section for frequency adjustment.
PLLIN(PinA8):ExternalClockSynchronizationInputtothe
Phase Detector. This pin is internally terminated to SGND
with a 50k resistor. Apply a clock above 2V and below
IN
INTV subjecttominimumon-timeandminimumoff-time
CC
requirements. See the Applications Information section.
TOP VIEW
A
B
C
D
E
V
IN
f
BANK 1
SET
V
D
SGND
MARG0
MARG1
DRV
V
FB
PGOOD
SGND
NC
CC
PGND
BANK 2
F
G
H
J
V
K
L
NC
NC
OUT
BANK 3
FCB
M
1
2 3 4 5 6 7 8 9 10 11 12
LGA PACKAGE
133-LEAD (15mm × 15mm × 4.32mm)
LTM4613 Pin Configuration
4613f
7
LTM4613
PIN FUNCTIONS
V
(Pin F12): The Negative Input of the Error Ampli-
COMP (Pins A11, D11): Current Control Threshold and
Error Amplifier Compensation Point. The current com-
parator threshold increases with this control voltage. The
voltage ranges from 0V to 2.4V with 0.7V corresponding
to zero sense voltage (zero current).
FB
fier. Internally, this pin is connected to V
with a 100k
OUT
0.5% precision resistor. Different output voltages can be
programmed with an additional resistor between the V
FB
and SGND pins. See the Applications Information section.
MARG0 (Pin C12): LSB Logic Input for the Margining
Function. Together with the MARG1 pin, the MARG0 pin
will determine if a margin high, margin low, or no margin
state is applied. The pin has an internal pull-down resistor
of 50k. See the Applications Information section.
PGOOD (Pin G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within 10% of the regulation point,
after a 25µs power bad mask timer expires.
RUN (Pins A10, B9): Run Control Pins. A voltage above
1.9V will turn on the module, and below 1V will turn off
the module. A programmable UVLO function can be ac-
MARG1(PinsC11, D12):MSBLogicInputfortheMargin-
ingFunction.TogetherwiththeMARG0pin,theMARG1pin
will determine if a margin high, margin low, or no margin
stateisapplied.Thepinshaveaninternalpull-downresistor
of 50k. See the Applications Information section.
complished with a resistor from V to this pin that has a
IN
5.1V Zener to ground. Maximum pin voltage is 5V.
MTP (Pins J12, K12, L12): No Connect Pins. Leave float-
ing. Used for mounting to PCB.
SGND (Pins D9, H12): Signal Ground Pins. These pins
connect to PGND at output capacitor point.
4613f
8
LTM4613
BLOCK DIAGRAM
> 1.9V = ON
< 1V = OFF
MAX = 5V
V
OUT
RUN
PGOOD
COMP
INPUT
FILTER
V
IN
24V TO 36V
+
5.1V
ZENER
1µF
C
IN
100k
V
D
INTERNAL
COMP
10µF
50V
× 3
POWER CONTROL
M1
M2
SGND
2.2µH
V
OUT
12V
MARG1
MARG0
AT 8A
NOISE
V
FB
10µF
50k 50k
CANCEL-
LATION
+
f
SET
R
FB
C
OUT
5.23k
133k
PGND
FCB
10k
MPGM
TRACK/SS
PLLIN
C
SS
50k
4.7µF
INTV
DRV
CC
CC
Figure 1. Simplified Block Diagram
DECOUPLING REQUIREMENTS Specifications are at TA = 25°C. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
External Input Capacitor Requirement
IN
I
= 8A
30
100
µF
IN
OUT
(V = 24V to 36V, V
= 12V)
OUT
C
External Output Capacitor Requirement
(V = 24V to 36V, V = 12V)
I
= 8A
100
220
µF
OUT
OUT
IN
OUT
4613f
9
LTM4613
OPERATION
Power Module Description
off and bottom FET M2 is turned on and held on until the
overvoltage condition clears.
The LTM4613 is a standalone nonisolated switch mode
DC/DC power supply. It can deliver 8A of DC output cur-
rent with minimal external input and output capacitors.
This module provides a precisely regulated output voltage
Input filter and noise cancellation circuitry reduce the
noise coupling to inputs and outputs, and ensure the
electromagnetic interference (EMI) meets the limits of
EN55022 Class B (see Figure 7).
programmable via one external resistor from 3.3V to
DC
15V over a wide 5V to 36V input voltage. The typical
application schematic is shown in Figure 18.
DC
Pulling the RUN pin below 1V forces the controller into
its shutdown state, turning off both M1 and M2. At light
load currents, discontinuous mode (DCM) operation can
be enabled to achieve higher efficiency compared to con-
tinuous mode (CCM) by setting FCB pin higher than 0.6V.
The LTM4613 has an integrated constant on-time current
mode regulator, ultralow R
FETs with fast switching
DS(ON)
speedandintegratedSchottkydiodes.Thetypicalswitching
frequencyis600kHzatfullloadat12Voutput.Withcurrent
mode control and internal feedback loop compensation,
the LTM4613 module has sufficient stability margins and
good transient performance under a wide range of operat-
ing conditions and with a wide range of output capacitors,
even all ceramic output capacitors.
WhentheDRV pinisconnectedtoINTV , anintegrated
CC
CC
5V linear regulator powers the internal gate drivers. If a
5V external bias supply is applied on DRV pin, then an
CC
efficiencyimprovementwilloccurduetothereducedpower
loss in the internal linear regulator. This is especially true
at the higher input voltage range.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limiting. Moreover, foldback current limiting is provided in
The MPGM, MARG0, and MARG1 pins are used to sup-
port voltage margining, where the percentage of margin
is programmed by the MPGM pin, while the MARG0 and
MARG1 select positive or negative margining. The PLLIN
pin provides frequency synchronization of the device to
an external clock. The TRACK/SS pin is used for power
supply tracking and soft-start programming.
an overcurrent condition when V drops. Internal over-
FB
voltageandundervoltagecomparatorspulltheopen-drain
PGOOD output low if the output feedback voltage exits a
10% window around the regulation point. Furthermore,
in an overvoltage condition, internal top FET M1 is turned
APPLICATIONS INFORMATION
The typical LTM4613 application circuit is shown in Fig-
ure 18. External component selection is primarily deter-
minedbytheinputvoltage, themaximumloadcurrentand
the output voltage. Refer to Table 2 for specific external
capacitor requirements for a particular application.
Output Voltage Programming and Margining
The PWM controller has an internal 0.6V reference volt-
age. As shown in the Block Diagram, a 100k 0.5% internal
feedbackresistorconnectstheV
andV pinstogether.
FB
OUT
FB
Adding a resistor, R , from the V pin to the SGND pin
FB
programs the output voltage.
V to V
Stepdown Ratios
IN
OUT
100k + RFB
VOUT = 0.6V •
RFB
There are restrictions in the maximum V and V
step
IN
OUT
down ratio that can be achieved for a given input voltage.
These constraints are shown in the Typical Performance
or equivalently,
Characteristic curve labeled “V to V
Step-Down
IN
OUT
Ratio.” Note that additional thermal derating may be ap-
plied. See the Thermal Considerations and Output Current
Derating section in this data sheet.
100k
R
=
FB
V
OUT
− 1
0.6V
4613f
10
LTM4613
APPLICATIONS INFORMATION
Table 1. RFB Standard 1% Resistor Values vs VOUT
Operating Frequency
V
R
(V)
3.3
5
6
8
10
12
14
15
OUT
The operating frequency of the LTM4613 is optimized to
achieve the compact package size and the minimum
output ripple voltage while still keeping high efficiency.
As shown in Figure 2, the frequency is linearly increased
with larger output voltages to keep the low output cur-
rent ripple. Figure 3 shows the inductor current ripple ∆I
with different output voltages. In most applications, no
additional frequency adjusting is required.
(kΩ) 22.1 13.7
11
8.06 6.34 5.23 4.42 4.12
FB
The MPGM pin programs a current that when multiplied
by an internal 10k resistor sets up the 0.6V reference
offset for margining. A 1.18V reference divided by the
R
PGM
resistor on the MPGM pin programs the current.
Calculate V
:
OUT(MARGIN)
%VOUT
100
If lower output ripple is required, the operating frequency
VOUT(MARGIN)
=
• VOUT
f can be increased by adding a resistor R
pin and SGND, as shown in Figure 19.
between f
fSET
SET
Where %V
is the percentage of V
to be margined,
OUT
OUT
and V
is the margin quantity in volts:
OUT(MARGIN)
VOUT
f =
1.5 •10− 10
R
(
||133k
fSET
VOUT
1.18V
0.6V VOUT(MARGIN)
)
RPGM
=
•
•10k
1000
800
600
400
200
0
Where R
is the resistor value to place on the MPGM
PGM
pin to ground.
The output margining will be margining of the value.
This is controlled by the MARG0 and MARG1 pins. See
the truth table below:
MARG1
LOW
MARG0
LOW
MODE
NO MARGIN
MARGIN UP
MARGIN DOWN
NO MARGIN
LOW
HIGH
LOW
2
4
6
8
10
OUTPUT VOLTAGE (V)
12
14
16
HIGH
HIGH
HIGH
4613 F02
Figure 2. Operating Frequency vs Output Voltage
Parallel Operation
9
8
7
6
5
4
3
The LTM4613 device is an inherently current mode con-
trolled device. This allows the paralleled modules to have
very good current sharing and balanced thermal on the
design.Figure21showsaschematicoftheparalleldesign.
The voltage feedback equation changes with the variable
N as modules are paralleled. The equation:
100k
V
V
V
V
= 16V
= 24V
= 28V
= 36V
IN
IN
IN
IN
2
1
0
N
VOUT
RFB =
− 1
2
4
6
8
16
10
12
14
0.6V
OUTPUT VOLTAGE (V)
4613 F03
where N is the number of paralleled modules.
Figure 3. Pk-Pk Inductor Current Ripple vs Output Voltage
4613f
11
LTM4613
APPLICATIONS INFORMATION
For output voltages more than 12V, the frequency can be
higher than 600kHz, thus reducing the efficiency signifi-
cantly. Additionally, the minimum off time 400ns normally
limits the operation when the input voltage is close to the
output voltage. Therefore, it is recommended to lower the
frequency in these conditions by connecting a resistor
required. Always contact the capacitor manufacturer for
derating requirements.
In a typical 8A output application, three very low ESR,
X5R or X7R, 10µF ceramic capacitors are recommended
for C1-C3. This decoupling capacitance should be placed
directly adjacent to the module V pins in the PCB layout
D
(R ) from the f pin to V , as shown in Figure 20.
fSET
SET
IN
to minimize the trace inductance and high frequency AC
noise. Each 10µF ceramic is typically good for 2A of RMS
ripple current. Refer to your ceramics capacitor catalog
for the RMS current ratings.
VOUT
f =
3 •RfSET •133k
5 •10− 11
R
− 2 •133k
fSET
Toattenuatethehighfrequencynoise,extrainputcapacitors
should be connected to the V pads and placed before the
The load current can affect the frequency due to its con-
stant on-time control. If constant frequency is a necessity,
the PLLIN pin can be used to synchronize the frequency
of the LTM4613 to an external clock subject to minimum
on-time and off-time limits, as shown in Figures 21 to 23.
IN
high frequency inductor to form the π filter. One of these
low ESR ceramic input capacitors is recommended to be
closetotheconnectionintothesystemboard. Alargebulk
100µF capacitor is only needed if the input source imped-
ance is compromised by long inductive leads or traces.
Input Capacitors
Output Capacitors
LTM4613 is designed to achieve the low input conducted
EMI noise due to the fast switching of turn-on and turn-
off. Additionally, a high-frequency inductor is integrated
The LTM4613 is designed for low output voltage ripple.
The bulk output capacitors defined as C
are chosen
OUT
with low enough effective series resistance (ESR) to meet
into the input line for noise attenuation. V and V pins
D
IN
theoutputvoltagerippleandtransientrequirements. C
are available for external input capacitors to form a high
OUT
can be low ESR tantalum capacitor, low ESR polymer ca-
pacitor or ceramic capacitor. The typical capacitance is 4 ×
47µF if all ceramic output capacitors are used. Additional
output filtering may be required by the system designer,
if further reduction of output ripple or dynamic transient
spikeisrequired.Table2showsamatrixofdifferentoutput
voltages and output capacitors to minimize the voltage
droop and overshoot during a 4A load transient. The table
optimizes total equivalent ESR and total bulk capacitance
to maximize transient performance.
frequency π filter. As shown in Figure 18, the ceramic
capacitors, C1-C3, on the V pins is used to handle most
D
of the RMS current into the converter, so careful attention
is needed for capacitors C1-C3 selection.
For a buck converter, the switching duty cycle can be
estimated as:
VOUT
D=
V
IN
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
Multiphase operation with multiple LTM4613 devices in
parallel will also lower the effective output ripple current
due to the phase interleaving operation. Refer to Figure 4
for the normalized output ripple current versus the duty
cycle. Figure 4 provides a ratio of peak-to-peak output
ripple current to the inductor ripple current as functions
of duty cycle and the number of paralleled phases. Pick
the corresponding duty cycle and the number of phases
to get the correct output ripple current value. For example,
IOUT(MAX)
ICIN(RMS)
=
• D• 1–D
(
)
η
In this equation,
η
is the estimated efficiency of the
power module. Note the capacitor ripple current ratings
are often based on temperature and hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
each phase’s inductor ripple current ∆I is ~5.0A for a 36V
L
4613f
12
LTM4613
APPLICATIONS INFORMATION
Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 19)
TYPICAL MEASURED VALUES
VENDORS
Murata
PART NUMBER
VENDORS
Murata
TDK
PART NUMBER
GRM32ER61C476KEI5L (47µF, 16V)
GRM32ER61C226KE20L (22µF, 16V)
GRM32ER71H106K (10µF, 50V)
C3225X5RIC226M (22µF, 16V)
Murata
LOAD STEP
V
C
C
C
V
DROOP PK-TO-PK RECOVERY
LOAD
SLEW RATE
(A/µS)
R
FB
OUT
IN
IN
OUT1
IN
(V)
3.3
3.3
3.3
3.3
3.3
3.3
5
(CERAMIC)
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
2 × 10µF 50V
(BULK)
(CERAMIC)
2 × 22uF 16V
4 × 47uF 16V
2 × 22uF 16V
4 × 47uF 16V
2 × 22uF 16V
4 × 47uF 16V
2 × 22uF 16V
4 × 47uF 16V
2 × 22uF 16V
4 × 47uF 16V
2 × 22uF 16V
4 × 47uF 16V
2 × 22uF 16V
4 × 47uF 16V
2 × 22uF 16V
4 × 47uF 16V
C
OUT2
(BULK) (V)
150µF 16V
None
150µF 16V
None
150µF 16V
None
150µF 16V
None
150µF 16V
None
150µF 16V
None
150µF 16V
None
(mV)
84
(mV)
175
181
188
191
200
197
222
238
228
238
231
247
363
488
369
500
TIME (µs) STEP (A)
(kΩ)
22.1
22.1
22.1
22.1
22.1
22.1
13.7
13.7
13.7
13.7
13.7
13.7
5.23
5.23
5.23
5.23
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
100µF 50V
5
5
50
40
50
40
50
40
60
50
60
50
60
50
150
90
150
90
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
91
12
12
24
24
12
12
24
24
36
36
24
24
36
36
100
100
113
103
109
122
119
122
125
128
178
238
181
244
5
5
5
5
5
12
12
12
12
150µF 16V
None
1.00
1-PHASE
2-PHASE
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
3-PHASE
4-PHASE
6-PHASE
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
IN
4612 F04
O
Figure 4. Normalized Output Ripple Current vs Duty Cycle, ∆IL = VOT/LI
4613f
13
LTM4613
APPLICATIONS INFORMATION
to 12V design. The duty cycle is about 0.33. The 2-phase
curve shows a ratio of ~0.33 for a duty cycle of 0.33. This
0.33 ratio of output ripple current to the inductor ripple
another regulator can be easily tracked.
Output Voltage Tracking
current ∆I at 5.0A equals 1.65A of the output ripple cur-
L
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. Figure 5 shows an ex-
ample of coincident tracking where the master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider.
Ratiometricmodesoftrackingcanbeachievedbyselecting
differentresistorvaluestochangetheoutputtrackingratio.
The master output must be greater than the slave output
rent (∆I ).
O
The output voltage ripple has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
The equation is:
∆IO
8 • f •N •C
ESR • ∆IO
∆VOUT(P−P)
≈
+
N
OUT
Where f is the frequency and N is the number of paral-
leled phases.
V
IN
Fault Conditions: Current Limit and
Overcurrent Foldback
10µF
51k
×3
V
V
PLLIN
D
IN
SLAVE
PGOOD
V
OUT
OUTPUT
LTM4613 has a current mode controller, which inherently
limitsthecycle-by-cycleinductorcurrentnotonlyinsteady
state operation, but also in transient.
RUN
V
FB
C
OUT
C
COMP
FCB
MARG0
MARG1
MPGM
IN
LTM4613
INTV
CC
CC
MASTER
OUTPUT
DRV
To further limit current in the event of an overload condi-
tion,theLTM4613providesfoldbackcurrentlimiting.Ifthe
output voltage falls by more than 50%, then the maximum
output current is progressively lowered to about one sixth
of its full current limit value.
R2
100k
f
SET
TRACK/SS
SGND PGND
TRACK
CONTROL
R
FB
5.23k
R1
5.23k
4613 F05
Figure 5. Coincident Tracking
Soft-Start and Tracking
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A
capacitor on this pin will program the ramp rate of the
output voltage. A 1.5µA current source will charge up the
external soft-start capacitor to 80% of the 0.6V internal
voltage reference plus or minus any margin delta. This will
control the ramp of the internal reference and the output
voltage. The total soft-start time can be calculated as:
MASTER OUTPUT
SLAVE OUTPUT
OUTPUT
VOLTAGE
CSS
1.5µA
tSOFTSTART ≅ 0.8 • 0.6± 0.6 • V Margin % •
(
)
OUT
4613 F06
TIME
If the RUN pin falls below 2.5V, then the soft-start pin
is reset to allow for the proper soft-start again. Current
foldback and force continuous mode are disabled during
the soft-start process. The soft-start function can also
be used to control the output ramp rising time, so that
Figure 6. Coincident Output Tracking
4613f
14
LTM4613
APPLICATIONS INFORMATION
for the tracking to work. Figure 6 shows the coincident
output tracking.
pin has an internal 5.1V Zener to ground. The pin can be
driven with 5V logic levels.
Ratiometric tracking can be achieved by a few simple
calculationsandtheslewratevalueappliedtothemaster’s
TRACK pin. The TRACK pin has a control range from 0 to
0.6V. The master’s TRACK pin slew rate is directly equal to
the master’s output slew rate in Volts/Time. The equation:
The RUN pin can also be used as an undervoltage lockout
(UVLO) function by connecting a resistor divider from
the input supply to the RUN pin. The equation for UVLO
threshold:
RA + RB
VUVLO
=
•1.5V
RB
MR
•100k = R2
SR
where R is the top resistor, and R is the bottom resistor.
A
B
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus R2 is
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point, and tracks
with margining.
equal the 100k. R is derived from equation:
TA
0.6V
R1=
VTRACK
R2
V
V
FB
FB
+
–
100k RFB
COMP Pin
The pin is the external compensation pin. The module
has already been internally compensated for most output
voltages. Linear Technology provides LTpowerCAD™ for
more control loop optimization.
where V is the feedback voltage reference of the regula-
FB
tor, and V
is 0.6V. Since R2 is equal to the 100k top
TRACK
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then R1 is equal to R with V
=
FB
FB
V
. Therefore R2 = 100k, and R1 = 5.23k in Figure 5.
TRACK
FCB Pin
Inratiometrictracking, adifferentslewratemaybedesired
for the slave regulator. R2 can be solved for when SR is
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold enables discontinuous
operation where the bottom MOSFET turns off when in-
ductor current reverses. FCB pin below the 0.6V threshold
forcescontinuoussynchronousoperation,allowingcurrent
to reverse at light loads and maintaining high frequency
operation.
For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then
R2 = 125k. Solve for R1 to equal to 5.18k.
Each of the TRACK pins will have the 1.5µA current source
on when a resistive divider is used to implement tracking
on that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 100k is
used then a 10k can be used to reduce the TRACK pin
offset to a negligible value.
PLLIN Pin
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector.ThisallowstheinternaltopMOSFETturn-ontobe
lockedtotherisingedgeoftheexternalclock. Theexternal
clock frequency range must be within 30% around the
set operating frequency. A pulse detection circuit is used
to detect a clock on the PLLIN pin to turn on the phase-
locked loop. The pulse width of the clock has to be at least
RUN Enable
The RUN pin is used to enable the power module. The
400ns. The clock high level must be above 2V and clock
4613f
15
LTM4613
APPLICATIONS INFORMATION
low level below 0.3V. During the start-up of the regulator,
the phase-locked loop function is disabled.
to achieve the low radiated EMI noise. Figure 7 shows a
typical example for the LTM4613 to meet the EN55022
Class B radiated emission limit.
INTV and DRV Connection
CC
CC
Thermal Considerations and Output Current Derating
An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRV
In different applications, LTM4613 operates in a variety
of thermal environments. The maximum output current is
limited by the environment thermal condition. Sufficient
cooling should be provided to help ensure reliable opera-
tion. When the cooling is limited, proper output current
derating is necessary, considering ambient temperature,
airflow, input/output condition, and the needfor increased
reliability.
CC
for driving the internal power MOSFETs. Therefore, if
the system does not have a 5V power rail, the LTM4613
can be directly powered by V . The gate driver current
IN
through the LDO is about 20mA. The internal LDO power
dissipation can be calculated as:
P
= 20mA • (V – 5V)
IN
LDO_LOSS
TheLTM4613alsoprovidestheexternalgatedrivervoltage
The thermal resistances reported in the Pin Configura-
tion section of the data sheet are consistent with those
parametersdefinedbyJESD51-9.Theyareintendedforuse
with finite element analysis (FEA) software modeling tools
that leverage the outcome of thermal modeling, simula-
tion and correlation to hardware evaluation performed on
a µModule package mounted to a hardware test board.
This is also defined by JESD51-9, “Test Boards for Area
Array Surface Mount Package Thermal Measurements.”
The motivation for providing these thermal coefficients in
found in JESD51-12, “Guidelines for Reporting and Using
Electronic Package Thermal Information.”
pin DRV . If there is a 5V rail in the system, it is recom-
CC
mended to connect the DRV pin to the external 5V rail.
CC
This is especially true for higher input voltages. Do not
apply more than 6V to the DRV pin.
CC
Radiated EMI Noise
High radiated EMI noise is a disadvantage for switching
regulators by nature. Fast switching turn-on and turn-off
make the large di/dt change in the converters, which act
as the radiation sources in most systems. LTM4613 inte-
grates the feature to minimize the radiated EMI noise to
meet the most applications with low noise requirements.
An optimized gate driver for the MOSFET and a noise
cancellation network are installed inside the LTM4613
Many designers may opt to use laboratory equipment
70
60
50
EN55022B LIMIT
40
30
20
10
0
–10
30
226.2
422.4
613.6
814.3 1010.0
FREQUENCY (MHz)
4613 F07
Figure 7. Radiated Emission Scan with 24VIN to
12VOUT at 8A Measured in 10 Meter Chamber
4613f
16
LTM4613
APPLICATIONS INFORMATION
and a test vehicle, such as the demo board, to anticipate
the µModule regulator’s thermal performance in their ap-
plicationatvariouselectricalandenvironmentaloperating
conditions to compliment any FEA activities. Without
FEA software, the thermal resistances reported in the
Pin Configuration section are in and of themselves not
relevant to providing guidance of thermal performance.
Instead, the derating curves provided in the data sheet
can be used in a manner that yields insight and guid-
ance pertaining to one’s application usage, and can be
adapted to correlate thermal performance to one’s own
application.
dissipation flowing through the bottom of the pack-
age. In the typical µModule regulator, the bulk of the
heat flows out of the bottom of the package, but there
is always heat flow out into the ambient environment.
As a result, this thermal resistance value may be useful
for comparing packages, but the test conditions do not
generally match the user’s application.
•
θ
, the thermal resistance from the junction to the
JCtop
top of the product case, is determined with nearly all of
the component power dissipation flowing through the
top of the package. As the electrical connections of the
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
The Pin Configuration section of the data sheet typi-
cally gives four thermal coefficients, explicitly defined in
JESD51-12. These coefficients are quoted or paraphrased
below:
As in the case of θ
, this value may be useful
JCbottom
for comparing packages, but the test conditions do not
generally match the user’s application.
•
θ ,thethermalresistancefromjunction-to-ambient,is
JA
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
toaJESD51-9definedtestboard,whichdoesnotreflect
an actual application or viable operating condition.
•
θ , the thermal resistance from the junction to the
JB
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
thebottomoftheµModuleregulatorandintotheboard.
It is really the sum of the θ
and the thermal
JCbottom
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from the
package,usingatwo-sided,two-layerboard.Thisboard
is described in JESD51-9.
•
θ
, the thermal resistance from the junction to
JCbottom
thebottomoftheproductcase, isthejunction-to-board
thermal resistance with all of the component power
JUNCTION-TO-AMBIENT RESISTANCE (JESD51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
A
t
JUNCTION-TO-CASE (BOTTOM)
RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
µModule REGULATOR
4613 F08
Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients
4613f
17
LTM4613
APPLICATIONS INFORMATION
A graphical representation of the aforementioned thermal
resistances is given in Figure 8. Blue resistances are
contained within the µModule package, whereas green
resistances are external to the µModule package.
3. The model and FEA software is used to evaluate the
µModule regulator with heat sinks and airflow;
4.Havingsolvedfor,andanalyzedthesethermalresistance
values and simulated various operating conditions in
the software model, a thorough laboratory evaluation
replicatesthesimulatedconditionswiththermocouples
within a controlled environment chamber while operat-
ing the device at the same power loss as that which
was simulated.
As a practical matter, it should be clear to the reader that
no individual or sub group of the four thermal resistance
parameters defined by JESD51-12, or provided in the
Pin Configuration section, replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bottom
An outcome of this process and due diligence yields a set
of derating curves provided in other sections of this data
sheet. After these laboratory tests have been performed
of the package—as the standard defines for θ
JCbottom
and
JCtop
and correlated to the µModule regulator model, the θ
JB
θ
,respectively.Inpractice,powerlossisthermally
and θ are summed together to correlate quite well with
JA
dissipated in both directions away from the package.
Granted, in the absence of a heat sink and airflow, the
majority of the heat flow is into the board.
the µModule regulator model, with no airflow or heat sink-
ing, in a properly defined chamber. This θ + θ value
JB
JA
is shown in the Pin Configuration section, and should
Within a SIP (System-In-Package) module, be aware that
therearemultiplepowerdevicesandcomponentsdissipat-
ingpower,withaconsequencethatthethermalresistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet:
accurately equal the θ value in this section, because
JA
approximately 100% of power loss flows from the junc-
tion through the board into ambient with no airflow or top
mounted heat sink.
The power loss curves in Figures 9 and 10 can be used
in coordination with the load current derating curves in
Figures 11 to 16 for calculating an approximate θ for
JA
the module. Each figure has three curves that are taken
at three different airflow conditions. Graph designation
delineatesbetweennoheatsink,andaBGAheatsink.Each
of the load current derating curves will lower the maxi-
mum load current as a function of the increased ambient
temperature to keep the maximum junction temperature
of the power module at 125°C maximum. This will main-
tain the maximum operating temperature below 125°C.
1. Initially, FEA software is used to accurately build the
mechanical geometry of the µModule regulator and the
specifiedPCBwithallofthecorrectmaterialcoefficients,
along with accurate power loss source definitions;
Table 3 provides the approximate θ for Figures 11 to 16.
JA
2. This model simulates a software-defined JEDEC envi-
ronment consistent with JSED51-9 to predict power
loss heat flow and temperature readings at different
interfaces that enable the calculation of the JEDEC-
defined thermal resistance values;
A complete explanation of the thermal characteristics is
provided in the thermal application note, AN110.
4613f
18
LTM4613
APPLICATIONS INFORMATION
8
7
6
5
7
7
36V TO 5V
IN
OUT
6
6
5
4
3
2
1
0
5
4
3
2
1
0
4
3
2
1
0
OLFM
200LFM
400LFM
36V TO 15V
IN
OUT
OUT
24V TO 12V
IN
65
75
95
55
105
2
4
6
10
85
0
8
2
4
6
10
0
8
AMBIENT TEMPERATURE (°C)
LOAD CURRENT (A)
LOAD CURRENT (A)
4613 F11
4613 F10
4613 F09
Figure 9. Power Loss at 12VOUT and 15VOUT
Figure 10. Power Loss at 5VOUT
Figure 11. No Heat Sink with 36VIN
to 5VOUT
8
7
6
5
8
7
6
5
8
7
6
5
4
3
4
3
4
3
2
1
0
2
1
0
2
OLFM
200LFM
400LFM
OLFM
200LFM
400LFM
OLFM
1
200LFM
400LFM
0
65
75
95
65
75
95
55
105
55
105
85
85
65
75
95
55
105
85
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4613 F13
4613 F14
4613 F12
Figure 12. BGA Heat Sink with 36VIN to 5VOUT
Figure 13. No Heat Sink
with 24VIN to 12VOUT
Figure 14. BGA Heat Sink
with 24VIN to 12VOUT
8
7
6
5
8
7
6
5
4
3
4
3
2
1
0
2
OLFM
200LFM
400LFM
OLFM
1
200LFM
400LFM
0
45 55 65 75
AMBIENT TEMPERATURE (°C)
95
25 35
105
85
45 55 65
85 95
25 35
105
75
AMBIENT TEMPERATURE (°C)
4613 F16
4613 F15
Figure 15. No Heat Sink with 36VIN to 15VOUT
Figure 16. BGA Heat Sink with 36VIN to 15VOUT
4613f
19
LTM4613
APPLICATIONS INFORMATION
Table 3. 12V and 15V Outputs
DERATING CURVE
Figures 13, 15
Figures 13, 15
Figures 13, 15
Figures 14, 16
Figures 14, 16
Figures 14, 16
V
(V)
POWER LOSS CURVE
Figure 9
AIRFLOW (LFM)
HEAT SINK
None
θ
JA
(°C/W)
≈14
≈10
≈10
≈13
≈8
IN
24, 36
24, 36
24, 36
24, 36
24, 36
24, 36
0
Figure 9
200
400
0
None
Figure 9
None
Figure 9
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 9
200
400
Figure 9
≈8
Table 4. 5V Output
DERATING CURVE
Figure 11
V
(V)
POWER LOSS CURVE
Figure 10
AIRFLOW (LFM)
HEAT SINK
None
θ
(°C/W)
≈11
≈9
IN
JA
36
0
Figure 11
36
36
36
36
36
Figure 10
200
400
0
None
Figure 11
Figure 10
None
≈9
Figure 12
Figure 10
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
≈11
Figure 12
Figure 10
200
400
≈8.5
≈8.5
Figure 12
Figure 10
Heat Sink Manufacturer
Wakefield Engineering
Part No: LTN20069
Phone: 603-635-2800
Safety Considerations
• UseroundcornersforthePCBcopperlayertominimize
the radiated noise.
The LTM4613 modules do not provide isolation from V
IN
• To minimize the EMI noise and reduce module thermal
stress, use multiple vias for interconnection between
top layer and other power layers.
to V . There is no internal fuse. If required, a slow blow
OUT
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic
failure.
• Do not put vias directly on pads.
• If vias are placed onto the pads, the the vias must be
Layout Checklist/Example
capped.
The high integration of LTM4613 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
• Interstitialvia placementcan also beused ifnecessary.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
• Use large PCB copper areas for high current path, in-
cluding V , PGND and V . It helps to minimize the
IN
OUT
• Place one or more high frequency ceramic capacitors
PCB conduction loss and thermal stress.
close to the connection into the system board.
• Place high frequency ceramic input and output capaci-
Figure17givesagoodexampleoftherecommendedlayout.
tors next to the V , PGND and V
pins to minimize
D
OUT
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
4613f
20
LTM4613
APPLICATIONS INFORMATION
V
IN
C
IN
C
VD
C
VD
GND
C
C
OUT
OUT
V
OUT
4613 F17
Figure 17. Recommended PCB Layout
PULL-UP SUPPLY ≤ 5V
CLOCK SYNC
V
IN
22V TO 36V
C1 TO C3
10µF
50V
×3
R4
51k
R3
51k
V
V
PLLIN
IN
D
V
OUT
V
OUT
PGOOD
RUN
12V
C5
+
C
C
22µF
16V
OUT2 8A
OUT1
LTM4613
22pF
180µF
16V
V
ON/OFF
COMP
C
FB
IN
R
FB
5.23k
10µF
INTV
CC
CC
50V CERAMIC
FCB
DRV
MARG0
MARG1
MPGM
f
MARGIN
REFER TO TABLE 2
SET
CONTROL
TRACK/SS
C4
0.1µF
SGND PGND
R1
392k
5% MARGIN
4613 F18
Figure 18. Typical 22V to 36VIN, 12V at 8A Design
4613f
21
LTM4613
APPLICATIONS INFORMATION
PULL-UP SUPPLY ≤ 5V
CLOCK SYNC
V
IN
5V TO 36V
C1 TO C3
10µF
50V
×3
R4
51k
R3
51k
V
V
PLLIN
IN
D
V
3.3V
8A
OUT
V
OUT
PGOOD
RUN
COMP
C5
C
22µF
6.3V
+
C
C
OUT1
OUT2
IN
22pF
180µF
6.3V
10µF
50V CERAMIC
V
ON/OFF
FB
LTM4613
R
FB
22.1k
INTV
CC
FCB
EXTERNAL 5V SUPPLY
IMPROVES EFFICIENCY—
ESPECIALLY FOR HIGH
INPUT VOLTAGES
REFER TO TABLE 2
DRV
CC
MARG0
MARG1
MPGM
f
MARGIN
SET
CONTROL
TRACK/SS
R
93.1k
1%
fSET
SGND PGND
R1
392k
5% MARGIN
C4
0.1µF
4613 F19
Figure 19. Typical 5V to 36VIN, 3.3V at 8A Design with 400kHz Frequency
PULL-UP SUPPLY ≤ 5V
CLOCK SYNC
V
IN
26V TO 36V
C1 TO C3
10µF
50V
×3
R4
51k
R3
51k
V
V
PLLIN
D
IN
V
15V
5A
OUT
V
OUT
PGOOD
RUN
C5
+
C
22µF
16V
C
OUT2
220µF
16V
OUT1
LTM4613
22pF
V
FB
ON/OFF
COMP
R
R
562k
1%
FB
4.12k
fSET
INTV
CC
CC
FCB
DRV
MARG0
MARG1
MPGM
f
MARGIN
SET
REFER TO TABLE 2
CONTROL
TRACK/SS
C
10µF
50V
IN
C4
0.1µF
R1
392k
5% MARGIN
SGND PGND
CERAMIC
4613 F20
Figure 20. 26V to 36VIN, 15V at 5A Design with 600kHz Frequency
4613f
22
LTM4613
APPLICATIONS INFORMATION
PULL-UP SUPPLY ≤ 5V
V
IN
20V TO 36V
C1
10µF
50V
×3
CLOCK SYNC
0° PHASE
R2
51k
R4
51k
V
D
V
PLLIN
IN
V
12V
16A
OUT
PGOOD
RUN
COMP
V
OUT
C6
47pF
LTM4613
C3
22µF
16V
+
C4
180µF
16V
V
FB
FCB
INTV
CC
CC
C2
10µF
50V
DRV
f
MARG0
MARG1
MPGM
MARGIN
CONTROL
SET
TRACK/SS
C5
100µF
50V
+
C7
0.33µF
R1
392k
R
FB
2.61k
SGND PGND
2-PHASE
OSCILLATOR
+
5% MARGIN
100k/N + R
V
OUT1
FB
V
OUT
= 0.6V •
R
GND OUT2
SET MOD
C11
0.1µF
R5
166k
FB
C11
10µF
50V
×3
LTC6908-1
CLOCK SYNC
180° PHASE
V
D
V
PLLIN
IN
V
PGOOD
RUN
COMP
OUT
C9
22µF
16V
LTM4613
C10
180µF
16V
+
V
FB
C8
FCB
INTV
CC
10µF
50V
MARG0
MARG1
MPGM
DRV
CC
f
SET
TRACK/SS
R6
392k
SGND PGND
4613 F21
Figure 21. 2-Phase, Parallel 12V at 16A Design with 600kHz Frequency
4613f
23
LTM4613
APPLICATIONS INFORMATION
PULL-UP SUPPLY ≤ 5V
V
IN
22V TO 36V
C1
10µF
50V
×3
CLOCK SYNC
0° PHASE
R4
51k
R2
51k
V
V
IN
PLLIN
D
12V
6A
PGOOD
RUN
COMP
V
OUT
C6
22pF
C4
180µF
16V
C3
22µF
16V
+
LTM4613
V
FB
FCB
INTV
CC
CC
DRV
C2
10µF
50V
f
MARG0
MARG1
MPGM
MARGIN
SET
CONTROL
TRACK/SS
C5
100µF
50V
+
R1
392k
R
FB1
5.23k
C7
0.1µF
SGND PGND
2-PHASE
OSCILLATOR
+
5% MARGIN
PULL-UP SUPPLY ≤ 5V
V
OUT1
GND OUT2
SET MOD
C11
0.1µF
R5
166k
C11
10µF
50V
×3
LTC6908-1
CLOCK SYNC
180° PHASE
R3
51k
R7
51k
V
V
PLLIN
D
IN
10V
6A
V
PGOOD
RUN
COMP
OUT
C1
22pF
C10
180µF
16V
C9
22µF
16V
+
LTM4613
V
FB
FCB
INTV
CC
12V TRACK
R8
10µF
50V
MARG0
MARG1
MPGM
MARGIN
DRV
CC
C8
CONTROL
100k
f
SET
TRACK/SS
R6
392k
R
R9
6.34k
FB2
SGND PGND
6.34k
4613 F22
Figure 22. 2-Phase, 12V and 10V at 6A Design with 600kHz Frequency and Output Voltage Tracking
4613f
24
LTM4613
APPLICATIONS INFORMATION
5V
V
IN
7V TO 36V
C1
10µF
50V
×3
CLOCK SYNC
0° PHASE
R4
51k
R2
51k
V
V
PLLIN
D
IN
5V
8A
V
OUT
PGOOD
RUN
COMP
C6
22pF
+
C3
22µF
6.3V
C4
180µF
6.3V
LTM4613
V
FB
INTV
CC
C2
10µF
50V
FCB
DRV
CC
MARG0
MARG1
MPGM
f
MARGIN
SET
CONTROL
TRACK/SS
C5
100µF
50V
+
R
fSET1
133k
R1
392k
R
FB1
13.7k
C7
0.15µF
SGND PGND
2-PHASE
OSCILLATOR
+
5% MARGIN
3.3V
V
OUT1
GND OUT2
SET MOD
C11
0.1µF
R5
200k
C11
10µF
50V
×3
LTC6908-1
CLOCK SYNC
180° PHASE
R3
51k
R7
51k
V
V
PLLIN
D
IN
3.3V
8A
V
PGOOD
RUN
COMP
OUT
C1
22pF
C9
22µF
6.3V
C10
180µF
6.3V
+
V
FB
LTM4613
FCB
INTV
CC
5V TRACK
MARG0
MARG1
MPGM
MARGIN
DRV
R8
CC
C8
10µF
50V
CONTROL
100k
f
SET
TRACK/SS
R6
392k
R
R9
R
fSET2
FB2
SGND PGND
22.1k
22.1k 64.9k
4613 F23
Figure 23. 2-Phase, 5V and 3.3V at 8A Design with 500kHz Frequency and Output Voltage Tracking
4613f
25
LTM4613
PACKAGE DESCRIPTION
Pin Assignment Tables
(Arranged by Pin Function)
PIN NAME
PIN NAME
PGND
PIN NAME
PIN NAME
A1
A2
A3
A4
A5
V
IN
V
IN
V
IN
V
IN
V
IN
D1
D2
D3
D4
D5
D6
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
V
OUT
A6
V
D
PGND
PGND
PGND
PGND
PGND
A7
INTV
CC
A8
A9
A10
A11
A12
PLLIN
TRACK/SS
RUN
COMP
MPGM
B1
B2
B3
B4
B5
V
V
V
V
V
IN
IN
IN
IN
IN
E1
E2
E3
E4
E5
E6
E7
E8
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
B6
V
V
–
D
D
B7
B8
B9
RUN
–
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
V
V
V
V
V
V
V
V
V
V
V
B10
B11
B12
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MPGM
f
SET
F1
F2
F3
F4
F5
F6
F7
F8
F9
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
C1
V
V
V
V
V
V
V
–
–
D
D
D
D
D
D
D
C2
C3
C4
C5
C6
C7
C8
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
V
V
V
V
V
V
V
V
V
V
V
C9
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
C10
C11
C12
DRV
CC
MARG1
MARG0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
D7
–
–
D8
D9
SGND
–
D10
D11
D12
COMP
MARG1
E9
–
–
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
V
V
V
V
V
V
V
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
E10
E11
E12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
DRV
DRV
CC
CC
F10
F11
F12
–
–
V
FB
G12
H12
J12
K12
L12
M12
PGOOD
SGND
NC
NC
NC
FCB
4613f
26
LTM4613
PACKAGE DESCRIPTION
Z
/ / b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
a a a
Z
4613f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTM4613
PACKAGE PHOTOGRAPH
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM4606
EN55022B Compliant 28V , 6A DC/DC µModule
EN55022 Class B Certified with PLL, Output Tracking and Margining,
IN
Regulator
LTM4600
10A DC/DC µModule Regulator
Military Plastic 10A DC/DC µModule Regulator
Basic 10A DC/DC µModule Regulator, LGA Package
LTM4600HVMP
Guaranteed Operation from –55°C to 125°C Ambient, LGA Package
LTM4601/
LTM4601A
12A DC/DC µModule Regulator with PLL, Output
Tracking/ Margining and Remote Sensing
Synchronizable, PolyPhase Operation, LTM4601-1/LTM4601A-1 Version
Has No Remote Sensing, LGA Package
LTM4602
LTM4603
6A DC/DC µModule Regulator
Pin Compatible with the LTM4600, LGA Package
6A DC/DC µModule Regulator with PLL and Output
Tracking/Margining and Remote Sensing
Synchronizable, PolyPhase Operation, LTM4603-1 Version Has No Remote
Sensing, Pin Compatible with the LTM4601, LGA Package
LTM4604A
Low V 4A DC/DC µModule Regulator
2.375V ≤ V ≤ 5.5V, 0.8V ≤ V
≤ 5V, 9mm × 15mm × 2.3mm
IN
IN
OUT
LGA Package
LTM4608A
LTM8020
Low V 8A DC/DC µModule Regulator
2.7V ≤ V ≤ 5.5V; 0.6V ≤ V
≤ 5V; 9mm × 15mm × 2.8mm LGA Package
OUT
IN
IN
High V 0.2A DC/DC Step-Down µModule Regulator
4V ≤ V ≤ 36V, 1.25V ≤ V
≤ 5V 6.25mm × 6.25mm × 2.3mm
IN
IN
OUT
LGA Package
LTM8021
High V 0.5A DC/DC Step-Down µModule Regulator
3V ≤ V ≤ 36V, 0.8V ≤ V
≤ 5V 6.25mm × 11.25mm × 2.8mm
OUT
IN
IN
LGA Package
LTM8022/
LTM8023
36V , 1A and 2A DC/DC µModule Regulator
Pin Compatible; 3.6V ≤ V ≤ 36V; 9mm × 11.25mm × 2.8mm
IN
IN
LGA Package
LTM4612
EN55022B Compliant 36V , 5A µModule Regulator
PLL Input, 5V ≤ V ≤ 36V, 15mm × 15mm × 2.8mm LGA Package
IN
IN
4613f
LT 0411 • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTM4614IV#PBF
LTM4614 - Dual 4A per Channel Low VIN DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C
Linear
LTM4615EV#PBF
LTM4615 - Triple Output, Low Voltage DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明