LTM4615IV#PBF_技术文档

LTM4615

Triple Output, Low Voltage

DC/DC µModule Regulator

FeaTures

DescripTion

n

Dual 4A Output Power Supply with 1.5A VLDO™

The LTM^®4615 is a complete 4A dual output switching

mode DC/DC power supply plus an additional 1.5A VLDO

(very low dropout) linear regulator. Included in the pack-

age are the switching controllers, power FETs, inductors,

a 1.5A regulator and all support components. The dual 4A

DC/DC converters operate over an input voltage range of

2.375V to 5.5V, and the VLDO operates from a 1.14V to

3.5V input. The LTM4615 supports output voltages rang-

ing from 0.8V to 5V for the DC/DC converters, and 0.4V

to 2.6V for the VLDO. The three regulator output voltages

are set by a single resistor for each output. Only bulk input

and output capacitors are needed to complete the design.

n

Short-Circuit and Overtemperature Protection

Power Good Indicators

n

Switching Regulators Section—Current Mode Control

n

Input Voltage Range: 2.375V to 5.5V

n

4A DC Typical, 5A Peak Output Current Each

n

0.8V Up to 5V Output Each, Parallelable

n

2% Total DC Output Error

n

Output Voltage Tracking

n

Up to 95% Efficiency

n

Programmable Soft-Start

VLDO Section

n

The low profile package (2.82mm) enables utilization of

unused space on the bottom of PC boards for high density

point of load regulation. High switching frequency and a

current mode architecture enables a very fast transient

response to line and load changes without sacrificing

stability. The device supports output voltage tracking for

supply rail sequencing.

VLDO, 1.14V to 3.5V Input Range

VLDO, 0.4V to 2.6V, 1.5A Output

VLDO, 40dB Supply Rejection at f

1% Total DC Output Error

SW

Small and Very Low Profile Package:

15mm × 15mm × 2.82mm

applicaTions

Additional features include overvoltage protection, over-

current protection, thermal shutdown and programmable

soft-start. The power module is offered in a space saving

and thermally enhanced 15mm × 15mm × 2.82mm LGA

package. The LTM4615 is RoHS compliant with Pb-free

finish.

n

Telecom and Networking Equipment

Industrial Power Systems

Low Noise Applications

FPGA, SERDES Power

L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule and PolyPhase are registered

trademarks and VLDO and LTpowerCAD are trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents

including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174.

Typical applicaTion

Efficiency vs Output Current

1.2V at 4A, 1.5V at 4A and 1V at 1A DC/DC µModule^®Regulator

91

V

IN

= 3.3V

89

87

85

83

81

79

77

75

V

3V TO 5.5V

IN

PGOOD1

10µF

6.3V

PGOOD2

10µF

6.3V

V

OUT2

1.5V

V

IN2

PGOOD2

IN1

PGOOD1

10k

V

1.5V

4A

V

OUT2

OUT1

1.2V

4A

V

OUT1

1.2V

V

OUT2

FB2

OUT1

V

OUT3

1V

LTM4615

GND2

FB1

22µF

6.3V

(V = 1.2V)

IN

22µF

6.3V

V

TRACK1

RUN/SS1

LDO_IN

EN3

TRACK2

RUN/SS2

LDO_OUT

FB3

PGOOD3

V

IN

10k

5.76k

V

OUT3

1V AT 1A

1.2V

100µF

6.3V

100µF

6.3V

10µF

6.3V

PGOOD3

3.32k

0

1

2

3

4

10µF

GND1

GND3

10k

4615 TA01a

OUTPUT CURRENT (A)

V

OUT3

4615 TA01b

4615fb

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For more information www.linear.com/LTM4615

LTM4615

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

Switching Regulators

IN1 IN2

TOP VIEW

TRACK1

COMP1

V

, V , PGOOD1, PGOOD2...................... –0.3V to 6V

RUN/SS1 PGOOD1

FB1

COMP1, COMP2, RUN/SS1, RUN/SS2

, V ,TRACK1, TRACK2 ...................... –0.3V to V

M

L

V

FB1 FB2

IN

OUT1

SW, V

...................................... –0.3V to (V + 0.3V)

OUT

IN

K

J

Very Low Dropout Regulator

V

IN1

SW1

GND1

LDO_IN, PGOOD3, EN3................................ –0.3V to 6V

LDO_OUT........................................................–0.3 to 4V

FB3 ........................................ –0.3V to (LDO_IN + 0.3V)

LDO_OUT Short-Circuit.................................... Indefinite

Internal Operating Temperature Range

GND1

H

G

F

LDO_IN

LDO_OUT

GND3

FB3

GND3 EN3

PGOOD3

GND2

FB2 BOOST3

E

RUN/SS2

D

C

B

A

(Notes 2, 5)............................................ –40°C to 125°C

Junction Temperature ........................................... 125°C

Storage Temperature Range .................. –55°C to 125°C

V

IN2

OUT2

GND2

1

2

3

4

5

6

7

8

9

10

11

12

TRACK2

COMP2 SW2

PGOOD2

LGA PACKAGE

144-LEAD (15mm × 15mm × 2.82mm)

T

= 125°C, θ

= 2-3°C/W, θ = 15°C/W, θ

= 25°C/W,

JMAX

JCbottom

JA

JCtop

θ VALUES DETERMINED FROM 4 LAYER 76mm × 95mm PCB

WEIGHT = 1.6g

orDer inForMaTion

†

LEAD FREE FINISH

LTM4615EV#PBF

LTM4615IV#PBF

TRAY

PART MARKING*

LTM4615V

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTM4615EV#PBF

LTM4615IV#PBF

–40°C to 125°C

144-Lead (15mm × 15mm × 2.82mm) LGA

LTM4615V

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

†

See Note 2.

4615fb

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For more information www.linear.com/LTM4615

LTM4615

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full internal

operating temperature range (Note 2), otherwise specifications are at T_A= 25°C, V_IN= 5V, LDO_IN = 1.2V unless otherwise noted.

Per Typical Application Figure 12.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Switching Regulator Section: per Channel

l

V

Input DC Voltage Range

Output DC Voltage Range

Output Voltage

2.375

0.8

5.5

5.0

V

IN(DC)

OUT(DC)

C

IN

V

IN

= 22µF, C

= 100µF, R = 5.76k,

OUT FB

= 2.375V to 5.5V, I

= 0A to 4A (Note 6)

OUT

0°C ≤ T ≤ 125°C

1.460

1.45

1.49

1.512

V

J

l

V

Undervoltage Lockout Threshold

Input Inrush Current at Start-Up

I

= 0A

1.6

2

2.3

V

IN(UVLO)

OUT

I

= 0A, C = 22µF, C

= 100µF, V

= 1.5V,

OUT

INRUSH(VIN)

OUT

IN

OUT

V

IN

= 5.5V

0.35

A

I

Input Supply Bias Current

Input Supply Current

V

= 2.375V, V = 1.5V, Switching Continuous

OUT

28

45

7

mA

µA

Q(VIN)

IN

= 5.5V, V

= 1.5V, Switching Continuous

OUT

Shutdown, RUN = 0, V = 5V

12

4

IN

I

V

IN

V

IN

= 2.375V, V

= 1.5V, I = 4A

OUT

3.2

1.48

A

S(VIN)

OUT

= 5.5V, V

= 1.5V, I

= 4A

OUT

Output Continuous Current Range

Load and Line Regulation Accuracy

V

= 5.5V, V

= 1.5V (Note 6)

0

A

OUT(DC)

IN

OUT

= 1.5V, 0A to 4A (Note 6)

IN

∆V

OUT

OUT(LOAD + LINE)

V

= 2.375V to 5.5V

1.0

1.3

1.30

1.6

%

V

OUT

l

V

Output Ripple Voltage

I

= 0A, C

IN

= 100µF

OUT

OUT(AC)

OUT

V

= 5V, V

= 1.5V

12

mV

P-P

f

Output Ripple Voltage Frequency

Turn-On Overshoot

= 4A, V = 5V, V = 1.5V

OUT

1.25

MHz

s

OUT

IN

C

= 100µF, V

= 0A

= 1.5V, RUN/SS = 10nF,

∆V

OUT

OUT(START)

I

OUT

V

= 3.3V

= 5V

20

mV

IN

V

t

Turn-On Time

C

= 100µF, V

= 1.5V, I

= 1A Resistive

OUT

START

OUT

IN

Load, TRACK = V and RUN/SS = Float

V

= 5V

0.5

25

ms

mV

IN

Peak Deviation for Dynamic Load

Load: 0% to 50% to 0% of Full Load,

= 100µF, V = 5V, V = 1.5V

∆V

OUT(LS)

C

OUT

IN

OUT

t

Settling Time for Dynamic Load

Step

Load: 0% to 50% to 0% of Full Load,

IN

10

8

µs

A

SETTLE

V

= 5V, V

= 1.5V

OUT

I

Output Current Limit

Voltage at FB Pin

C

= 100µF, V = 5V, V

= 1.5V

OUT(PK)

OUT

IN

OUT

V

I

= 0A, V

= 1.5V

0.790

0.786

0.8

0.807

0.809

V

FB

OUT

l

I

0.2

0.75

0.2

30

µA

V

FB

V

RUN Pin On/Off Threshold

TRACK Pin Current

Offset Voltage

0.6

0.9

RUN

I

µA

mV

V

TRACK

V

TRACK = 0.4V

TRACK(OFFSET)

TRACK(RANGE)

Tracking Input Range

0

0.8

R

Resistor Between V

and FB Pins

OUT

4.96

4.99

7.5

90

5.02

kΩ

%

FBHI

∆V

PGOOD Range

PGOOD

R

PGOOD Resistance

Open-Drain Pull-Down

150

Ω

PGOOD

4615fb

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For more information www.linear.com/LTM4615

LTM4615

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full internal

operating temperature range (Note 2), otherwise specifications are at T_A= 25°C, V_IN= 5V, LDO_IN = 1.2V unless otherwise noted.

Per Typical Application Figure 12.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VLDO Section

l

V

Operating Voltage

(Note 3)

1.14

3.5

V

mA

µA

V

LDO_IN

I

Operating Current

I

= 0mA, V = 1V, EN3 = 1.2V

OUT

1

IN(LDO_IN)

IN(SHDN)

OUT

Shutdown Current

EN3 = 0V, LDO_IN = 1.5V

EN3 = 1.2V

0.6

5

20

V

BOOST3 Output Voltage

Undervoltage Lockout

FB3 Internal Reference Voltage

4.8

5.2

BOOST3

4.3

V

BOOST3(UVLO)

FB3

1mA ≤ I

≤ 1.5A, 1.14V ≤ V

≤ 3.5V,

0.397

0.395

0.4

0.404

0.405

V

OUT

LDO_IN

l

BOOST3 = 5V, 1V ≤ V

≤ 2.59V

OUT

V

Output Voltage Range

Dropout Voltage

0.4

2.6

250

5.02

V

mV

kΩ

A

LDO_OUT

V

= 1.5V, V = 0.38V, I

= 1.5A (Note 4)

100

DO

LDO_IN

FB3

OUT

LDO_RHI

LDO Top Feedback Resistor

Output Current

4.96

1.5

4.99

l

I

= 1.2V

EN3

OUT

LIM

Output Current Limit

Output Voltage Noise

EN3 Input High Voltage

EN3 Input Low Voltage

EN3 Input Current

(Note 5)

Frequency = 10Hz to 1MHz, I

2.5

A

e

= 1A

300

µRMS

V

n

LOAD

V

1.14V ≤ V

≤ 3.5V

1

IH_EN3

IL_EN3

IN_EN3

LDO_IN

0.4

1

V

I

–1

µA

V

PGOOD Low Voltage

I

= 2mA

0.1

0.4

OL_PGOOD3

PGOOD3

PGOOD Threshold Output Threshold

Relative to V

PGOOD3 High to Low

PGOOD3 Low to High

–14

–4

–12

–3

–10

–2

%

FB3

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: Minimum operating voltage required for regulation is:

≥ V + V

Note 4: Dropout voltage is the minimum input to output differential needed

V

IN

OUT(MIN)

DROPOUT

to maintain regulation at a specified output current. In dropout the output

Note 2: The LTM4615 is tested under pulsed load conditions such that

voltage will be equal to V – V

.

IN

DROPOUT

T ≈ T . The LTM4615E is guaranteed to meet performance specifications

J

A

Note 5: The LTM4615 has overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperatures will exceed 125°C when overtemperature is activated.

Continuous overtemperature activation can impair long-term reliability.

over the 0°C to 125°C internal operating temperature range. Specifications

over the –40°C to 125°C internal operating temperature range are assured

by design, characterization and correlation with statistical process

controls. The LTM4615I is guaranteed to meet specifications over the full

internal operating temperature range. Note that the maximum ambient

temperature is determined by specific operating conditions in conjunction

with board layout, the rated package thermal resistance and other

environmental factors.

Note 6: See output current derating curves for different V , V

and T .

A

IN OUT

4615fb

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For more information www.linear.com/LTM4615

LTM4615

Typical perForMance characTerisTics

Switching Regulators

Efficiency vs Output Current

V_IN= 2.5V

Efficiency vs Output Current

V_IN= 3.3V

Efficiency vs Output Current

V_IN= 5V

100

95

90

100

95

90

85

80

85

80

75

70

65

85

80

75

V

= 3.3V

= 2.5V

= 1.8V

= 1.5V

= 1.2V

= 0.8V

OUT

75

70

65

V

= 2.5V

= 1.8V

= 1.5V

= 1.2V

= 0.8V

OUT

V

= 1.8V

= 1.5V

= 1.2V

= 0.8V

OUT

70

65

1

2

4

0

3

1

2

4

0

1

2

3

4

0

3

OUTPUT CURRENT (A)

4615 G01

4615 G03

4615 G02

Minimum Input Voltage

at 4A Load

Load Transient Response

3.5

3.0

V

= 3.3V

= 2.5V

= 1.8V

= 1.5V

= 1.2V

= 0.8V

OUT

I

LOAD

2.5

2A/DIV

V

2.0

1.5

1.0

0.5

OUT

V

OUT

20mV/DIV

4615 G06

V

C

= 5V

20µs/DIV

IN

4615 G05

V

C

= 5V

20µs/DIV

IN

= 1.5V

OUT

= 1.2V

OUT

= 100µF, 6.3V CERAMICS

0

1.5

2.5

2

3

3.5

4 4.5

5 5.5

0.5

1

V

(V)

IN

4615 G04

Load Transient Response

I

LOAD

2A/DIV

I

LOAD

2A/DIV

V

OUT

V

OUT

20mV/DIV

OUT

20mV/DIV

4615 G07

4615 G08

4615 G09

V

C

= 5V

20µs/DIV

V

C

= 5V

20µs/DIV

V

C

= 5V

OUT

20µs/DIV

= 100µF, 6.3V CERAMICS

IN

= 1.8V

= 2.5V

= 3.3V

OUT

= 100µF, 6.3V CERAMICS

4615fb

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For more information www.linear.com/LTM4615

LTM4615

Typical perForMance characTerisTics

Start-Up

V_FBvs Temperature

806

804

V

OUT

1V/DIV

802

800

I

IN

I

IN

1A/DIV

798

796

794

4615 G10

4615 G11

V

C

= 5V

200µs/DIV

V

C

= 5V

200µs/DIV

IN

= 2.5V

OUT

= 100µF

NO LOAD

4A LOAD

(0.01µF SOFT-START CAPACITOR)

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

4615 G12

Short-Circuit Protection

1.5V Short, No Load

Short-Circuit Protection

1.5V Short, 4A Load

Current Limit

1.6

1.4

1.2

1.0

V

OUT

0.5V/DIV

I

IN

0.8

0.6

1A/DIV

V

= 1.5V

0.4

0.2

0

OUT

4615 G15

4615 G14

100µs/DIV

20µs/DIV

V

= 5V

= 3.3V

= 2.5V

IN

4

5

7

3

8

6

OUTPUT CURRENT (A)

4615 G13

VLDO

V_FB3vs Temperature

Dropout Voltage vs Input Voltage

Ripple Rejection

200

180

160

140

120

100

80

404

403

402

401

400

399

398

397

396

60

50

40

30

20

10

0

V

= 0.38V

FB3

10kHz

1MHz

I

=1.5A

LDO_OUT

100kHz

1mA

1.5A

60

–40°C

25°C

85°C

125°C

V

I

= 5V

BOOST3

40

=1.2V

V

= 5V

= 1.5V

=1.2V

LDO_OUT

BOOST3

LDO_IN

LDO_OUT

= 800mA

OUT

20

C

= 10µF

0

1.2 1.4

1.6 1.8 2.0

2.2 2.4 2.6

0

25

50

100 125

1.2

1.8 2.0 2.2

2.4

2.6

–50 –25

75

1.4

1.6

V

(V)

TEMPERATURE (°C)

V

(V)

LDO_IN

4615 G17

4615 G16

4615 G18

4615fb

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For more information www.linear.com/LTM4615

LTM4615

Typical perForMance characTerisTics

Delay from Enable to Power Good

Ripple Rejection

Output Current Limit

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

70

60

50

40

30

20

10

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

V

= 0.8V

= 8Ω

V

= 0V

LDO_OUT

R

T

= 25°C

A

–40°C

25°C

85°C

CURRENT LIMIT

V

OUT

C

= 5V

BOOST3

LDO_IN

= 1.5V

=1.2V

THERMAL LIMIT

LDO_OUT

I

= 800mA

= 10µF

OUT

1.0

1.5

2.0

V

2.5

(V)

3.0

3.5

1000

10000

1000000 1E+07

1.5

2.0

V

3.0

2.5

(V)

100

100000

1.0

3.5

FREQUENCY (Hz)

LDO_IN

4615 G21

4615 G19

4615 G20

Output Load Transient Response

IN Supply Transient Response

1.5A

2mA

I

LDO_OUT

2V

V

LDO_IN

1.5V

V

LDO_OUT

AC

20mV/DIV

V

LDO_OUT

AC

10mV/DIV

4615 G22

4615 G23

V

C

V

= 1.5V

50µs/DIV

V

I

= 1.2V

LDO_OUT

OUT

LDO_IN

BOOST3

10µs/DIV

LDO_OUT

OUT

BOOST3

= 25°C

= 10µF

= 800mA

= 1.7V

= 5V

C

= 10µF

= 5V

V

T

A

BOOST3 Ripple and Feedthrough to

V_{LDO_OUT}

BOOST3/OUT Start-Up

HI

EN3

LO

5V

BOOST3

AC 20mV/DIV

BOOST3

1V

1.5V

V

LDO_OUT

AC 5mV/DIV

V

LDO_OUT

0V

4615 G25

4615 G24

V

I

= 1.2V

= 1A

200µs/DIV

T

R

V

= 25°C

LDO_OUT

LDO_IN

20µs/DIV

A

= 1.5V

= 1Ω

LDO_OUT

= 1.7V

LDO_OUT

LDO_IN

C

= 10µF

OUT

T

= 25°C

A

4615fb

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For more information www.linear.com/LTM4615

LTM4615

pin FuncTions

V

, V (J1-J5, K1-K5); (C1-C6, D1-D5): Power Input

COMP1, COMP2 (L5, E5): Current Control Threshold

and Error Amplifier Compensation Point. The current

comparator threshold increases with this control voltage.

Two power modules can current share when this pin is

connected in parallel with the adjacent module’s COMP

pin. Each channel has been internally compensated. See

the Applications Information section.

IN1 IN2

Pins. Apply input voltage between these pins and GND

pins. Recommend placing input decoupling capacitance

directly between V pins and GND pins.

IN

V

, V

(K9-K12, L9-L12, M9-M12); (C9-C12,

OUT2

OUT1

D9-D12, E11-E12): Power Output Pins. Apply output load

between these pins and GND pins. Recommend placing

outputdecouplingcapacitancedirectlybetweenthesepins

and GND pins. Review Table 4.

PGOOD1, PGOOD2 (L4, E4): Output Voltage Power

Good Indicator. Open-drain logic output that is pulled to

ground when the output voltage is not within 7.5% of

the regulation point.

GND1, GND2, (H1, H7-H12, J6-J12, K6-K8 L1, L7-L8,

M1-M8); (A1-A12, B1, B7-B12, C7-C8, D6-D8, E1,

E8-E10): Power Ground Pins for Both Input and Output

Returns.

RUN/SS1, RUN/SS2 (L2, E2): Run Control and Soft-Start

Pin. A voltage above 0.8V will turn on the module, and

below 0.5V will turn off the module. This pin has a 1M

TRACK1, TRACK2 (L3, E3): Output Voltage Tracking Pins.

When the module is configured as a master output, then a

soft-start capacitor is placed on the RUN/SS pin to ground

to control the master ramp rate, or an external ramp can

be applied to the master regulator’s track pin to control it.

Slave operation is performed by putting a resistor divider

from the master output to ground, and connecting the

center point of the divider to this pin on the slave regulator.

If tracking is not desired, then connect the TRACK pin to

resistor to V and a 1000pF capacitor to GND. See the

IN

ApplicationsInformationsectionforsoft-startinformation.

SW1, SW2 (H2-H6, B2-B6): The switching node of the

circuit is used for testing purposes. This can be connected

tocopperontheboardforimprovedthermalperformance.

SW1andSW2mustbefloatingonseparatecopperplanes.

LDO_IN (G1-G4): VLDO Input Power Pins. Place input

capacitor close to these pins.

V . Load current must be present for tracking. See the

IN

LDO_OUT (G9-G12): VLDO Output Power Pins. Place

output capacitor close to these pins. Minimum 1mA load

is necessary for proper output voltage accuracy.

Applications Information section.

FB1, FB2 (L6, E6): The Negative Input of the Switching

Regulators’ Error Amplifier. Internally, these pins are con-

BOOST3 (E7): Boost Supply for Driving the Internal VLDO

NMOS Into Full Enhancement. The pin is use for testing

the internal boost converter. The output is typically 5V.

nected to V

with a 4.99k precision resistor. Different

OUT

output voltages can be programmed with an additional

resistorbetweentheFBandGNDpins.Twopowermodules

can current share when this pin is connected in parallel

with the adjacent module’s FB pin. See the Applications

Information section.

GND3(F1-F5,F7,F9-F12,G6-G8):Thepowergroundpins

for both input and output returns for the internal VLDO.

PGOOD3 (G5): VLDO Power Good Pin.

EN3 (F8): VLDO Enable Pin.

FB3 (F6): The Negative Input of the LDO Error Amplifier.

Internally the pin is connected to LDO_OUT with a 4.99k

resistor.Differentoutputvoltagescanbeprogrammedwith

an additional resistor between the FB3 and GND pins. See

the Applications Information section.

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LTM4615

siMpliFieD block DiagraM

Switching Regulator Block Diagram

V

PGOOD

RUN/SS

IN

V

IN

2.375V TO 5.5V

22µF

6.3V

4.7µF

6.3V

R

SS

1M

C

SS

1000pF

C

M1

M2

SSEXT

0.47µH

470pF

V

OUT

CONTROL, DRIVE

POWER FETS

4.99k

TRACK

COMP

1.5V

TRACK

SUPPLY

4.7µF

6.3V

4A

22µF

6.3V

×3

5.76k

R

FBHI

4.99k

INTERNAL

COMP

GND

FB

SW

4615 F01a

R

FB

5.76k

VLDO Block Diagram

BOOST3

4.7µF

5V BOOST

LDO_IN

V

IN

1.14V TO 3.5V

4.7µF

6.3V

GND3

10µF

0.4V

+

–

V

OUT

GND3

LDO_OUT

CONTROL

1V

10µF 1.5A

4.7µF

6.3V

GND3

EN3

LDO_RHI

4.99k

ENABLE

GND3

FB3

R

FBLDO

PGOOD3

POWER GOOD

3.32k

GND3

10k

4615 F01b

GND

1V

Figure 1. Simplified LTM4615 Block Diagram of Each Switching Regulator Channel and the VLDO

Decoupling requireMenTs ^T_A^{= 25°C. Use Figure 1 configuration for each channel.}

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

C

IN

External Input Capacitor Requirement

IN

I

= 4A

22

µF

OUT

(V = 2.375V to 5.5V, V

= 1.5V)

OUT

C

External Output Capacitor Requirement

IN

I

= 4A

66

100

10

µF

OUT

(V = 2.375V to 5.5V, V

= 1.5V)

OUT

LDO_IN

LDO Input Capacitance

I

= 1A

4.7

10

µF

OUT

LDO_OUT

LDO Output Capacitance

OUT

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LTM4615

operaTion

LTM4615 POWER MODULE DESCRIPTION

The LTM4615 is internally compensated to be stable over

the operating conditions. Table 4 provides a guideline

for input and output capacitance for several operating

conditions. The LTpowerCAD™ Design Tool is provided

for transient and stability analysis.

Dual Switching Regulator Section

The LTM4615 is a standalone dual nonisolated switching

mode DC/DC power supply with an additional onboard

1.5A VLDO. It can deliver up to 4A of DC output current

for each channel with few external input and output ca-

pacitors. This module provides two precisely regulated

output voltages programmable via one external resistor

for each channel from 0.8V DC to 5V DC over a 2.375V

to 5.5V input voltage range. The VLDO is an independent

1.5A linear regulator that can be powered from either

switching converter. The typical application schematic is

shown in Figure 12.

The FB pins are used to program the specific output volt-

age with a single resistor to ground.

VLDO Section

The VLDO (very low dropout) linear regulator operates

from a 1.14V to 3.5V input. The VLDO uses an internal

NMOS transistor as the pass device in a source-follower

configuration. The BOOST3 pin is the output of an inter-

nal boost converter that supplies the higher supply drive

to the pass device for low dropout enhancement. The

internal boost converter operates on very low current,

thus optimizing high efficiency for the VLDO in close to

dropout operation.

The LTM4615 has two integrated constant frequency cur-

rent mode regulators, with built-in power MOSFETs with

fast switching speed. The typical switching frequency is

1.25MHz.Withcurrentmodecontrolandinternalfeedback

loop compensation, these switching regulators have suf-

ficient stability margins and good transient performance

under a wide range of operating conditions, and with a

wide range of output capacitors, even all ceramic output

capacitors.

An undervoltage lockout comparator on the LDO ensures

that the boost voltage is greater than 4.2V before enabling

the LDO, otherwise the LDO is disabled.

TheLDOprovidesahighaccuracyoutputcapableofsupply

1.5A of output current with a typical drop out of 100mV.

A single ceramic 10µF capacitor is all that is required

for output capacitor bypassing. A low reference voltage

allows the VLDO to have lower output voltages than the

commonly available LDO.

Currentmodecontrolprovidescycle-by-cyclefastcurrent

limit. Besides, current limiting is provided in an overcur-

rentconditionwiththermalshutdown.Inaddition,internal

overvoltage and undervoltage comparators pull the open-

drain PGOOD outputs low if the particular output feedback

voltageexitsa 7.5%windowaroundtheregulationpoint.

Furthermore, in an overvoltage condition, internal top FET,

M1, is turned off and bottom FET, M2, is turned on and

held on until the overvoltage condition clears, or current

limit is exceeded.

The device also includes current limit and thermal over-

load protection. The NMOS follower architecture has fast

transient response without the traditional high drive cur-

rents in dropout. The VLDO includes a soft-start feature

to prevent excessive current on the input during start-up.

When the VLDO is enabled, the soft-start circuitry gradu-

ally increases the reference voltage from 0V to 0.4V over

a period of approximately 200µs.

Pulling each specific RUN/SS pin below 0.8V forces the

specific regulator controller into its shutdown state, turn-

ing off both M1 and M2 for each power stage. At low load

current, each regulator works in continuous current mode

by default to achieve minimum output voltage ripple.

The TRACK pins are used for power supply tracking for

each specific regulator. See the Applications Information

section.

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LTM4615

applicaTions inForMaTion

Dual Switching Regulator

current requirements. A 47µF bulk capacitor can be used

for more input capacitance. This 47µF capacitor is only

needed if the input source impedance is compromised by

long inductive leads or traces. The bulk capacitor can be

a switcher-rated aluminum electrolytic OS-CON capacitor.

The typical LTM4615 application circuit is shown in Fig-

ure 12. External component selection is primarily deter-

mined by the maximum load current and output voltage.

RefertoTable4forspecificexternalcapacitorrequirements

for a particular application.

For a buck converter, the switching duty cycle can be

estimated as:

V to V

Step-Down Ratios

IN

OUT

V_OUT

D =

There are restrictions in the maximum V to V

step-

IN

OUT

V

IN

down ratio that can be achieved for a given input voltage

on the two switching regulators. The LTM4615 is 100%

Without considering the inductor ripple current, the RMS

current of the input capacitor can be estimated as:

duty cycle, but the V to V

minimum dropout will be

OUT

IN

a function the load current. A typical 0.5V minimum is

I_OUT(MAX)

sufficient.

I_CIN(RMS)

=

• D• 1–D

(

)

η%

Output Voltage Programming

In the above equation, η% is the estimated efficiency of

the power module. If a low inductance plane is used to

powerthedevice,thennoinputcapacitanceisrequired.The

internal4.7µFceramicsoneachchannelinputaretypically

rated for 1A of RMS ripple current up to 85°C operation.

Theworse-caseripplecurrentforthe4Amaximumcurrent

is2Aorless. Anadditional10µFor22µFceramiccapacitor

can be used to supplement the internal capacitor with an

additional 1A to 2A ripple current rating.

Each regulator channel has an internal 0.8V reference

voltage. As shown in the block diagram, a 4.99k internal

feedback resistor connects the V

and FB pins together.

OUT

The output voltage will default to 0.8V with no feedback

resistor. Adding a resistor R from the FB pin to GND

FB

programs the output voltage:

4.99k+R_FB

V_OUT= 0.8V •

R_FB

Output Capacitors

or equivalently,

The LTM4615 switchers are designed for low output volt-

age ripple on each channel. The bulk output capacitors

are chosen with low enough effective series resistance

(ESR) to meet the output voltage ripple and transient

requirements. The output capacitors can be a low ESR

tantalum capacitor, low ESR polymer capacitor or ceramic

capacitor. The typical output capacitance range is 66µF

to 100µF. Additional output filtering may be required by

the system designer if further reduction of output ripple

or dynamic transient spikes is required. Table 4 shows a

matrix of different output voltages and output capacitors

to minimize the voltage droop and overshoot during a 2A/

µs transient. The table optimizes total equivalent ESR and

totalbulk capacitance to maximize transient performance.

4.99k

R_FB=

V_OUT

0.8V

−1

Table 1. FB Resistor Table vs Various Output Voltages

V

0.8V

1.2V

10k

1.5V

1.8V

2.5V

3.3V

OUT

FB

Open

5.76k

3.92k

2.37k

1.62k

Input Capacitors

The LTM4615 module should be connected to a low AC

impedance DC source. One 4.7µF ceramic capacitor is

included inside the module for each regulator channel.

Additional input capacitors are needed if a large load step

is required, up to the full 4A level, and for RMS ripple

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LTM4615

applicaTions inForMaTion

Fault Conditions: Current Limit and Overtemperature

where R and C are shown in the block diagram of

SS SS

Protection

Figure 1, and the 1.8V is soft-start upper range. The soft-

startfunctioncanalsobeusedtocontroltheoutputramp-up

time, so that another regulator can be easily tracked to it.

The LTM4615 has current mode control, which inher-

ently limits the cycle-by-cycle inductor current not only

in steady-state operation, but also in transient.

Output Voltage Tracking

Along with current limiting in the event of an overload

condition, the LTM4615 has overtemperature shutdown

protection that inhibits switching operation around 150°C

for each channel.

Output voltage tracking can be programmed externally

using the TRACK pins. Either output can be tracked up

or down with another regulator. The master regulator’s

output is divided down with an external resistor divider

that is the same as the slave regulator’s feedback divider

to implement coincident tracking. The LTM4615 uses a

very accurate 4.99k resistor for the internal top feedback

resistor.Figure 2showsanexampleofcoincidenttracking.

Run Enable and Soft-Start

The RUN/SS pins provide a dual function of enable and

soft-start control for each channel. The RUN/SS pins are

used to control turn on of the LTM4615. While each enable

pin is below 0.5V, the LTM4615 will be in a low quiescent

current state. At least a 0.8V level applied to the enable

pins will turn on the LTM4615 regulators. This pin can be

used to sequence the regulator channels. The soft-start

Equations:

⎛

⎜

⎝

⎞

⎟

⎠

R_FB1

4.99k +R

TRACK1=

•Master

FB1

⎛

⎞

control is provided by a 1M pull-up resistor (R ) and a

4.99k

R_FB1

SS

Slave = 1+

• TRACK1

⎜

⎟

1000pF capacitor (C ) as drawn in the block diagram

SS

⎝

⎠

for each channel. An external capacitor can be applied to

the RUN/SS pin to increase the soft-start time. A typical

value is 0.01µF. The approximate equation for soft-start:

⎛

⎜

⎝

⎞

⎟

⎠

V

IN

t_SOFTSTART=In

•R_SS•C_SS

V – 1.8V

IN

V

IN

3V TO 5.5V

C2

10µF

6.3V

C1

10µF

6.3V

PGOOD2

PGOOD1

R4

10k

R3

V

IN2

PGOOD2

IN1

10k

PGOOD1

MASTER

1.5V

SLAVE

1.2V

4A

V

FB1

V

OUT2

OUT1

4A

FB2

COMP2

TRACK2

RUN/SS2

LDO_OUT

FB3

PGOOD3

R

TB

4.99k

COMP1

TRACK1

RUN/SS1

LDO_IN

EN3

C10

22µF

6.3V

C3

22µF

6.3V

C6

22µF

6.3V

C8

22µF

6.3V

R

FB2

1.5V

R

V OR A CONTROL RAMP

LTM4615

GND2

IN

5.76k

L1 0.2µH*

1V LOW NOISE AT 1A

C5

22µF

6.3V

C4

22µF

6.3V

1.2V

C7

C9

C11

10µF

6.3V

22µF

6.3V

BOOST3

PGOOD3

R5

3.32k

C12

R

TA

C13

SSEXT

FB1

R6

10k

GND1

GND3

10µF

10k

C

1V

LOW NOISE

4615 F02

*FAIR-RITE 0805 2508056007Y6

OPTIONAL FILTER

Figure 2. Dual Outputs (1.5V and 1.2V) with Tracking

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LTM4615

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TRACK1 is the track ramp applied to the slave’s track pin.

TRACK1appliesthetrackreferencefortheslaveoutputup

to the point of the programmed value at which TRACK1

proceeds beyond the 0.8V reference value. The TRACK1

pin must go beyond the 0.8V to ensure the slave output

has reached its final value.

Figure 3 shows the output voltage tracking waveform for

coincident tracking.

Inratiometrictracking, adifferentslewratemaybedesired

for the slave regulator. R can be solved for when SR is

TB

slower than MR. Make sure that the slave supply slew

rate is chosen to be fast enough so that the slave output

voltage will reach it final value before the master output.

Ratiometric tracking can be achieved by a few simple

calculationsandtheslewratevalueappliedtothemaster’s

TRACK pin. As mentioned above, the TRACK pin has a

control range from 0V to 0.8V. The control ramp slew rate

applied to the master’s TRACK pin is directly equal to the

master’s output slew rate in Volts/Time.

For example, MR = 2.5V/ms and SR = 1.8V/1ms. Then

R = 6.98k. Solve for R to equal to 3.24k. The master

TB

TA

output must be greater than the slave output for the

tracking to work. Output load current must be present

for tracking to operate properly during power-down.

The equation:

Power Good

MR

SR

• 4.99k =R_TB

PGOOD1 and PGOOD2 are open-drain pins that can be

used to monitor valid output voltage regulation. These

pinsmonitora 7.5%windowaroundtheregulationpoint.

If the output is disabled, the respective pin will go low.

where MR is the master’s output slew rate and SR is the

slave’s output slew rate in Volts/Time. When coincident

tracking is desired, then MR and SR are equal, thus R

TB

COMP Pin

is equal to 4.99k. R is derived from equation:

TA

This pin is the external compensation pin. The module

has already been internally compensated for all output

voltages. Table 4 is provided for most application require-

ments. The LTpowerCAD Design Tool is provided for other

control loop optimization. The COMP pins must be tied

together in parallel operation.

0.8V

R_TA

=

V_FB

V_FBV_TRACK

+

–

4.99k R_FB

R_TB

where V is the feedback voltage reference of the regula-

FB

TRACK

tor, and V

is 0.8V. Since R is equal to the 4.99k top

TB

feedback resistor of the slave regulator in equal slew rate

or coincident tracking, then R is equal to R with V

Parallel Switching Regulator Operation

=

FB

TA

FB

V

. Therefore R = 4.99k and R = 10k in Figure 2.

The LTM4615 switching regulators are inherently current

modecontrol.Parallelingwillhaveverygoodcurrentshar-

ing. This will balance the thermals on the design. Figure

13 shows a schematic of a parallel design. The voltage

feedback equation changes with the variable N as chan-

nels are paralleled.

TRACK

TB

TA

MASTER OUTPUT

SLAVE OUTPUT

The equation:

4.99k

+R_FB

N

V_OUT= 0.8V •

R_FB

N is the number of paralleled channels.

TIME

4615 F03

Figure 3. Output Voltage Coincident Tracking

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LTM4615

applicaTions inForMaTion

VLDO SECTION

pacitance can be used, but a ceramic capacitor must be

used in parallel at the output.

Adjustable Output Voltage

Extra consideration should be given to the use of ceramic

capacitors related to dielectrics, temperature and DC bias

effects on the capacitor. The VLDO requires a minimum

10µF value. The X7R and X5R dielectrics are more stable

with DC bias and temperature, thus more preferred.

The output voltage is set by the ratio of two resistors. A

4.99k resistor is built onboard the module from LDO_OUT

toFB3.Anadditionalresistor(R

)isrequiredfromFB3

FBLDO

to GND3 to set the output voltage over a range of 0.4V to

2.6V. Minimum output current of 1mA is required for full

output voltage range.

Short-Circuit/Thermal Protection

The VLDO has built-in short-circuit current limiting of

~3A as well as overtemperature protection. During short-

circuit conditions the device is in control to 3A, and as

the internal temperature rises to approximately 150°C,

then the internal boost and LDO are shut down until the

internal temperature drops back to 140°C. The device will

cycle in and out of this mode with no latchup or damage.

Long term over stress in this condition can degrade the

device over time.

The equation:

4.99k+R_FBLDO

V_{LDO_OUT}= 0.4V •

R_FBLDO

or equivalently,

4.99k

R_FBLDO

=

V_{LDO_OUT}

−1

0.4V

Reverse Current Protection

Power Good Operation

The VLDO features reverse current protection to limit

current draw from any supplementary power source at

the output. Figure 4 shows the reverse input current limit

The VLDO includes an open-drain power good (PGOOD3)

pin with hysteresis. If the VLDO is in shutdown or under

UVLO conditions (BOOST3 < 4.2V), then PGOOD3 is low

impedance to ground. PGOOD3 becomes high imped-

ance when the VLDO output voltage rises to 93% of its

regulated voltage. PGOOD3 stays high impedance until

the output voltage falls to 91% of its regulated voltage. A

pull-up resistor can be inserted between the PGOOD3 pin

and a positive logic supply such as the VLDO output or

versus input voltage for a nominal V

setpoint of

LDO_OUT

1.5V. Note: Positive input current represents current flow-

ing into the LDO_IN pin. With LDO_OUT held at or below

the output regulation voltage and LDO_IN varied, input

current flow will follow the Figure 4 curve. Input reverse

currentrampsupto16µAasLDO_INapproachesLDO_OUT.

V . LDO_IN should be at least 1.14V or greater for power

IN

30

good to operate properly.

IN CURRENT

LIMIT ABOVE 1.45V

20

10

Output Capacitance and Transient Response

The VLDO is designed to be stable with a wide range of

ceramic output capacitors. The ESR of the output capaci-

torsaffectsstability,especiallysmallervaluecapacitors.An

output capacitor of 10µF or greater with an ESR of 0.05Ω

or less is recommended to ensure stability. Larger value

capacitors can be used to reduce the transient deviations

under load changes. Bypass capacitors that are used at

the load device can also increase the effective output

capacitance. High ESR tantalum or electrolytic bulk ca-

0

–10

–20

–30

0

0.9

LDO_IN VOLTAGE (V)

1.5

0.3

0.6

1.2

1.8

4615 F04

Figure 4. Reverse Current Limit for VLDO

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LTM4615

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Reverse input current will spike up as LDO_IN gets to

withinabout30mVofLDO_OUTasreversecurrentprotec-

tion circuitry is disabled and normal operation resumes.

AsLDO_INtransitionsaboveLDO_OUTthereversecurrent

transitions into short circuit current as long as LDO_OUT

is held below the regulation voltage.

while lowering output current or power with increasing

ambient temperature. The 120°C value is chosen to allow

for a 5°C margin window relative to the maximum 125°C

limit. The decreased output current will decrease the inter-

nal module loss as ambient temperature is increased. The

power loss curves in Figures 5 and 6 show this amount of

power loss as a function of load current that is specified

for both channels. The monitored junction temperature of

120°Cminustheambientoperatingtemperaturespecifies

how much module temperature rise can be allowed. As

an example, in Figure 7 the load current is derated to 3A

for each channel with 0LFM at ~90°C and the power loss

for both channels at 5V to 1.2V at 3A output is ~1.4W.

Add the VDLO power loss of 0.5W to equal 1.9W. If the

90°C ambient temperature is subtracted from the 120°C

maximumjunctiontemperature,thenthedifferenceof30°C

divided by 1.9W equals a 15.7°C/W thermal resistance.

Table 2 specifies a 15°C/W value which is very close. Table

2 and Table 3 provide equivalent thermal resistances for

1.2V and 3.3V outputs with and without air flow and heat

sinking. The combined power loss for the two 4A outputs

plus the VLDO power loss can be summed together and

multiplied by the thermal resistance values in Tables 2 and

3 for module temperature rise under the specified condi-

tions. The printed circuit board is a 1.6mm thick four layer

boardwithtwoouncecopperforthetwoouterlayersand1

ouncecopperforthetwoinnerlayers.ThePCBdimensions

are 95mm × 76mm. The BGA heat sinks are listed below

Thermal Considerations and Output Current Derating

The power loss curves in Figures 5 and 6 can be used

in coordination with the load current derating curves in

Figures 7 to 10 for calculating an approximate θ thermal

JA

resistance for the LTM4615 with various heat sinking and

airflow conditions. Both of the LTM4615 outputs are at full

4A load current, and the power loss curves in Figures 5

and 6 are combined power losses plotted for both output

voltages up to 4A each. The VLDO regulator is set to have

a power dissipation of 0.5W since it is generally used with

dropout voltages of 0.5V or less. For example: 1.2V to 1V,

1.5V to 1V, 1.5V to 1.2V and 1.8V to 1.5V. Other dropout

voltages can be supported at VLDO maximum load, but

further thermal analysis will be required for the VLDO.

The 4A output voltages are 1.2V and 3.3V. These voltages

are chosen to include the lower and higher output voltage

ranges for correlating the thermal resistance. Thermal

models are derived from several temperature measure-

ments in a controlled temperature chamber along with

thermal modeling analysis. The junction temperatures are

monitoredwhileambienttemperatureisincreasedwithand

without airflow. The junctions are maintained at ~120°C

Table 3. The data sheet lists the θ (Junction to Case)

JC

thermal resistances under the Pin Configuration diagram.

3.0

2.5

V

= 5V

V

= 5V

IN

2.5

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

1

2

3

4

0

1

2

3

4

LOAD CURRENT (A)

4615 F06

4615 F05

Figure 5. 1.2V Power Loss

Figure 6. 3.3V Power Loss

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LTM4615

applicaTions inForMaTion

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

4.5

V

= 5V

V

= 5V

IN

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0LFM HEATSINK

200LFM HEATSINK

400LFM HEATSINK

0LFM NO HEATSINK

200LFM NO HEATSINK

400LFM NO HEATSINK

0

40 50 60 70 80

120

90 100 110

40 50 60 70 80 90

AMBIENT TEMPERATURE (°C)

120

100 110

AMBIENT TEMPERATURE (°C)

4615 F08

4615 F07

Figure 7. 1.2V No Heat Sink

Figure 8. 1.2V Heat Sink

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

V

= 5V

V

= 5V

IN

0LFM HEATSINK

200LFM HEATSINK

400LFM HEATSINK

0LFM NO HEATSINK

200LFM NO HEATSINK

400LFM NO HEATSINK

0

40 50 60 70 80

120

90 100 110

40 50 60 70 80

AMBIENT TEMPERATURE (°C)

120

90 100 110

AMBIENT TEMPERATURE (°C)

4615 F10

4615 F09

Figure 9. 3.3V No Heat Sink

Figure 10. 3.3V Heat Sink

4615fb

16

For more information www.linear.com/LTM4615

LTM4615

applicaTions inForMaTion

Table 2. 1.2V Output

DERATING CURVE

Figure 7

V

(V)

POWER LOSS CURVE

Figure 5

AIRFLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

15

IN

5

0

Figure 7

5

Figure 5

200

400

0

None

12

Figure 7

Figure 5

None

10

Figure 8

Figure 5

BGA Heat Sink

14

Figure 8

Figure 5

200

400

9

Figure 8

Figure 5

8

Table 3. 3.3V Output

DERATING CURVE

Figure 9

V

(V)

POWER LOSS CURVE

Figure 6

AIRFLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

15

IN

5

0

Figure 9

Figure 6

200

400

0

None

12

Figure 9

Figure 6

None

10

Figure 10

Figure 6

BGA Heat Sink

14

Figure 10

Figure 6

200

400

9

Figure 10

Figure 6

8

HEAT SINK MANUFACTURER

Aavid

PART NUMBER

WEBSITE

375424B00034G

www.aavid.com

Cool Innovations

4-050503P to 4-050508P

www.coolinnovations.com

4615fb

17

For more information www.linear.com/LTM4615

LTM4615

applicaTions inForMaTion

Safety Considerations

•ꢀ Placeꢀhighꢀfrequencyꢀceramicꢀinputꢀandꢀoutputꢀcapaci-

tors next to the V , GND and V

pins to minimize

IN

OUT

The LTM4615 modules do not provide galvanic isolation

high frequency noise.

from V to V . There is no internal fuse. If required,

IN

OUT

a slow blow fuse with a rating twice the maximum input

current needs to be provided to protect each unit from

catastrophic failure.

•ꢀ Placeꢀaꢀdedicatedꢀpowerꢀgroundꢀlayerꢀunderneathꢀtheꢀ

unit.

•ꢀ Toꢀminimizeꢀtheꢀviaꢀconductionꢀlossꢀandꢀreduceꢀmoduleꢀ

thermal stress, use multiple vias for interconnection

between the top layer and other power layers.

Layout Checklist/Example

The high integration of LTM4615 makes the PCB board

layoutverysimpleandeasy.However,tooptimizeitselectri-

cal and thermal performance, some layout considerations

are still necessary.

•ꢀ Doꢀnotꢀputꢀviaꢀdirectlyꢀonꢀpadsꢀunlessꢀtheꢀviaꢀisꢀcapped.

Figure11givesagoodexampleoftherecommendedlayout.

•ꢀ Useꢀ largeꢀ PCBꢀ copperꢀ areasꢀ forꢀ highꢀ currentꢀ path,ꢀ

including V , GND and V . It helps to minimize the

IN

OUT

PCB conduction loss and thermal stress.

V

CONTROL

GND1

OUT1

C

IN1

GND1

M

L

C

OUT1 OUT2

V

OUT1

K

J

V

IN1

SW1

GND1

H

G

F

C

IN2

C

OUT3

LD0_IN

GND3

GND2

LDO_OUT

GND3

E

C

OUT4 OUT5

CONTROL

D

C

B

A

V

OUT2

V

IN2

GND2

C

1

2

3

4

5

6

7

8

9

10 11 12

GND2

IN3

4615 F11

GND2

SW2

Figure 11. Recommended PCB Layout

4615fb

18

For more information www.linear.com/LTM4615

LTM4615

applicaTions inForMaTion

V

3V TO 5.5V

IN

C

10µF

6.3V

C

IN2

IN1

10µF

PGOOD1

PGOOD2

6.3V

R3

10k

R4

10k

V

IN2

PGOOD2

IN1

PGOOD1

V

1.5V

4A

V

OUT2

OUT1

1.2V

V

FB1

V

OUT1

OUT2

4A

FB2

COMP2

TRACK2

RUN/SS2

LDO_OUT

FB3

PGOOD3

C

OUT2

COMP1

TRACK1

RUN/SS1

LDO_IN

EN3

100µF

6.3V

R

22µF

6.3V

22µF

6.3V

FB2

100µF

6.3V

5.76k

V

IN

LTM4615

GND2

IN

V

OUT3

L1 0.2µH*

1V LOW NOISE AT 1A

C

OUT1

1.2V

22µF

6.3V

22µF

6.3V

C11

10µF

6.3V

BOOST3

PGOOD3

R5

C12

10µF

R

FB1

R6

10k

GND1

GND3

3.32k

10k

V

OUT3

4615 F12

*FAIR-RITE 0805 2508056007Y6

IF MORE FILTERING REQUIRED

Figure 12. Typical 3V to 5.5V_IN, 1.5V and 1.2V at 4A and 1V at 1A Design

Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 12) 0A to 2.5A Load Step Typical Measured Values

C

AND C

C

AND C

OUT1

OUT2

OUT1 OUT2

CERAMIC VENDORS

VALUE

PART NUMBER

BULK VENDORS

VALUE

PART NUMBER

10TPD150M

4TPE220MF

TDK

22µF 6.3V

22µF 16V

100µF 6.3V

C3216X7SOJ226M

Sanyo POSCAP

150µF 10V

220µF 4V

VALUE

Murata

TDK

GRM31CR61C226KE15L Sanyo POSCAP

C4532X5R0J107MZ

GRM32ER60J107M

C

IN

BULK VENDORS

PART NUMBER

10CE100FH

Murata

Sanyo POSCAP

100µF 10V

V

C

AND C

C

AND C

V

DROOP PEAK-TO-PEAK RECOVERY LOAD STEP

R

FB

(kΩ)

10

OUT

IN

OUT1

OUT2

OUT1

OUT2

IN

(V)

1.2

1.5

1.8

2.5

3.3

(CERAMIC) (BULK)*

(CER) EACH

(POSCAP) EACH

I

(mV)

33

25

33

25

30

28

30

27

34

30

50

33

50

DEVIATION

TIME (µs)

(A/µs)

2.5

TH

100µF

None

220µF

None

220µF

None

220µF

None

220µF

None

220µF

None

150µF

None

5

68

50

68

50

60

56

68

60

90

60

95

90

11

9

8

10µF ×2

100µF, 22µF ×2

22µF ×1

100µF, 22µF ×2

22µF ×1

100µF, 22µF ×2

22µF ×1

100µF, 22µF ×2

22µF ×1

None 3.3

10

11

10

12

10

12

10

None

5

5.76

3.92

2.37

1.62

None 3.3

None

5

100µF, 22µF ×2

22µF ×1

None 3.3

22µF ×1

None

5

100µF

None 3.3

None

5

22µF ×1

*Bulk capacitance is optional if V has very low input impedance.

IN

4615fb

19

For more information www.linear.com/LTM4615

LTM4615

applicaTions inForMaTion

V

3V TO 5.5V

IN

C2

10µF

6.3V

C1

10µF

6.3V

PGOOD1

R3

10k

V

IN2

PGOOD2

IN1

PGOOD1

V

1.2V

8A

OUT2

1.2V

V

FB1

COMP1

TRACK1

RUN/SS1

V

OUT1

OUT2

FB2

COMP2

TRACK2

RUN/SS2

FB2

COMP2

C6

100µF

6.3V

C5

100µF

6.3V

COMP2

V

LTM4615

GND2

IN

L1*

0.2µH

RUN/SS2

V

1V LOW NOISE AT 1A

OUT3

1.2V

LDO_IN

EN3

BOOST3

LDO_OUT

FB3

PGOOD3

C11

10µF

6.3V

PGOOD3

C13

0.01µF

R5

3.32k

C12

10µF

R1

4.99k

R6

10k

GND1

GND3

1V

LOW NOISE

*FAIR-RITE 0805 2508056007Y6

IF MORE FILTERING REQUIRED

4615 F13

Figure 13. LTM4615 Parallel 1.2V at 8A Design, 1V at 1A Design

V

IN

5V

C1

10µF

6.3V

C1

10µF

6.3V

PGOOD1

PGOOD2

R4

10k

R3

10k

V

IN2

PGOOD2

IN1

PGOOD1

V

3.3V

4A

OUT1

2.5V

4A

SLAVE

3.3V

MASTER

OUT2

V

FB1

V

OUT1

OUT2

FB2

COMP2

TRACK2

RUN/SS2

LDO_OUT

FB3

PGOOD3

R

TB

C3

22µF

6.3V

C6

22µF

6.3V

COMP1

TRACK1

RUN/SS1

LDO_IN

EN3

R

4.99k

FB2

1.62k

V OR A CONTROL RAMP

IN

LTM4615

GND2

V

1.8V AT 1A

R5

PGOOD3

OUT3

C5

22µF

6.3V

C4

C9

2.5V

22µF

6.3V

C11

10µF

6.3V

22µF

6.3V

BOOST3

C12

10µF

R

1.43k

FB1

TA

R6

10k

GND1

GND3

2.37k

1.8V

4615 F14

Figure 14. 3.3V and 2.5V at 4A with Output Voltage Tracking Design, 1.8V at 1A

4615fb

20

For more information www.linear.com/LTM4615

LTM4615

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

Z

b b b

Z

6 . 9 8 5 0

5 . 7 1 5 0

4 . 4 4 5 0

3 . 1 7 5 0

1 . 9 0 5 0

0 . 6 3 5 0

0 . 0 0 0 0

0 . 6 3 5 0

1 . 9 0 5 0

3 . 1 7 5 0

4 . 4 4 5 0

5 . 7 1 5 0

6 . 9 8 5 0

a a a

Z

4615fb

21

For more information www.linear.com/LTM4615

LTM4615

package DescripTion

LTM4615 Component LGA Pinout

PIN ID

A1

FUNCTION

GND2

PIN ID

B1

FUNCTION

GND2

SW2

PIN ID

C1

FUNCTION

PIN ID

D1

FUNCTION

PIN ID

E1

FUNCTION

GND2

PIN ID

F1

FUNCTION

GND3

FB3

V

IN2

V

IN2

V

IN2

V

IN2

V

IN2

V

IN2

V

IN2

V

IN2

V

IN2

V

IN2

V

IN2

A2

B2

C2

D2

E2

RUN/SS2

TRACK2

PGOOD2

COMP2

FB2

F2

A3

B3

SW2

C3

D3

E3

F3

A4

B4

SW2

C4

D4

E4

F4

A5

B5

SW2

C5

D5

E5

F5

A6

B6

SW2

C6

D6

GND2

E6

F6

A7

B7

GND2

C7

GND2

D7

E7

BOOST3

GND2

F7

GND3

EN3

A8

B8

C8

D8

E8

F8

A9

B9

C9

V

OUT2

V

OUT2

V

OUT2

V

OUT2

D9

V

OUT2

V

OUT2

V

OUT2

V

OUT2

E9

GND2

F9

GND3

A10

A11

A12

B10

B11

B12

C10

C11

C12

D10

D11

D12

E10

E11

E12

GND2

F10

F11

F12

V

OUT2

PIN ID

G1

FUNCTION

LDO_IN

PGOOD3

GND3

PIN ID

H1

FUNCTION

GND1

SW1

PIN ID

J1

FUNCTION

PIN ID

K1

FUNCTION

PIN ID

L1

FUNCTION

GND1

PIN ID

M1

FUNCTION

GND1

V

IN1

V

IN1

V

IN1

V

IN1

V

IN1

V

IN1

G2

H2

J2

K2

L2

RUN/SS1

TRACK1

PGOOD1

COMP1

FB1

M2

G3

H3

SW1

J3

K3

L3

M3

G4

H4

SW1

J4

K4

L4

M4

G5

H5

SW1

J5

K5

L5

M5

G6

H6

SW1

J6

GND1

K6

GND1

L6

M6

G7

GND3

H7

GND1

J7

K7

L7

GND1

M7

G8

GND3

H8

J8

K8

L8

GND1

M8

G9

LDO_OUT

H9

J9

K9

V

L9

V

M9

V

OUT1

G10

G11

G12

H10

H11

H12

J10

J11

J12

K10

K11

K12

L10

L11

L12

M10

M11

M12

4615fb

22

For more information www.linear.com/LTM4615

LTM4615

revision hisTory

REV

DATE

01/12 Added pin functions to the Pin Configuration diagram. Updated EN3 in the Absolute Maximum Ratings section.

Corrected the V accuracy limit.

DESCRIPTION

PAGE NUMBER

A

2

OUT

Clarified the SW1 and SW2 electrical connections.

Added the internal power inductor value to the Block Diagram.

Clarified the PGOOD behavior.

8

9

13

14

17

12

Clarified the reverse current protection behavior.

Added the suggested heat sink.

B

07/13 Changed “Overcurrent Foldback” to “Overtemperature”

4615fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

For more information www.linear.com/LTM4615

LTM4615

package phoTograph

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LTM4628

LTM4627

LTM4611

LTM4618

LTM4613

LTM4601AHV

26V, Dual 8A, DC/DC Step-Down μModule Regulator 4.5V ≤ V ≤ 26.5V, 0.6V ≤ V

≤ 5V, Remote Sense Amplifier, Internal

IN

OUT

Temperature Sensing Output, 15mm × 15mm × 4.32mm LGA

20V, 15A DC/DC Step-Down μModule Regulator

4.5V ≤ V ≤ 20V, 0.6V ≤ V ≤ 5V, PLL Input, V Tracking,

IN

OUT

Remote Sense Amplifier, 15mm × 15mm × 4.32mm LGA

1.5V , 15A DC/DC Step-Down μModule

1.5V ≤ V ≤ 5.5V, 0.8V ≤ V ≤ 5V, PLL Input, Remote Sense Amplifier,

OUT

IN(MIN)

IN

OUT

Regulator

V

Tracking, 15mm × 15mm × 4.32mm LGA

6A DC/DC Step-Down μModule Regulator

4.5V ≤ V ≤ 26.5V, 0.8V ≤ V

≤ 5V, PLL Input, V

Tracking,

IN

OUT

9mm × 15mm × 4.32mm LGA

5V ≤ V ≤ 36V, 3.3V ≤ V ≤ 15V, PLL Input, V Tracking and Margining,

OUT

8A EN55022 Class B DC/DC Step-Down μModule

Regulator

IN

OUT

15mm × 15mm × 4.32mm LGA

28V, 12A DC/DC Step-Down μModule Regulator

20V, 12A DC/DC Step-Down μModule Regulator

60V, 4A DC/DC Step-Down μModule Regulator

4.5V ≤ V ≤ 28V, 0.6V ≤ V

≤ 5V, PLL Input, Remote Sense Amplifier,

OUT

IN

OUT

V

Tracking and Margining, 15mm × 15mm × 2.8mm LGA or

OUT

15mm × 15mm × 3.42mm BGA

LTM4601A

4.5V ≤ V ≤ 20V, 0.6V ≤ V

IN

V

Tracking and Margining, 15mm × 15mm × 2.8mm LGA or

OUT

15mm × 15mm × 3.42mm BGA

LTM8027

LTM8033

4.5V ≤ V ≤ 60V, 2.5V ≤ V

≤ 24V, CLK Input, 15mm × 15mm × 4.32mm LGA

≤ 24V, Synchronizable,

IN

OUT

36V, 3A EN55022 Class B DC/DC Step-Down

μModule Regulator

3.6V ≤ V ≤ 36V, 0.8V ≤ V

IN

OUT

11.25mm × 15mm × 4.32mm LGA

LTM8061

32V, 2A Step-Down μModule Battery Charger with

Programmable Input Current Limit

Compatible with Single Cell or Dual Cell Li-Ion or Li-Poly Battery Stacks

(4.1V, 4.2V, 8.2V, or 8.4V), 4.95V ≤ V ≤ 32V, C/10 or Adjustable Timer Charge

IN

Termination, NTC Resistor Monitor Input, 9mm × 15mm × 4.32mm LGA

4615fb

LT 0713 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

For more information www.linear.com/LTM4615

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

●

 LINEAR TECHNOLOGY CORPORATION 2009


型号：	LTM4615IV#PBF
厂家：	Linear
描述：	LTM4615 - Triple Output, Low Voltage DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C 开关
文件：	总24页 (文件大小：515K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4615IV#PBF [Linear]

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