LTM4615IVPBF_技术文档

LTM4615

Triple Output, Low Voltage

DC/DC µModule Regulator

FEATURES

DESCRIPTION

TheLTM^®4615isacomplete4Adualoutputswitchingmode

DC/DC power supply plus an additional 1.5A VLDO (very

low dropout) linear regulator. Included in the package are

the switching controllers, power FETs, inductors, a 1.5A

regulator and all support components. The dual 4A DC/DC

converters operate over an input voltage range of 2.375V

to 5.5V, and the VLDO operates from a 1.14V to 3.5V input.

TheLTM4615supportsoutputvoltagesrangingfrom0.8V

to 5V for the DC/DC converters, and 0.4V to 2.6V for the

VLDO. The three regulator output voltages are set by a

single resistor for each output. Only bulk input and output

capacitors are needed to complete the design.

n

Dual 4A Output Power Supply with 1.5A VLDO™

n

Short-Circuit and Overtemperature Protection

Power Good Indicators

n

Switching Regulators Section—Current Mode Control

n

Input Voltage Range: 2.375V to 5.5V

n

4A DC Typical, 5A Peak Output Current Each

n

0.8V Up to 5V Output Each, Parallelable

n

2% Total DC Output Error

n

Output Voltage Tracking

n

Up to 95% Efﬁciency

n

Programmable Soft-Start

VLDO Section

n

The low proﬁle package (2.82mm) enables utilization of

unused space on the bottom of PC boards for high density

point of load regulation. High switching frequency and a

current mode architecture enables a very fast transient

response to line and load changes without sacriﬁcing

stability. The device supports output voltage tracking for

supply rail sequencing.

VLDO, 1.14V to 3.5V Input Range

n

VLDO, 0.4V to 2.6V, 1.5A Output

n

VLDO, 40dB Supply Rejection at f

1% Total DC Output Error

Small and Very Low Proﬁle Package:

15mm × 15mm × 2.82mm

SW

n

APPLICATIONS

Additional features include overvoltage protection,

foldback overcurrent protection, thermal shutdown and

programmable soft-start. The power module is offered in

a space saving and thermally enhanced 15mm × 15mm

× 2.82mm LGA package. The LTM4615 is Pb-free and

RoHS compliant.

n

Telecom and Networking Equipment

n

Industrial Power Systems

n

Low Noise Applications

FPGA, SERDES Power

n

L, LT, LTC, LTM, Linear Technology, the Linear logo and μModule are registered trademarks of

Linear Technology Corporation. VLDO is a trademark of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U.S. Patents including

5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174.

TYPICAL APPLICATION

Efﬁciency vs Output Current

1.2V at 4A, 1.5V at 4A and 1V at 1A DC/DC μModule^®Regulator

91

89

87

85

83

81

79

77

75

V

= 3.3V

IN

V

3V TO 5.5V

IN

PGOOD1

10μF

6.3V

PGOOD2

10μF

6.3V

V

OUT2

1.5V

V

IN2

PGOOD2

IN1

PGOOD1

10k

V

1.5V

4A

V

OUT2

OUT1

1.2V

4A

V

OUT1

1.2V

V

FB1

TRACK1

RUN/SS1

LDO_IN

EN3

V

OUT1

OUT2

FB2

V

OUT3

1V

LTM4615

GND2

22μF

6.3V

22μF

6.3V

V

TRACK2

RUN/SS2

LDO_OUT

FB3

PGOOD3

V

IN

(V = 1.2V)

IN

10k

5.76k

V

OUT3

1V AT 1A

1.2V

100μF

6.3V

100μF

6.3V

10μF

6.3V

PGOOD3

3.32k

10μF

GND1

GND3

10k

0

1

2

3

4

4615 TA01a

V

LOAD CURRENT (A)

OUT3

4615 TA01b

4615f

1

LTM4615

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

(See Pin Functions, Pin Conﬁguration Table)

Switching Regulators

IN1 IN2

TOP VIEW

V

, V , PGOOD1, PGOOD2 ..................... –0.3V to 6V

M

COMP1, COMP2, RUN/SS1, RUN/SS2

, V ,TRACK1, TRACK2 .......................–0.3V to V

L

K

J

V

FB1 FB2

IN

SW, V ........................................–0.3V to (V + 0.3V)

OUT

IN

Very Low Dropout Regulator

H

G

F

LDO_IN, PGOOD3........................................ –0.3V to 6V

LDO_OUT........................................................–0.3 to 4V

(EN3, FB3) to GND3............... –0.3V to (LDO_IN + 0.3V)

LDO_OUT Short-Circuit.................................... Indeﬁnite

Internal Operating Temperature Range

E

D

C

B

A

(Note 2).................................................. –40°C to 125°C

Junction Temperature ........................................... 125°C

Storage Temperature Range................... –55°C to 125°C

1

2

3

4

5

6

7

8

9

10

11

12

LGA PACKAGE

144-LEAD (15mm s 15mm s 2.8mm)

T

= 125°C, θ

= 2-3°C/W, θ = 15°C/W, θ

= 25°C/W, wt = 1.61g

JC-TOP

JMAX

JC-BOTTOM

JA

ORDER INFORMATION

LEAD FREE FINISH

LTM4615EV#PBF

LTM4615IV#PBF

TRAY

PART MARKING*

LTM4615V

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTM4615EV#PBF

LTM4615IV#PBF

144-Lead (15mm × 15mm × 2.8mm) LGA

LTM4615V

–40°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full internal

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 5V, LDO_IN = 1.2V unless otherwise noted.

Per Typical Application Figure 12.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Switching Regulator Section: per Channel

l

V

Input DC Voltage Range

Output DC Voltage Range

Output Voltage

2.375

0.8

5.5

5.0

V

IN(DC)

OUT(DC)

C

IN

V

IN

= 22μF, C

= 100μF, R = 5.76k,

OUT FB

= 2.375V to 5.5V, I

= 0A to 4A (Note 6)

OUT

0°C ≤ T ≤ 125°C

1.460

1.45

1.49

1.12

1.512

V

J

l

V

Undervoltage Lockout Threshold

I

= 0A

1.6

2

2.3

V

IN(UVLO)

OUT

4615f

2

LTM4615

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full internal

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 5V, LDO_IN = 1.2V unless otherwise noted.

Per Typical Application Figure 12.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

I

Input Inrush Current at Start-Up

I

= 0A, C = 22μF, C

IN

= 100μF, V

= 1.5V,

OUT

INRUSH(VIN)

OUT

V

IN

OUT

= 5.5V

0.35

A

I

Input Supply Bias Current

Input Supply Current

V

= 2.375V, V

= 1.5V, Switching Continuous

OUT

28

45

7

mA

μA

Q(VIN)

IN

= 5.5V, V

= 1.5V, Switching Continuous

OUT

Shutdown, RUN = 0, V = 5V

12

4

IN

I

V

IN

V

IN

= 2.375V, V

= 1.5V, I = 4A

OUT

3.2

1.48

A

S(VIN)

OUT

= 5.5V, V

= 1.5V, I

= 4A

OUT

Output Continuous Current Range

Load and Line Regulation Accuracy

V

= 5.5V, V

= 1.5V (Note 6)

0

A

OUT(DC)

IN

OUT

= 1.5V, 0A to 4A (Note 6)

IN

ΔV

OUT

OUT(LOAD + LINE)

V

= 2.375V to 5.5V

1.0

1.3

1.30

1.6

%

V

OUT

l

V

Output Ripple Voltage

I

= 0A, C

IN

= 100μF

OUT

OUT(AC)

OUT

V

= 5V, V

= 1.5V

12

mV

P-P

f

Output Ripple Voltage Frequency

Turn-On Overshoot

= 4A, V = 5V, V = 1.5V

OUT

1.25

MHz

s

OUT

IN

C

= 100μF, V

= 0A

= 1.5V, RUN/SS = 10nF,

ΔV

OUT

OUT(START)

I

OUT

V

= 3.3V

= 5V

20

mV

IN

V

t

Turn-On Time

C

= 100μF, V

= 1.5V, I

= 1A Resistive

OUT

START

OUT

IN

Load, TRACK = V and RUN/SS = Float

V

= 5V

0.5

25

ms

mV

IN

Peak Deviation for Dynamic Load

Load: 0% to 50% to 0% of Full Load,

= 100μF, V = 5V, V = 1.5V

ΔV

OUT(LS)

C

OUT

IN

OUT

t

Settling Time for Dynamic Load

Step

Load: 0% to 50% to 0% of Full Load,

10

8

μs

A

SETTLE

V

= 5V, V

= 1.5V

IN

OUT

I

Output Current Limit

Voltage at FB Pin

C

= 100μF, V = 5V, V

= 1.5V

OUT

OUT(PK)

OUT

IN

V

I

= 0A, V

= 1.5V

0.790

0.786

0.8

0.807

0.809

V

FB

OUT

l

I

0.2

0.75

0.2

μA

V

FB

V

RUN Pin On/Off Threshold

TRACK Pin Current

Offset Voltage

0.6

0.9

RUN

I

μA

mV

V

TRACK

V

TRACK = 0.4V

30

TRACK(OFFSET)

V

Tracking Input Range

0

0.8

TRACK(RANGE)

R

Resistor Between V

and FB Pins

OUT

4.96

4.99

7.5

90

5.02

kΩ

%

FBHI

ΔV

PGOOD Range

PGOOD

R

PGOOD Resistance

Open-Drain Pull-Down

(Note 3)

150

3.5

Ω

VLDO Section

l

V

Operating Voltage

Operating Current

Shutdown Current

1.14

4.8

V

mA

μA

V

LDO_IN

I

= 0mA, V = 1V, EN3 = 1.2V

OUT

1

IN(LDO_IN)

IN(SHDN)

OUT

EN3 = 0V, LDO_IN = 1.5V

EN3 = 1.2V

0.6

5

20

V

BOOST3 Output Voltage

Undervoltage Lockout

5.2

BOOST3

4.3

V

BOOST3(UVLO)

4615f

3

LTM4615

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full internal

operating temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 5V, LDO_IN = 1.2V unless otherwise noted.

Per Typical Application Figure 12.

SYMBOL

PARAMETER

CONDITIONS

1mA ≤ I ≤ 1.5A, 1.14V ≤ V ≤ 3.5V,

LDO_IN

MIN

TYP

MAX

UNITS

V

FB3

FB3 Internal Reference Voltage

0.397

0.395

0.4

0.404

0.405

V

OUT

l

BOOST3 = 5V, 1V ≤ V

≤ 2.59V

OUT

V

Output Voltage Range

Dropout Voltage

0.4

2.6

250

5.02

V

mV

kꢀ

A

LDO_OUT

V

= 1.5V, V = 0.38V, I

= 1.5A (Note 4)

100

DO

LDO_IN

FB3

OUT

LDO_RHI

LDO Top Feedback Resistor

Output Current

4.96

1.5

4.99

l

I

= 1.2V

EN3

OUT

LIM

Output Current Limit

Output Voltage Noise

EN3 Input High Voltage

EN3 Input Low Voltage

EN3 Input Current

(Note 5)

Frequency = 10Hz to 1MHz, I

2.5

A

e

n

= 1A

300

μRMS

V

LOAD

V

1.14V ≤ V

≤ 3.5V

1

IH_EN3

IL_EN3

IN_EN3

LDO_IN

0.4

1

V

I

–1

μA

V

PGOOD Low Voltage

I

= 2mA

0.1

0.4

OL_PGOOD3

PGOOD3

PGOOD Threshold Output Threshold

Relative to V

PGOOD3 High to Low

PGOOD3 Low to High

–14

–4

–12

–3

–10

–2

%

FB3

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: Minimum operating voltage required for regulation is:

≥ V + V

Note 4: Dropout voltage is the minimum input to output differential needed

V

IN

OUT(MIN)

DROPOUT

to maintain regulation at a speciﬁed output current. In dropout the output

Note 2: The LTM4615E is guaranteed to meet performance speciﬁcations

over the 0°C to 125°C internal operating temperature range. Speciﬁcations

over the –40°C to 125°C internal operating temperature range are assured

by design, characterization and correlation with statistical process

controls. The LTM4615I is guaranteed to meet speciﬁcations over the full

internal operating temperature range. Note that the maximum ambient

temperature is determined by speciﬁc operating conditions in conjunction

with board layout, the rated package thermal resistance and other

environmental factors.

voltage will be equal to V – V

.

IN

DROPOUT

Note 5: The IC has overtemperature protection that is intended to protect

the device during momentary overload conditions. Junction temperatures

will exceed 125°C when overtemperature is activated. Continuous

overtemperature activation can impair long-term reliability.

Note 6: See output current derating curves for different V , V

and T .

A

IN OUT

4615f

4

LTM4615

TYPICAL PERFORMANCE CHARACTERISTICS

Switching Regulators

Efﬁciency vs Output Current

V_IN= 2.5V

Efﬁciency vs Output Current

V_IN= 3.3V

Efﬁciency vs Output Current

V_IN= 5V

95

90

100

95

100

95

90

85

80

85

80

75

70

65

85

80

75

V

= 3.3V

= 2.5V

= 1.8V

= 1.5V

= 1.2V

= 0.8V

OUT

75

70

65

V

= 2.5V

= 1.8V

= 1.5V

= 1.2V

= 0.8V

OUT

V

= 1.8V

= 1.5V

= 1.2V

= 0.8V

OUT

70

65

1

2

4

0

1

2

3

4

0

3

1

2

4

0

3

OUTPUT CURRENT (A)

4615 G03

4615 G01

4615 G02

Minimum Input Voltage

at 4A Load

Load Transient Response

3.5

3.0

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

= 3.3V

= 2.5V

= 1.8V

= 1.5V

= 1.2V

= 0.8V

I

LOAD

2.5

2A/DIV

V

OUT

2.0

1.5

1.0

0.5

V

OUT

20mV/DIV

4615 G06

V

C

= 5V

20μs/DIV

IN

4615 G05

V

C

= 5V

20μs/DIV

IN

= 1.5V

OUT

= 1.2V

OUT

= 100μF, 6.3V CERAMICS

0

1.5

2.5

2

3

3.5

4 4.5

5 5.5

0.5

1

V

(V)

IN

4615 G04

Load Transient Response

I

LOAD

2A/DIV

I

LOAD

2A/DIV

V

OUT

V

OUT

20mV/DIV

OUT

20mV/DIV

4615 G07

4615 G08

4615 G09

V

C

= 5V

20μs/DIV

V

C

= 5V

20μs/DIV

V

C

= 5V

OUT

20μs/DIV

= 100μF, 6.3V CERAMICS

IN

= 1.8V

= 2.5V

= 3.3V

OUT

= 100μF, 6.3V CERAMICS

4615f

5

LTM4615

TYPICAL PERFORMANCE CHARACTERISTICS

Start-Up

V_FBvs Temperature

806

804

V

OUT

1V/DIV

802

800

I

IN

I

IN

1A/DIV

798

796

794

4615 G10

4615 G11

V

C

= 5V

200μs/DIV

V

C

= 5V

200μs/DIV

IN

= 2.5V

OUT

= 100μF

NO LOAD

4A LOAD

(0.01μF SOFT-START CAPACITOR)

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

4615 G12

Short-Circuit Protection

1.5V Short, No Load

Short-Circuit Protection

1.5V Short, 4A Load

Current Limit Foldback

1.6

1.4

1.2

1.0

V

OUT

0.5V/DIV

I

IN

0.8

0.6

1A/DIV

4A/DIV

V

= 1.5V

0.4

0.2

0

OUT

4615 G14

4615 G15

20μs/DIV

100μs/DIV

V

IN

V

IN

V

IN

= 5V

= 3.3V

= 2.5V

4

5

7

3

8

6

OUTPUT CURRENT (A)

4615 G13

VLDO

V_FB3vs Temperature

Dropout Voltage vs Input Voltage

Ripple Rejection

200

180

160

140

120

100

80

404

403

402

401

400

399

398

397

396

60

50

40

30

20

10

0

V

= 0.38V

FB3

10kHz

1MHz

I

=1.5A

LDO_OUT

100kHz

1mA

1.5A

60

–40°C

25°C

85°C

125°C

V

I

= 5V

BOOST3

40

=1.2V

V

= 5V

= 1.5V

=1.2V

LDO_OUT

BOOST3

LDO_IN

LDO_OUT

= 800mA

OUT

20

C

= 10μF

OUT

0

1.4

1.6 1.8 2.0

2.4 2.6

1.2

2.2

0

25

50

100 125

1.2

1.8 2.0 2.2

2.4

2.6

–50 –25

75

1.4

1.6

V

(V)

TEMPERATURE (°C)

V

(V)

LDO_IN

4615 G17

4615 G16

4615 G18

4615f

6

LTM4615

TYPICAL PERFORMANCE CHARACTERISTICS

Delay from Enable to Power Good

Ripple Rejection

Output Current Limit

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

70

60

50

40

30

20

10

0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

V

= 0.8V

= 8Ω

V

= 0V

LDO_OUT

R

T

= 25°C

A

–40°C

25°C

85°C

CURRENT LIMIT

V

= 5V

BOOST3

LDO_IN

= 1.5V

=1.2V

THERMAL LIMIT

LDO_OUT

I

= 800mA

OUT

C

= 10μF

OUT

1.0

1.5

2.0

V

2.5

(V)

3.0

3.5

1000

10000

1000000 1E+07

1.5

2.0

V

3.0

2.5

(V)

100

100000

1.0

3.5

FREQUENCY (Hz)

LDO_IN

4615 G21

4615 G19

4615 G20

Output Load Transient Response

IN Supply Transient Response

1.5A

2mA

I

LDO_OUT

2V

V

LDO_IN

1.5V

V

LDO_OUT

AC

20mV/DIV

V

LDO_OUT

AC

10mV/DIV

4615 G22

4615 G23

V

C

V

= 1.5V

50μs/DIV

V

I

= 1.2V

LDO_OUT

OUT

LDO_IN

BOOST3

10μs/DIV

LDO_OUT

OUT

BOOST3

= 25°C

= 10μF

= 800mA

= 1.7V

= 5V

C

= 10μF

= 5V

V

T

A

BOOST3 Ripple and Feedthrough to

V_{LDO_OUT}

BOOST3/OUT Start-Up

HI

EN3

LO

5V

BOOST3

AC 20mV/DIV

BOOST3

1V

1.5V

V

LDO_OUT

AC 5mV/DIV

V

LDO_OUT

0V

4615 G25

4615 G24

V

I

= 1.2V

= 1A

200μs/DIV

T

R

V

= 25°C

LDO_OUT

LDO_IN

20μs/DIV

A

= 1.5V

= 1Ω

LDO_OUT

= 1.7V

LDO_OUT

LDO_IN

C

= 10μF

OUT

T

= 25°C

A

4615f

7

LTM4615

PIN FUNCTIONS

V

, V (J1-J5, K1-K5); (C1-C6, D1-D5): Power Input

COMP1, COMP2 (L5, E5): Current Control Threshold

and Error Ampliﬁer Compensation Point. The current

comparator threshold increases with this control voltage.

Two power modules can current share when this pin is

connected in parallel with the adjacent module’s COMP

pin. Each channel has been internally compensated. See

the Applications Information section.

IN1 IN2

Pins. Apply input voltage between these pins and GND

pins. Recommend placing input decoupling capacitance

directly between V pins and GND pins.

IN

V

, V

(K9-K12, L9-L12, M9-M12); (C9-C12,

OUT2

OUT1

D9-D12, E11-E12): Power Output Pins. Apply output load

between these pins and GND pins. Recommend placing

outputdecouplingcapacitancedirectlybetweenthesepins

and GND pins. Review Table 4.

PGOOD1, PGOOD2 (L4, E4): Output Voltage Power

Good Indicator. Open-drain logic output that is pulled to

ground when the output voltage is not within 7.5% of

the regulation point.

GND1, GND2, (H1, H7-H12, J6-J12, K6-K8 L1, L7-L8,

M1-M8); (A1-A12, B1, B7-B12, C7-C8, D6-D8, E1,

E8-E10): Power Ground Pins for Both Input and Output

Returns.

RUN/SS1, RUN/SS2 (L2, E2): Run Control and Soft-Start

Pin.Avoltageabove0.8Vwillturnonthemodule,andbelow

0.5V will turn off the module. This pin has a 1M resistor to

TRACK1, TRACK2 (L3, E3): Output Voltage Tracking Pins.

When the module is conﬁgured as a master output, then a

soft-start capacitor is placed on the RUN/SS pin to ground

to control the master ramp rate, or an external ramp can

be applied to the master regulator’s track pin to control it.

Slave operation is performed by putting a resistor divider

from the master output to the ground, and connecting the

center point of the divider to this pin on the slave regulator.

If tracking is not desired, then connect the TRACK pin to

V and a 1000pF capacitor to GND. See the Applications

IN

Information section for soft-start information.

SW1, SW2 (H2-H6, B2-B6): The switching node of the

circuitisusedfortestingpurposes.Thiscanbeconnectedto

copper on the board for improved thermal performance.

LDO_IN (G1-G4): VLDO Input Power Pins. Place input

capacitor close to these pins.

LDO_OUT (G9-G12): VLDO Output Power Pins. Place

output capacitor close to these pins. Minimum 1mA load

is necessary for proper output voltage accuracy.

V . Load current must be present for tracking. See the

Applications Information section.

IN

FB1, FB2 (L6, E6): The Negative Input of the Switching

BOOST3 (E7): Boost Supply for Driving the Internal VLDO

NMOS Into Full Enhancement. The pin is use for testing

the internal boost converter. The output is typically 5V.

Regulators’ Error Ampliﬁer. Internally, these pins are con-

nected to V

with a 4.99k precision resistor. Different

OUT

output voltages can be programmed with an additional

resistorbetweentheFBandGNDpins.Twopowermodules

can current share when this pin is connected in parallel

with the adjacent module’s FB pin. See the Applications

Information section.

GND3(F1-F5,F7,F9-F12,G6-G8):Thepowergroundpins

for both input and output returns for the internal VLDO.

PGOOD3 (G5): VLDO Power Good Pin.

EN3 (F8): VLDO Enable Pin.

FB3 (F6): The Negative Input of the LDO Error Ampliﬁer.

Internally the pin is connected to LDO_OUT with a 4.99k

resistor.Differentoutputvoltagescanbeprogrammedwith

an additional resistor between the FB3 and GND pins. See

the Applications Information section.

4615f

8

LTM4615

SIMPLIFIED BLOCK DIAGRAM

Switching Regulator Block Diagram

V

PGOOD

IN

V

IN

2.375V TO 5.5V

22μF

6.3V

4.7μF

6.3V

R

SS

1M

RUN/SS

C

SS

1000pF

SSEXT

M1

M2

V

L

V

OUT

CONTROL, DRIVE

POWER FETS

4.99k

TRACK

COMP

1.5V

TRACK

SUPPLY

C2

470pF

4.7μF

6.3V

4A

22μF

6.3V

s3

5.76k

R1

4.99k

INTERNAL

COMP

GND

FB

SW

4615 F01a

R

FB

5.76k

VLDO Block Diagram

BOOST3

4.7μF

5V BOOST

LDO_IN

V

IN

1.14V TO 3.5V

4.7μF

6.3V

GND3

10μF

0.4V

+

–

V

OUT

GND3

LDO_OUT

CONTROL

1V

10μF 1.5A

4.7μF

6.3V

GND3

EN3

LDO_RHI

4.99k

ENABLE

GND3

FB3

R

FBLDO

PGOOD3

POWER GOOD

3.32k

GND3

10k

4615 F01b

GND

1V

Figure 1. Simpliﬁed LTM4615 Block Diagram of Each Switching Regulator Channel and the VLDO

DECOUPLING REQUIREMENTS ^T_A^{= 25°C. Use Figure 1 conﬁguration for each channel.}

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

C

External Input Capacitor Requirement

I

= 4A

22

μF

IN

OUT

(V = 2.375V to 5.5V, V

= 1.5V)

IN

OUT

C

External Output Capacitor Requirement

I

= 4A

66

100

10

μF

OUT

(V = 2.375V to 5.5V, V

= 1.5V)

IN

OUT

LDO_IN

LDO Input Capacitance

I

= 1A

4.7

10

μF

OUT

LDO_OUT

LDO Output Capacitance

OUT

4615f

9

LTM4615

OPERATION

LTM4615 POWER MODULE DESCRIPTION

The LTM4615 is internally compensated to be stable over

the operating conditions. Table 4 provides a guideline for

input and output capacitance for several operating condi-

tions. The Linear Technology ꢁModule Power Design Tool

will be provided for transient and stability analysis.

Dual Switching Regulator Section

The LTM4615 is a standalone dual nonisolated switching

modeDC/DCpowersupplywithanadditionalonboard1.5A

VLDO. It can deliver up to 4A of DC output current for each

channelwithfewexternalinputandoutputcapacitors.This

module provides two precisely regulated output voltages

programmable via one external resistor for each channel

from0.8VDCto5VDCovera2.375Vto5.5Vinputvoltage.

The VLDO is an independent 1.5A linear regulator that can

be powered from either switching converter. The typical

application schematic is shown in Figure 12.

The FB pins are used to program the speciﬁc output volt-

age with a single resistor to ground.

VLDO Section

The VLDO (very low dropout) linear regulator operates

from a 1.14V to 3.5V input. The VLDO uses an internal

NMOS transistor as the pass device in a source-follower

conﬁguration. The BOOST3 pin is the output of an inter-

nal boost converter that supplies the higher supply drive

to the pass device for low dropout enhancement. The

internal boost converter operates on very low current,

thus optimizing high efﬁciency for the VLDO in close to

dropout operation.

The LTM4615 has two integrated constant frequency cur-

rent mode regulators, with built-in power MOSFETs with

fast switching speed. The typical switching frequency is

1.25MHz.Withcurrentmodecontrolandinternalfeedback

loop compensation, these switching regulators have suf-

ﬁcient stability margins and good transient performance

under a wide range of operating conditions, and with a

wide range of output capacitors, even all ceramic output

capacitors.

An undervoltage lockout comparator on the LDO ensures

that the boost voltage is greater than 4.2V before enabling

the LDO, otherwise the LDO is disabled.

TheLDOprovidesahighaccuracyoutputcapableofsupply

1.5A of output current with a typical drop out of 100mV.

A single ceramic 10μF capacitor is all that is required

for output capacitor bypassing. A low reference voltage

allows the VLDO to have lower output voltages than the

commonly available LDO.

Currentmodecontrolprovidescycle-by-cyclefastcurrent

limit.Besides,currentlimitingisprovidedinanovercurrent

condition with thermal shutdown. In addition, internal

overvoltage and undervoltage comparators pull the open-

drain PGOOD outputs low if the particular output feedback

voltageexitsa 7.5%windowaroundtheregulationpoint.

Furthermore, in an overvoltage condition, internal top FET,

M1, is turned off and bottom FET, M2, is turned on and

held on until the overvoltage condition clears, or current

limit is exceeded.

The device also includes current limit and thermal over-

load protection. The NMOS follower architecture has fast

transient response without the traditional high drive cur-

rents in dropout. The VLDO includes a soft-start feature

to prevent excessive current on the input during start-up.

When the VLDO is enabled, the soft-start circuitry gradu-

ally increases the 0.4V reference voltage over a period of

approximately 200μs.

Pulling each speciﬁc RUN pin below 0.8V forces the spe-

ciﬁc regulator controller into its shutdown state, turning

off both M1 and M2 for each power stage. At low load

current, each regulator works in continuous current mode

by default to achieve minimum output voltage ripple.

The TRACK/SS pins are used for power supply tracking

and soft-start programming for each speciﬁc regulator.

See the Applications Information section.

4615f

10

LTM4615

APPLICATIONS INFORMATION

Dual Switching Regulator

For a buck converter, the switching duty cycle can be

estimated as:

The typical LTM4615 application circuit is shown in

Figure 12. External component selection is primarily

determined by the maximum load current and output

voltage. Refer to Table 4 for speciﬁc external capacitor

requirements for a particular application.

V_OUT

D =

V

IN

Without considering the inductor current ripple, the RMS

current of the input capacitor can be estimated as:

V to V

Step-Down Ratios

IN

OUT

I_OUT(MAX)

There are restrictions in the maximum V and V

step-

IN

OUT

I_CIN(RMS)

=

• D • 1–D

(

)

η%

down ratio than can be achieved for a given input voltage

on the two switching regulators. The LTM4615 is 100%

In the above equation, η% is the estimated efﬁciency of

the power module. The bulk capacitor can be a switcher-

rated electrolytic aluminum OS-CON capacitor for bulk

input capacitance due to high inductance traces or leads.

If a low inductance plane is used to power the device,

then no input capacitance is required. The internal 4.7μF

ceramicsoneachchannelinputaretypicallyratedfor1Aof

RMS ripple current up to 85°C operation. The worse-case

ripple current for the 4A maximum current is 2A or less.

An additional 10μF or 22μF ceramic capacitor can be used

to supplement the internal capacitor with an additional 1A

to 2A ripple current rating.

duty cycle, but the V to V

minimum dropout will be

OUT

IN

a function the load current. A typical 0.5V minimum is

sufﬁcient.

Output Voltage Programming

Each regulator channel has an internal 0.8V reference

voltage. As shown in the block diagram, a 4.99k internal

feedback resistor connects the V

and FB pins together.

OUT

The output voltage will default to 0.8V with no feedback

resistor. Adding a resistor R from the FB pin to GND

FB

programs the output voltage:

4.99k +R_FB

V_OUT= 0.8V •

R_FB

Output Capacitors

The LTM4615 switchers are designed for low output volt-

age ripple on each channel. The bulk output capacitors are

chosen with low enough effective series resistance (ESR)

to meet the output voltage ripple and transient require-

ments. The output capacitors can be a low ESR tantalum

capacitor,lowESRpolymercapacitororceramiccapacitor.

The typical output capacitance range is 66μF to 100μF.

Additional output ﬁltering may be required by the system

designer, if further reduction of output ripple or dynamic

transient spike is required. Table 4 shows a matrix of dif-

ferent output voltages and output capacitors to minimize

the voltage droop and overshoot during a 2A/μs transient.

The table optimizes total equivalent ESR and total bulk

capacitance to maximize transient performance.

Table 1. FB Resistor Table vs Various Output Voltages

V

0.8V

1.2V

10k

1.5V

1.8V

2.5V

3.3V

OUT

FB

Open

5.76k

3.92k

2.37k

1.62k

Input Capacitors

The LTM4615 module should be connected to a low AC

impedance DC source. One 4.7μF ceramic capacitor is

included inside the module for each regulator channel.

Additional input capacitors are needed if a large load step

is required up to the full 4A level and for RMS ripple cur-

rent requirements. A 47μF bulk capacitor can be used for

more input bulk capacitance. This 47μF capacitor is only

needed if the input source impedance is compromised by

long inductive leads or traces.

4615f

11

LTM4615

APPLICATIONS INFORMATION

Fault Conditions: Current Limit and Overcurrent

Foldback

where R and C are shown in the block diagram of

SS

Figure 1, and the 1.8V is soft-start upper range. The

soft-start function can also be used to control the output

ramp-up time, so that another regulator can be easily

tracked to it.

The LTM4615 has current mode control, which inher-

ently limits the cycle-by-cycle inductor current not only

in steady-state operation, but also in transient.

Output Voltage Tracking

Along with foldback current limiting in the event of an

overload condition, the LTM4615 has overtemperature

shutdown protection that inhibits switching operation

around 150°C for each channel.

Output voltage tracking can be programmed externally

using the TRACK pins. Either output can be tracked up

or down with another regulator. The master regulator’s

output is divided down with an external resistor divider

thatisthesameastheslaveregulator’sfeedbackdividerto

implement coincident tracking. The LTM4615 uses a very

accurate4.99kresistorfortheinternaltopfeedbackresistor.

Figure 2 shows an example of coincident tracking.

Run Enable and Soft-Start

The RUN/SS pins provide a dual function of enable and

soft-start control for each channel. The RUN/SS pins are

used to control turn on of the LTM4615. While each enable

pin is below 0.5V, the LTM4615 will be in a low quiescent

current state. At least a 0.8V level applied to the enable

pins will turn on the LTM4615 regulators. This pin can be

used to sequence the regulator channels. The soft-start

Equations:

⎛

⎞

R_FB1

4.99k +R

TRACK1=

•Master

⎜

⎟

⎝

⎠

FB1

control is provided by a 1M pull-up resistor (R ) and a

SS

1000pF capacitor (C ) as drawn in the block diagram for

SS

⎛

⎞

4.99k

R_FB1

Slave = 1+

• TRACK1

each channel. An external capacitor can be applied to the

RUN/SS pin to increase the soft-start time. A typical value

is 0.01μF. The approximate equation for soft-start:

⎜

⎝

⎟

⎠

⎛

⎞

V

IN

t_SOFTSTART= In

•R_SS•C_SS

⎜

⎟

V – 1.8V

⎝

⎠

IN

V

IN

3V TO 5.5V

C2

10μF

6.3V

C1

10μF

6.3V

PGOOD2

PGOOD1

R4

10k

R3

V

IN2

PGOOD2

IN1

10k

PGOOD1

MASTER

1.5V

SLAVE

1.2V

4A

V

FB1

V

OUT1

OUT2

4A

FB2

COMP2

TRACK2

RUN/SS2

LDO_OUT

FB3

PGOOD3

R

TB

4.99k

COMP1

TRACK1

RUN/SS1

LDO_IN

EN3

C10

22μF

6.3V

C3

22μF

6.3V

C6

22μF

6.3V

C8

22μF

6.3V

R

FB2

1.5V

R

V OR A CONTROL RAMP

LTM4615

GND2

IN

5.76k

L1 0.2μH*

1V LOW NOISE AT 1A

C5

22μF

6.3V

C4

22μF

6.3V

1.2V

C7

C9

C11

10μF

6.3V

22μF

6.3V

BOOST3

PGOOD3

R5

3.32k

C12

R

TA

C13

SSEXT

FB1

R6

10k

GND1

GND3

10μF

10k

C

1V

LOW NOISE

4615 F02

*FAIR-RITE 0805 2508056007Y6

OPTIONAL FILTER

Figure 2. Dual Outputs (1.5V and 1.2V) with Tracking

4615f

12

LTM4615

APPLICATIONS INFORMATION

Figure 3 shows the output voltage tracking waveform for

coincident tracking.

TRACK1 is the track ramp applied to the slave’s track pin.

TRACK1appliesthetrackreferencefortheslaveoutputup

to the point of the programmed value at which TRACK1

proceeds beyond the 0.8V reference value. The TRACK1

pin must go beyond the 0.8V to ensure the slave output

has reached its ﬁnal value.

Inratiometrictracking, adifferentslewratemaybedesired

for the slave regulator. R can be solved for when SR is

TB

slower than MR. Make sure that the slave supply slew rate

ischosentobefastenoughsothattheslaveoutputvoltage

will reach it ﬁnal value before the master output.

Ratiometric tracking can be achieved by a few simple

calculationsandtheslewratevalueappliedtothemaster’s

TRACK pin. As mentioned above, the TRACK pin has a

control range from 0V to 0.8V. The control ramp slew rate

applied to the master’s TRACK pin is directly equal to the

master’s output slew rate in Volts/Time.

For example, MR = 2.5V/ms and SR = 1.8V/1ms. Then

R

= 6.98k. Solve for R to equal to 3.24k. The master

TB

TA

output must be greater than the slave output for the

tracking to work. Output load current must be present

for tracking to operate properly during power-down.

The equation:

Power Good

MR

SR

• 4.99k = R_TB

PGOOD1 and PGOOD2 are open-drain pins that can be

usedtomonitorvalidoutputvoltageregulation.Thesepins

monitor a 7.5% window around the regulation point.

where MR is the master’s output slew rate and SR is the

slave’s output slew rate in Volts/Time. When coincident

tracking is desired, then MR and SR are equal, thus R

is equal to 4.99k. R is derived from equation:

COMP Pin

TB

This pin is the external compensation pin. The module has

alreadybeeninternallycompensatedforalloutputvoltages.

Table4isprovidedformostapplicationrequirements. The

Linear Technology μModule Power Design Tool will be

provided for other control loop optimization. The COMP

pins must be tied together in parallel operation.

TA

0.8V

V_FB

R_TA

=

V_TRACK

R_TB

V_FB

+

–

4.99k R_FB

where V is the feedback voltage reference of the regula-

FB

tor, and V

is 0.8V. Since R is equal to the 4.99k top

TB

Parallel Switching Regulator Operation

TRACK

feedback resistor of the slave regulator in equal slew rate

or coincident tracking, then R is equal to R with V

The LTM4615 switching regulators are inherently current

mode control. Paralleling will have very good current

sharing. This will balance the thermals on the design.

Figure 13 shows a schematic of a parallel design. The

voltage feedback equation changes with the variable N

as channels are paralleled.

=

FB

TA

FB

V . Therefore R = 4.99k and R = 10k in Figure 2.

TRACK

TB

TA

MASTER OUTPUT

SLAVE OUTPUT

The equation:

4.99k

+R_FB

N

V_OUT= 0.8V •

R_FB

N is the number of paralleled channels.

TIME

4615 F03

Figure 3. Output Voltage Coincident Tracking

4615f

13

LTM4615

APPLICATIONS INFORMATION

VLDO SECTION

10μF value. The X7R and X5R dielectrics are more stable

with DC bias and temperature, thus more preferred.

Adjustable Output Voltage

Short-Circuit/Thermal Protection

The output voltage is set by the ratio of two resistors. A

4.99k resistor is built onboard the module from LDO_OUT

The VLDO has built-in short-circuit current limiting of

~3A as well as overtemperature protection. During short-

circuit conditions the device is in control to 3A, and as

the internal temperature rises to approximately 150°C,

then the internal boost and LDO are shut down until the

internal temperature drops back to 140°C. The device will

cycle in and out of this mode with no latchup or damage.

Long term over stress in this condition can degrade the

device over time.

toFB3.Anadditionalresistor(R )isrequiredfromFB3

FBLDO

to GND3 to set the output voltage over a range of 0.4V to

2.6V. Minimum output current of 1mA is required for full

output voltage range.

The equation:

4.99k +R_FBLDO

V_OUT= 0.4V •

R_FBLDO

Reverse Current Protection

Power Good Operation

The VLDO features reverse current protection to limit

current draw from any supplementary power source at

the output. Figure 4 shows the reverse output current

limit for constant input and output cases. Note: Positive

input current represents current ﬂowing into the LDO_IN

pin. With LDO_OUT held at or below the output regula-

tion voltage and LDO_IN varied, input current ﬂow will

follow Figure 4 curves. Input reverse current ramps up

to 16μA as the LDO_IN approaches LDO_OUT. Reverse

input current will spike up as LDO_IN approaches with in

30mV of LDO_OUT as reverse current protection circuitry

is disabled and normal operation resumes. As LDO_IN

transitions above LDO_OUT the reverse current transi-

tions into short circuit current as long as LDO_OUT is

held below the regulation voltage.

The VLDO includes an open-drain power good (PGOOD3)

pin with hysteresis. If the VLDO is in shutdown or under

UVLO conditions (BOOST3 < 4.2V), then PGOOD3 is low

impedance to ground. PGOOD3 becomes high imped-

ance when the VLDO output voltage rises to 93% of its

regulated voltage. PGOOD3 stays high impedance until

the output voltage falls to 91% of its regulated voltage. A

pull-up resistor can be inserted between the PGOOD3 pin

and a positive logic supply such as the VLDO output or

V . LDO_IN should be at least 1.14V or greater for power

IN

good to operate properly.

Output Capacitance and Transient Response

The VLDO is designed to be stable with a wide range of

ceramic output capacitors. The ESR of the output capaci-

torsaffectsstability,especiallysmallervaluecapacitors.An

output capacitor of 10μF or greater with an ESR of 0.05Ω

or less is recommended to ensure stability. Larger value

capacitors can be used to reduce the transient deviations

under load changes. Bypass capacitors that are used at

the load device can also increase the effective output

capacitance. High ESR tantalum or electrolytic bulk ca-

pacitance can be used, but a ceramic capacitor must be

used in parallel at the output.

30

IN CURRENT

LIMIT ABOVE 1.45V

20

10

0

–10

–20

–30

Extra consideration should be given to the use of ceramic

capacitors related to dielectrics, temperature and DC bias

effects on the capacitor. The VLDO requires a minimum

0

0.9

INPUT VOLTAGE (V)

1.5

0.3

0.6

1.2

1.8

4615 F04

Figure 4. Reverse Current Limit for VLDO

4615f

14

LTM4615

TYPICAL APPLICATIONS

Thermal Considerations and Output Current Derating

power loss curves in Figures 5 and 6 show this amount of

power loss as a function of load current that is speciﬁed

for both channels. The monitored junction temperature of

120°Cminustheambientoperatingtemperaturespeciﬁes

how much module temperature rise can be allowed. As an

example in Figure 7 the load current is derated to 3A for

each channel with 0LFM at ~90°C and the power loss for

both channels at 5V to 1.2V at 3A output are ~1.4W, then

include the VDLO power loss of 0.5W to equal 1.9W. If the

90°C ambient temperature is subtracted from the 120°C

maximum junction temperature, then the difference of

30°C divided 1.9W equals a 15.7°C/W thermal resistance.

Table 2 speciﬁes a 15°C/W value which is very close. Table

2 and Table 3 provide equivalent thermal resistances for

1.2V and 3.3V outputs with and without air ﬂow and heat

sinking. The combined power loss for the two 4A outputs

plus the VLDO power loss can be summed together and

multiplied by the thermal resistance values in Tables 2

and 3 for module temperature rise under the speciﬁed

conditions. The printed circuit board is a 1.6mm thick

four layer board with two ounce copper for the two outer

layers and 1 ounce copper for the two inner layers. The

PCB dimensions are 95mm × 76mm. The BGA heat sinks

The power loss curves in Figures 5 and 6 can be used

in coordination with the load current derating curves in

Figures 7 to10 for calculating an approximate θ thermal

JA

resistance for the LTM4615 with various heat sinking and

airﬂow conditions. Both of the LTM4615 outputs are at full

4A load current, and the power loss curves in Figures 5

and 6 are combined power losses plotted for both output

voltages up to 4A each. The VLDO regulator is set to have

a power dissipation of a 0.5W since it is generally used

with dropout voltages of 0.5V or less. For example: 1.2V

to 1V, 1.5V to 1V, 1.5V to 1.2V and 1.8V to 1.5V. Other

drop voltages can be supported at VLDO maximum load,

but further thermal analysis will be required for the VLDO.

The 4A output voltages are 1.2V and 3.3V. These voltages

are chosen to include the lower and higher output voltage

ranges for correlating the thermal resistance. Thermal

models are derived from several temperature measure-

ments in a controlled temperature chamber along with

thermal modeling analysis. The junction temperatures are

monitoredwhileambienttemperatureisincreasedwithand

without airﬂow. The junctions are maintained at ~120°C

while lowering output current or power while increasing

ambient temperature. The 120°C is chosen to allow for

a 5°C margin window relative to the maximum 125°C.

The decreased output current will decrease the internal

module loss as ambient temperature is increased. The

are listed below Table 3. The data sheet lists the θ (Junc-

JP

tion to pin) and θ (Junction to case) thermal resistances

JC

under the Pin Conﬁguration diagram.

3.0

2.5

V

= 5V

V

= 5V

IN

2.5

2.0

1.5

1.0

0.5

0

2.0

1.5

1.0

0.5

0

1

2

3

4

0

1

2

3

4

LOAD CURRENT (A)

4615 F06

4615 F05

Figure 5. 1.2V Power Loss

Figure 6. 3.3V Power Loss

4615f

15

LTM4615

APPLICATIONS INFORMATION

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

4.5

V

= 5V

V

= 5V

IN

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0LFM HEATSINK

200LFM HEATSINK

400LFM HEATSINK

0LFM NO HEATSINK

200LFM NO HEATSINK

400LFM NO HEATSINK

0

40 50 60 70 80

120

90 100 110

40 50 60 70 80 90

AMBIENT TEMPERATURE (°C)

120

100 110

AMBIENT TEMPERATURE (°C)

4615 F08

4615 F07

Figure 7. 1.2V No Heat Sink

Figure 8. 1.2V Heat Sink

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

V

= 5V

V

= 5V

IN

0LFM HEATSINK

200LFM HEATSINK

400LFM HEATSINK

0LFM NO HEATSINK

200LFM NO HEATSINK

400LFM NO HEATSINK

0

40 50 60 70 80

120

90 100 110

40 50 60 70 80

AMBIENT TEMPERATURE (°C)

120

90 100 110

AMBIENT TEMPERATURE (°C)

4615 F10

4615 F09

Figure 9. 3.3V No Heat Sink

Figure 10. 3.3V Heat Sink

4615f

16

LTM4615

APPLICATIONS INFORMATION

Table 2. 1.2V Output

DERATING CURVE

Figure 7

V

IN

(V)

POWER LOSS CURVE

Figure 5

AIRFLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

15

5

0

Figure 7

5

Figure 5

200

400

0

None

12

Figure 7

Figure 5

None

10

Figure 8

Figure 5

BGA Heat Sink

14

Figure 8

Figure 5

200

400

9

Figure 8

Figure 5

8

Table 3. 3.3V Output

DERATING CURVE

Figure 9

V

IN

(V)

POWER LOSS CURVE

Figure 6

AIRFLOW (LFM)

HEAT SINK

None

θ

JA

(°C/W)

15

5

0

Figure 9

Figure 6

200

400

0

None

12

Figure 9

Figure 6

None

10

Figure 10

Figure 6

BGA Heat Sink

14

Figure 10

Figure 6

200

400

9

Figure 10

Figure 6

8

HEAT SINK MANUFACTURER

PART NUMBER

WEBSITE

Aavid

375424b00034G

www.aavid.com

4615f

17

LTM4615

APPLICATIONS INFORMATION

Safety Considerations

• Place high frequency ceramic input and output capaci-

tors next to the V , GND and V

pins to minimize

IN

OUT

TheLTM4615modulesdonotprovideisolationfromV to

IN

high frequency noise.

V

.Thereisnointernalfuse.Ifrequired,aslowblowfuse

OUT

with a rating twice the maximum input current needs to be

• Place a dedicated power ground layer underneath the

unit.

provided to protect each unit from catastrophic failure.

• Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between the top layer and other power layers.

Layout Checklist/Example

The high integration of LTM4615 makes the PCB board

layoutverysimpleandeasy.However,tooptimizeitselectri-

cal and thermal performance, some layout considerations

are still necessary.

• Do not put via directly on pads unless the via is

capped.

Figure 11 gives a good example of the recommended

layout.

• Use large PCB copper areas for high current path,

including V , GND and V . It helps to minimize the

IN

OUT

PCB conduction loss and thermal stress.

V

CONTROL

GND1

OUT1

C

IN1

GND1

M

L

C

OUT1 OUT2

V

OUT1

K

J

V

IN1

SW1

GND1

H

G

F

C

IN2

OUT3

LD0_IN

GND3

GND2

LDO_OUT

GND3

E

C

OUT4 OUT5

CONTROL

D

C

B

A

V

OUT2

V

IN2

GND2

C

IN3

1

2

3

4

5

6

7

8

9

10 11 12

GND2

4615 F11

GND2

SW2

Figure 11. Recommended PCB Layout

4615f

18

LTM4615

APPLICATIONS INFORMATION

V

3V TO 5.5V

IN

C

10μF

6.3V

C

IN2

IN1

10μF

PGOOD1

PGOOD2

6.3V

R3

10k

R4

10k

V

IN2

PGOOD2

IN1

PGOOD1

V

1.5V

4A

V

OUT2

OUT1

1.2V

V

FB1

V

OUT1

OUT2

4A

FB2

COMP2

TRACK2

RUN/SS2

LDO_OUT

FB3

PGOOD3

C

OUT2

COMP1

TRACK1

RUN/SS1

LDO_IN

EN3

100μF

6.3V

R

22μF

6.3V

22μF

6.3V

FB2

100μF

6.3V

5.76k

V

IN

LTM4615

GND2

IN

V

OUT3

L1 0.2μH*

1V LOW NOISE AT 1A

C

OUT1

1.2V

22μF

6.3V

22μF

6.3V

C11

10μF

6.3V

BOOST3

PGOOD3

R5

C12

10μF

R

FB1

R6

10k

GND1

GND3

3.32k

10k

V

OUT3

4615 F12

*FAIR-RITE 0805 2508056007Y6

IF MORE FILTERING REQUIRED

Figure 12. Typical 3V to 5.5V_IN, 1.5V and 1.2V at 4A and 1V at 1A Design

Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 12) 0A to 2.5A Load Step Typical Measured Values

C

AND C

C

AND C

OUT1

OUT2

OUT1 OUT2

CERAMIC VENDORS

VALUE

PART NUMBER

BULK VENDORS

VALUE

PART NUMBER

10TPD150M

4TPE220MF

TDK

22μF 6.3V

22μF 16V

100μF 6.3V

C3216X7SOJ226M

Sanyo POSCAP

150μF 10V

220μF 4V

VALUE

Murata

TDK

GRM31CR61C226KE15L Sanyo POSCAP

C4532X5R0J107MZ

GRM32ER60J107M

C

IN

BULK VENDORS

PART NUMBER

10CE100FH

Murata

Sanyo POSCAP

100μF 10V

V

C

AND C

C

AND C

V

DROOP PEAK-TO-PEAK RECOVERY LOAD STEP

R

FB

(kΩ)

10

OUT

IN

OUT1

OUT2

OUT1

OUT2

IN

(V)

1.2

1.5

1.8

2.5

3.3

(CERAMIC) (BULK)*

(CER) EACH

(POSCAP) EACH

I

(mV)

33

25

33

25

30

28

30

27

34

30

50

33

50

DEVIATION

TIME (μs)

(A/μs)

2.5

TH

100μF

None

220μF

None

220μF

None

220μF

None

220μF

None

220μF

None

150μF

None

5

68

50

68

50

60

56

68

60

90

60

95

90

11

9

8

10μF ×2

100μF, 22μF ×2

22μF ×1

100μF, 22μF ×2

22μF ×1

100μF, 22μF ×2

22μF ×1

100μF, 22μF ×2

22μF ×1

None 3.3

10

11

10

12

10

12

10

None

5

5.76

3.92

2.37

1.62

None 3.3

None

5

100μF, 22μF ×2

22μF ×1

None 3.3

22μF ×1

None

5

100μF

None 3.3

None

5

22μF ×1

*Bulk capacitance is optional if V has very low input impedance.

IN

4615f

19

LTM4615

APPLICATIONS INFORMATION

V

3V TO 5.5V

IN

C2

10μF

6.3V

C1

10μF

6.3V

PGOOD1

R3

10k

V

IN2

PGOOD2

IN1

PGOOD1

V

1.2V

8A

OUT2

1.2V

V

FB1

COMP1

TRACK1

RUN/SS1

V

OUT1

OUT2

FB2

COMP2

TRACK2

RUN/SS2

FB2

COMP2

C6

100μF

6.3V

C5

100μF

6.3V

COMP2

V

LTM4615

GND2

IN

L1*

0.2μH

RUN/SS2

V

1V LOW NOISE AT 1A

OUT3

1.2V

LDO_IN

EN3

BOOST3

LDO_OUT

FB3

PGOOD3

C11

10μF

6.3V

PGOOD3

C13

0.01μF

R5

3.32k

C12

10μF

R1

4.99k

R6

10k

GND1

GND3

1V

LOW NOISE

*FAIR-RITE 0805 2508056007Y6

IF MORE FILTERING REQUIRED

4615 F13

Figure 13. LTM4615 Parallel 1.2V at 8A Design, 1V at 1A Design

4615f

20

LTM4615

APPLICATIONS INFORMATION

V

5V

IN

C1

10μF

6.3V

C1

10μF

PGOOD1

6.3V

PGOOD2

R4

10k

R3

10k

V

IN2

PGOOD2

IN1

PGOOD1

V

3.3V

4A

OUT1

2.5V

4A

SLAVE

3.3V

MASTER

OUT2

V

FB1

V

OUT1

OUT2

FB2

COMP2

TRACK2

RUN/SS2

LDO_OUT

FB3

PGOOD3

R

TB

C3

22μF

6.3V

C6

22μF

6.3V

COMP1

TRACK1

RUN/SS1

LDO_IN

EN3

R

4.99k

FB2

1.62k

V OR A CONTROL RAMP

IN

LTM4615

GND2

V

1.8V AT 1A

R5

PGOOD3

OUT3

C5

22μF

6.3V

C4

C9

2.5V

22μF

6.3V

C11

10μF

6.3V

22μF

6.3V

BOOST3

C12

10μF

2.37k

R

TA

1.43k

FB1

R6

10k

GND1

GND3

2.37k

1.8V

4615 F14

Figure 14. 3.3V and 2.5V at 4A with Output Voltage Tracking Design, 1.8V at 1A

4615f

21

LTM4615

PACKAGE DESCRIPTION

Z

b b b

Z

6 . 9 8 5 0

5 . 7 1 5 0

4 . 4 4 5 0

3 . 1 7 5 0

1 . 9 0 5 0

0 . 6 3 5 0

0 . 0 0 0 0

0 . 6 3 5 0

1 . 9 0 5 0

3 . 1 7 5 0

4 . 4 4 5 0

5 . 7 1 5 0

6 . 9 8 5 0

4615f

22

LTM4615

PACKAGE DESCRIPTION

LTM4615 Component LGA Pinout

PIN ID

A1

FUNCTION

GND2

PIN ID

B1

FUNCTION

GND2

SW2

PIN ID

C1

FUNCTION

PIN ID

D1

FUNCTION

PIN ID

E1

FUNCTION

GND2

PIN ID

F1

FUNCTION

GND3

FB3

V

IN2

A2

B2

C2

D2

E2

RUN/SS2

TRACK2

PGOOD2

COMP2

FB2

F2

A3

B3

SW2

C3

D3

E3

F3

A4

B4

SW2

C4

D4

E4

F4

A5

B5

SW2

C5

D5

E5

F5

A6

B6

SW2

C6

D6

GND2

E6

F6

A7

B7

GND2

C7

GND2

D7

E7

BOOST3

GND2

F7

GND3

EN3

A8

B8

C8

D8

E8

F8

A9

B9

C9

V

D9

V

E9

GND2

F9

GND3

OUT2

A10

A11

A12

B10

B11

B12

C10

C11

C12

D10

D11

D12

E10

E11

E12

GND2

F10

F11

F12

V

OUT2

PIN ID

G1

FUNCTION

LDO_IN

PGOOD3

GND3

PIN ID

H1

FUNCTION

GND1

SW1

PIN ID

J1

FUNCTION

PIN ID

K1

FUNCTION

PIN ID

L1

FUNCTION

GND1

PIN ID

M1

FUNCTION

GND1

V

IN1

G2

H2

J2

K2

L2

RUN/SS1

TRACK1

PGOOD1

COMP1

FB1

M2

G3

H3

SW1

J3

K3

L3

M3

G4

H4

SW1

J4

K4

L4

M4

G5

H5

SW1

J5

K5

L5

M5

G6

H6

SW1

J6

GND1

K6

GND1

L6

M6

G7

GND3

H7

GND1

J7

K7

L7

GND1

M7

G8

GND3

H8

J8

K8

L8

GND1

M8

G9

LDO_OUT

H9

J9

K9

V

L9

V

M9

V

OUT1

G10

G11

G12

H10

H11

H12

J10

J11

J12

K10

K11

K12

L10

L11

L12

M10

M11

M12

4615f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTM4615

PACKAGE PHOTOGRAPH

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

4.5V ≤ V ≤ 28V, 0.6V ≤ V

LTM4600HV

10A DC/DC μModule

≤ 5V, LGA Package

OUT

IN

LTM4600HVMP

Military Plastic 10A DC/DC μModule

Guaranteed Operation from –55°C to 125°C Ambient, LGA Package

LTM4601/LTM4601A 12A DC/DC μModule with PLL, Output Tracking/Margining Synchronizable PolyPhase^®Operation, LTM4601-1/LTM4601A-1

and Remote Sensing

Version Has No Remote Sensing, LGA Package

LTM4602

LTM4603

6A DC/DC μModule

Pin Compatible with the LTM4600, LGA Package

6A DC/DC μModule with PLL and Output Tracking/

Margining and Remote Sensing

Synchronizable, PolyPhase Operation, LTM4603-1 Version Has No

Remote Sensing, Pin Compatible with the LTM4601, LGA Package

LTM4604A

LTM4605

LTM4607

LTM4608A

Low V 4A DC/DC μModule

2.375V ≤ V ≤ 5.5V, 0.8V ≤ V

≤ 5V, 9mm × 15mm × 2.3mm

IN

OUT

LGA Package

5A to 12A Buck-Boost μModule

4.5V ≤ V ≤ 20V, 0.8V ≤ V

≤ 16V, 15mm × 15mm × 2.8mm

≤ 25V, 15mm × 15mm × 2.8mm

≤ 5V, 9mm × 15mm × 2.8mm

≤ 5V, 15mm × 15mm × 2.8mm

IN

OUT

LGA Package

4.5V ≤ V ≤ 36V, 0.8V ≤ V

IN

LGA Package

Low V 8A DC/DC Step-Down μModule

2.7V ≤ V ≤ 5.5V, 0.6V ≤ V

IN

OUT

LGA Package

LTM4614

LTM4616

Dual 4A Low V DC/DC μModule

2.375V ≤ V ≤ 5.5V, 0.8V ≤ V

IN

OUT

Dual 8A Low V DC/DC μModule

Current Share Input or Output, Similar to LTM4608,

15mm × 15mm × 2.8mm

IN

LTM8020

LTM8021

LTM8022

LTM8023

High V 0.2A DC/DC Step-Down μModule

4V ≤ V ≤ 36V, 1.25V ≤ V

≤ 5V, 6.25mm × 6.25mm × 2.3mm

IN

OUT

LGA Package

High V 0.5A DC/DC Step-Down μModule

3V ≤ V ≤ 36V, 0.4V ≤ V

≤ 5V, 6.25mm × 11.25mm × 2.8mm

IN

OUT

LGA Package

High V 1A DC/DC Step-Down μModule

3.6V ≤ V ≤ 36V, 0.8V ≤ V

≤ 10V, 11.25mm × 9mm × 2.8mm

IN

OUT

LGA Package

High V 2A DC/DC Step-Down μModule

3.6V ≤ V ≤ 36V, 0.8V ≤ V

IN

LGA Package

PolyPhase is a registered trademark of Linear Technology Corporation.

4615f

LT 0709 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTM4615IVPBF
厂家：	Linear
描述：	Triple Output, Low Voltage DC/DC μModule Regulator 三路输出，低电压DC / DC μModule稳压器稳压器
文件：	总24页 (文件大小：408K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4615IVPBF [Linear]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E