LTM4628IV#PBF [Linear]
LTM4628 - Dual 8A or Single 16A DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C;型号: | LTM4628IV#PBF |
厂家: | Linear |
描述: | LTM4628 - Dual 8A or Single 16A DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C 开关 |
文件: | 总36页 (文件大小:1024K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM4628
Dual 8A or Single 16A
DC/DC µModule Regulator
FEATURES
DESCRIPTION
The LTM®4628 is a complete dual 8A output switching
mode DC/DC power supply and can be easily configured
to provide a single 2-phase 16A output. Included in the
packagearetheswitchingcontroller,powerFETs,inductor,
and all supporting components. Operating from an input
voltage range of 4.5V to 26.5V, the LTM4628 supports
two outputs each with an output voltage range of 0.6V to
5.5V, set by a single external resistor. Its high efficiency
design delivers 8A continuous current for each output.
Only a few input and output capacitors are needed.
n
Complete Standalone Dual Power Supply
n
Single 16A or Dual 8A Output
n
Wide Input Voltage Range: 4.5V to 26.5V
n
Output Voltage Range: 0.6V to 5.5V
n
1.5ꢀ ꢁotal DC Output Error
n
Differential Remote Sense Amplifier
n
Current Mode Control/Fast ꢁransient Response
n
Adjustable Switching Frequency
n
n
Overcurrent Foldback Protection
Multiphase Parallel Current Sharing with
Multiple LꢁM4628s
The device supports frequency synchronization, multi-
phaseoperation,BurstModeoperationandoutputvoltage
tracking for supply rail sequencing. It has an onboard
temperature diode for device temperature monitoring.
High switching frequency and a current mode architec-
ture enable a very fast transient response to line and load
changes without sacrificing stability.
n
n
n
n
n
n
Frequency Synchronization
Internal ꢁemperature Sensing Diode Output
Selectable Burst Mode® Operation
Soft-Start/Voltage Tracking
Output Overvoltage Protection
Small Surface Mount Footprint, Low Profile
15mm × 15mm × 4.32mm LGA and
15mm × 15mm × 4.92mm BGA Packages
Fault protection features include overvoltage and over-
current protection. The power module is offered in space
saving and thermally enhanced 15mm × 15mm × 4.32mm
LGA and 15mm × 15mm × 4.92mm BGA packages. The
LTM4628 is available with SnPb (BGA) or RoHS compli-
ant terminal finish.
APPLICATIONS
n
Telecom and Networking Equipment
n
Storage and ATCA Cards
n
Industrial Equipment
L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule, Burst Mode and PolyPhase
are registered and LTpowerCAD is a trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
Dual 8A, 1.5V and 1.2V Output DC/DC µModule® Regulator
4.7µF
Efficiency and Power Loss
at 12V Input
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
V
IN
95
90
85
80
75
70
65
60
55
50
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
OUT1
1.5V AT 8A
4.5V TO
26.5V
1.2V
V
IN
V
OUT1
10µF
35V
×4
1.5V
EFFICIENCY
100µF
6.3V
*
*
TEMP
V
120k
OUTS1
470µF
6.3V
10k
RUN1
DIFFOUT
RUN2
SW1
TRACK1
TRACK2
V
V
FB1
FB2
LTM4628
5.1V ZENER
40.2k
f
0.1µF
COMP1
COMP2
SET
60.4k
POWER LOSS
PHASMD
V
OUTS2
V
OUT2
1.2V AT 8A
V
100k
OUT2
SW2
100µF
6.3V
470µF
6.3V
PGOOD2
0
1
2
3
4
5
6
7
8
SGND
GND
DIFFP
DIFFN
LOAD CURRENT (A)
* PULL-UP RESISTOR AND
ZENER ARE OPTIONAL.
4628 TA01b
4628 TA01a
4628fe
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For more information www.linear.com/LTM4628
LTM4628
ABSOLUTE MAXIMUM RATINGS (Note 1)
DIFFP, DIFFN .........................................–0.3V to INTV
FB1 FB2
V ............................................................. –0.3V to 28V
SW1 SW2
CC
IN
V
, V , COMP1, COMP2 (Note 6)........ –0.3V to 2.7V
V
, V
....................................................–1V to 28V
INTV Peak Output Current................................100mA
PGOOD1, PGOOD2, RUN1, RUN2,
CC
Internal Operating Temperature Range
INTV , EXTV ........................................... –0.3V to 6V
CC
CC
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Package Body Temperature .......................... 245°C
MODE_PLLIN, f , TRACK1, TRACK2,
SET
DIFFOUT, PHASMD...............................–0.3V to INTV
OUT1 OUT2 OUTS1 OUTS2
CC
V
, V
, V
, V
..................... –0.3V to 6V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
M
M
V
V
IN
IN
L
K
J
L
K
J
EXTV
CC
TEMP
EXTV
CC
TEMP
INTV
INTV
CC
CC
H
G
F
H
G
F
SW1
SW2
SW1
SW2
PHASMD CLKOUT
PGOOD2 PGOOD1
DIFFOUT RUN2
PHASMD CLKOUT
PGOOD2 PGOOD1
DIFFOUT RUN2
SGND
SGND
MODE_PLLIN RUN1
MODE_PLLIN RUN1
GND
GND
GND
GND
TRACK1 COMP1 COMP2 DIFFP
DIFFN
TRACK1 COMP1 COMP2 DIFFP
DIFFN
E
E
V
V
FB2
V
V
FB1
SGND
TRACK2
FB1
FB2
SGND
TRACK2
D
C
B
A
D
C
B
A
V
f
V
SGND
V
f
V
OUTS1
SET
OUTS2
SGND
OUTS1
SET
OUTS2
V
VOUT2
GND
OUT1
GND
V
VOUT2
OUT1
1
2
3
4
5
6
7
8
9
10 11 12
1
2
3
4
5
6
7
8
9
10 11 12
LGA PACKAGE
144-LEAD (15mm × 15mm × 4.32mm)
= 125°C, θ = 17°C/W,θ = 2.75°C/W,
BGA PACKAGE
144-LEAD (15mm × 15mm × 4.92mm)
= 125°C, θ = 17°C/W,θ = 2.75°C/W,
T
T
JMAX
θ
JCtop
JCbottom
JMAX
θ
JCtop
JCbottom
+ θ = 11°C/W, θ = 9.5°C/W–11°C/W,
+ θ = 11°C/W, θ = 9.5°C/W–11°C/W,
JB
BA
JA
JB BA JA
θ
= BOARD TO AMBIENT RESISTANCE, θ VALUES DEFINED PER JESD 51-12
θ
= BOARD TO AMBIENT RESISTANCE, θ VALUES DEFINED PER JESD 51-12
BA
BA
WEIGHT = 2.7g
WEIGHT = 2.9g
ORDER INFORMATION
PARꢁ MARKING*
PACKAGE
ꢁYPE
MSL
ꢁEMPERAꢁURE RANGE
(Note 2)
PARꢁ NUMBER
LTM4628EV#PBF
LTM4628IV#PBF
LTM4628EY#PBF
LTM4628IY#PBF
LTM4628IY
PAD OR BALL FINISH
Au (RoHS)
DEVICE
FINISH CODE
RAꢁING
LTM4628V
LTM4628V
LTM4628Y
LTM4628Y
LTM4628Y
e4
e4
e1
e1
e0
LGA
LGA
BGA
BGA
BGA
3
3
3
3
3
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
Au (RoHS)
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
• Terminal Finish Part Marking:
www.linear.com/leadfree
4628fe
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For more information www.linear.com/LTM4628
LTM4628
ELECTRICAL CHARACTERISTICS ꢁhe l denotes the specifications which apply over the full internal
operating temperature range (Note 2). Specified as each individual output channel. ꢁA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted, per the typical application in Figure 28.
SYMBOL
PARAMEꢁER
CONDIꢁIONS
MIN
4.5
ꢁYP
MAX UNIꢁS
l
l
V
V
Input DC Voltage
Output Voltage
26.5
5.5
V
V
IN
0.6
OUT
V
V
,
Output Voltage, Total Variation with
Line and Load
C
= 22µF × 3, C
= 100µF × 1
OUT1(DC)
OUT2(DC)
IN
OUT
Ceramic, 470µF POSCAP, MODE_PLLIN =
GND, RFB1, RFB2 = 40.2k, V = 4.5V to 26.5V,
l
1.477
1.1
1.5
1.523
1.40
V
IN
I
= 0A to 8A
OUT
Input Specifications
V
V
, V
RUN Pin On/Off Threshold
RUN Pin On Hysteresis
RUN Rising
1.25
150
1
V
mV
A
RUN1 RUN2
, V
RUN1HYS RUN2HYS
I
Input Inrush Current at Start-Up
I
= 0A, C = 22µF × 3,
INRUSH(VIN)
OUT
IN
C
V
= 100µF , 470µF POSCAP V
= 1.5V,
OUT
OUT2
OUT1
= 1.5V, V = 12V, TRACK = 0.01µF
IN
I
Input Supply Bias Current
Input Supply Current
V
V
V
= 12V, V
= 1.5V, Burst Mode Operation
= 1.5V, Pulse-Skipping Mode
5
mA
mA
mA
µA
Q(VIN)
IN
IN
IN
OUT
OUT
= 12V, V
15
65
60
= 12V, V = 1.5V, Switching Continuous
OUT
Shutdown, RUN = 0, V = 12V
IN
I
V
IN
V
IN
V
IN
= 4.75V, V
= 1.5V, I
= 8A
2.9
1.18
0.575
A
A
A
S(VIN)
OUT
OUT
= 12V, V
= 1.5V, I
= 8A
OUT
OUT
= 26.5V, V
= 1.5V, I
= 8A
OUT
OUT
Output Specifications
, I
I
Output Continuous
Current Range
V
V
= 12V, V = 1.5V (Note 7)
OUT
0
8
A
%/V
%
OUT1(DC) OUT2(DC)
IN
l
l
ΔV
ΔV
/V
Line Regulation Accuracy
Load Regulation Accuracy
Output Ripple Voltage
= 1.5V, V from 4.5V to 26.5V
0.010
0.15
15
0.04
0.3
OUT1(LINE) OUT1
OUT
IN
/V
I
= 0A for Each Output,
OUT
OUT2(LINE) OUT2
ΔV
ΔV
/V
For Each Output, V
= 1.5V, 0A to 8A
OUT1(LOAD) OUT1
OUT
/V
V
= 12V (Note 7)
OUT2(LOAD) OUT2
IN
V
, V
I
= 0A, C
= 100µF X5R Ceramic,
mV
P-P
OUT1(AC) OUT2(AC)
OUT
OUT
470µF POSCAP
V
IN
= 12V, V
= 1.5V
OUT
f (Each Channel)
Output Ripple Voltage Frequency
SYNC Capture Range
V
IN
= 12V, V
= 1.5V, f = 2.5V (Note 4)
780
kHz
kHz
S
OUT
SET
f
400
780
SYNC
(Each Channel)
ΔV
Turn-On Overshoot
Turn-On Time
C
V
= 100µF X5R Ceramic, 470µF POSCAP,
10
5
mV
ms
OUTSTART
OUT
OUT
(Each Channel)
= 1.5V, I
= 0A V = 12V
OUT IN
t
C
OUT
= 100µF X5R Ceramic, 470µF POSCAP,
START
(Each Channel)
No Load, TRACK/SS with 0.01µF to GND,
V
= 12V
IN
ΔV
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load
30
mV
OUT(LS)
(Each Channel)
C
= 22µF × 3 X5R Ceramic, 470µF POSCAP
OUT
V
= 12V, V
= 1.5V
IN
OUT
t
Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load,
20
15
µs
A
SETTLE
(Each Channel)
V
= 12V, C
= 100µF, C
= 470µF
OUT
IN
OUT
I
Output Current Limit
V
IN
= 12V, V
= 1.5V
OUT(PK)
OUT
(Each Channel)
Control Section
l
l
V
, V
Voltage at V Pins
I
= 0A, V
= 1.5V
0.592
0.64
0.600 0.606
V
FB1 FB2
FB
OUT
OUT
I
, I
Leakage Current of V , V
(Note 6)
–5
–20
nA
FB1 FB2
FB1 FB2
V
Feedback Overvoltage Lockout
0.66
0.68
V
OVL
4628fe
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For more information www.linear.com/LTM4628
LTM4628
ELECTRICAL CHARACTERISTICS ꢁhe l denotes the specifications which apply over the full internal
operating temperature range (Note 2). Specified as each individual output channel. ꢁA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V
unless otherwise noted, per the typical application in Figure 28.
SYMBOL
, I
PARAMEꢁER
CONDIꢁIONS
MIN
ꢁYP
MAX UNIꢁS
I
Track Pin Soft-Start Pull-Up Current TRACK1, TRACK2 = 0V
1
1.25
1.5
µA
TRACK1 TRACK2
UVLO
Undervoltage Lockout Threshold
Minimum On-Time
V
V
Falling
Rising
3.3
3.9
V
V
IN
IN
UVLO Hysteresis
0.6
90
V
ns
t
(Note 6)
ON(MIN)
R
, R
Resistor Between V
, V
60.05
60.4
60.75
0.3
5
kΩ
FBHI1 FBHI2
OUTS1 OUTS2
and V , V Pins for Each Output
FB1 FB2
V
PGOOD Voltage Low
I
= 2mA
= 5V
0.1
V
OL_PGOOD
PGOOD
(Each Channel)
I
PGOOD Leakage Current
PGOOD Trip Level
V
µA
PGOOD
PGOOD
V
V
V
V
with Respect to Set Output Voltage
Ramping Negative
Ramping Positive
PGOOD
FB
FB
FB
–10
10
%
%
INꢁV Linear Regulator
CC
V
Internal V Voltage
6V < V < 26.5V
4.8
4.5
5
5.2
2
V
INTVCC
CC
IN
V
INTV Load Regulation
I
CC
= 0mA to 50mA
0.5
%
INTVCC
CC
Load Regulation
V
V
V
EXTV Switchover Voltage
EXTV Ramping Positive
4.7
50
V
mV
mV
EXTVCC
CC
CC
EXTV Dropout
I
CC
= 20mA, V = 5V
EXTVCC
100
EXTVCC(DROP)
EXTVCC(HYST)
CC
EXTV Hysteresis
200
CC
Oscillator and Phase-Locked Loop
f
f
f
I
Nominal Frequency
f
f
f
= 1.2V
450
210
700
9
500
250
780
10
550
290
860
11
kHz
kHz
kHz
µA
NOM
LOW
HIGH
fSET
SET
SET
SET
Lowest Frequency
= 0V (Note 5)
> 2.4V, Up to INTV
Highest Frequency
CC
Frequency Set Current
Mode_PLLIN Input Resistance
R
250
kΩ
MODE_PLLIN
Ph
Phase (Relative to V
)
PHASMD = GND
PHASMD = Float
PHASMD = INTV
60
90
120
Deg
Deg
Deg
CLKOUT
OUT1
CC
V
V
Clock High Output Voltage
Clock Low Output Voltage
2
V
V
OH_CLKOUT
OL_CLKOUT
0.2
3
Differential Amplifier
A
Voltage Gain
1
V/V
kΩ
mV
dB
V
R
Input Resistance
Measured at DIFFP Input
= V = 1.5V, I
80
IN
V
Input Offset Voltage
V
DIFFP
= 100µA
DIFFOUT
OS
DIFFOUT
PSRR
Power Supply Rejection Ratio
Maximum Output Current
Maximum Output Voltage
Gain Bandwidth Product
5V < V < 20V
90
3
IN
I
mA
V
CL
DIFFOUT (MAX)
GBW
I
= 300µA
INTV – 1.4V
CC
DIFFOUT
3
MHz
4628fe
4
For more information www.linear.com/LTM4628
LTM4628
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: Two outputs are tested separately and the same testing condition
is applied to each output.
Note 4: The switching frequency is programmable for 400kHz to 750kHz.
Note 5: LTM4628 device is designed to operate from 400kHz to 750kHz
Note 6: 100% tested at wafer level.
Note 2: The LTM4628 is tested under pulsed load conditions such that
T ≈ T . The LTM4628E is guaranteed to meet specifications from
J
A
Note 7: See output current derating curves for different V , V
and T .
A
IN OUT
0°C to 125°C internal temperature. Specifications over the –40°C to
125°C internal operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTM4628I is guaranteed over the full –40°C to 125°C internal operating
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
TYPICAL PERFORMANCE CHARACTERISTICS
5VIN Efficiency
12VIN Efficiency
24VIN Efficiency
100
95
90
85
80
75
70
65
60
55
100
95
90
85
80
75
70
65
95
90
85
80
75
70
65
60
55
50
FREQ = 500kHz, 700kHz for 3.3V AND 5V
FREQ = 500kHz, 700kHz for 3.3V AND 5V
FREQ = 500kHz
5V
OUT
3.3V
2.5V
1.5V
1.2V
0.8V
3.3V
2.5V
1.5V
1.2V
0.8V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
5V
OUT
3.3V
2.5V
1.5V
OUT
OUT
OUT
4
5
0
1
2
3
6
7
8
4
5
4
5
0
1
2
3
6
7
8
0
1
2
3
6
7
8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4628 G02
4628 G01
4628 G03
Burst Mode Pulse-Skipping
Efficiency
0.8V Load ꢁransient
1.2V Load ꢁransient
100
90
80
70
60
50
40
30
20
10
0
Burst Mode OPERATION
V
V
OUT
OUT
50mV/DIV
50mV/DIV
I
I
OUT
OUT
2A/DIV
2A/DIV
4628 G05
4628 G06
PULSE-SKIPPING MODE
100µs/DIV
100µs/DIV
12V , 0.8V
OUT1
, 0A TO 4A LOAD STEP AT 4A/µs
IN
OUT
12V , 1.2V
OUT1
, 0A TO 4A LOAD STEP AT 4A/µs
OUT
IN
C
4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE
C
, 4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE
0.01
OUTPUT CURRENT (A)
SWITCHING FREQUENCY 400kHz
CAPACITOR = 47pF
0.001
0.1
1
10
SWITCHING FREQUENCY 500kHz
CAPACITOR = 47pF
C
FF
C
FF
4628 G04
4628fe
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For more information www.linear.com/LTM4628
LTM4628
TYPICAL PERFORMANCE CHARACTERISTICS
1.5V Load ꢁransient
1.8V Load ꢁransient
2.5V Load ꢁransient
V
OUT
100mV/DIV
V
V
OUT
OUT
50mV/DIV
50mV/DIV
I
I
OUT
I
OUT
OUT
2A/DIV
2A/DIV
2A/DIV
4628 G07
4628 G08
4628 G09
100µs/DIV
100µs/DIV
100µs/DIV
12V , 1.5V
OUT1
, 0A TO 4A LOAD STEP AT 4A/µs
12V , 1.8V
OUT1
, 0A TO 4A LOAD STEP AT 4A/µs
12V , 2.5V
OUT1
SWITCHING FREQUENCY 500kHz
C CAPACITOR = 47pF
FF
, 0A TO 4A LOAD STEP AT 4A/µs
OUT
IN
OUT
IN
OUT
IN
C
4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE
C
4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE
C
, 4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE
SWITCHING FREQUENCY 500kHz
CAPACITOR = 47pF
SWITCHING FREQUENCY 500kHz
CAPACITOR = 47pF
C
C
FF
FF
3.3V Load ꢁransient
Output Start-Up
Output Start-Up
V
OUT
100mV/DIV
V
V
OUT
OUT
1V/DIV
1V/DIV
5ms/DIV
5ms/DIV
INPUT
CURRENT
1A/DIV
INPUT
CURRENT
1A/DIV
I
OUT
2A/DIV
4628 G10
4628 G12
4628 G11
100µs/DIV
20ms/DIV
20ms/DIV
V
V
I
= 12V
V
V
I
= 12V
IN
IN
12V , 3.3V
OUT1
, 0A TO 4A LOAD STEP AT 4A/µs
OUT
, 4× 100µF 6.3V X5R CERAMIC 1210 CASE SIZE
IN
= 2.5V
= 8A
= 2.5V
= 0A
OUT
OUT
OUT
OUT
C
SWITCHING FREQUENCY 500kHz
CAPACITOR = 47pF
C
FF
Output Short-Circuit
Output Short-Circuit
Coincident ꢁracking
V
V
OUT
OUT
1V/DIV
1V/DIV
5ms/DIV
5ms/DIV
INPUT
CURRENT
2A/DIV
INPUT
CURRENT
2A/DIV
4628 G13
4628 G14
4628 G15
50µs/DIV
50µs/DIV
10ms/DIV
= 1.8V AT 8A
= 1.2V AT 8A
V
V
I
= 12V
V
= 12V
IN
IN
V
V
OUT1
OUT2
= 2.5V
= 0A
V
I
= 2.5V
OUT
= 8A
OUT
OUT
OUT
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LTM4628
TYPICAL PERFORMANCE CHARACTERISTICS
COMP1 and COMP2
vs Output Current
IOUꢁ1 and IOUꢁ2 vs ꢁotal Current
for Parallel Operation
9
8
7
6
5
4
3
2
1
0
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
I
I
V
ITH2
OUT1
OUT2
ITH1
V
8
10
0
2
4
6
12 14 16
3
4
0
1
2
5
6
7
8
9
TOTAL OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4628 G16
4628 G17
(Recommended to Use ꢁest Points to Monitor Signal Pin Connections.)
PIN FUNCTIONS
V
(A1-A5, B1-B5, C1-C4): Power Output Pins. Apply
f
(C6): Frequency Set Pin. A 10µA current is sourced
OUꢁ1
SEꢁ
outputloadbetweenthesepinsandGNDpins.Recommend
placing output decoupling capacitance directly between
these pins and GND pins. Review Table 4.
from this pin. A resistor from this pin to ground sets a
voltage that in turn programs the operating frequency.
Alternatively, this pin can be driven with a DC voltage
that can set the operating frequency. See the Applications
Information section.
GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12,
F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1,
J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power
Ground Pins for Both Input and Output Returns.
SGND(C7, D6, G6-G7, F6-F7):SignalGroundPin. Return
ground path for all analog and low power circuitry. Tie a
single connection to the output capacitor GND in the ap-
plication. See layout guidelines in Figure 27.
V
(A8-A12, B8-B12, C9-C12): Power Output Pins.
OUꢁ2
Apply output load between these pins and GND pins. Rec-
ommend placing output decoupling capacitance directly
between these pins and GND pins. Review Table 4.
V
, V
(D5, D7): The Negative Input of the Error
FB1
FB2
Amplifier for Each Channel. Internally, this pin is con-
nected to V or V with a 60.4kΩ precision
OUTS1
OUTS2
V
, V
(C5, C8): This pin is connected to the top
OUꢁS1 OUꢁS2
resistor. Different output voltages can be programmed
of the internal top feedback resistor for each output. The
pin can be directly connected to its specific output, or
connected to DIFFOUT when the remote sense amplifier
with an additional resistor between V and GND pins. In
FB
PolyPhase® operation, tying the V pins together allows
FB
for parallel operation. See the Applications Information
section for details.
is used. In paralleling modules, one of the V
pins is
OUTS
connectedtotheDIFFOUTpininremotesensingordirectly
to V with no remote sensing. It is very important to
OUT
connect these pins to either the DIFFOUT or V
since
OUT
this is the feedback path, and cannot be left open. See the
Applications Information section.
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LTM4628
PIN FUNCTIONS (Recommended to Use ꢁest Points to Monitor Signal Pin Connections.)
ꢁRACK1, ꢁRACK2 (E5, D8): Output Voltage Tracking Pin
and Soft-Start Inputs. Each channel has a 1.3µA pull-up
current source. When one channel is configured to be
master of the two channels, then a capacitor from this pin
to ground will set a soft-start ramp rate. The remaining
channel can be set up as the slave, and have the master’s
output applied through a voltage divider to the slave out-
put’s track pin. This voltage divider is equal to the slave
output’s feedback divider for coincidental tracking. See
the Applications Information section.
DIFFOUꢁ (F8): Internal Remote Sense Amplifier Output.
Connect this pin to V or V depending on which
OUTS1
OUTS2
output is using remote sense. In parallel operation con-
nect one
of the V
pin to DIFFOUT for remote sensing.
OUTS
Leave floating if the remote sense amplifier is not used.
SW1, SW2 (G2, G11): Switching node of each channel
that is used for testing purposes. Also an R-C snubber
network can be applied to reduce or eliminate switch node
ringing, otherwise leave floating. See the Applications
Information section.
COMP1, COMP2 (E6, E7): Current control threshold and
error amplifier compensation point for each channel. The
current comparator threshold increases with this control
voltage. Tie the COMP pins together for parallel operation.
The device is internal compensated.
PHASMD(G4):ConnectthispintoSGND,INTV ,orfloat-
CC
ing this pin to select the phase of CLKOUT to 60 degrees,
120 degrees, and 90 degrees respectively.
CLKOUꢁ (G5): Clock output with phase control using the
PHASMD pin to enable multiphase operation between
devices. See the Applications Information section.
DIFFP (E8): Positive input of the remote sense amplifier.
Thispinisconnectedtotheremotesensepointoftheoutput
voltage. Use of the remote sense amplifier is limited to an
outputvoltagebetween0.6Vand3.3Vinclusive.Connectto
GNDifnotused. SeetheApplicationsInformationsection.
PGOOD1, PGOOD2 (G9, G8): Output Voltage Power
Good Indicator. Open drain logic output that is pulled to
ground when the output voltage is not within 7.5% of
the regulation point.
DIFFN (E9): Negative input of the remote sense amplifier.
This pin is connected to the remote sense point of the
output GND. See the Applications Information section.
INꢁV (H8): Internal 5V Regulator Output. The control
CC
circuits and internal gate drivers are powered from this
voltage. INTV is controlled and enabled when RUN1 or
CC
MODE_PLLIN (F4): Force Continuous Mode, Burst Mode
Operation, or Pulse-Skipping Mode Selection Pin and
External Synchronization Input to Phase Detector Pin.
Connect this pin to SGND to force both channels into
RUN2 is activated high. Decouple this pin to PGND with
a 4.7µF low ESR tantalum or ceramic.
ꢁEMP (J6): Onboard Temperature Diode for Monitoring
the VBE Junction Voltage Change with Temperature. See
the Applications Information section.
force continuous mode of operation. Connect to INTV
CC
to enable pulse-skipping mode of operation. Leaving the
pin floating will enable Burst Mode operation. A clock on
the pin will force both channels into continuous mode of
operation and synchronized to the external clock applied
to this pin.
EXꢁV (J7): External power input that is enabled through
CC
a switch to INTV whenever EXTV is greater than 4.7V.
CC
CC
Do not exceed 6V on this input, and connect this pin to
V when operating V on 5V. An efficiency increase will
IN
IN
occur that is a function of the (V – INTV ) multiplied by
RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above
1.25V will turn on each channel in the module. A voltage
below 1.25V on the RUN pin will turn off the related chan-
nel. Each RUN pin has a 1µA pull-up current, once the
RUN pin reaches 1.2V an additional 4.5µA pull-up current
is added to this pin.
IN
CC
powerMOSFETdrivercurrent.Typicalcurrentrequirement
is 30mA. V must be applied before EXTV , and EXTV
IN
CC
CC
must be removed before V .
IN
V (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11):
IN
Power Input Pins. Apply input voltage between these pins
and GND pins. Recommend placing input decoupling
capacitance directly between V pins and GND pins.
IN
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LTM4628
SIMPLIFIED BLOCK DIAGRAM
PGOOD1
TRACK1
SS CAP
V
IN
C
10µF
35V
C
10µF
35V
IN1
IN2
1µF
GND
R
T
V
TEMP
CLKOUT
RUN1
IN
100µA =
V
IN
MTOP1
MBOT1
R
T
SW1
V
0.68µH
1.5V/8A
OUT1
+
MODE_PLLIN
PHASEMD
2.2µF
C
OUT1
GND
V
OUTS1
COMP1
60.4k
V
FB1
INTERNAL
COMP
R
FB1
40.2k
SGND
POWER
CONTROL
PGOOD2
TRACK2
V
IN
INTV
CC
C
10µF
35V
C
10µF
35V
IN3
IN4
SS CAP
1µF
4.7µF
EXTV
GND
CC
MTOP2
MBOT2
SW2
V
0.68µH
1.2V/8A
OUT2
+
RUN2
2.2µF
C
OUT2
GND
V
OUTS2
60.4k
COMP2
XI
V
FB2
+
–
R
FB2
60.4k
INTERNAL
COMP
f
SET
INTERNAL
FILTER
R
fSET
SGND
DIFFOUT
DIFFN
DIFFP
4628 BD
Figure 1. Simplified LꢁM4628 Block Diagram
ꢁA = 25°C. Use Figure 1 configuration.
CONDIꢁIONS
DECOUPLING REQUIREMENTS
SYMBOL
PARAMEꢁER
MIN
ꢁYP
MAX
UNIꢁS
External Input Capacitor Requirement
C
C
, C
IN2 IN4
(V = 4.5V to 26.5V, V
= 1.5V)
= 1.5V)
I
I
= 8A
= 8A
22
22
µF
µF
IN1 IN3
IN1
OUT1
OUT2
OUT1
OUT2
, C
(V = 4.5V to 26.5V, V
IN2
External Output Capacitor Requirement
C
C
(V = 4.5V to 26.5V, V
= 1.5V)
= 1.5V)
I
I
= 8A
= 8A
300
300
µF
µF
OUT1
OUT2
IN1
OUT1
OUT2
OUT1
OUT2
(V = 4.5V to 26.5V, V
IN2
4628fe
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LTM4628
OPERATION
Power Module Description
The LTM4628 is internally compensated to be stable over
all operating conditions. Table 2 provides a guideline
for input and output capacitances for several operating
conditions. LTpowerCAD™ is available for transient and
The LTM4628 is a dual-output standalone nonisolated
switching mode DC/DC power supply. It can provide two
8A outputs with few external input and output capacitors
and setup components. This module provides precisely
regulated output voltages programmable via external
stability analysis. The V pin is used to program the
FB
output voltage with a single external resistor to ground.
A differential remote sense amplifier is available for sens-
ing the output voltage accurately on one of the outputs at
the load point, or in parallel operation sensing the output
voltage at the load point.
resistors from 0.6V to 5V over 4.5V to 26.5V input
DC
DC
voltages. The typical application schematic is shown in
Figure 28.
TheLTM4628hasdualintegratedconstant-frequencycur-
rent mode regulators and built-in power MOSFET devices
withfastswitchingspeed. Thetypicalswitchingfrequency
is 550kHz. For switching-noise sensitive applications, it
can be externally synchronized from 400kHz to 780kHz.
A resistor can be used to program a free run frequency
Multiphase operation can be easily employed with the
MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12
phases can be cascaded to run simultaneously with re-
spect to each other by programming the PHASMD pin to
different levels. See the Applications Information section.
on the f pin. See the Applications Information section.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation or pulse-skipping
operation using the MODE_PLLIN pin. These light load
features will accommodate battery operation. Efficiency
graphs are provided for light load operation in the Typical
PerformanceCharacteristics section.SeetheApplications
Information section for details.
SET
With current mode control and internal feedback loop
compensation, the LTM4628 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limitandfoldbackcurrentlimitinanovercurrentcondition.
Internal overvoltage and undervoltage comparators pull
the open-drain PGOOD outputs low if the output feedback
voltageexitsa 7.5%windowaroundthe regulationpoint.
If the output voltage exceeds 10% above its normal op-
erating point then the bottom power MOSFET will try to
clamp the output to protect it.
Atemperaturediodeisincludedinsidethemoduletomoni-
tor the temperature of the module. See the Applications
Information section for details.
The switch pins are available for functional operation
monitoring and a resistor-capacitor snubber circuit can
be carefully placed on the switch pin to ground to dampen
any high frequency ringing on the transition edges. See
the Applications Information section for details.
Pulling the RUN pins below 1.1V forces the regulators into
ashutdownstate,byturningoffbothMOSFETs.TheTRACK
pinsareusedforprogrammingtheoutputvoltagerampand
voltage tracking during start-up or used for soft-starting
the regulator. See the Applications Information section.
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LTM4628
APPLICATIONS INFORMATION
The typical LTM4628 application circuit is shown in
Figure 28. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 4 for specific external capacitor
requirements for particular applications.
In parallel operation the V pins have an I current of
FB FB
20nA maximum each channel. To reduce output voltage
error due to this current, an additional V pin can be
OUTS
tied to V , and an additional R resistor can be used
OUT
FB
to lower the total Thevenin equivalent resistance seen by
this current. For example in Figure 2, the total Thevenin
equivalentresistanceoftheV pinis(60.4k//R ), which
V to V
Step-Down Ratios
IN
OUꢁ
FB
FB
is 30.2k where R is equal to 60.4k for a 1.2V output.
FB
There are restrictions in the maximum V and V
step-
IN
OUT
Four phases connected in parallel equates to a worse case
down ratio that can be achieved for a given input voltage.
feedbackcurrentof4•I equals80nAmaximum.Thevolt-
FB
Each output of the LTM4628 is capable of 98% duty cycle,
age error is 80nA•30.2k = 2.4mV. If V
is connected
OUTS2
but the V to V
minimum dropout is still shown as a
OUT
IN
as shown in Figure 2 to V , and another 60.4k resistor is
OUT
function of its load current and will limit output current
connected from V to ground, then the voltage error is
FB2
capability related to high duty cycle on the top side switch.
Minimum on-time t
reduced to 1.2mV. If the voltage error is acceptable then
is another consideration in
ON(MIN)
no additional connections are necessary. The onboard
operating at a specified duty cycle while operating at a
certain frequency due to the fact that t < D/f
60.4k resistor is 0.5% accurate and the V resistor can
FB
,
SW
ON(MIN)
be chosen by the user to be as accurate as needed.
where D is duty cycle and f is the switching frequency.
SW
t
is specified in the electrical parameters as 90ns.
AllCOMPpinsaretiedtogetherforcurrentsharingbetween
thephases.TheTRACKpinscanbetiedtogetherandasingle
soft-start capacitor can be used to soft-start the regula-
tor. The soft-start equation will need to have the soft-start
current parameter increased by the number of paralleled
channels. See the Output Voltage Tracking section.
ON(MIN)
Output Voltage Programming
ThePWM controllerhasaninternal0.6Vreferencevoltage.
AsshownintheBlockDiagram,a60.4kΩinternalfeedback
resistor connects between the V
to V and V
OUTS1
FB1 OUTS2
to V . It is very important that these pins be connected
FB2
4 PARALLELED OUTPUTS
FOR 1.2V AT 32A
to their respective outputs for proper feedback regulation.
LTM4628
60.4k
V
V
COMP1
COMP2
OUT1
OUT2
OvervoltagecanoccuriftheseV
andV
pinsare
OUTS1
OUTS2
left floating when used as individual regulators, or at least
one of them is used in paralleled regulators. The output
voltage will default to 0.6V with no feedback resistor on
V
OUTS1
OUTS2
V
OPTIONAL CONNECTION
OPTIONAL
V
FB1
either V or V . Adding a resistor R from V pin to
FB1
FB2
FB
FB
60.4k
TRACK1
TRACK2
GND programs the output voltage:
V
FB2
60.4k + RFB
R
FB
60.4k
VOUT = 0.6V •
RFB
LTM4628
60.4k
V
COMP1
COMP2
OUT1
OUT2
USED TO LOWER TOTAL
V
THEVENIN EQUIVALENT TO
ꢁable 1. VFB Resistor ꢁable vs Various Output Voltages
0.6V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V
Open 90.9k 60.4k 40.2k 30.2k 19.1k 13.3k 8.25k
LOWER I VOLTAGE ERROR
FB
V
V
OUTS1
OUTS2
V
5.0V
OUꢁ
R
FB
V
FB1
60.4k
For parallel operation of multiple channels the same feed-
back setting resistor can be used for the parallel design.
TRACK1
TRACK2
V
FB2
0.1µF
R
FB
This is done by connecting the V
to the output as
4628 F02
OUTS1
60.4k
shown in Figure 2, thus tying one of the internal 60.4k
resistors to the output. All of the V pins tie together with
FB
Figure 2. 4-Phase Parallel Configurations
one programming resistor as shown in Figure 2.
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LTM4628
APPLICATIONS INFORMATION
Input Capacitors
to optimize the transient performance. Stability criteria
are considered in the Table 4 matrix, and LTpowerCAD™
is available for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the num-
ber of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
afunctionofstabilityandtransientresponse.LTpowerCAD
can calculate the output ripple reduction as the number of
implemented phases increases by N times. A small value
The LTM4628 module should be connected to a low ac-
impedance DC source. For the regulator input three 22µF,
or four 10µF input ceramic capacitors are used for RMS
ripple current. A 47µF to 100µF surface mount aluminum
electrolytic bulk capacitor can be used for more input bulk
capacitance. This bulk input capacitor is only needed if
the input source impedance is compromised by long in-
ductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
10Ω to 50Ω resistor can be placed in series from V
OUT
to the V
pin to allow for a bode plot analyzer to inject
OUTS
For a buck converter, the switching duty-cycle can be
estimated as:
a signal into the control loop and validate the regulator
stability. The same resistor could be placed in series from
V
toDIFFPandabodeplotanalyzercouldinjectasignal
OUT
VOUT
into the control loop and validate the regulator stability.
D =
V
IN
Burst Mode Operation
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
The LTM4628 is capable of Burst Mode operation on
each regulator in which the power MOSFETs operate
intermittentlybasedonloaddemand,thussavingquiescent
current. For applications where maximizing the efficiency
at very light loads is a high priority, Burst Mode operation
should be applied. Burst Mode operation is enabled with
the MODE_PLLIN pin floating. During this operation, the
peak current of the inductor is set to approximately one
third of the maximum peak current value in normal opera-
tion even though the voltage at the COMP pin indicates
a lower value. The voltage at the COMP pin drops when
the inductor’s average current is greater than the load
requirement. As the COMP voltage drops below 0.5V, the
Burst comparator trips, causing the internal sleep line to
go high and turn off both power MOSFETs.
IOUT(MAX)
ICIN(RMS)
=
• D • 1− D
(
)
η%
Intheaboveequation,η%istheestimatedefficiencyofthe
power module. The bulk capacitor can be a switcher-rated
aluminum electrolytic capacitor or a Polymer capacitor.
Output Capacitors
The LTM4628 is designed for low output voltage ripple
noise and good transient response. The bulk output
capacitors defined as C
are chosen with low enough
OUT
effective series resistance (ESR) to meet the output volt-
age ripple and transient requirements. C can be a low
OUT
ESR tantalum capacitor, the low ESR polymer capacitor
orceramiccapacitor.Thetypicaloutputcapacitancerange
for each output is from 200µF to 470µF. Additional output
filtering may be required by the system designer, if further
reduction of output ripples or dynamic transient spikes
is required. Table 4 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 4A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
In sleep mode, the internal circuitry is partially turned off,
reducing the quiescent current to about 450µA for each
output. The load current is now being supplied from the
output capacitors. When the output voltage drops, caus-
ing COMP to rise above 0.5V, the internal sleep line goes
low, and the LTM4628 resumes normal operation. The
next oscillator cycle will turn on the top power MOSFET
and the switching cycle repeats. Either regulator can be
configured for Burst Mode operation.
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LTM4628
APPLICATIONS INFORMATION
Pulse-Skipping Mode Operation
should be used. Forced continuous operation can be
enabled by tying the MODE_PLLIN pin to SGND. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
alwaysturnsonwitheachoscillatorpulse.Duringstart-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4628’s output
voltage is in regulation. Either regulator can be configured
for forced continuous mode.
Inapplicationswherelowoutputrippleandhighefficiency
at intermediate currents are desired, pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4628 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
the MODE_PLLIN pin to INTV enables pulse-skipping
CC
operation. At light loads the internal current comparator
may remain tripped for several cycles and force the top
MOSFETtostayoffforseveralcycles,thusskippingcycles.
The inductor current does not reverse in this mode. This
modewillmaintainhighereffectivefrequenciesthuslower
output ripple and lower noise than Burst Mode operation.
Eitherregulatorcanbeconfiguredforpulse-skippingmode.
Multiphase Operation
For output loads that demand more than 8A of current,
two outputs in LTM4628 or even multiple LTM4628s can
be paralleled to run out of phase to provide more output
currentwithoutincreasinginputandoutputvoltageripple.
TheMODE_PLLINpinallowstheLTM4628tosynchronize
to an external clock (between 400kHz and 780kHz) and
theinternalphase-lockedloopallowstheLTM4628tolock
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
PHASMD PIN STATUS AND CORRESPONDING
PHASE RELATIONSHIP
2-PHASE DESIGN
FLOAT
CLKOUT
MODE_PLLIN
PHASMD SGND FLOAT INTV
CC
CONTROLLER1
CONTROLLER2
CLKOUT
0°
0°
0°
180°
60°
180°
90°
240°
120°
0 PHASE
180 PHASE
V
OUT1
V
OUT2
SGND OR FLOAT
PHASMD
4-PHASE DESIGN
90 DEGREE
CLKOUT
MODE_PLLIN
CLKOUT
MODE_PLLIN
0 PHASE
FLOAT
180 PHASE
90 PHASE
270 PHASE
V
OUT1
V
V
OUT1
V
OUT2
OUT2
FLOAT
PHASMD
PHASMD
6-PHASE DESIGN
60 DEGREE
60 DEGREE
CLKOUT
MODE_PLLIN
CLKOUT
CLKOUT
MODE_PLLIN
MODE_PLLIN
0 PHASE
SGND
180 PHASE
60 PHASE
SGND
240 PHASE
120 PHASE
FLOAT
300 PHASE
V
OUT1
V
V
V
V
OUT1
V
OUT2
OUT2
OUT1
OUT2
PHASMD
PHASMD
PHASMD
4628 F03
Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD ꢁable
4628fe
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LTM4628
APPLICATIONS INFORMATION
onto incoming clock phase as well. The CLKOUT signal
can be connected to the MODE_PLLIN pin of the following
stage to line up both the frequency and the phase of the
thanthenumberofphasesusedtimestheoutputvoltage).
Theoutputrippleamplitudeisalsoreducedbythenumber
of phases used when all of the outputs are tied together
to achieve a single high output current design.
entire system. Tying the PHASMD pin to INTV , SGND,
CC
or left floating generates a phase difference (between
MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees,
or 90 degrees respectively. A total of 12 phases can be
cascadedtorunsimultaneouslywithrespecttoeachother
byprogrammingthePHASMDpinofeachLTM4628chan-
nel to different levels. Figure 3 shows a 2-phase design,
4-phase design and a 6-phase design example for clock
phasing with the PHASMD table.
The LTM4628 device is an inherently current mode con-
trolled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Figure 31 shows an example of parallel operation
and pin connection.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphaseoperation.TheinputRMSripplecurrentcancel-
lationmathematicalderivationsarepresented,andagraph
isdisplayedrepresentingtheRMSripplecurrentreduction
asafunctionofthenumberofinterleavedphases. Figure4
shows this graph.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
OUT IN
4628 F04
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
4628fe
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APPLICATIONS INFORMATION
Frequency Selection and Phase-Locked Loop
The output of the PLL phase detector has a pair of comple-
mentary current sources that charge and discharge the
internal filter network. When the external clock is applied
(MODE_PLLIN and f Pins)
SEꢁ
TheLTM4628deviceisoperatedoverarangeoffrequencies
toimprovepowerconversionefficiency.Itisrecommended
to operate the lower output voltages or lower duty cycle
conversions at lower frequencies to improve efficiency by
lowering power MOSFET switching losses. Higher output
voltages or higher duty cycle conversions can be operated
at higher frequencies to limit inductor ripple current. The
efficiencygraphswillshowanoperatingfrequencychosen
for that condition.
thef frequencyresistorisdisconnectedwithaninternal
SET
switch, and the current sources control the frequency
adjustment to lock to the incoming external clock. When
no external clock is applied, then the internal switch is on,
thus connecting the external f
for free run operation.
frequency set resistor
SET
Minimum On-ꢁime
Minimum on-time t is the smallest time duration that
ON
The LTM4628 switching frequency can be set with an
the LTM4628 is capable of turning on the top MOSFET on
either channel. It is determined by internal timing delays,
and the gate charge required to turn on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
external resistor from the f
pin to SGND. An accurate
SET
10µA current source into the resistor will set a voltage
that programs the frequency or a DC voltage can be
applied. Figure 5 shows a graph of frequency setting
verses programming voltage. An external clock can be
VOUT
applied to the MODE_PLLIN pin from 0V to INTV over
CC
> tON(MIN)
a frequency range of 400kHz to 780kHz. The clock input
high threshold is 1.6V and the clock input low threshold
is 0.5V. The LTM4628 has the PLL loop filter components
on board. The frequency setting resistor should always
be present to set the initial switching frequency before
locking to an external clock. Both regulators will operate
in continuous mode while being externally clocked.
V •FREQ
IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles.Theoutputvoltagewillcontinuetoberegulated,but
the output ripple and current will increase. The minimum
on-time can be increased by lowering the switching fre-
quency. A good rule of thumb is to use an 110ns on-time.
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
2.5
f
PIN VOLTAGE (V)
SET
4628 F05
Figure 5. Operating Frequency vs fSEꢁ Pin Voltage
4628fe
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LTM4628
APPLICATIONS INFORMATION
INTV
CC
C10
4.7µF
R2
10k
PGOOD
5V TO 16V INTERMEDIATE BUS
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
1.5V AT 8A
V
V
OUT1
IN
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
R1
10k
R6
120k
C6
100µF
6.3V
C8
TEMP
V
OUTS1
SW1
470µF
6.3V
RUN1
RUN2
V
V
FB1
FB2
TRACK1
TRACK2
D1
MASTER
LTM4628
R
FB
40.2k
COMP1
COMP2
5.1V ZENER
60.4k
C
SS
R
R
TA
TB
f
SET
0.1µF
60.4k
60.4k
PHASMD
V
OUTS2
1.2V AT 8A
SLAVE
V
OUT2
SW2
1.5V
PGOOD
C4
C7
470µF
6.3V
R4
100k
100µF
6.3V
RAMP TIME
t
PGOOD2
DIFFN DIFFOUT
= (C /1.3µA) • 0.6V
SS
SOFTSTART
INTV
CC
SGND
GND
DIFFP
R9
10k
4628 F06
Figure 6. Example of Output ꢁracking Application Circuit
Output Voltage ꢁracking
Output voltage tracking can be programmed externally
using the TRACK pins. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4628 uses an
accurate 60.4k resistor internally for the top feedback
resistor for each channel. Figure 6 shows an example of
coincident tracking. Equations:
MASTER OUTPUT
SLAVE OUTPUT
TIME
60.4k
RTA
4628 F07
VOUT _SLAVE = 1+
• V
TRACK
Figure 7. Output Coincident ꢁracking Waveform
V
V
is the track ramp applied to the slave’s track pin.
has a control range of 0V to 0.6V, or the internal
TRACK
TRACK
TheTRACKpinofthemastercanbecontrolledbyacapaci-
tor placed on the master regulator TRACK pin to ground.
A 1.3µA current source will charge the TRACK pin up to
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
thereferencevoltageandthenproceeduptoINTV . After
CC
the 0.6V ramp, the TRACK pin will no longer be in con-
trol, and the internal voltage reference will control output
regulation from the feedback divider. Foldback current
limit is disabled during this sequence of turn-on during
tracking or soft-starting. The TRACK pins are pulled low
tracking is disabled when V
is more than 0.6V. R
TRACK
TA
in Figure 6 will be equal to the R for coincident tracking.
FB
Figure 7 shows the coincident tracking waveforms.
4628fe
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APPLICATIONS INFORMATION
when the RUN pin is below 1.2V. The total soft-start time
can be calculated as:
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then
CSS
1.3µA
tSOFT-START
=
• 0.6V
R
= 76.8k. Solve for R to equal to 49.9k.
TB
TA
Each of the TRACK pins will have the 1.3µA current source
on when a resistive divider is used to implement tracking
on that specific channel. This will impose an offset on the
TRACK pin input. Smaller values resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
RegardlessofthemodeselectedbytheMODE_PLLINpin,
the regulator channels will always start in pulse-skipping
mode up to TRACK = 0.5V. Between TRACK = 0.5V and
0.54V,itwilloperateinforcedcontinuousmodeandrevert
to the selected mode once TRACK > 0.54V. In order to
track with another channel once in steady state operation,
the LTM4628 is forced into continuous mode operation
as soon as V is below 0.54V regardless of the setting
FB
Power Good
on the MODE_PLLIN pin.
The PGOOD pins are open drain pins that can be used to
monitor valid output voltage regulation. This pin monitors
a 7.5% window around the regulation point. A resistor
can be pulled up to a particular supply voltage no greater
than 6V maximum for monitoring.
Ratiometric tracking can be achieved by a few simple cal-
culations and the slew rate value applied to the master’s
TRACK pin. As mentioned above, the TRACK pin has a
control range from 0 to 0.6V. The master’s TRACK pin
slew rate is directly equal to the master’s output slew rate
in Volts/Time. The equation:
Stability Compensation
MR
SR
The module has already been internally compensated for
alloutputvoltages.Table4isprovidedformostapplication
requirements. LTpowerCAD is available for other control
loop optimization.
• 60.4k = RTB
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus R
TB
Run Enable
is equal the 60.4k. R is derived from equation:
TA
TheRUNpinshaveanenablethresholdof1.4Vmaximum,
typically 1.25V with 150mV of hysteresis. They control
the turn-on of each of the channels. These pins can be
0.6V
RTA
=
VTRACK
RTB
V
V
FB
FB
+
−
60.4k RFB
pulled up to V for 5V operation, or a 5V Zener diode can
IN
be placed on the pins and a 10k to 100k resistor can be
placed up to higher than 5V input for enabling the chan-
nels. The RUN pins can also be used for output voltage
sequencing. In parallel operation the RUN pins can be
tie together and controlled from a single control. See the
Typical Application circuits in Figure 28. The RUN pin can
also be left floating. The RUN pin has a 1µA pull-up cur-
rent source that increases by an additional 4.5µA during
ramp-up once above the on/off threshold.
where V is the feedback voltage reference of the regula-
FB
tor, and V
is 0.6V. Since R is equal to the 60.4k
TRACK
TB
top feedback resistor of the slave regulator in equal slew
rate or coincident tracking, then R is equal to R with
TA
FB
V
= V
. Therefore R = 60.4k, and R = 60.4k in
TRACK TB TA
FB
Figure 6.
Inratiometrictracking, adifferentslewratemaybedesired
for the slave regulator. R can be solved for when SR
TB
is slower than MR. Make sure that the slave supply slew
4628fe
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APPLICATIONS INFORMATION
INꢁV and EXꢁV
inductance in combination with the MOSFET interconnect
bond wire inductance.
CC
CC
The LTM4628 module has an internal 5V low dropout
regulator that is derived from the input voltage. This
regulator is used to power the control circuitry and the
power MOSFET drivers. This regulator can source up to
70mA, and typically uses ~30mA for powering the device
at the maximum frequency.
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring fre-
quency can be measured for its value. The impedance Z
can be calculated:
Z = 2πfL,
L
EXTV allowsanexternal5VsupplytopowertheLTM4628
CC
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
itsimpedanceisequaltotheresistorattheringfrequency.
andreducepowerdissipationfromtheinternallowdropout
5Vregulator. Thepowerlosssavingscanbecalculatedby:
(V – 5V) • 30mA = P
IN
LOSS
EXTV has a threshold of 4.7V for activation, and a maxi-
CC
Calculatedby:Z =1/(2πfC).Thesevaluesareagoodplace
C
mum rating of 6V. When using a 5V input, connect this
to start with. Modification to these components should
be made to attenuate the ringing with the least amount
the power loss.
5V input to EXTV also to maintain a 5V gate drive level.
CC
V has to be sequenced on before EXTV , and EXTV
IN
CC
CC
must be sequenced off before V .
IN
ꢁemperature Diode Monitoring
Differential Remote Sense Amplifier
The LTM4628 has anonboard1N4148 silicon diode at the
TEMP pin that can be used to monitor temperature. The
diode is mounted very close to internal power switches.
The forward voltage of a silicon diode is temperature
dependent based on the following equation:
Anaccuratedifferentialremotesenseamplifierisprovided
to sense low output voltages accurately at the remote
load points. This is especially true for high current loads.
The amplifier can be used on one of the two channels, or
on a single parallel output. It is very important that the
DIFFP and DIFFN are connected properly at the output,
VD
η • V
and DIFFOUT is connected to either V
or V
.
OUTS1
OUTS2
I = I • e
D
S
In parallel operation, the DIFFP and DIFFN are connected
properly at the output, and DIFFOUT is connected to
T
or
one of the V
pins. Review the parallel schematics in
OUTS
I
VD = η • VT •ln D
Figure 31 and review Figure 2.
I
SW Pins
where I is the diode current, V is the diode voltage, η is
D
D
The SW pins are generally for testing purposes by moni-
toring these pins. These pins can also be used to dampen
out switch node ringing caused by LC parasitic in the
switched current paths. Usually a series R-C combina-
tion is used, called a snubber circuit. The resistor will
dampen the resonance and the capacitor is chosen to
only affect the high frequency ringing across the resistor.
If the stray inductance or capacitance can be measured or
approximated then a somewhat analytical technique can
be used to select the snubber values. The inductance is
usuallyeasiertopredict.Itcombinesthepowerpathboard
the ideality factor (typically close to 1.0) and I (satura-
S
tion current) is a process dependent parameter. V can
T
be broken out to:
k • T
q
VT =
where T is the diode junction temperature in Kelvin, q is
the electron charge and k is Boltzmann’s constant. V is
T
approximately 26mV at room temperature (298K) and
scales linearly with Kelvin temperature. It is this linear
4628fe
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APPLICATIONS INFORMATION
It is important that the bias current source be accurate and
powered from a high impedance source. This is because
the forward voltage drop is also a function of the current
through the diode.
temperature relationship that makes diodes suitable
temperature sensors. The I term in the equation above
S
is the extrapolated current through a diode junction when
the diode has zero volts across the terminals. The I term
S
varies from process to process, varies with temperature,
The below equations show that when currents are a de-
and by definition must always be less than I . Combining
D
cade apart the V difference is 60mV; therefore the 10µA
D
all of the constants into one term:
current source error will affect the diode forward voltage
at temperature.
η •k
q
KD =
kT/q = 26mV
−5
V
– V = kT/q ln(I )/(I )
D2 D1 D2
where K = 8.62 , and knowing ln(I /I ) is always posi-
D1
D
D S
tive because I is always greater than I , leaves us with
the equation that:
D
S
where V – V is the difference in the diode forward
voltage with the I and I current difference.
D1
D2
D1
D2
I
IS
VD = T(KELVIN)•KD •ln D
Several 1N4148 diodes were tested with 100µA of current
and Figure 9 shows the results. The 100µA current source
provided the best repeatability for each diode.
where V appears to increase with temperature. It is com-
D
Thetesteddiodesareverycloseto–2.2mV/°Cto–2.4mV/°C
slope while each are biased with 100µA through a 120k
pull-up resistor to 12V. The Figure 9 graph can be used
to calibrate and measure LTM4628 internal temperature
mon knowledge that a silicon diode biased with a current
source has an approximate –2mV/°C temperature rela-
tionship (Figure 8), which is at odds with the equation. In
fact, the I term increases with temperature, reducing the
S
by measuring the diode V value.
D
ln(I /I ) absolute value yielding an approximate –2mV/°C
D S
composite diode voltage slope.
1.4
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I
= 10µA
D
1.2
1.0
0.8
0.6
0.4
0.2
0
–273
–173
–73
27
127
227
–100 –50
0
50
100
150
200
TEMPERATURE (°C)
TEMPERATURE (°C)
4628 F08
4628 F09
Figure 8. Silicon Diode Voltage VD vs ꢁemperature
Figure 9. ꢁhe 1N4148 Diode Voltage VD vs ꢁemperature
4628fe
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APPLICATIONS INFORMATION
ꢁhermal Considerations and Output Current Derating
2 θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottomofthepackage.InthetypicalµModuleregulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditionsdon’tgenerallymatchtheuser’sapplication.
The thermal resistances reported in the Pin Configura-
tion section of the data sheet are consistent with those
parameters defined by JESD 51-12 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation per-
formed on a µModule package mounted to a hardware
test board defined by JESD 51-9 (“Test Boards for Area
Array Surface Mount Package Thermal Measurements”).
The motivation for providing these thermal coefficients is
foundinJESD51-12(“GuidelinesforReportingandUsing
Electronic Package Thermal Information”).
3 θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetopof
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
for comparing packages but the test conditions don’t
generally match the user’s application.
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the µModule regulator’s thermal performance in their ap-
plicationatvariouselectricalandenvironmentaloperating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant
to providing guidance of thermal performance; instead,
the derating curves provided later in this data sheet can
be used in a manner that yields insight and guidance per-
taining to one’s application-usage, and can be adapted to
correlate thermal performance to one’s own application.
, this value may be useful
JCbottom
4 θ , the thermal resistance from junction to the printed
JB
circuit board, is the junction-to-board thermal resis-
tance where almost all of the heat flows through the
bottom of the µModule regulator and into the board,
and is really the sum of the θ
and the thermal
JCbottom
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from the
package, using a two sided, two layer board. This board
is described in JESD 51-9.
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD 51-12; these coefficients
are quoted or paraphrased below:
1 θ , the thermal resistance from junction to ambient, is
JA
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure.Thisenvironmentissometimesreferredtoas“still
air”althoughnaturalconvectioncausestheairtomove.
This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
A graphical representation of the aforementioned thermal
resistances is given in Figure 10; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
4628fe
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APPLICATIONS INFORMATION
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4628 F10
µMODULE DEVICE
Figure 10. Graphical Representation of JESD 51-12 ꢁhermal Coefficients
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operatingconditionsofaµModuleregulator. Forexample,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
the LTM4628 and the specified PCB with all of the cor-
rect material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD 51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4628 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulate conditions
with thermocouples within a controlled environment
chamber while operating the device at the same power
loss as that which was simulated. The outcome of this
process and due diligence yields a set of derating curves
provided in other sections of this data sheet. After these
laboratory tests have been performed the θ and θ are
for θ
and θ
, respectively. In practice, power
JCtop
JCbottom
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4628, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware
is used to accurately build the mechanical geometry of
JB
BA
summedtogethertocorrelatequitewellwiththeLTM4628
model with no airflow or heat sinking in a properly de-
fined chamber. This θ + θ value is shown in the Pin
JB
BA
Configuration section and should accurately equal the θ
JA
value because approximately 100% of power loss flows
from the junction through the board into ambient with no
airflow or top mounted heat sink.
4628fe
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APPLICATIONS INFORMATION
The 1.0V and 3.3V power loss curves in Figures 11 and 12
can be used in coordination with the load current derating
curves in Figures 13 to 24 for calculating an approximate
no air or heat sink and the power loss for the 12V to 1.0V
at12Aoutputisabout3.65W.The3.65Wlossiscalculated
with the ~2.7W room temperature loss from the 12V to
1.0V power loss curve at 12A, and the 1.35 multiplying
θ thermal resistance for the LTM4628 with various heat
JA
sinking and airflow conditions. The power loss curves are
taken at room temperature, and are increased with mul-
tiplicative factors according to the ambient temperature.
The approximate factors are: 1.35 for 115°C and 1.4 for
-
factor at 120°C junction. If the 80°C ambient tempera
ture is subtracted from the 120°C junction temperature,
then the difference of 40°C divided by 3.65W equals a
10.9°C/W θ thermal resistance. Table 2 specifies a
JA
120°C. The derating curves are plotted with V
OUT2
and
9.5°C/W to 10°C/W value which is very close. Table 2 and
Table 3provideequivalentthermalresistancesfor1.0Vand
3.3V outputs with and without airflow and heat sinking.
The derived thermal resistances in Tables 2 and 3 for the
various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
OUT1
V
in parallel single output operation starting at 16A
and the ambient temperature at 40°C. The output volt-
ages are 1.0V, and 3.3V. These are chosen to include the
lower and higher output voltage ranges for correlating
the thermal resistance. Thermal models are derived from
several temperature measurements in a controlled tem-
perature chamber along with thermal modeling analysis.
The junction temperatures are monitored while ambi-
ent temperature is increased with and without airflow.
Thepowerlossincreasewithambienttemperaturechange
is factored into the derating curves. The junctions are
maintained at 115°C to 120°C maximum while lowering
output current or power with increasing ambient tem-
perature. The decreased output current will decrease the
internal module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
temperature rise can be allowed. As an example, in
Figure 14 the load current is derated to ~12A at ~80°C with
temperature. Theno-airflowθ
valueshavesomevariation
JA
from9.5°C/Wto11°C/Wdependingonthe115°Cto120°C
holding junction temperature. All other airflow thermal
resistance values are more accurate. Room temperature
power loss can be derived from the efficiency curves in
the Typical Performance Characteristics section and ad
-
justed with the above ambient temperature multiplicative
factors. The printed circuit board is a 1.6mm thick four
layer board withtwo ounce copper for the two outer layers
and one ounce copper for the two inner layers. The PCB
dimensions are 95mm × 76mm. The BGA heat sinks are
listed in Table 3.
4628fe
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APPLICATIONS INFORMATION
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
16
14
12
10
8
24V TO 1V
12V TO 1V
5V TO 1V
24V TO 3.3V POWER LOSS
12V TO 3.3V POWER LOSS
5V TO 3.3V POWER LOSS
0 LFM
200 LFM
400 LFM
6
4
2
0
0
2
4
6
8
10 12 14 16
0
2
4
6
8
10 12 14 16
0
20
40
60
80
100
120
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
4628 F12
4628 F11
4628 F13
Figure 11. 1V Power Loss
Figure 12. 3.3V Power Loss
Figure 13. 5V to 1V Derating
Curves, No Heat Sink
16
14
12
10
8
16
14
12
10
8
16
14
12
10
8
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
6
6
6
4
4
4
2
2
2
0
0
0
0
20
40
60
80
100
120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4628 F16
4628 F15
4628 F14
Figure 16. 5V to 1V Derating
Curves, with BGA Heat Sink
Figure 15. 24V to 1V Derating
Curves, No Heat Sink
Figure 14. 12V to 1V Derating
Curves, No Heat Sink
16
14
12
10
8
16
14
12
10
8
16
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
14
12
10
8
6
6
6
4
4
4
2
2
2
0
0
0
0
20
40
60
80
100
120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 19. 5V to 3.3V Derating4628 F19
Curves, No Heat Sink
4628 F18
4628 F17
Figure 18. 24V to 1V Derating
Curves with BGA Heat Sink
Figure 17. 12V to 1V Derating
with BGA Heat Sink
4628fe
23
For more information www.linear.com/LTM4628
LTM4628
APPLICATIONS INFORMATION
16
16
14
12
10
8
16
0 LFM
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
400 LFM
200 LFM
14
14
400 LFM
12
12
10
10
8
8
6
6
6
4
4
4
2
2
2
0
0
0
0
20
40
60
80
100
120
0
20
40
60
80
100
120
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 20. 12V to 3.3V Deratin4g628 F20
Curves, No Heat Sink
4628 F21
Figure 21. 24V to 3.3V Derating
Curves, No Heat Sink
Figure 22. 5V to 3.3V Derating4628 F22
Curves with Heat Sink
16
14
12
10
8
16
0 LFM
200 LFM
400 LFM
0 LFM
200 LFM
14
400 LFM
12
10
8
6
6
4
4
2
2
0
0
0
20
40
60
80
100
120
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 23. 12V to 3.3V Deratin4g628 F23
Curves, with Heat Sink
Figure 24. 24V to 3.3V Deratin4g628 F24
Curves with Heat Sink
4628fe
24
For more information www.linear.com/LTM4628
LTM4628
APPLICATIONS INFORMATION
ꢁable 2. 1.0V Output
DERAꢁING CURVE
Figures 13, 14, 15
Figures 13, 14, 15
Figures 13, 14, 15
Figures 16, 17, 18
Figures 16, 17, 18
Figures 16, 17, 18
V
(V)
POWER LOSS CURVE
Figure 11
AIR FLOW (LFM)
HEAꢁ SINK
None
θ
(°C/W)
IN
JA
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
0
9.5 to 11
6.4
Figure 11
200
400
0
None
Figure 11
None
5.6
Figure 11
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
9.0 to 10.5
6.5
Figure 11
200
400
Figure 11
4.8
ꢁable 3. 3.3V Output
DERAꢁING CURVE
Figures 19, 20, 21
Figures 19, 20, 21
Figures 19, 20, 21
Figures 22, 23, 24
Figures 22, 23, 24
Figures 22, 23, 24
V
(V)
POWER LOSS CURVE
Figure 12
AIR FLOW (LFM)
HEAꢁ SINK
None
θ
(°C/W)
IN
JA
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
5, 12, 24
0
9.5 to 11
6.75
Figure 12
200
400
0
None
Figure 12
None
6.4
Figure 12
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
9.0 to 10.5
6.3
Figure 12
200
400
Figure 12
4.8
HEAꢁ SINK MANUFACꢁURER
PARꢁ NUMBER
WEBSIꢁE
www.aavid.com
Aavid Thermalloy
375424B00034G
4628fe
25
For more information www.linear.com/LTM4628
LTM4628
APPLICATIONS INFORMATION
ꢁable 4 Output Voltage Response vs Component Matrix (Refer to Figure 28) 0A to 4A Load Step ꢁypical Measured Values
C
AND C
C
AND C
C
IN
PARꢁ
NUMBER
OUꢁ1
OUꢁ2
OUꢁ1
OUꢁ2
CERAMIC VENDORS
VALUE
PARꢁ NUMBER
BULK VENDORS
VALUE
PARꢁ NUMBER (BULK)
VENDORS
AVX
10µF 35V 1812DD106KAT
Sanyo POSCAP 470µF 2R5 2R5TPD470M5 47µF 35V 35SVPD47M Sanyo Oscon
Murata
TDK
22µF 16V GRM43ER61C226KE01 Sanyo POSCAP 470µF 6.3V
100µF 6.3V C4532X5R0J107MZ
6TPD470M
Murata
AVX
100µF 6.3V GRM32ER60J107M
100µF 6.3V 18126D107MAT
P-P
LOAD
V
C
C
C
C
C
V
DROOP Deviation RECOVERY SꢁEP
R
FB
Freq.
(kHz)
OUꢁ
IN
IN
OUꢁ1
OUꢁ2
FF
IN
(V)
(CERAMIC)
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
(BULK)*
47µF
47µF
47µF
47µF
47µF
47µF
47µF
47µF
47µF
47µF
47µF
47µF
47µF
(CERAMIC)
(BULK)
(pF)
(V)
(mV)
(mV)
120
100
120
110
120
120
120
130
140
140
160
200
200
ꢁIME (µs) (A/µs)
(kΩ)
90.9
90.9
60.4
60.4
40.2
40.2
30.1
30.1
19.1
19.1
13.3
13.3
8.25
1
100µF
470µF
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
12
60
30
20
30
20
30
20
30
20
30
30
30
30
30
4
4
4
4
4
4
4
4
4
4
4
4
4
400
400
500
500
500
500
500
500
500
500
700
700
750
1
100µF × 4
100µF
47
50
1.2
1.2
1.5
1.5
1.8
1.8
2.5
2.5
3.3
3.3
5
470µF
470µF
470µF
60
100µF × 4
100µF
47
55
60
100µF × 4
100µF
47
66
60
100µF × 4
100µF × 4
100µF
47
47
65
70
470µF
470µF
70
100µF
80
100µF
47
47
100
125
100µF
220µF
* Bulk capacitance is optional if V has very low input impedance.
IN
4628fe
26
For more information www.linear.com/LTM4628
LTM4628
APPLICATIONS INFORMATION
Figures 25 and 26 show thermal images of the LTM4628
in LGA package with or without BGA heat sink and no air
flow or 200LFM air flow.
These images equate to a paralleled 3.3V output at 16A
design operating at 92% efficiency from 12V input.
Figure 25a.12VIN to 3.3VOUꢁ, 16A, No Heat Sink, No Air Flow
Figure 25
Figure 25b.12VIN to 3.3VOUꢁ, 16A, No Heat Sink, 200LFM
Figure 26a. 12VIN to 3.3VOUꢁ,16A, with Heat Sink, No Air Flow
Figure 26
Figure 26b. 12VIN to 3.3VOUꢁ,16A, with Heat Sink, 200LFM
4628fe
27
For more information www.linear.com/LTM4628
LTM4628
APPLICATIONS INFORMATION
Safety Considerations
• Place a dedicated power ground layer underneath the
unit.
The LTM4628 modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
• To minimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and over current protection. A temperature
diode is provided for monitoring internal temperature.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
Layout Checklist/Example
The high integration of LTM4628 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
• For parallel modules, tie the V , V , and COMP pins
OUT FB
together. Use an internal layer to closely connect these
pins together. The TRACK pin can be tied a common
capacitor for regulator soft-start.
• Use large PCB copper areas for high current paths,
including V , GND, V
and V . It helps to mini-
• Bring out test points on the signal pins for monitoring.
IN
OUT1
OUT2
mize the PCB conduction loss and thermal stress.
Figure 27 gives a good example of the recommended
layout. LGA and BGA PCB layouts are identical with the
exceptionofcirclepadsforBGA(seePackageDescription).
• Place high frequency ceramic input and output capaci-
tors next to the V , PGND and V
pins to minimize
IN
OUT
high frequency noise.
C
C
IN1
IN2
V
IN
M
L
K
J
GND
GND
H
G
F
SGND
C
C
OUT2
OUT1
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
V
GND
V
OUT2
OUT1
4628 F27
CNTRL
CNTRL
Figure 27. Recommended PCB Layout (LGA Shown, for BGA Use Circle Pads)
4628fe
28
For more information www.linear.com/LTM4628
LTM4628
TYPICAL APPLICATIONS
INTV
CC
C10
4.7µF
R2
10k
PGOOD1
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
7V TO 16V
1.5V AT 8A
V
IN
V
INTERMEDIATE
OUT1
C
C
22µF
25V
C
22µF
25V
C
22µF
25V
C
OUT1
IN1
IN2
IN3
OUT2
BUS
R1
10k
R6
120k
TEMP
V
100µF
6.3V
OUTS1
470µF
6.3V
RUN1
SW1
RUN2
V
V
FB1
FB2
TRACK1
D1
TRACK1
LTM4628
R6
R8
C
FF
TRACK2
COMP1
COMP2
5.1V ZENER
40.2k
60.4k
TRACK2
100pF
1.2V
C5
0.1µF
f
SET
C9
0.1µF
PHASMD
V
OUTS2
1.2V AT 8A
V
OUT2
SW2
R4
100k
INTV
C4
C7
470µF
6.3V
CC
100µF
10k
PGOOD2
6.3V
PGOOD2
DIFFN DIFFOUT
SGND
GND
DIFFP
4628 F28
Figure 28. 7VIN to 16VIN, 1.5V and 1.2V Outputs
INTV
CC
C10
4.7µF
R2
5k
PGOOD1
7V TO 16V
INTERMEDIATE BUS
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
V
V
OUT1
IN
C3
C11
22µF
25V
C2
22µF
25V
C1
22µF
25V
C6
100µF
6.3V
C8
470µF
6.3V
+
+
R1
R6
TEMP
V
OUTS1
SW1
22µF
10k
25V
120k
RUN1
RUN2
V
V
FB1
FB2
R5
TRACK1
TRACK1
TRACK2
D1
LTM4628
40.2k
COMP1
COMP2
5.1V ZENER
C9
0.1µF
f
SET
PHASMD
V
OUTS2
1.5V
AT 16A
V
OUT2
SW2
C4
100µF
6.3V
C7
470µF
6.3V
R4
100k
PGOOD2
DIFFN DIFFOUT
PGOOD1
SGND
GND
DIFFP
4628 F29
Figure 29. ꢁwo Phases, 1.5V at 16A Design
4628fe
29
For more information www.linear.com/LTM4628
LTM4628
TYPICAL APPLICATIONS
INTV
CC
C10
4.7µF
R2
10k
PGOOD1
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
5V TO 16V
INTERMEDIATE BUS
1.2V AT 8A
V
IN
V
OUT1
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
+
R1
10k
C6
100µF
6.3V
C8
470µF
6.3V
R6
120k
TEMP
V
OUTS1
SW1
RUN1
RUN2
V
V
FB1
FB2
TRACK1
TRACK2
D1
LTM4628
R5
60.4k
R8
90.9k
COMP1
COMP2
5.1V ZENER
C5
0.1µF
R7
90.9k
R9
60.4k
f
SET
PHASMD
V
OUTS2
1V AT 8A
V
OUT2
SW2
1.2V
INTV
+
CC
C4
100µF
6.3V
C7
470µF
6.3V
R4
100k
10k
PGOOD2
PGOOD2
DIFFN DIFFOUT
SGND
GND
DIFFP
4628 F30
Figure 30. 1.2V and 1V Output ꢁracking
4628fe
30
For more information www.linear.com/LTM4628
LTM4628
TYPICAL APPLICATIONS
INTV
CC
C10
4.7µF
R2
5k
CLK1
PGOOD1
7V TO 16V
INTERMEDIATE BUS
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
V
V
OUT1
IN
C3
22µF
25V
C2
22µF
25V
C1
22µF
25V
C6
100µF
6.3V
C8
470µF
6.3V
+
R1
10k
R6
10k
TEMP
V
OUTS1
SW1
RUN1
RUN
V
V
FB1
RUN2
FB
V
R5
FB2
TRACK1
TRACK1
TRACK2
D1
LTM4628
60.4k
COMP1
COMP2
5.1V ZENER
f
COMP
SET
PHASMD
V
OUTS2
V
OUT2
SW2
C4
100µF
6.3V
C7
470µF
6.3V
+
R4
100k
PGOOD2
DIFFN DIFFOUT
PGOOD1
SGND
GND
DIFFP
1.2V
AT 32A
C16
4.7µF
CLK1
PGOOD1
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
7V TO 16V INTERMEDIATE BUS
V
V
OUT1
IN
C12
22µF
25V
C15
22µF
25V
C5
22µF
25V
C13
100µF
6.3V
C14
470µF
6.3V
+
+
R9
TEMP
V
OUTS1
SW1
10k
RUN1
RUN1
RUN2
V
V
V
FB
FB1
FB2
TRACK1
TRACK1
TRACK2
LTM4628
COMP1
COMP2
COMP
C19
0.22µF
f
SET
PHASMD
V
OUTS2
V
OUT2
SW2
C17
100µF
6.3V
C18
470µF
6.3V
R10
100k
PGOOD2
PGOOD1
SGND
GND
DIFFP
DIFFN DIFFOUT
4628 F31
INTVCC
Figure 31. 4-Phase, 1.2V at 32A
4628fe
31
For more information www.linear.com/LTM4628
LTM4628
PACKAGE DESCRIPTION
ꢁable 5. LꢁM4628 Component Pinout
PIN ID FUNCꢁION PIN ID FUNCꢁION
PIN ID FUNCꢁION
PIN ID
B1
FUNCꢁION
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
GND
PIN ID
E1
FUNCꢁION
GND
PIN ID
F1
FUNCꢁION
GND
A1
A2
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
GND
C1
C2
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1S
D1
D2
GND
GND
B2
E2
GND
F2
GND
A3
B3
C3
D3
GND
E3
GND
F3
GND
A4
B4
C4
D4
GND
E4
GND
F4
MODE_PLLIN
RUN1
A5
B5
C5
D5
VFB1
SGND
VFB2
TRACK2
GND
E5
TRACK1
COMP1
COMP2
DIFFP
DIFFN
GND
F5
A6
B6
C6
f
D6
E6
F6
SGND
SET
A7
GND
B7
GND
C7
SGND
VOUT2S
VOUT2
VOUT2
VOUT2
VOUT2
D7
E7
F7
SGND
A8
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
B8
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
C8
D8
E8
F8
DIFFOUT
RUN2
A9
B9
C9
D9
E9
F9
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
GND
E10
E11
E12
F10
F11
F12
GND
GND
GND
GND
GND
GND
GND
PIN ID FUNCꢁION
PIN ID
H1
FUNCꢁION
GND
PIN ID
J1
FUNCꢁION PIN ID FUNCꢁION
PIN ID
L1
FUNCꢁION
GND
VIN
PIN ID
M1
FUNCꢁION
GND
VIN
G1
G2
GND
SW1
GND
VIN
K1
K2
GND
VIN
H2
GND
J2
L2
M2
G3
GND
H3
GND
J3
VIN
K3
VIN
L3
VIN
M3
VIN
G4
PHASMD
CLKOUT
SGND
SGND
PGOOD2
PGOOD1
GND
H4
GND
J4
VIN
K4
VIN
L4
VIN
M4
VIN
G5
H5
GND
J5
GND
TEMP
EXTVCC
GND
VIN
K5
GND
GND
GND
GND
VIN
L5
VIN
M5
VIN
G6
H6
GND
J6
K6
L6
VIN
M6
VIN
G7
H7
GND
J7
K7
L7
VIN
M7
VIN
G8
H8
INTVCC
GND
J8
K8
L8
VIN
M8
VIN
G9
H9
J9
K9
L9
VIN
M9
VIN
G10
G11
G12
H10
H11
H12
GND
J10
J11
J12
VIN
K10
K11
K12
VIN
L10
L11
L12
VIN
M10
M11
M12
VIN
SW2
GND
VIN
VIN
VIN
VIN
GND
GND
GND
GND
GND
GND
PACKAGE PHOTOS
4.32mm
4.92mm
15mm
15mm
15mm
15mm
LGA
BGA
4628fe
32
For more information www.linear.com/LTM4628
LTM4628
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
Z
b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
4628fe
33
For more information www.linear.com/LTM4628
LTM4628
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
Z
/ / b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
a a a
Z
4628fe
34
For more information www.linear.com/LTM4628
LTM4628
REVISION HISTORY
REV
DAꢁE
DESCRIPꢁION
PAGE NUMBER
A
06/11 Updated Typical Application Efficiency graph
Updated Pin Configuration
1
2
Updated Electrical Characteristics
Updated Pin Functions section
3, 4
7, 8
Updated Decoupling Requirements table
Updated Figure 3
9
13
Various text updated in Applications Information section
Updated Figures 29 and 31
11 to 22
30, 32
B
C
7/11
8/12
Changed Typical value of R
, R
to 60.4kΩ
3
9
FBHI1 FBHI2
Updated Decoupling Requirements table
Updated Pin Configuration to add the BGA package.
Added V – V formula.
2
19
2
D1
D2
D
E
11/12 Updated the Pin Configuration section.
02/14 Add SnPb BGA package option
1, 2
4628fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTM4628
TYPICAL APPLICATION
5V
C10
4.7µF
R2
10k
PGOOD1
24V
MODE_PLLIN CLKOUT INTV
EXTV
PGOOD1
CC
CC
5V AT 8A
V
V
OUT1
IN
C8
10µF
35V
C3
10µF
35V
C2
10µF
35V
C1
10µF
35V
R1
10k
R6
240k
C
C
OUT2
TEMP
OUT1
V
OUTS1
SW1
100µF
6.3V
470µF
RUN1
6.3V
RUN2
V
V
FB1
FB2
TRACK1
TRACK2
D1
TRACK1
LTM4628
R6
R8
COMP1
COMP2
5.1V ZENER
8.25k
13.3k
TRACK2
C5
0.1µF
INTV
f
CC
SET
C9
0.1µF
PHASMD
V
OUTS2
3.3V AT 8A
C4
100µF
6.3V
V
OUT2
SW2
C7
470µF
6.3V
3.3V
10k
PGOOD2
PGOOD2
DIFFN DIFFOUT
SGND
GND
DIFFP
4628 F32
Figure 32. 24VIN, 5V and 3.3V Outputs
RELATED PARTS
PARꢁ NUMBER
LTM4619
DESCRIPꢁION
Dual 26V , 4A DC/DC µModule Regulator
COMMENꢁS
4.5V ≤ V ≤ 26.5V; 0.8V ≤ V ≤ 5V
OUT
IN
IN
LTM4615
Triple Low V , 4A DC/DC µModule Regulator
2.375 ≤ V ≤ 5.5V; Two 4A and One 1.5A Output
IN
IN
LTM4616
Dual 8A, Low V , DC/DC µModule Regulator
2.7V ≤ V ≤ 5.5V; 0.6V ≤ V
≤ 5V
OUT
IN
IN
LTM4614
Dual 4A, Low V , DC/DC µModule Regulator
2.375V ≤ V ≤ 5.5V; 0.8V ≤ V
≤ 5V
OUT
IN
IN
LTM4627
15A DC/DC µModule Regulator
4.5V ≤ V ≤ 20V; 0.6V ≤ V
≤ 5V
OUT
IN
4628fe
LT 0214 REV E • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4628
●
●
LINEAR TECHNOLOGY CORPORATION 2010
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