LTM4632_技术文档

LTM4632

Ultrathin, Triple Output,

Step-Down µModule Regulator

for DDR-QDR4 Memory

FEATURES

DESCRIPTION

The LTM^®4632 is an ultrathin triple output step-down

µModule^®(power module) regulator to provide complete

power solution for DDR-QDR4 SRAM. Operating from a

3.6V to 15V input voltage, the LTM4632 supports two 3A

output rails, both sink and source capable, for VDDQ and

VTT, plus a 10mA low noise reference VTTR output. Both

n

Complete DDR-QDR4 SRAM Power Solution

Including VDDQ, VTT, VTTR (or VREF)

2

n

Solution in 0.5cm (Dual-Sided PCB)

n

Wide Input Voltage Range: 3.6V to 15V

n

3.3V Input Compatible with V Tied to INTV

IN

CC

n

0.6V to 2.5V Output Voltage Range

Dual 3A DC Output Current with Sink and Source

Capability

VTT and VTTR track and are equal to VDDQ/2. Housed

in a 6.25mm × 6.25mm × 1.82mm LGA and 6.25mm ×

6.25mm × 2.42mm BGA packages, the LTM4632 includes

the switching controller, power FETs, inductors and sup-

port components. Alternatively, the power module can

also be configured as a two phase single 6A output

VTT. Only a few ceramic input and output capacitors are

needed to complete the design.

n

1.5%, 10mA Buffered VTTR = VDDQ/2 Output

3A VDDQ + 3A VTT or Dual Phase Single 6A VTT

1.5% Maximum Total Output Voltage Regulation

Error Over Load, Line and Temperature

Current Mode Control, Fast Transient Response

External Frequency Synchronization

n

Multiphase Parallelable with Current Sharing

The LTM4632 supports selectable Burst Mode operation

(CH1 only) and output voltage tracking for supply rail

sequencing. Its high switching frequency and current

mode control enable a very fast transient response to

line and load changes without sacrificing stability.

Selectable Burst Mode^®Operation

Overvoltage Input and Overtemperature Protection

Power Good Indicator

Ultrathin 6.25mm × 6.25mm × 1.82mm LGA and

6.25mm × 6.25mm × 2.42mm BGA Packages

Fault protection features include overvoltage input, over-

current and overtemperature protection.

APPLICATIONS

The LTM4632 is available with SnPb (BGA) or RoHS com-

pliant terminal finish

L, LT, LTC, LTM, µModule, Burst Mode, Linear Technology and the Linear logo are registered

trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners.

n

DDR Memory Power Supply

n

General Purpose Point-of-Load Conversion

n

Telecom, Networking and Industrial Equipment

TYPICAL APPLICATION

Output Efficiency vs Load Current

QDR4 Memory Power µModule Regulator

95

VDDQ

90

85

80

75

70

65

1.3V, 3A

22µF

4V

PGOOD1 PGOOD2

V

IN

V

IN

V

3.6V TO 15V

OUT1

OUT2

RUN1

RUN2

INTV

SYNC/MODE

TRACK/SS1

VTT

0.65V, 3A

10µF

25V

LTM4632

22µF

4V

VTTR

FB1

CC

VTTR

0.65V, 10mA

COMP1

COMP2

VDDQ

V

DDQIN

GND

52.3k

5V INPUT

12V INPUT

4632 TA01a

0

1

2

3

LOAD CURRENT (A)

4632 TA01b

4632fc

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For more information www.linear.com/LTM4632

LTM4632

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(See Pin Functions, Pin Configuration Table)

(Note 1)

V ............................................................. –0.3V to 16V

OUT

IN

TOP VIEW

V

............................................................. –0.3V to 6V

SYNC/

PGOOD1, PGOOD2..................................... –0.3V to 16V

RUN1, RUN2 ...................................... –0.3V to V +0.3V

COMP2 GND MODE GND COMP1

IN

5

GND

PGOOD2

INTV , TRACK/SS1, V

, VTTR......... –0.3V to 3.6V

PGOOD1

V

CC

DDQIN

4

3

2

1

FB1

INTV

CC

MODE/SYNC, COMP1, COMP2,

V

IN

VTTR

TRACK/SS1

RUN1

V

IN

FB1, FB2................................................–0.3V to INTV

Operating Internal Temperature Range

CC

RUN2

V

IN

V

OUT2

GND

IN

V

OUT1

(Notes 2, 3, 5)........................................ –40°C to 125°C

Storage Temperature Range .................. –55°C to 125°C

Peak Solder Reflow Body Temperature.................260°C

A

B

C

D

E

LGA PACKAGE 25-LEAD (6.25mm × 6.25mm × 1.82mm)

BGA PACKAGE 25-LEAD (6.25mm × 6.25mm × 2.42mm)

T

JMAX

= 125°C, θ

θ

= 17°C/W, θ = 11°C/W,

BA JA

WEIGHT = 0.21g

JCtop

JCbottom

+θ = 22°C/W, θ = 20°C/W

JB

http://www.linear.com/product/LTM4632#orderinfo

ORDER INFORMATION

PART MARKING*

PACKAGE

MSL

TEMPERATURE RANGE

(SEE NOTE 2)

PART NUMBER

LTM4632EV#PBF

LTM4632IV#PBF

LTM4632EY#PBF

LTM4632IY#PBF

LTM4632IY

PAD OR BALL FINISH

Au (RoHS)

DEVICE

FINISH CODE

TYPE

LGA

BGA

RATING

LTM4632V

LTM4632Y

e4

e1

e0

3

–40°C to 125°C

Au (RoHS)

SAC305 (RoHS)

SnPb (63/37)

• Consult Marketing for parts specified with wider operating temperature

ranges. *Device temperature grade is indicated by a label on the shipping

container. Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Recommended LGA and BGA PCB Assembly and Manufacturing

Procedures: www.linear.com/umodule/pcbassembly

• LGA and BGA Package and Tray Drawings: www.linear.com/packaging

• Terminal Finish Part Marking: www.linear.com/leadfree

4632fc

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For more information www.linear.com/LTM4632

LTM4632

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications that apply over the specified internal

operating temperature range (Note 2). Specified as each individual output channel at T_A= 25°C (Note 2), V_IN= 12V, unless otherwise

noted, per the typical application in Figure 19

SYMBOL

PARAMETER

CONDITIONS

MIN

3.6

3.1

0.6

TYP

MAX

15

UNITS

l

V

Input DC Voltage

3.3V Input DC Voltage

Output Voltage Range

V

IN

V

= INTV

CC

3.3

3.5

IN_3.3

IN

l

V

= 3.6V to 15V

2.5

1.8

V

OUT1(RANGE)

OUT2(RANGE)

IN

Output Specification (Channel 1)

l

V

(DC)

CH1 Output Voltage, Total Variation C = 22µF, C = 100µF Ceramic

OUT

1.28

–3

1.30

1.32

3

V

A

OUT1

IN

R

with Line and Load

= 51.7k, MODE = GND, I

= –3A to 3A

FB1

OUT

I

(DC)

CH1 Output Continuous Current

Range

V

IN

= 12V, V

= 1.3V (Note 3)

OUT1

IQ1(V )

CH1 Input Supply Bias Current

V

= 12V, V

= 1.3V, MODE = GND

= 1.3V, MODE = INTV

13

400

40

mA

µA

IN

OUT1

CC

Shutdown, RUN1 = GND

IS1(V )

CH1 Input Supply Current

V

= 12V, V

= 1.3V, I = 3A

OUT

0.4

0.01

0.2

A

%/V

%

IN

OUT1

l

ΔV

(Line)/V

CH1 Line Regulation Accuracy

CH1 Load Regulation Accuracy

CH1 Output Ripple Voltage

= 1.3V, V = 3.6V to 15V, I = 0A

OUT1

0.05

1.0

OUT1

IN

(Load)/V

OUT1

= 1.3V, I

= –3A to 3A

OUT

OUT1

V (AC)

OUT1

I

= 0A, C = 47µF Ceramic

OUT

30

mV

OUT

V

= 12V, V

= 1.3V

IN

OUT1

ΔV

(START)

CH1 Turn-On Overshoot

Turn-On Time

I

= 0A, C = 47µF Ceramic,

OUT

30

1.2

85

mV

ms

mV

µs

OUT1

OUT

TRACK/SS1 = –0.1µF, V = 12V, V

= 1.3V

IN

OUT1

t

C

= 100µF Ceramic, TRACK/SS1 = 0.01µF

START

OUT

No Load, V = 12V, V

= 1.3V

IN

OUT1

ΔV

CH1 Peak Deviation for Dynamic

Load

Load: 0% to 25% to 0% of Full Load

= 47µF Ceramic, V = 12V, V

OUT1

OUTLS1

C

= 1.3V

OUT

IN

t

CH1 Settling Time for Dynamic

Load Step

Load: 0% to 25% to 0% of Full Load

C

20

SETTLE1

= 47µF Ceramic, V = 12V, V

IN OUT1

OUT

IOUTPK1

CH1 Output Current Limit

V

IN

= 12V, V

= 1.3V

4.5

A

OUT1

Output Specification (Channel 2)

l

V

(DC)

CH2 Output Voltage, Total Variation C = 22µF, C = 100µF Ceramic

OUT

637

–3

650

663

3

mV

A

OUT2

IN

V

with Line and Load

= 1.3V, MODE = GND, I

= –3A to 3A

DDQIN

OUT

I

(DC)

CH2 Output Continuous Current

Range

V

= 12V, V

= 1.3V (Note 3)

OUT2

IN

DDQIN

IQ2(V )

CH2 Input Supply Bias Current

V

= 12V, V

= 1.3V, MODE = GND

7

40

mA

µA

IN

DDQIN

Shutdown, RUN2 = 0

IS2(V )

CH2 Input Supply Current

V

= 12V, V

= 1.3V, I = 3A

OUT

0.25

0.01

0.2

A

%/V

%

IN

DDQIN

l

ΔV

OUT2

ΔV

OUT2

(Line)/V

CH2 Line Regulation Accuracy

CH2 Load Regulation Accuracy

CH2 Output Ripple Voltage

= 1.3V, V = 3.6V to 15V, I = 0A

OUT2

0.05

1.0

OUT2

DDQIN

IN

(Load)/V

= 1.3V, I

= –3A to 3A

OUT2

OUT

V (AC)

OUT2

I

= 0A, C

= 100µF Ceramic

= 1.3V

30

mV

OUT

DDQIN

V

= 12V, V

IN

ΔV

CH2 Peak Deviation for Dynamic

Load

Load: 0% to 25% to 0% of Full Load

= 47µF Ceramic, V = 12V, V

OUT1

85

20

mV

µs

A

OUTLS2

SETTLE2

C

= 1.3V

OUT

IN

t

CH2 Settling Time for Dynamic

Load Step

Load: 0% to 25% to 0% of Full Load

= 47µF Ceramic, V = 12V, V

OUT1

C

OUT

IN

IOUTPK2

CH2 Output Current Limit

4.5

4632fc

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For more information www.linear.com/LTM4632

LTM4632

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications that apply over the specified internal

operating temperature range (Note 2). Specified as each individual output channel at T_A= 25°C (Note 2), V_IN= 12V, unless otherwise

noted, per the typical application in Figure 19

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Control Section

l

V

Voltage at V Pin

I

= 0A, V = 1.3V

OUT1

0.593

0.600

0.607

30

V

nA

kΩ

FB1

OUT

I

Current at V Pin

(Note 4)

FB1

RFBHI1

Resistor Between V

and

60.00

60.40

0.50x

60.80

OUT1

V

Pins

FB1

l

VTTR

VTTR Voltage Reference

V

= 1.3V,

0.492x

0.508x

V

DDQIN

V

DDQIN

IVTTR = 10mA, CVTTR < 10nF

V

DDQIN

V

, V

RUN Pin On Threshold

RUN Threshold Rising

RUN Threshold Falling

1.18

0.95

1.28

1.01

1.39

1.05

V

RUN1 RUN2

I

, I

RUN Pin Leakage Current

0

1

µA

RUN1 RUN2

TRACK/SS1 Pin Soft-Start Pull-Up TRACK/SS1 = 0V

Current

1.2

TRACK/SS1

t

Minimum On-Time

Minimum Off-Time

PGOOD Trip Level

(Note 4)

20

45

ns

ON(MIN)

OFF(MIN)

VPGOOD

V

With Respect to 0.6V

OUT2

Ramping Negative

Ramping Positive

FB

With Respect to V

/2 (Note 4)

DDQIN

–8

8

–14

14

%

RPGOOD

PGOOD Pull-Down Resistance

1mA Load

15

3.3

1.3

1

Ω

V

Internal V Voltage

V

= 3.6V to 15V

= 0 to 50mA

3.1

3.5

INTVCC

OSC

CC

IN

Load Reg

INTV Load Regulation

I

%

CC

f

Oscillator Frequency

SYNC Threshold Voltage

MODE Input Current

MHz

V

SYNC

0.95

–1.5

I

SYNC/MODE = INTV

µA

SYNC/MODE

CC

Note 1. Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3. See output current derating curves for different V , V

Note 4. 100% tested at wafer level.

Note 5. This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 125°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

and T .

IN OUT A

Note 2. The LTM4632 is tested under pulsed load conditions such that

T ≈ T . The LTM4632E is guaranteed to meet performance specifications

J

A

over the 0°C to 125°C internal operating temperature range. Specifications

over the –40°C to 125°C internal operating temperature range are assured

by design, characterization and correlation with statistical process

controls. The LTM4632I is guaranteed to meet specifications over the

full –40°C to 125°C internal operating temperature range. Note that the

maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board

layout, the rated package thermal resistance and other environmental

factors.

4632fc

4

For more information www.linear.com/LTM4632

LTM4632

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Load Current at

3.6V_IN

Efficiency vs Load Current at

12V_IN

Efficiency vs Load Current at 5V_IN

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

1V

OUT

1.2V

1.5V

1.8V

2.5V

1.2V

1.5V

1.8V

2.5V

1.2V

1.5V

1.8V

2.5V

OUT

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

LOAD CURRENT (A)

4632 G01

4632 G02

4632 G03

1V Output Transient Response

1.2V Output Transient Response

1.5V Output Transient Response

V

OUT

AC-COUPLED

50mV/DIV

OUT

AC-COUPLED

50mV/DIV

AC-COUPLED

50mV/DIV

LOAD STEP

1A/DIV

LOAD STEP

1A/DIV

LOAD STEP

1A/DIV

4632 G04

4632 G05

4632 G06

20µs/DIV

V

S

= 12V

OUT

= 1MHz

V

S

= 12V

= 1.2V

= 1MHz

V

S

= 12V

= 1.5V

= 1MHz

IN

OUT

IN

OUT

= 1V

f

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

LOAD STEP = 2.25A TO 3A

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

LOAD STEP = 2.25A TO 3A

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

LOAD STEP = 2.25A TO 3A

Start-Up with No Load Current

Applied

1.8V Output Transient Response

2.5V Output Transient Response

SW

10V/DIV

V

OUT

AC-COUPLED

50mV/DIV

OUT

AC-COUPLED

50mV/DIV

V

OUT

1A/DIV

LOAD STEP

1A/DIV

LOAD STEP

1A/DIV

I

IN

0.5A/DIV

4632 G07

4632 G08

4632 G09

20µs/DIV

V

S

= 12V

= 1.8V

= 1MHz

V

S

= 12V

= 2.5V

= 1MHz

V

= 12V

= 1.8V

= 1MHz

IN

OUT

IN

OUT

IN

OUT

f

I

S

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

LOAD STEP = 2.25A TO 3A

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

LOAD STEP = 2.25A TO 3A

= 0A

OUT

INPUT CAPACITOR = 1 × 22µF CERAMIC

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

SOFT-START CAPACITOR = 0.1µF

4632fc

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For more information www.linear.com/LTM4632

LTM4632

TYPICAL PERFORMANCE CHARACTERISTICS

Start-Up with 3A Load Current

Applied

Short-Circuit with No Load

Current Applied

Short-Circuit with 3A Load

Current Applied

SW

10V/DIV

SW

10V/DIV

SW

10V/DIV

V

OUT

1V/DIV

OUT

V

OUT

1V/DIV

I

IN

I

IN

2A/DIV

IN

0.5A/DIV

2A/DIV

4632 G10

4632 G11

4632 G12

20ms/DIV

20µs/DIV

V

= 12V

V

= 12V

V

= 12V

= 1.8V

= 1MHz

IN

OUT

IN

OUT

IN

OUT

= 1.8V

= 1MHz

= 1.8V

= 1MHz

f

I

f

I

f

I

S

OUT

S

OUT

S

= 3A

= 0A

= 3A

OUT

INPUT CAPACITOR = 1 × 22µF CERAMIC

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

SOFT-START CAPACITOR = 0.1µF

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

Recover from Short-Circuit with

No Load Current Applied

Steady-State Output Voltage

Ripple

Start-Up Into Pre-Biased Output

SW

V

SW

OUT

5V/DIV

AC-COUPLED

50mV/DIV

10V/DIV

V

OUT

1V/DIV

V

OUT

1V/DIV

SW

5V/DIV

RUN

10V/DIV

I

IN

2A/DIV

4632 G13

4632 G14

4632 G15

20µs/DIV

1µs/DIV

50ms/DIV

V

= 12V

V

= 12V

V

= 12V

= 1.8V

= 1MHz

IN

OUT

IN

OUT

IN

OUT

= 1.8V

= 1MHz

= 1.8V

= 1MHz

f

I

f

I

f

I

S

OUT

S

OUT

S

= 0A

OUT

INPUT CAPACITOR = 1 × 22µF CERAMIC

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

INPUT CAPACITOR = 1 × 22µF CERAMIC

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

INPUT CAPACITOR = 1 × 22µF CERAMIC

OUTPUT CAPACITOR = 1 × 47µF CERAMIC

4632fc

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For more information www.linear.com/LTM4632

LTM4632

PIN FUNCTIONS

V_IN(A2, B3, D3, E2): Power Input Pins. Apply input

voltage between these pins and GND pins. Recommend

placing input decoupling capacitance directly between V_IN

pins and GND pins.

shuts down the specific regulator channel. Do not float

this pin.

COMP1 (E5), COMP2 (A5): Current Control Threshold and

Error Amplifier Compensation Point of Each Switching

Mode Regulator Channel. The current comparator’s trip

threshold is linearly proportional to this voltage, whose

normal range is from 0.3V to 1.8V. The device is inter-

nal compensated. Tie COMP pins together in Dual Phase

Single Output VTT Configuration. See the Applications

Information section for details.

V

(D1, E1), V

(A1, B1): Power Output Pins of

OUT1

OUT2

each Switching Mode Regulator. Apply output load be-

tween these pins and GND pins. Recommend placing out-

put decoupling capacitance directly between these pins

and GND pins.

GND (C1-C2, C4, B5, D5): Power Ground Pins for Both

Input and Output Returns.

FB1 (E4): The Negative Input of the Error Amplifier for

the Channel 1 Switching Mode Regulator. Internally,

this pin is connected to V_OUT1with a 60.4k precision

resistor. Different output voltages can be programmed

with an additional resistor between FB1 and GND pins.

PGOOD1 (D4): Output Power Good with Open-Drain Logic

of the Channel 1 Switching Mode Regulator. PGOOD1 is

pulled to ground when the voltage on the FB1 pin is not

within 8% (typical) of the internal 0.6V reference. This

threshold has 15mV of hysteresis.

Connect this pin to INTV in Dual Phase Single Output

CC

VTT Configuration. See the Applications Information sec-

tion for details.

PGOOD2 (B4): Output Power Good with Open-Drain Logic

of the Channel 2 Switching Mode Regulator. PGOOD2 is

pulled to ground when the voltage on the V

not within 8% (typical) of the V

threshold has 15mV of hysteresis.

TRACK/SS1 (E3): Output Tracking and Soft-Start Pin of

the Channel 1 Switching Mode Regulator. It allows the

user to control the rise time of the output voltage. Putting

a voltage below 0.6V on this pin bypasses the internal

reference input to the error amplifier, instead it servos the

FB pin to the TRACK/SS voltage. Above 0.6V, the tracking

function stops and the internal reference resumes control

of the error amplifier. There’s an internal 1.2µA pull-up

pin is

/2 vo^Olt^Ua^Tg²e. This

DDQIN

SYNC/MODE (C5): Mode Select and External

Synchronization Input. Tie this pin to ground to force

continuous synchronous operation at all output loads.

Floating this pin or tying it to INTV enables high effi-

CC

ciency Burst Mode operation at light loads. Drive this

pin with a clock to synchronize the LTM4632 switching

frequency. An internal phase-locked loop will force the

bottom power NMOS’s turn on signal to be synchronized

with the rising edge of the clock signal. When this pin is

driven with a clock, forced continuous mode is automati-

cally selected.

current from INTV on this pin, so putting a capacitor

CC

here provides a soft-start function.

VTTR (A3): Reference Output. This output is used to sup-

ply the VREF voltage for DDR memory. An on-chip buffer

amplifier outputs a low noise reference voltage equal to

V

/2. This output is capable of supplying 10mA. VTTR

DDQIN

has internal 0.01µF capacitor. Additional R-C filter can

be used to further reduce the ripple on VTTR. The error

amplifier for channel 2 uses this voltage as its reference

voltage.

INTV_CC(C3): Internal 3.3V Regulator Output of the

Switching Mode Regulator Channel. The internal power

drivers and control circuits are powered from this volt-

age. This pin is internally decoupled to GND with a 2.2µF

low ESR ceramic capacitor. No more external decoupling

capacitor needed.

V

(A4): External Reference Input for Channel 2. An

DDQIN

internal resistor divider sets the VTTR pin voltage to be

equal to half the voltage applied to this input. Channel 2

uses the VTTR pin voltage as its error amplifier reference.

RUN1 (D2), RUN2 (B2): Run Control Input of Each

Switching Mode Regulator Channel. Enables chip opera-

tion by tying RUN above 1.28V. Tying this pin below 1V

4632fc

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For more information www.linear.com/LTM4632

LTM4632

BLOCK DIAGRAM

VDDQ

VDDQIN

V

OUT1

V

OUT2

60.4k

10k

PGOOD1

PGOOD2

FB1

INTV

CC

51.7k

VTTR

BUFFER

CC

0.01µF

INTV

CC

V

IN

V

IN

2.2µF

3.6V TO 15V

0.22µF

10µF

22µF

SYNC/MODE

TRACK/SS1

0.82µH

VDDQ

1.3V

3A

V

OUT1

GND

0.1µF

1µF

RUN1

RUN2

0.22µF

COMP1

POWER CONTROL

INTERNAL

COMP

0.82µH

VTT

0.65V

3A

V

OUT2

GND

COMP2

1µF

22µF

INTERNAL

COMP

FREQ

312k

SGND

4632 BD

DECOUPLING REQUIREMENTS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

C

External Input Capacitor Requirement

I

= 3A

4.7

10

µF

IN

OUT

(V = 3.6V to 15V, V

= 1.5V)

IN

OUT

External Output Capacitor Requirement

(V = 3.6V to 15V, V = 1.5V)

I

= 3A

10

22

µF

OUT

IN

OUT

4632fc

8

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LTM4632

OPERATION

The LTM4632 is a dual output standalone non-isolated

switch mode DC/DC power supply for DDR-QDR4 SRAM

memory supplies and bus termination. It can deliver two

output rails which could both sink and source 3A DC cur-

rent with few external input and output ceramic capaci-

tors, plus a 10mA buffered VTTR (VREF) reference voltage

With current mode control and internal feedback loop

compensation, the LTM4632 module has sufficient sta-

bility margins and good transient performance with a wide

range of output capacitors, even with all ceramic output

capacitors.

Current mode control provides cycle-by-cycle fast cur-

rent limiting. An internal overvoltage and undervoltage

comparators pull the open-drain PGOOD output low if

the output feedback voltage exits a 8% window around

the regulation point. Furthermore, an input overvoltage

protection been utilized by shutting down both power

which equal to one half of V

voltage.

DDQIN

Two or more module outputs can be easily paralleled to

achieve a single VTT output with a higher sink and source

current capability. Up to 8 phases can be paralleled to run

simultaneously with a good current sharing guaranteed

by current mode control loop.

MOSFETs when V rises above 17.5V to protect internal

IN

devices.

This module provides precisely regulated output voltage

(V

) programmable via one external resistor from 0.6V

Pulling the RUN pin below 1V forces the controller into

its shutdown state, turning off both power MOSFETs and

most of the internal control circuitry. At light load cur-

rents, burst mode operation can be enabled to achieve

higher efficiency compared to continuous mode (CCM) by

to^O2^U.5^TV¹over 3.6V to 15V input voltage range. With INTV_CC

tied to V , this module is able to operate from 3.3V input.

IN

The LTM4632 has an integrated a dual constant on-time

valley current mode regulator, power MOSFETs, induc-

tor, and other supporting discrete components. The typi-

cal switching frequency is internally set to 1MHz. For

switching noise-sensitive applications, the µModule can

be externally synchronized to a clock within 30% of the

set frequency. See the Applications Information section.

setting MODE pin to INTV . The TRACK/SS pin is used

CC

for power supply tracking and soft-start programming.

See the Applications Information section.

APPLICATIONS INFORMATION

The typical LTM4632 application circuit is shown in

Figure 19. External component selection is primarily deter-

mined by the input voltage, the output voltage and the

maximum load current. Refer to Table 5 for specific exter-

nal capacitor requirements for a particular application.

where t

is the minimum off-time, 45ns typical for

OFF(MIN)

LTM4632, and f is the switching frequency. Conversely

SW

the minimum on-time limit imposes a minimum duty

cycle of the converter which can be calculated as

D

MIN

= t

• f

ON(MIN) SW

V to V

Step-Down Ratios

where t

is the minimum on-time, 20ns typical for

IN

OUT

ON(MIN)

LTM4632. In the rare cases where the minimum duty

cycle is surpassed, the output voltage will still remain

in regulation, but the switching frequency will decrease

from its programmed value. Note that additional thermal

derating may be applied. See the Thermal Considerations

and Output Current Derating section in this data sheet.

There are restrictions in the maximum V and V

step

IN

OUT

down ratio that can be achieved for a given input voltage

due to the minimum off-time and minimum on-time limits

of the regulator. The minimum off-time limit imposes a

maximum duty cycle which can be calculated as:

D

MAX

= 1 – t

• f

OFF(MIN) SW

4632fc

9

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LTM4632

APPLICATIONS INFORMATION

Channel 1 Output Voltage Programming (Configured

as VDDQ)

Without considering the inductor current ripple, for each

output, the RMS current of the input capacitor can be

estimated as:

The PWM controller for the V

has an internal 0.6V

OUT1

I_OUT(MAX)

reference voltage. As shown in the Block Diagram, a 60.4k

I_CIN(RMS)

=

• D•(1–D)

internal feedback resistor connects V

and FB1 pins

OUT1

η%

together. Adding a resistor R from FB1 pin to GND pro-

FB

where η% is the estimated efficiency of the power module.

grams the output voltage:

0.6V

V_OUT– 0.6V

Output Decoupling Capacitors

R_FB

=

• 60.4k

With an optimized high frequency, high bandwidth design,

only single piece of 22µF low ESR output ceramic capaci-

tor is required for each LTM4632 output to achieve low

output voltage ripple and very good transient response.

Additional output filtering may be required by the sys-

tem designer, if further reduction of output ripples or

dynamic transient spikes is required. Table 5 shows a

matrix of different output voltages and output capacitors

to minimize the voltage droop and overshoot during a

0.75A (25%) load step transient. Multiphase operation

will reduce effective output ripple as a function of the

number of phases. Application Note 77 discusses this

noise reduction versus output ripple current cancella-

tion, but the output capacitance will be more a function

of stability and transient response. The Linear Technology

LTpowerCAD Design Tool is available to download online

for output ripple, stability and transient response analysis

and calculating the output ripple reduction as the number

of phases implemented increases by N times.

Table 1. V Resistor Table (1%) vs Various Output Voltages

FB

V

(V)

OUT

0.6

1.0

1.2

1.3

1.5

1.8

2.5

R (k)

FB

OPEN

90.9

60.4

52.3

40.2

30.1

19.1

Channel 2 Output Voltage Programming (Configured

as VTT)

The PWM controller for the V

uses VTTR voltage as

a reference voltage. V_OUT2is^Od^Ui^Tr²ectly connected to the

negative side of the error compiler to internally program

V

to equal to VTTR voltage, which equals to one half

OUT2

of V

voltage.

DDQIN

V

= VTTR = V

/2

DDQIN

OUT2

In a complete DDR memory power application which

require both VDDQ supply and VTT terminal outputs,

configure LTM4632 Channel 1 as VDDQ output by add-

ing a feed-back resistor from FB1 pin to GND. Feed V

(VDDQ output) voltage to V_DDQINpin to program Cha^On^Un^Te¹l

2 as VTT output which equals half of the Channel 1 (VDDQ

output) voltage.

Burst Mode Operation

In applications where high efficiency at intermediate

current are more important than output voltage ripple,

burst mode operation could be used on Channel 1 by

Input Decoupling Capacitors

The LTM4632 module should be connected to a low

AC-impedance DC source. For each regulator channel,

one piece 4.7µF input ceramic capacitor is required for

RMS ripple current decoupling. Bulk input capacitor is

only needed when the input source impedance is com-

promised by long inductive leads, traces or not enough

source capacitance. The bulk capacitor can be an electro-

lytic aluminum capacitor and polymer capacitor.

connecting SYNC/MODE pin to INTV to improve light

CC

load efficiency. In Burst Mode operation, a current rever-

sal comparator (IREV) detects the negative inductor cur-

rent and shuts off the bottom power MOSFET, resulting

in discontinuous operation and increased efficiency. Both

power MOSFETs will remain off and the output capacitor

will supply the load current until the COMP voltage rises

above the zero current level to initiate another cycle.

4632fc

10

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LTM4632

APPLICATIONS INFORMATION

Force Continuous Current Mode (CCM) Operation

The two switching mode regulator channels inside the

LTM4632 are internally set to operate 180° out of phase.

Multiple LTM4632s could easily operate 90 degrees,

60 degrees or 45 degrees shift which corresponds to

4-phase, 6-phase or 8-phase operation by letting SYNC/

MODE of the LTM4632 synchronize to an external multi-

phase oscillator like LTC6902. Figure 2 shows a 4-phase

single output VTT termination supply design example for

clock phasing.

In applications where fixed frequency operation is more

critical than low current efficiency, and where the low-

est output ripple is desired, forced continuous opera-

tion should be used. Forced continuous operation can

be enabled by tying the SYNC/MODE pin to GND. In this

mode, inductor current is allowed to reverse during low

output loads, the COMP voltage is in control of the current

comparator threshold throughout, and the top MOSFET

always turns on with each oscillator pulse. During start-

up, forced continuous mode is disabled and inductor

current is prevented from reversing until the LTM4632’s

output voltage is in regulation.

33.2k

3.3

INTV

LTM4632

CC

0°

V

12A

+

TT

V

SET

MOD

OUT1

OUT2

SYNC/

MODE

180°

V

PH

LTC6902

Operating Frequency

0°

LTM4632

V

DIV

GND

90°

OUT1

SYNC/

The operating frequency of the LTM4632 is optimized to

achieve the compact package size and the minimum output

ripple voltage while still keeping high efficiency. The default

operating frequency is internally set to 1MHz. In most appli-

cations, no additional frequency adjusting is required.

MODE

90°

270°

V

OUT2

4632 F02

Figure 2. Example of Clock Phasing for 4-Phase

Single Output VTT Operation with LTC6902

Frequency Synchronization

Tie FB1 pin of the LTM4632 to its INTV pin to put the

CC

module into two phase single VTT output operation mode.

This will internally switch the Channel 1 error amplifier

reference voltage from 0.6V to VTTR voltage, which is the

same as Channel 2. Repeat this for each LTM4632 module

in multiple LTM4632s paralleling application.

The power module has a phase-locked loop comprised

of an internal voltage controlled oscillator and a phase

detector. This allows the internal top MOSFET turn-on to

be locked to the rising edge of the external clock. The

external clock frequency range must be within 30%

around the set operating frequency. A pulse detection

circuit is used to detect a clock on the SYNC/MODE pin

to turn on the phase locked loop. The pulse width of the

clock has to be at least 100ns. The clock high level must

be above 2V and clock low level below 0.3V. The presence

of an external clock will place both regulator channels into

forced continuous mode operation. During the start-up of

the regulator, the phase-locked loop function is disabled.

Also tie RUN, TRACK/SS and COMP pin of each paral-

leling channel together. Figure 20 shows an example of

paralleled multiphase single output VTT termination sup-

ply operation and pin connection.

The LTM4632 device is an inherently current mode con-

trolled device, so parallel modules will have very good cur-

rent sharing. This will balance the thermals on the design.

Multiphase Operation (Configured as VDDQ+VTT)

Multiphase Operation (Configured as Multiphase

Single Output VTT)

For application which both VDDQ and VTT termination

output loads demand more than 3A of current, two or

multiple Channel 1 outputs from different LTM4632 mod-

ules can be easily paralleled to provide a multiphase sin-

gle VDDQ output while Channel 2 outputs from different

LTM4632 modules can paralleled to provide a multiphase

For VTT termination output loads that demand more than

3A of current, two outputs in the LTM4632 or even mul-

tiple LTM4632s can be paralleled to run out of phase to

provide a multiphase single output VTT termination supply

capable of souring and sinking higher current.

single VTT output.

4632fc

11

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LTM4632

APPLICATIONS INFORMATION

In this case, multiple LTM4632s should be setup to oper-

ate 180 degrees, 120 degrees or 90 degrees shift which

corresponds to 2-phase, 3-phase or 4-phase operation

by letting SYNC/MODE of the LTM4632 synchronize to

an external multiphase oscillator like LTC6902.

Tie RUN1, TRACK/SS1 FB1 and COMP1 pin of each par-

alleling module together for VDDQ output. Tie RUN2,

DDQIN

together for VTT output. Figure 22 shows an example of

two LTM4632 get paralleled to provide 6A VDDQ and 6A

VTT termination supply.

V

, FB2 and COMP2 pin of each paralleling module

33.2k

3.3

INTV

Input and Output RMS Ripple Current Cancellation

CC

VDDQ

6A

0°

+

V

SYNC/

MODE

SET

MOD

OUT1

OUT2

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output

capacitors. The RMS input ripple current is reduced by,

and the effective ripple frequency is multiplied by, the

number of phases used (assuming that the input volt-

age is greater than the number of phases used times

the output voltage). The output ripple amplitude is also

reduced by the number of phases used when all of the

outputs are tied together to achieve a single high output

current design.

180°

VTT

6A

PH

0°

DIV

GND

180°

360°

V

SYNC/

MODE

OUT1

180°

OUT2

4632 F03

Figure 3. Example of Clock Phasing for 2-Phase

VDDQ Plus 2-Phase VTT Operation with LTC6902

0.60

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY CYCLE (V /V

)

OUT IN

4632 F04

Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle

4632fc

12

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LTM4632

APPLICATIONS INFORMATION

Application Note 77 provides a detailed explanation of

multiphase operation. The input RMS ripple current can-

cellation mathematical derivations are presented, and

a graph is displayed representing the RMS ripple cur-

rent reduction as a function of the number of interleaved

phases. Figure 4 shows this graph.

The R_FB(SL)is the feedback resistor and the R_TR(TOP)

TR(BOT)

the slave regulator, as shown in Figure 6.

/

R

is the resistor divider on the TRACK/SS pin of

Following the upper equation, the master’s output slew

rate (MR) and the slave’s output slew rate (SR) in Volts/

Time is determined by:

R_FB(SL)

Channel 1 Output Voltage Tracking and Soft-Start

R_FB(SL)+60.4k

R_TR(BOT)

R_TR(TOP)+R_TR(BOT)

MR

SR

The TRACK/SS pin provides a means to either soft-start

the Channel 1 regulator or track it to a different power

supply. A capacitor on the TRACK/SS pin will program

the ramp rate of the channel 1 output voltage. An internal

1.2µA current source will charge up the external soft-start

=

For example, V_OUT(MA)= 1.5V, MR = 1.5V/1ms and

= 1.2V, SR = 1.2V/1ms. From the equation, we

capacitor towards INTV voltage. When the TRACK/SS

CC

V

OUT(SL)

voltage is below 0.6V, it will take over the internal 0.6V

reference voltage to control the output voltage. The total

soft-start time can be calculated as:

could solve out that R

= 60.4k and R

= 40.2k

TR(TOP)

is a good combination for the Ratiometric^Tt^Rra^(Bc^Ok^Tin⁾g.

C_SS

t_SS= 0.6 •

1.2µA

MASTER OUTPUT

SLAVE OUTPUT

where C_SSis the capacitance on the TRACK/SS pin.

Forced continuous mode are disabled during the soft-

start process.

Channel 1 output voltage tracking can also be programmed

externally using the TRACK/SS pin. The output can be

tracked up and down with another regulator. Figure 5 and

Figure 6 show an example waveform and schematic of a

Ratiometric tracking where the slave regulator’s output

slew rate is proportional to the master’s.

TIME

4632 F05

Figure 5. Output Ratiometric Tracking Waveform

Since the slave regulator’s TRACK/SS is connected to

the master’s output through a R

/R

resistor

TR(TOP) TR(BOT)

The TRACK pins will have the 1.2µA current source on

when a resistive divider is used to implement tracking on

that specific channel. This will impose an offset on the

TRACK pin input. Smaller values resistors with the same

ratios as the resistor values calculated from the above

equation can be used. For example, where the 60.4k is

used then a 6.04k can be used to reduce the TRACK pin

offset to a negligible value.

divider and its voltage used to regulate the slave output

voltage when TRACK/SS voltage is below 0.6V, the slave

output voltage and the master output voltage should sat-

isfy the following equation during the start-up.

R_FB(SL)

V_OUT(SL)

•

=

R_FB(SL)+60.4k

R_TR(BOT)

V_OUT(MA)

•

The Coincident output tracking can be recognized as a

special Ratiometric output tracking which the master’s

output slew rate (MR) is the same as the slave’s output

slew rate (SR), as waveform shown in Figure 7.

R_TR(TOP)+R_TR(BOT)

4632fc

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LTM4632

APPLICATIONS INFORMATION

PGOOD1

PGOOD2

V

IN

V

OUT1

1.5V, 3A

V

3.6V TO 15V RAIL

IN

OUT1

OUT2

22µF

4V

RUN1

RUN2

10µF

16V

VTTR

FB1

LTM4632

INTV

CC

SYNC/MODE

TRACK/SS1

COMP1

COMP2

40.2k

0.1µF

V

DDQIN

GND

PGOOD1

PGOOD2

V

OUT2

V

IN

OUT1

OUT2

1.2V, 3A

22µF

4V

RUN1

RUN2

VTTR

FB1

LTM4632

INTV

CC

SYNC/MODE

TRACK/SS1

COMP1

COMP2

60.4k

V

OUT1

60.4k

40.2k

V

DDQIN

GND

4632 F06

Figure 6. Example Schematic of Ratiometric Output Voltage Tracking

From the equation, we could easily find out that, in the

Coincident tracking, the slave regulator’s TRACK/SS pin

resistor divider is always the same as its feedback divider.

MASTER OUTPUT

R_FB(SL)

R_TR(BOT)

=

SLAVE OUTPUT

R_FB(SL)+60.4k R_TR(TOP)+R_TR(BOT)

For example, R

= 60.4k and R

= 60.4k is a

TR(TOP)

TR(BOT)

good combination for Coincident tracking for V

=

OUT(MA)

1.5V and V

= 1.2V application.

OUT(SL)

TIME

4632 F07

Figure 7. Output Coincident Tracking Waveform

4632fc

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LTM4632

APPLICATIONS INFORMATION

Power Good

Overtemperature Protection

The internal overtemperature protection monitors the

junction temperature of the module. If the junction

temperature reaches approximately 170°C, both power

switches will be turned off until the temperature drops

about 10°C cooler.

The PGOOD pins are open drain pins that can be used to

monitor valid output voltage regulation. This pin monitors

a 8% window around the regulation point. A resistor can

be pulled up to a particular supply voltage for monitoring.

To prevent unwanted PGOOD glitches during transients

or dynamic V

changes, the LTM4632’s PGOOD falling

OUT

Input Overvoltage Protection

edge includes a blanking delay of approximately 40μs.

In order to protect the internal power MOSFET devices

against transient voltage spikes, the LTM4632 constantly

monitors each V_INpin for an overvoltage condition. When

Stability Compensation

The LTM4632 module internal compensation loop is

de-signed and optimized for low ESR ceramic output

capacitors only application. Table 5 is provided for most

application requirements. The LTpowerCAD Design Tool is

available to download for control loop analysis for further

optimization.

V rises above 17.5V, the regulator suspends operation

IN

by shutting off both power MOSFETs on the correspond-

ing channel. Once V drops below 16.5V, the regulator

IN

immediately resumes normal operation. The regulator

executes its soft-start function when exiting an overvolt-

age condition.

RUN Enable

Thermal Considerations and Output Current Derating

Pulling the RUN pin to ground forces the LTM4632 into

its shutdown state, turning off both power MOSFETs and

most of its internal control circuitry. Tying the RUN pin

voltage above 1.28V will turn on the entire chip.

The thermal resistances reported in the Pin Configuration

section of the data sheet are consistent with those param-

eters defined by JESD51-9 and are intended for use with

finite element analysis (FEA) software modeling tools that

leverage the outcome of thermal modeling, simulation,

and correlation to hardware evaluation per-formed on a

µModule package mounted to a hardware test board—

also defined by JESD51-9 (“Test Boards for Area Array

Surface Mount Package Thermal Measurements”). The

motivation for providing these thermal coefficients in

found in JESD51-12 (“Guidelines for Reporting and Using

Electronic Package Thermal Information”).

Low Input Application

The LTM4632 is capable to run from 3.3V input when

the V pin is tied to INTV pin. See Figure 21 for the

IN

CC

application circuit. Please note the INTV pin has 3.6V

CC

ABS max voltage rating.

Pre-Biased Output Start-Up (Channel 1)

There may be situations that require the power supply to

start up with a pre-bias on the output capacitors. In this

case, it is desirable to start up without discharging that

output pre-bias. The LTM4632 channel 1 can safely power

up into a pre-biased output without discharging it.

Many designers may opt to use laboratory equipment and

a test vehicle such as the demo board to anticipate the

µModule regulator’s thermal performance in their appli-

cation at various electrical and environmental operating

conditions to compliment any FEA activities. Without

FEA software, the thermal resistances reported in the

Pin Configuration section are in-and-of themselves not

relevant to providing guidance of thermal performance;

instead, the derating curves provided in the data sheet can

be used in a manner that yields insight and guidance per-

taining to one’s application-usage, and can be adapted to

correlate thermal performance to one’s own application.

4632fc

The LTM4632 accomplishes this by forcing discontinuous

mode (DCM) operation until the TRACK/SS1 pin voltage

reaches 80% of the 0.6V reference voltage for channel 1.

This will prevent the BG from turning on during the pre-

biased output start-up which would discharge the out-

put. Do not pre-bias LTM4632 with a voltage higher than

INTV (3.3V) voltage.

CC

15

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LTM4632

APPLICATIONS INFORMATION

The Pin Configuration section typically gives four thermal

coefficients explicitly defined in JESD 51-12; these coef-

ficients are quoted or paraphrased below:

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 8; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the µModule package.

1. θ , the thermal resistance from junction to ambient,

JA

is the natural convection junction-to-ambient air ther-

mal resistance measured in a one cubic foot sealed

enclosure. This environment is sometimes referred to

as “still air” although natural convection causes the

air to move. This value is determined with the part

mounted to a JESD 51-9 defined test board, which

does not reflect an actual application or viable operat-

ing condition.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a μModule. For example, in nor-

mal board-mounted applications, never does 100% of

the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the µModule package as the standard defines for

2. θ_JCbottom, the thermal resistance from junction to

ambient, is the natural convection junction-to-ambi-

ent air thermal resistance measured in a one cubic

foot sealed enclosure. This environment is sometimes

referred to as “still air” although natural convection

causes the air to move. This value is determined with

the part mounted to a JESD 51-9 defined test board,

which does not reflect an actual application or viable

operating condition.

θ

and θ

, respectively. In practice, power loss

JCtop

JCbottom

is thermally dissipated in both directions away from the

package–granted, in the absence of a heat sink and air-

flow, a majority of the heat flow is into the board.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are

not exactly linear with respect to total package power loss.

To reconcile this complication without sacrificing model-

ing simplicity–but also, not ignoring practical realities–an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JESD51-12 to predict power loss heat flow and tempera-

ture readings at different interfaces that enable the cal-

culation of the JEDEC-defined thermal resistance values;

(3) the model and FEA software is used to evaluate the

µModule with heat sink and airflow; (4) having solved for

and analyzed these thermal resistance values and simu-

lated various operating conditions in the software model,

a thorough laboratory evaluation replicates the simulated

conditions with thermocouples within a controlled-envi-

ronment chamber while operating the device at the same

3. θ

, the thermal resistance from junction to top of

JCtop

the product case, is determined with nearly all of the

component power dissipation flowing through the top

of the package. As the electrical connections of the

typical µModule are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of θ

, this value may be useful

JCbottom

for comparing packages but the test conditions don’t

generally match the user’s application.

4. θ_JB, the thermal resistance from junction to the

printed circuit board, is the junction-to-board thermal

resistance where almost all of the heat flows through

the bottom of the µModule and into the board, and

is really the sum of the θ_JCbottomand the thermal

resistance of the bottom of the part through the solder

joints and through a portion of the board. The board

temperature is measured a specified distance from

the package, using a two sided, two layer board. This

board is described in JESD 51-9.

4632fc

16

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LTM4632

APPLICATIONS INFORMATION

power loss as that which was simulated. The outcome of

this process and due diligence yields the set of derating

curves provided in other sections of this data sheet. After

these laboratory test have been performed and correlated

curves. The junctions are maintained at 120°C maximum

while lowering output current or power with increasing

ambient temperature. The decreased output current will

decrease the internal module loss as ambient tempera-

ture is increased. The monitored junction temperature of

120°C minus the ambient operating temperature speci-

fies how much module temperature rise can be allowed.

As an example in Figure 12 the load current is derated

to ~3A at ~100°C with no air or heat sink and the power

loss for the 5V to 1V at 3A output is about 0.95W. The

0.95W loss is calculated with the ~0.7W room tempera-

ture loss from the 5V to 1V power loss curve at 3A, and

the 1.35 multiplying factor at 120°C measured junction

temperature. If the 100°C ambient temperature is sub-

tracted from the 120°C junction temperature, then the

difference of 20°C divided by 0.95W equals a 20°C/W

to the µModule model, then the θ and θ are summed

JB

BA

together to correlate quite well with the µModule model

with no airflow or heat sinking in a properly define cham-

ber. This θ + θ value is shown in the Pin Configuration

JB

BA

section and should accurately equal the θ_JAvalue because

approximately 100% of power loss flows from the junc-

tion through the board into ambient with no airflow or top

mounted heat sink.

The 1.0V, 1.5V, and 2.5V power loss curves in Figures 9 to

11 can be used in coordination with the load current derat-

ing curves in Figures 12 to 17 for calculating an approxi-

mate θ_JAthermal resistance for the LTM4632 with no heat

sinking and various airflow conditions. The power loss

curves are taken at room temperature, and are increased

with multiplicative factors of 1.35 assuming junction

temperature at 120°C. The derating curves are plotted

with the output current starting at 6A by putting LTM4632

into two phase single output setup (Figure 20) and the

ambient temperature at 40°C. These output voltages are

chosen to include the lower and higher output voltage

ranges for correlating the thermal resistance. Thermal

models are derived from several temperature measure-

ments in a controlled temperature chamber along with

thermal modeling analysis. The junction temperatures

are monitored while ambient temperature is increased

with and without airflow. The power loss increase with

ambient temperature change is factored into the derating

θ

thermal resistance. Table 2 specifies a 19°C~20°C/W

JA

value which is very close. Table 2 to 4 provide equivalent

thermal resistances for 1.0V, 1.5V, and 2.5V outputs with

and without airflow. The derived thermal resistances in

Table 2 to 4 for the various conditions can be multiplied

by the calculated power loss as a function of ambient

temperature to derive temperature rise above ambient,

thus maximum junction temperature. Room temperature

power loss can be derived from the efficiency curves

in the Typical Performance Characteristics section and

adjusted with the above ambient temperature multiplica-

tive factors. The printed circuit board is a 1.6mm thick

four layer board with two ounce copper for the two outer

layers and one ounce copper for the two inner layers. The

PCB dimensions are 95mm × 76mm.

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION

AMBIENT

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

4638 F08

µMODULE DEVICE

Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients

4632fc

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For more information www.linear.com/LTM4632

LTM4632

APPLICATIONS INFORMATION

Figure 9. 1.0V Output Power Loss

Figure 10. 1.5V Output Power Loss

Figure 11. 2.5V Output Power Loss

4.0

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

4.0

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

4.0

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

12V

IN

12V

IN

5V

IN

3

IN

3

IN

3

0

1

2

4

5

6

0

1

2

4

5

6

0

1

2

4

5

6

LOAD CURRENT (A)

4632 F09

4632 F10

4632 F11

Figure 12. 5V to 1.0V Derating

Curve, No Heat Sink

Figure 13. 12V to 1.0V Derating

Curve, No Heat Sink

Figure 14. 5V to 1.5V Derating

Curve, No Heat Sink

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

30 40 50 60 70 80 90 100 110 120

AMBIENT TEMPERATURE (°C)

4632 F12

4632 F13

4632 F14

Figure 15. 12V to 1.5V Derating

Curve, No Heat Sink

Figure 16. 5V to 2.5V Derating

Curve, No Heat Sink

Figure 17. 12V to 2.5V Derating

Curve, No Heat Sink

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

0LFM

200LFM

400LFM

30 40 50 60 70 80 90 100 110 120

AMBIENT TEMPERATURE (°C)

4632 F15

4632 F16

4632 F17

4632fc

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For more information www.linear.com/LTM4632

LTM4632

APPLICATIONS INFORMATION

Table 2. 1.0V Output

DERATING CURVE

Figures 12, 13

V

(V)

POWER LOSS CURVE

Figure 9

AIRFLOW (LFM)

HEAT SINK

None

θ

(°C/W)

JA

IN

5, 12

0

19 to 20

18 to 19

17 to 18

Figure 9

200

400

None

Figure 9

None

Table 3. 1.5V Output

DERATING CURVE

Figures 14, 15

V

(V)

POWER LOSS CURVE

Figure 10

AIRFLOW (LFM)

HEAT SINK

None

(°C/W)

JA

IN

5, 12

0

19 to 20

18 to 19

17 to 18

Figures 14, 15

Figure 10

200

400

None

Figures 14, 15

Figure 10

None

Table 4. 2.5V Output

DERATING CURVE

Figures 16, 17

V

(V)

POWER LOSS CURVE

Figure 11

AIRFLOW (LFM)

HEAT SINK

None

(°C/W)

JA

IN

5, 12

0

19 to 20

18 to 19

17 to 18

Figures 16, 17

5, 12

Figure 11

200

400

None

Figures 16, 17

Figure 11

None

4632fc

19

For more information www.linear.com/LTM4632

LTM4632

APPLICATIONS INFORMATION

Table 5. Output Voltage Response for Each Regulator Channel vs Component Matrix (Refer to Figure 19)

25% Load Step Typical Measured Values

C

OUT2

(BULK)

IN

OUT1

(CERAMIC) PART NUMBER

VALUE

(CERAMIC) PART NUMBER

VALUE

PART NUMBER VALUE

Murata

GRM188R61E475KE11# 4.7µF, 25V, Murata

0603, X5R

GRM21R60J476ME15# 47µF, 6.3V, Panasonic 6TPC150M

0805, X5R

150µF, 6.3V 3.5

× 2.8 × 1.4mm

Murata

GRM188R61E106MA73# 10µF, 25V, Murata

0603, X5R

GRM188R60J226MEA0# 22µF, 6.3V,

0603, X5R

Taiyo Yuden TMK212BJ475KG-T

4.7µF, 25V, Taiyo

0805, X5R Yuden

JMK212BJ476MG-T

47µF, 6.3V,

0805, X5R

C

OUT2

P-P

RECOVERY

TIME

LOAD

STEP

(A)

LOAD STEP

IN

OUT1

V

(CERAMIC)

(µF)

C

(CERAMIC) (BULK)

C

V

DROOP DERIVATION

SLEW RATE

(A/µS)

R

FB

OUT

IN

FF

IN

(V)

(BULK)

(µF)

(pF)

(V)

(mV)

(µS)

(kΩ)

90.9

60.4

40.2

30.1

19.1

1

2 × 10

0

1 × 47µF

0

5, 12

0

77

15

18

20

0.75

10

1.2

1.5

1.8

2.5

0

83

0

94

0

105

138

0

4632fc

20

For more information www.linear.com/LTM4632

LTM4632

APPLICATIONS INFORMATION

SAFETY CONSIDERATIONS

•

Place a dedicated power ground layer underneath the

unit.

The LTM4632 modules do not provide galvanic isolation

from V to V . There is no internal fuse. If required,

To minimize the via conduction loss and reduce mod-

ule thermal stress, use multiple vias for interconnec-

tion between top layer and other power layers.

IN

OUT

a slow blow fuse with a rating twice the maximum input

current needs to be provided to protect each unit from

catastrophic failure. The device does support thermal

shutdown and over current protection.

•

Do not put via directly on the pad, unless they are

capped or plated over.

Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

LAYOUT CHECKLIST/EXAMPLE

The high integration of LTM4632 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

•

For parallel modules, tie the V_OUT, V_FB, and COMP

pins together. Use an internal layer to closely con-

nect these pins together. The TRACK pin can be tied

a common capacitor for regulator soft-start.

•

Use large PCB copper areas for high current paths,

including V_IN, GND, V_OUT1and V_OUT2. It helps to mini-

mize the PCB conduction loss and thermal stress.

• Bring out test points on the signal pins for monitoring.

Figure 18 gives a good example of the recommended

layout.

•

Place high frequency ceramic input and output capac-

itors next to the V_IN, PGND and V_OUTpins to minimize

high frequency noise.

GND

C

OUT

V

IN

V

IN

C

IN

GND

Figure 18. Recommend PCB Layout

4632fc

21

For more information www.linear.com/LTM4632

LTM4632

APPLICATIONS INFORMATION

VDDQ

1.3V, 3A

22µF

4V

PGOOD1 PGOOD2

V

IN

V

IN

OUT1

3.6V TO 15V RAIL

RUN1

RUN2

INTV

SYNC/MODE

TRACK/SS1

VTT

0.65V, 3A

22µF

25V

V

OUT2

LTM4632

22µF

4V

VTTR

FB1

COMP1

CC

VTTR

0.65V, 10mA

VDDQ

V

COMP2

DDQIN

GND

52.3k

4632 F19

Figure 19. 3.6V to 15V Input, 1.3V/3A VDDQ, 0.65V/ 3A VTT and 10mA VTTR Design

V

IN

VDDQ

1.8V, 36A

V

IN

OUT1

OUT2

4V TO 15V RAIL

100µF

4V

×6

LTM4630

GND

22µF

25V

×4

PGOOD1 PGOOD2

VTT

V

IN

OUT1

0.9V, 6A

RUN1

RUN2

47µF

4V

V

OUT2

22µF

25V

LTM4632

VTTR

INTV

CC

INTV

CC

FB1

COMP1

COMP2

SYNC/MODE

TRACK/SS1

VTTR

0.9V, 10mA

VDDQ

V

DDQIN

GND

4632 F20

Figure 20. 4V to 15V Input, Two Phase Single Output 6A VTT Termination Design with LTM4630 36A VDDQ Supply

4632fc

22

For more information www.linear.com/LTM4632

LTM4632

APPLICATIONS INFORMATION

VDDQ

1.5V, 3A

22µF

4V

PGOOD1 PGOOD2

V

IN

V

IN

OUT1

3.1V TO 3.5V RAIL

RUN1

RUN2

INTV

SYNC/MODE

TRACK/SS1

VTT

0.75V, 3A

22µF

6.3V

V

OUT2

LTM4632

22µF

4V

VTTR

FB1

COMP1

CC

VTTR

0.75V, 10mA

VDDQ

V

COMP2

DDQIN

GND

40.2k

4632 F21

Figure 21. 3.3V Input, 1.5V/3A VDDQ, 0.75V/ 3A VTT and 10mA VTTR Design

VDDQ

1.2V, 6A

22µF

4V

PGOOD1 PGOOD2

V

IN

V

IN

OUT1

OUT2

3.6V TO 15V RAIL

22µF

25V

VTT

RUN1

RUN2

V

0.6V, 6A

22µF

4V

LTM4632

VTTR

INTV

CC

INTV

CC

FB1

COMP1

COMP2

SYNC/MODE

TRACK/SS1

33.2k

VTTR

0.6V, 10mA

V

DDQIN

LTC6902

+

GND

1

2

3

4

5

10

9

INTV

V

SET

MOD

GND

CC

1µF

DIV

PH

8

7

OUT1

OUT2

OUT4

OUT3

6

PGOOD1 PGOOD2

V

IN

OUT1

OUT2

RUN1

RUN2

INTV

SYNC/MODE

TRACK/SS1

V

LTM4632

VTTR

FB1

CC

COMP1

COMP2

VDDQ

DDQIN

30.2k

GND

4632 F22

Figure 22. Two Module in Parallel, 3.6V to 15V Input, 1.2V/6A VDDQ, 0.6V/ 6A VTT and 10mA VTTR Design

4632fc

23

For more information www.linear.com/LTM4632

LTM4632

PACKAGE DESCRIPTION

PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

LTM4632 Component LGA and BGA Pinout

PIN ID

A1

FUNCTION

PIN ID

A2

FUNCTION

PIN ID

A3

FUNCTION

PIN ID

A4

FUNCTION

PIN ID

A5

FUNCTION

COMP2

GND

V

OUT2

V

OUT2

V

IN

VTTR

V

DDQIN

B1

B2

RUN2

GND

B3

V

B4

PGOOD2

SGND

B5

IN

C1

GND

C2

C3

INTV

C4

C5

SYNC/MODE

GND

CC

D1

V

D2

RUN1

D3

V

IN

D4

PGOOD1

FB1

D5

OUT1

E1

V

E2

V

IN

E3

TRACK/SS1

E4

E5

COMP1

4632fc

24

For more information www.linear.com/LTM4632

LTM4632

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTM4632#packaging for the most recent package drawings.

Z

/ / b b b Z

2 . 5 4 0

1 . 2 7 0

0 . 3 1 7 5

0 . 0 0 0

0 . 3 1 7 5

1 . 2 7 0

2 . 5 4 0

4632fc

25

For more information www.linear.com/LTM4632

LTM4632

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTM4632#packaging for the most recent package drawings.

Z

/ / b b b Z

2 . 5 4 0

1 . 2 7 0

0 . 3 1 7 5

0 . 0 0 0

0 . 3 1 7 5

1 . 2 7 0

2 . 5 4 0

4632fc

26

For more information www.linear.com/LTM4632

LTM4632

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

05/16 Added BGA package

1, 2, 26

B

09/16 Corrected equations of tracking start-up time from R

05/17 Changed VDDQ to 1.3V/3A and VTT to 0.65V

/[R

+ R

] to R

/[R

+ R ]

TR(BOT)

13, 14

22

TR(TOP)

TR(BOT)

TR(TOP)

C

4632fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

27

For more information www.linear.com/LTM4632

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTM4632

PACKAGE PHOTO

DESIGN RESOURCES

SUBJECT

DESCRIPTION

µModule Design and Manufacturing Resources

Design:

Manufacturing:

• Selector Guides

• Quick Start Guide

• Demo Boards and Gerber Files

• Free Simulation Tools

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

µModule Regulator Products Search

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

TechClip Videos

Quick videos detailing how to bench test electrical and thermal performance of µModule products.

Digital Power System Management

Linear Technology’s family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LTM4622

Ultrathin, Dual 2.5A or Single 5A Step-Down µModule 3.6V < V < 20V, 0.6V < V

< 5.5V, 6.25mm × 6.25mm × 1.82mm LGA

IN

OUT

Regulator

Package, 6.25mm × 6.25mm × 2.42 BGA Package

4V ≤ V ≤ 20V, 0.6V ≤ V ≤ 5.5V, 6.25mm × 6.25mm × 1.82mm LGA Package,

LTM4623

Ultrathin, Single 3A Step-Down µModule Regulator

IN

OUT

6.25mm × 6.25mm × 2.42 BGA Package

4V < V < 14V, 0.6V < V < 5.5V, 9mm × 15mm × 5.01mm BGA Package

LTM4644

LTM4630

Quad 4A Step-Down µModule Regulator

IN

OUT

µModule Regulator for Higher Power VDDQ Supply

4.5V < V < 15V, 0.6V <V

<1.8V, Single 36A or Dual 18A, 16mm × 16mm ×

IN

OUT

5.01mm BGA Package, 16mm × 16mm × 4.41mm LGA Package

LTM4650

LTM4639

LTM4675

LTM4677

LTC3717

LTC6902

µModule Regulator for High Power FPGA/ASIC

Core Supply

4.5V < V < 15V, 0.6V <V

<1.8V, Single 50A or Dual 25A, 16mm × 16mm ×

IN

OUT

5.01mm BGA Package

Low Input Voltage, Single 20A Step-Down µModule

Regulator

2.375V < V < 7V, 0.6V < V

< 5.5V, 15mm × 15mm × 4.92mm BGA Package

IN

OUT

µModule Regulator with PSM for High Power, High

Accuracy FPGA/ASIC Core Supply

DC/DC µModule with Digital Power System Management, 4.5V < V < 17V,

IN

0.5V < V

< 5.5V with 0.5% Accuracy, Single 18A or Dual 9A

OUT

µModule Regulator with PSM for High Power, High

Accuracy FPGA/ASIC Core Supply

DC/DC µModule with Digital Power System Management, 4.5V < V < 16V,

IN

0.5V < V

< 1.8V with 0.5% Accuracy, Single 36A or Dual 18A

OUT

Step-Down Controller for VTT for DDR Memory

Termination

4V < V < 36V, I

=

20A, Requires External Inductor and MOSFET

IN

OUT

Multiphase Oscillator for Multiphase Operation

2-, 3- or 4-Phase, 5kHz to 20MHz Frequency Range

4632fc

LT 0517 REV C • PRINTED IN USA

www.linear.com/LTM4632

28

For more information www.linear.com/LTM4632

 LINEAR TECHNOLOGY CORPORATION 2016


型号：	LTM4632
厂家：	Linear
描述：	Ultrathin, Triple Output, Step-Down Î¼Module Regulator for DDR-QDR4 Memory 双倍数据速率
文件：	总28页 (文件大小：2030K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4632 [Linear]

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