LTM4633_15_技术文档

LTM4633

Triple 10A Step-Down

DC/DC µModule Regulator

FeaTures

DescripTion

The LTM^®4633 µModule^®(micromodule) regulator com-

bines three complete 10A switching mode DC/DC con-

verters into one small package. Included in the package

are the switching controllers, power FETs, inductors, and

most support components. The LTM4633’s three regula-

tors operate from 4.7V to 16V input rail(s) or 2.375V to

n

Three Independent 10A DC Output Current Regulator

Channels

n

Input Voltage Range: 4.7V to 16V

n

2.375V to 16V with External 5V Bias

n

V

Voltage Range: 0.8V to 1.8V

OUT1,2

n

Voltage Range: 0.8V to 5.5V

OUT3

1.5ꢀ ꢁaxiꢂuꢂ Total DC Output Error

Current ꢁode Control/Fast Transient Response

Frequency Synchronization

16V with an external 5V bias. The V

range is 0.8V to 1.8V, while the V

to 5.5V. Each output is set by one external resistor.

and V

output

OUT1

OUT2

output range is 0.8V

OUT3

Output Overvoltage and Overcurrent Protection

ꢁultiphase Operation with Current Sharing

Highswitchingfrequencyandacurrentmodearchitecture

enable a very fast transient response to line and load

changes without sacrificing stability. The device supports

frequency synchronization, multiphase parallel operation

on V

and V

OUT1

OUT2

n

General Purpose Teꢂperature ꢁonitors

Soft-Start/Voltage Tracking

Power Good Monitors

of V

and V

, soft-start and output voltage tracking

OUT1

OUT2

for supply rail sequencing.

15mm × 15mm × 5.01mm BGA Package

Fault protection features include overvoltage protection,

overcurrent protection and temperature monitoring. The

power module is offered in a space saving, thermally

enhanced 15mm × 15mm × 5.01mm BGA package. The

LTM4633 is RoHS compliant with Pb-free finish.

L, LT, LTC, LTM, µModule, PolyPhase, Burst Mode, Linear Technology and the Linear logo are

registered trademarks and PowerPath and LTpowerCAD are trademarks of Linear Technology

Corporation. All other trademarks are the property of their respective owners. Protected by

U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066,

6580258 and 8163643. Other patents pending.

applicaTions

n

Telecom, Networking and Industrial Equipment

n

High Density Point of Load Regulation

Typical applicaTion

12V Input to 1.0V, 1.5V and 3.3V Output Regulator

Efficiency vs Load Current

95

12V

IN

4.7µF

6.3V

90

10k

V

EXTV

INTV

FREQ/PLLLPF

CC

IN1

IN2

IN3

CC

CNTL_PWR

RUN1

PGOOD12

PGOOD3

1.0V

13.3k

V

OUT1

85

10A

RUN2

242k

V

RUN3

FB1

LTM4633

1.5V

10A

80

75

70

TK/SS1

TK/SS2

TK/SS3

V

OUT2

69.8k

19.1k

V

FB2

12V , 3.3V OUTPUT

IN

3.3V

10A

12V , 1.5V OUTPUT

IN

OUT3

12V , 1V OUTPUT

IN

V

FB3

MODE/PLLIN GND SGND

0

1

2

3

4

5

6

7

8

9

10

4633 TA01a

LOAD CURRENT (A)

4633 TA01b

4633f

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For more information www.linear.com/LTM4633

LTM4633

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

TOP VIEW

CNTL_PWR ............................................... –0.3V to 18V

FREQ/PLLLPF

TKSS2

TK/SS1 TK/SS3

V

, V , V ........................................... –0.3V to 18V

OUT1 OUT2

COMP1

COMP2

FB1 GND

IN1 IN2 IN3

M

L

PGOOD12

PGOOD3

, V

............................................. –0.3V to 2.2V

MODE/PLLIN

RUN1

RUN2

RUN3

V

FB2

........................................................ –0.3V to 5.5V

OUT3

EXTV

CC

V

FB3

SGND

COMP3

K

J

Switch Voltage (SW1, SW2 and SW3) ...........–1V to 18V

GND

MODE/PLLIN, TK/SS1, TK/SS2, TK/SS3,

INTV

CC

CNTL_PWR

H

G

F

FREQ/PLLLPF, V , V , V ............–0.3V to INTV

FB1 FB2 FB3

CC

V

IN3

V

IN1

GND

IN2

COMP1, COMP2, COMP3 (Note 6)........–0.3V to INTV

RUN1, RUN2, RUN3, INTV , EXTV ,

CC

SW3

SW1

SW2

E

PGOOD12, PGOOD3..................................... –0.3V to 6V

GND

D

C

B

A

TEMP1, TEMP2......................................... –0.3V to 0.8V

INTV Peak Output Current..................................75mA

CC

V

OUT2

TEMP2

TEMP1

Operating Junction Temperature Range

V

OUT1

OUT3

(Note 2).................................................. –55°C to 125°C

Storage Temperature Range .................. –55°C to 125°C

Peak Solder Reflow Body Temperature................. 245°C

1

2

3

4

5

6

7

8

9

10 11 12

GND

BGA PACKAGE 144 LEAD (15mm × 15mm × 5.01mm)

= 125°C, θ = 7.5°C/W, θ = 4°C/W, θ = 5°C/W

T

JMAX

JA

JCbottom

JCtop

θ

DERIVED FROM 95mm × 76mm PCB WITH 4-LAYER, WEIGHT = 3.3g

JA

θ VALUES DETERMINED PER JESD 51-12

orDer inForMaTion

LEAD FREE FINISH

LTM4633EY#PBF

LTM4633IY#PBF

LTM4633MPY#PBF

TRAY

PART ꢁARKING*

LTM4633Y

PACKAGE DESCRIPTION

TEꢁPERATURE RANGE (NOTE 2)

–40°C to 125°C

LTM4633EY#PBF

LTM4633IY#PBF

LTM4633MPY#PBF

144-Lead (15mm × 15mm × 5.01mm) BGA

LTM4633Y

–40°C to 125°C

LTM4633Y

–55°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

4633f

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For more information www.linear.com/LTM4633

LTM4633

elecTrical characTerisTics ^Theldenotes the specifications which apply over the specified internal

operating teꢂperature range (Note 2), otherwise specifications are at T_A= 25°C. V_IN= 12V, per the typical application for each regulator

channel.

SYꢁBOL

PARAꢁETER

CONDITIONS

ꢁIN

TYP

ꢁAX

UNITS

l

V

IN

Input DC Voltage

CNTL_PWR Powered from Separate Supply

(5V to 16V Range)

2.375

16

V

l

CNTL_PWR Powered Tied to V Supply

4.7

16

V

IN

l

V

Output Voltage Range V

, V

OUT3

0.8

1.8

5.5

V

OUT(RANGE)

OUT1 OUT2

l

Output Voltage, Total Variation with Line

and Load, V , V , V

1.477

1.50

1.523

V

C

= 22µF × 3, C

= 100µF Ceramic × 3,

OUT(DC)

IN

FB

OUT

R

= 69k, MODE/PLLIN = 0V, V = 4.7V to 16V,

OUT1 OUT2 OUT3

IN

I

= 0A to 10A (Note 4)

OUT

Input Specifications

V

RUN1, RUN 2, RUN 3 Pin ON Threshold

RUN Pin Hysteresis

V

Rising

1.15

1.3

1.4

V

RUN

175

mV

RUN(HYS)

Q(VIN)

I

Input Supply Bias Current Each Channel

V

= 1.5V, Burst Mode Operation

= 1.5V, Pulse-Skipping Mode

= 1.5V, Switching Continuous

0.5

1

45

50

mA

µA

OUT

Shutdown, RUN = 0V

I

Input Supply Current Each Channel

V

= 1.5V, I = 10A

OUT

1.5

A

S(VIN)

OUT

Output Specifications

I

Output Continuous Current Range Each

Channel

V

= 1.5V (Note 4)

0

10

A

OUT(DC)

l

Line Regulation Accuracy per Channel

= 1.5V, V from 2.375V to 16V

0.015

0.3

0.02

%/V

∆V

V

OUT

IN

OUT(LINE)

I

= 0A, CNTL_PWR = 12V

V

OUT

Load Regulation Accuracy per Channel

V

= 1.5V, I

= 0A to 10A

OUT

0.5

%

OUT

OUT(LOAD)

(Note 4)

V

OUT

Output Ripple Voltage per Channel

Turn-On Overshoot per Channel

Turn-On Time per Channel

15

20

6

mV

ms

mV

I

= 0A, C

= 100µF Ceramic × 3,

OUT

OUT(AC)

OUT

V

= 1.5V

OUT

∆V

C

= 100µF Ceramic × 3, V

= 0A

= 1.5V,

OUT(START)

OUT

I

t

C

= 100µF Ceramic × 3, No Load,

START

OUT

TK/SS = 0.01µF

V

Peak Deviation for Dynamic Load per

Channel

Load: 0% to 50% to 0% of Full Load,

C

V

100

OUTLS

= 100µF Ceramic × 3,

= 1.5V Typical Bench Data

OUT

t

I

Settling Time for Dynamic Load Step per Load: 0% to 50% to 0% of Full Load,

40

13

µs

A

SETTLE

Channel

C

V

= 100µF Ceramic × 3,

OUT

= 1.5V Typical Bench Data

Output Current Limit per Channel

V

= 1.5V

OUT(PK)

OUT

Control Specifications

l

V

Voltage at V Pin per Channel

I

= 0A, V

= 1.5V

0.792

0.794

0.80

0.808

0.806

V

FB

OUT

I

FB

Current at V Pin per Channel

(Note 3)

–10

–50

nA

V

FB

V

Feedback Overvoltage Lockout per

Channel

0.84

1.1

0.86

0.88

OVL

I

Track Pin Soft-Start Pull-Up Current per

Channel

TK/SS = 0V

(Note 3)

1.5

1.9

µA

TK/SS

t

Minimum On-Time

90

ns

%

ON(MIN)

Max DC

Maximum Duty Cycle

2.375V to 2V at 10A, 5.5V to 5V at 0A (Note 6)

100

4633f

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For more information www.linear.com/LTM4633

LTM4633

elecTrical characTerisTics ^Theldenotes the specifications which apply over the specified internal

operating teꢂperature range (Note 2), otherwise specifications are at T_A= 25°C. V_IN= 12V, per the typical application for each regulator

channel.

SYꢁBOL

PARAꢁETER

CONDITIONS

ꢁIN

TYP

ꢁAX

UNITS

R

FBHI

Resistor Between V

and V Pins

60

60.4

60.8

kΩ

OUT

FB

V

PGOOD Trip Level

PGOOD12

PGOOD3

V

With Respect to Set Output

FB

PGOOD

FB

V

Ramping Negative

Ramping Positive

–7.5

7.5

%

V

PGOOD Voltage Low

I

= 2mA

PGOOD

0.1

0.3

5.2

V

PGL

INTV Linear Regulator

CC

V

Internal V Voltage

6V < V < 16V

4.8

4.5

5

V

INTVCC

CC

IN

V

Reg

Load

INTV Load Regulation

I

CC

= 0mA to 50mA

0.5

%

INTVCC

CC

Float

MODE/PLLIN EXTV Ramping Positive

l

V

EXTV Switchover Voltage

4.7

30

V

mV

EXTVCC

CC

EXT

EXTV Voltage Drop

I

CC

= 20mA, V = 5V

EXTVCC

75

LDO

CC

EXTV Hysteresis

200

LDOHYS

CC

Oscillator and Phase-Locked Loop

f

SYNC Capture Range

Clock Input Duty Cycle = 50%

600

700

750

800

kHz

kΩ

V

SYNC

S

Switching Frequency

V

= INTV

750

250

FREQ/PLLLPF

CC

R

MODE/PLLIN Input Resistance

Clock Input Level High

Clock Input Level Low

MODE/PLLIN

V

2.0

IH(MODE/PLLIN)

IL(MODE/PLLIN)

0.8

V

Clock Phase

V

OUT2

V

OUT3

V

OUT1

to V

Phase

V

= 1.2V (Note 3)

120

Deg

OUT1

OUT2

OUT3

FREQ/PLLLPF

V

Temperature Diode Forward Voltage

Temperature Coefficient

I

= 100µA at 25°C

TEMP

0.598

–2.0

V

TEMP1,2

TC V

mV/°C

TEMP

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: 100% tested at wafer level.

Note 4: See output current derating curves for different V , V

Note 5: Guaranteed by design.

Note 6: High duty designs need to be validated based on maximum

temperature rise and derating in ambient conditions.

and T .

IN OUT

A

Note 2: The LTM4633 is tested under pulsed load conditions such that

T ≈ T . The LTM4633E is guaranteed to meet performance specifications

J

A

over the 0°C to 125°C internal operating temperature range. Specifications

over the –40°C to 125°C internal operating temperature range are assured

by design, characterization and correlation with statistical process

controls. The LTM4633I is guaranteed to meet specifications over the

–40°C to 125°C internal operating temperature range. The LTM4633MP

is guaranteed and tested to meet specifications over the –55°C to 125°C

internal operating temperature range. Note that the maximum ambient

temperature consistent with these specifications is determined by specific

operating conditions in conjunction with board layout, the rated package

thermal resistance and other environmental factors.

4633f

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For more information www.linear.com/LTM4633

LTM4633

Typical perForMance characTerisTics

5V Input Efficiency

8V Input Efficiency

12V Input Efficiency

98

96

94

92

90

88

86

84

82

80

78

98

96

94

92

90

88

86

84

82

98

96

94

92

90

88

86

84

82

80

78

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

LOAD CURRENT (A)

4633 G02

4633 G03

LOAD CURRENT (A)

4633 G01

LOAD CURRENT (A)

8V TO 5V (700kHz)

8V TO 1.5V (700kHz)

5V TO 3.3V (700kHz)

5V TO 1.5V (700kHz)

12V TO 5V (700kHz)

12V TO 1.5V (700kHz)

IN

8V TO 3.3V (700kHz)

IN

8V TO 1.2V (700kHz)

IN

5V TO 2.5V (700kHz)

IN

5V TO 1.2V (700kHz)

IN

12V TO 3.3V (700kHz)

IN

12V TO 1.2V (700kHz)

IN

8V TO 2.5V (700kHz)

IN

8V TO 1.8V (700kHz)

IN

8V TO 1V (700kHz)

IN

5V TO 1.8V (700kHz)

IN

5V TO 1V (700kHz)

IN

12V TO 2.5V (700kHz)

IN

12V TO 1.8V (700kHz)

IN

12V TO 1V (700kHz)

IN

Light Load Efficiency

12V to 1V Load Step Response

12V to 1.2V Load Step Response

90

80

70

60

50

40

30

20

10

0

V

OUT

50mV/DIV

I

OUT

2A/DIV

OUT

2A/DIV

4633 G04

4633 G05

40µs/DIV

12V TO 1.5V CONT MODE

C

= 220pF, 0A TO 5A LOAD STEP AT 5A/µs

OUT

C

= 220pF, 0A TO 5A LOAD STEP AT 5A/µs

OUT

FF

12V TO 1.5V PULSE SKIP

12V TO 1.5V Burst Mode

OPERATION

= 2 × 100µF CERAMIC, 1 × 470µF POSCAP

0

0.5

1

1.5

2

2.5

5

3

3.5 4 4.5

LOAD CURRENT (A)

4633 G17

12V to 1.5V Load Step Response

12V to 1.8V Load Step Response

12V to 2.5V Load Step Response

V

OUT

100mV/DIV

50mV/DIV

I

OUT

I

OUT

2A/DIV

4633 G06

4633 G08

4633 G07

40µs/DIV

50µs/DIV

40µs/DIV

C

FF

C

OUT

= 220pF, 0A TO 5A LOAD STEP AT 5A/µs

C

FF

C

OUT

= 100pF, 0A TO 5A LOAD STEP AT 5A/µs

C

FF

C

OUT

= 220pF, 0A TO 5A LOAD STEP AT 5A/µs

= 2 × 100µF CERAMIC, 1 × 470µF POSCAP

= 2 × 100µF CERAMIC

= 2 × 100µF CERAMIC, 1 × 470µF POSCAP

4633f

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For more information www.linear.com/LTM4633

LTM4633

Typical perForMance characTerisTics

12V to 5V Load Step Response

3.3V to 1V Load Step Response

12V to 3.3V Load Step Response

V

OUT

V

OUT

100mV/DIV

50mV/DIV

100mV/DIV

I

OUT

I

OUT

2A/DIV

4633 G09

4633 G10

4633 G11

50µs/DIV

100µs/DIV

C

= 100pF, 0A TO 5A LOAD STEP AT 5A/µs

C

FF

C

OUT

= 100pF, 0A TO 5A LOAD STEP AT 5A/µs

C

FF

C

OUT

= NONE, 0A TO 5A LOAD STEP AT 5A/µs

= 4 × 100µF CERAMIC, 1 × 470µF POSCAP

FF

OUT

= 2 × 100µF CERAMIC

3.3V to 1.8V Load Step Response

12V to 1.5V No-Load Start-Up

12V to 1.5V Full-Load Start-Up

V

OUT

50mV/DIV

V

OUT

500mV/DIV

I

OUT

2A/DIV

4633 G12

4633 G13

4633 G14

100µs/DIV

25ms/DIV

TK/SS CAPACITOR = 0.1µF

25ms/DIV

TK/SS CAPACITOR = 0.1µF

C

= NONE, 0A TO 5A LOAD STEP AT 5A/µs

= 4 × 100µF CERAMIC, 1 × 470µF POSCAP

FF

OUT

C

OUT

= 2 × 100µF CERAMIC, 1 × 470µF POSCAP

C

OUT

= 2 × 100µF CERAMIC, 1 × 470µF POSCAP

12V to 1.5V, 10A Load

Short Circuit

12V to 1.5V No-Load Short Circuit

Start Into Pre-Bias Output

V

OUT

10V/DIV

0.5V/DIV

500mV/DIV

I

IN

I

1A/DIV

IN

1A/DIV

4633 G15

4633 G16

4633 G18

10ms/DIV

V

= 12V

OUT

PRE-BIASED AT 500mV

50ms/DIV

IN

= 1V

4633f

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For more information www.linear.com/LTM4633

LTM4633

pin FuncTions

PACKAGE ROW AND COLUꢁN LABELING ꢁAY VARY

CNTL_PWR (J6): Input Supply to an Internal Bias LDO to

Power the Internal Controller and MOSFET Drivers. This

pin is connected to an input supply voltage range of 4.7V

AꢁONG µꢁodule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

GND (A4, A8-A9, D1- D12, E1-E12, F4, F8, F12, G3-G4,

G7-G8, G11-G12, H3-H4, H7-H8, H11-H12, J1-J5, J7,

J9-J12, K1-K3, K8-K10, K12,L1-L2,L12, ꢁ1, ꢁ6-ꢁ8,

ꢁ12): Ground Pins for Both Input and Output Returns.

All ground pins need to connect with large copper areas

underneath the unit.

to 16V. If the voltage at CNTL_PWR is ≤5.5V, the INTV

CC

pin should be tied to CNTL_PWR for optimum efficiency.

If the voltage at CNTL_PWR is >5.5V, leave INTV floating

CC

with the recommended decoupling capacitor. When using

multiple input supplies, choose the lowest input supply

between 4.7V to 16V to supply the CNTL_PWR pin. This

will lower the internal power loss and improve efficiency.

V

, V

(A10-A12, B9-B12, and C10-C12);

OUT1 OUT2 OUT3

(A5-A7, B5-B8, C6-C8); (A1-A3, B1-B4, C1-C4): Power

Output Pins. Apply output load between these pins and

the GND pins. Recommend placing output decoupling

capacitance directly between these pins and the GND

pins. See Table 5.

INTV (J8): Output of the Internal Bias LDO for Powering

CC

InternalControlCircuitry.Connecta4.7µFceramiccapaci-

tor to ground for decoupling. If the voltage at CNTL_PWR

is ≤5.5V, tie the INTV pin to CNTL_PWR for optimum

CC

efficiency. If the voltage at CNTL_PWR is >5.5V, leave

INTV floating. See the Applications Information section.

CC

TEꢁP1 AND TEꢁP2 (C9, C5): Two Onboard Temperature

Diodes for Monitoring the VBE Junction Voltage Change

with Temperature. Each of these two temperature diode

connected PNP transistors is placed in the middle of

channel 1 and channel 2, and in the middle of channel 2

and channel 3. See the Applications Information section

and an example in Figure 19.

SGND (K6-K7, L6-L7): Signal Ground Connections. The

signal ground connection in the module is separated from

normal power ground (GND) by an internal 2.2Ω resistor.

This allows the designer to connect the signal ground pin

close to GND near the external output capacitors on the

regulatorchannel’soutputs.Theentireinternalsmall-signal

feedback circuitry is referenced to SGND, thus allowing

for better output regulation. See the recommended layout

in the Applications Information section.

V

,V ,V

IN1 IN2 IN3

(F9-F10,G9-G10,H9-H10);(F5-F6,G5-

G6,H5-H6);(F1-F2,G1-G2,H1-H2): Power Input Pins.

Apply input voltage between these pins and the GND pins.

Recommendplacinginputdecouplingcapacitancedirectly

between the V pins and the GND pins. The V paths

EXTV (L3): External Bias Power Input. The internal bias

CC

LDO is bypassed whenever the voltage at EXTV is above

IN

CC

can be all combined from one power source, or powered

4.7V. Never exceed 6V at this pin and ensure CNTL_PWR >

from independent power sources. The V paths can

EXTV atalltimestoavoidreversepolarityontheinternal

IN

CC

operate down to 2.375V when the CNTL_PWR is biased

separately from a supply in the range of 4.7V to 16V. See

the Applications Information section.

bias LDO. Connect a 1µF capacitor to ground when used

otherwise leave floating. When generating a 5V output on

channel 3, connect the 5V output to this pin to improve

efficiency.

SW1 (F11), SW2 (F7), SW3 (F3): The internal switch

node for each of the regulator channels for monitoring

the switching waveform. An R-C snubber circuit can be

placed on these pins to ground to eliminate switch node

ringing noise.

4633f

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For more information www.linear.com/LTM4633

LTM4633

pin FuncTions

FREQ/PLLLPF(L8):FrequencySetandPLLLowpassFilter

PGOOD12, PGOOD3 (ꢁ2, ꢁ3): Output voltage power

good indicator for V

and V are combined, and

OUT3

Pin.ThispinisdrivenwithaDCvoltagetosettheoperating

OUT1

OUT2

frequency. Generally the pin is just connected to INTV to

V

separate. The open-drain logic output is pulled to

CC

set the typical 750kHz operating frequency. Applying a DC

voltage of 1.4V to this pin will set the frequency to 600kHz

and 1.6V will set it to 700kHz. When an external clock is

used, then the FREQ/PLLLPF pin must not be connected

to any DC voltage. The pin must be floating and will have

the proper internal compensation for the internal loop

ground when the output voltage is not within 7.5% of the

regulation point.

COꢁP1, COꢁP2, COꢁP3 (ꢁ4, L4, K4): Current Control

Threshold and Error Amplifier Compensation Point. The

current comparator threshold increases with this control

voltage. The LTM4633 regulator channels are all internally

compensatedforproperstability. COMP1andCOMP2can

be tied together for PolyPhase^®20A parallel operation.

See the Applications Information section.

filter. For V

≤ 1.5V use 600kHz, and for V

OUT1,2,3

≥ 1.5V use ≥700kHz. These frequecny settings optimize

efficiency and eliminate minimum on-time issues for less

than 1V output. See the Applications Information section.

V , V , V (ꢁ5, L5, K5): The Negative Input of the

FB1 FB2 FB3

ꢁODE/PLLIN (L9): Force Continuous Mode, Burst Mode,

or Pulse-Skipping Mode Selection Pin and External Syn-

chronization Input to Phase Detector Pin. Connect this pin

to SGND to force all channels into the continuous mode

Error Amplifier for Each of the Three Channels. Internally,

each of these pins is connected to their respective output

with a 60.4k precision resistor. Different output voltages

can be programmed with an additional resistor between

of operation. Connect to INTV to enable pulse-skipping

CC

eachindividualV pinandground.InPolyPhaseoperation,

FB

modeofoperation.LeavingthepinfloatingwillenableBurst

Mode operation. A clock on the pin will force the controller

into continuous mode of operation and synchronize the

internal oscillator.

tying the V and V pins together allows for parallel

FB1

FB2

operation up to 20A. See the Applications Information

section for details.

TK/SS1,TK/SS2,TK/SS3(ꢁ9,ꢁ10,ꢁ11):OutputVoltage

TrackingandSoft-StartInputs.Whenoneparticularchannel

is configured to be the master, a capacitor to ground at

this pin sets the ramp rate for the master channel’s output

voltage. When the channel is configured to be the slave,

RUN1,RUN2,RUN3(L10,L11,K11):RunControlInputs.A

voltageabove1.3VonanyRUNpinturnsonthatparticular

channel. However, forcing any of these RUN pins below

1.2V causes that channel to shut down. Each of the RUN

pins has an internal 10k resistor to ground. This resistor

can be used with an external pull-up resistor to the input

voltage to set a UVLO for that channel, or simply to turn

on the channel. The RUN pins have a maximum voltage

of 6V. See the Applications Information section.

the V voltage of the master channel is reproduced by a

FB

resistor divider and applied to this pin. Internal soft-start

currents of 1.5μA are charging the soft-start capacitors.

In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to

be shorted externally.

4633f

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For more information www.linear.com/LTM4633

LTM4633

block DiagraM

MODE/PLLIN

FREQ/PLLLPF

CNTL_PWR

V

IN1

INTV

12V

CC

C

IN2

22µF

IN1

1µF

INTERNAL

FILTER

22µF

GND

SW1

MTOP1

MBOT1

R1

40.2k

0.36µH

V

OUT1

V

OUT1

SGND

RUN1

1.2V

10A

+

R

RUN1

R

FBHI1

0.1µF

10k

C

OUT1

60.4k

TK/SS1

COMP1

GND

SS

CAP1

SGND

R

V

FB1

V

FB1

121k

FB1

SGND

INTERNAL

COMP

LOCATED NEAR POWER STAGES

SGND

TEMP1

PNP

SGND

INTV

CC

R4

V

10k

IN2

V

IN

PGOOD12

INTV

4.5V TO 16V

C

IN4

22µF

IN3

1µF

22µF

GND

SW2

CC

MTOP2

MBOT2

4.7µF

0.36µH

V

1.5V

10A

OUT2

V

EXTV

OUT2

CC

+

12V

R

FBHI2

60.4k

0.1µF

C

OUT2

R2

40.2k

GND

3-CHANNEL

POWER CONTROL

RUN2

R

SGND

RUN2

10k

TK/SS2

SS

CAP2

TEMP2

PNP

SGND

INTV

CC

V

FB2

V

FB2

R5

10k

R

FB2

LOCATED NEAR

POWER STAGES

PGOOD3

COMP2

69.8k

SGND

V

IN3

C

IN6

22µF

IN5

1µF

INTERNAL

COMP

22µF

GND

SW3

OUT3

12V

R3

MTOP3

MBOT3

SGND

0.68µH

V

3.3V

10A

OUT3

V

40.2k

RUN3

+

R

FBHI3

60.4k

GND

R

0.1µF

RUN3

C

OUT3

10k

TK/SS3

COMP3

SS

CAP3

SGND

R

V

FB3

V

FB3

INTERNAL MODULE CONNECTION

SGND

FB3

19.1k

INTERNAL

COMP

SGND

2.2Ω

SGND

4633 F01

Figure 1. Siꢂplified LTꢁ4633 Block Diagraꢂ

4633f

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For more information www.linear.com/LTM4633

LTM4633

operaTion

Power ꢁodule Description

overvoltage is cleared. There are two temperature moni-

tors in the LTM4633. TEMP1 monitors the close relative

temperature of channels 1 and 2, and TEMP2 monitors

the close relative temperature of channels 2 and 3. The

two diode connected PNP transistors are grounded in the

module and can be used as general purpose temperature

monitors using a device that is designed to monitor the

single-ended connection.

The LTM4633 µModule regulator is a high performance

triple output nonisolated switching mode DC/DC power

supply. It can provide 10A per output with a few exter-

nal input and output capacitors. This module provides

precisely regulated output voltages programmable via

external resistors from 0.8V DC to 1.8V DC (V

and

OUT1

) over a 2.375V

V

), and 0.8V DC to 5.5V DC (V

OUT2

OUT3

to 16V input range with control bias on the CNTL_PWR

Pulling any of the RUN pins below 1.3V forces the cor-

responding regulator channel into a shutdown state. The

TK/SS pins are used for programming the output voltage

ramp and voltage tracking during start-up for each of the

channels. See the Applications Information section.

pin, or 4.7V to 16V with control bias tied to V . When

IN

applying control bias in the range from 4.7V to 5.5V, then

connect the bias to CNTL_PWR and INVT , otherwise

CC

if >5.5V only bias the CNTL_PWR pin. The typical applica-

tion schematic is shown in Figure 16.

TheLTM4633isinternallycompensatedtobestableoverall

operatingconditions.Table5providesaguidelineforinput

and output capacitances for several operating conditions.

The LTpowerCAD™ software tool is provided for transient

The LTM4633 has three integrated constant-frequency

current mode regulators, power MOSFETs, power induc-

tors, and other supporting discrete components. The

typical switching frequency is 750kHz. For switching

noise-sensitive applications, it can be externally syn-

chronized from 600kHz to 750kHz. See the Applications

Information section.

and stability analysis. The V pin is used to program the

FB

output voltage with a single external resistor to ground.

Each of the channels, operate with a 120° phase shift for

multiphase operation. V

and V

can be combined

OUT2

OUT1

With current mode control and internal feedback loop

compensation, the LTM4633 module has sufficient stabil-

ity margins and good transient performance with a wide

range of output capacitors, even with all ceramic output

capacitors.

to provide a single 20A output. The two channels will

not be operating 180° phase shift, but 120° phase when

combined for a 20A design. So the input RMS current

will be higher than a 180° phase shifted design. See the

Applications Information section.

Currentmodecontrolprovidescycle-by-cyclefastcurrent

limit in an overcurrent condition. An internal overvolt-

age monitor protects the output voltages in the event

of an overvoltage >7.5%. The top MOSFET is turned off

and the bottom MOSFET is turned on until the output

High efficiency at light loads can be accomplished with

selectable Burst Mode operation using the MODE/PLLIN

pin. These light load features will accommodate battery

operation. Efficiencygraphsareprovidedforlightloadop-

erationintheTypicalPerformanceCharacteristicssection.

4633f

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For more information www.linear.com/LTM4633

LTM4633

applicaTions inForMaTion

The typical LTM4633 application circuit is shown in Fig-

ure 16. External component selection is primarily deter-

mined by the maximum load current and output voltage.

RefertoTable5forspecificexternalcapacitorrequirements

for particular applications.

In the parallel operation the following pins should be tied

together, V

and V

pins, COMP1 and COMP2 pins,

FB1

FB2

TK/SS1 and TK/SS2, and RUN1 and RUN2.

Input Capacitors

The LTM4633 module should be connected to a low AC

impedance DC source. Additional input capacitors are

V to V

Step-Down Ratios

IN

OUT

There are restrictions in the V to V

step-down ratio

neededfortheRMSinputripplecurrentrating.TheI

IN

OUT

CIN(RMS)

that can be achieved for a given input voltage. The V to

equation which follows can be used to calculate the input

capacitor requirement for each channel. Typically 22µF

X7R ceramics are a good choice with RMS ripple current

ratings of ~2A each. A 47µF to 100µF surface mount alu-

minum electrolytic capacitor can be used for more input

bulk capacitance. This bulk input capacitor is only needed

if the input source impedance is compromised by long

inductive leads, traces or not enough source capacitance.

If low impedance power planes are used, then this bulk

capacitor is not needed.

IN

V

OUT

minimum dropout is a function of load current and

at very low input voltage and high duty cycle applications

output power may be limited as the internal top power

MOSFET is not rated for 10A operation at higher ambient

temperatures. At very low duty cycles the minimum 90ns

on-time must be maintained. See the Frequency Adjust-

ment section and temperature derating curves.

Output Voltage Prograꢂꢂing

The PWM controller has an internal 0.8V 1% reference

voltage. As shown in the Block Diagram, a 60.4k preci-

For a buck converter, the switching duty cycle can be

estimated as:

sion internal feedback resistor connects the V

pins together.

and V

OUT

FB

V_OUT

D=

V

IN

The output voltage will default to 0.8V with no feedback

resistor. Adding a resistor R from V to ground pro-

Without considering the inductor ripple current, for each

output, the RMS current of the input capacitor can be

estimated as:

FB

grams the output voltage:













60.4k+ R_FB

48.32k

V_OUT–0.8V

V_OUT= 0.8V •

, R_FB=

I

R_FB

(1)

I_CIN(RMS)

=

^OUT(MAX)• D• 1–D

(

)

η%

Table 1. V_FBResistor Table vs Various Output Voltages

In the previous equation, η% is the estimated efficiency

V

(V) 0.8

OUT

1.0

1.2

1.5

1.8

2.5

3.3

5.0

of the power module in decimal form (0.nn) for a given

R

FB

(kΩ) Open 242

121

69.8 48.7 28.7 19.1 11.5

V

OUT

-to-V ratio.

IN

For parallel operation of V

and V

, the following

OUT2

OUT1

The selection of C is simplified by the 3-phase architec-

IN

equation can be used to solve for R :

FB

ture and its impact on the worst-case RMS current draw

occurs when only one channel is operating. This is true

when the three channels are powered from a common

60.4k

2

R_FB=

V_OUT

V . The channel with the highest duty cycle D peaking at

IN

–1

0.5 and maximum load current needs to be used in the

0.8V

4633f

11

For more information www.linear.com/LTM4633

LTM4633

applicaTions inForMaTion

aboveformula. ThiswillgivethemaximumRMScapacitor

current requirement. Increasing the output current drawn

from the other channels will actually decrease the input

RMS ripple current from its maximum value. The out-of-

phase technique typically reduces the input capacitor’s

RMS ripple current by a factor of 50% when compared to

asinglephasepowersupplysolution. Ifthethreechannels

are powered from independent input sources, then each

of the input RMS current ratings will need to be calculated

specific to that channel.

even though the voltage at the COMP pin indicates a

lower value. The voltage at the COMP pin drops when

the inductor’s average current is greater than the load

requirement. As the COMP voltage drops below 0.5V, the

burst comparator trips, causing the internal sleep line to

go high and turn off both power MOSFETs.

In sleep mode, the internal circuitry is partially turned

off, reducing the quiescent current. The load current is

now being supplied from the output capacitors. When the

output voltage drops, causing COMP to rise, the internal

sleep line goes low, and the LTM4633 resumes normal

operation. The next oscillator cycle will turn on the top

power MOSFET and the switching cycle repeats.

Output Capacitors

The LTM4633 is designed for low output voltage ripple

noise. The bulk output capacitors defined as C

are

OUT

chosen with low enough effective series resistance (ESR)

to meet the output voltage ripple and transient require-

Pulse-Skipping ꢁode Operation

I

napplicationswherelowoutputrippleandhighefficiency

ments. C

canbealowESRtantalumcapacitor, lowESR

OUT

at intermediate currents are desired, pulse-skipping

mode should be used. Pulse-skipping operation allows

the LTM4633 to skip cycles at low output loads, thus

increasing efficiency by reducing switching loss. Tying

Polymercapacitororceramiccapacitor. Thetypicaloutput

capacitancerangeisfrom200µFto470µF.Additionaloutput

filtering may be required by the system designer if further

reduction of output ripple or dynamic transient spikes is

required.Table5showsamatrixofdifferentoutputvoltages

and output capacitors to minimize the voltage droop and

overshoot during a 5A/µs transient. The table optimizes

totalequivalentESRandtotalbulkcapacitancetooptimize

thetransientperformance.Stabilitycriteriaareconsidered

in the Table 5 matrix, and LTpowerCAD is available for free

to conduct stability analysis. LTpowerCAD can calculate

the output ripple reduction as the number of implemented

phases increases by N times.

the MODE/PLLIN pin to INTV enables pulse-skipping

CC

operation. With pulse-skipping mode at light load, the

internalcurrentcomparatormayremaintrippedforseveral

cycles, thus skipping operation cycles. This mode has

lower ripple than Burst Mode operation and maintains a

higher frequency operation than Burst Mode operation.

Forced Continuous Operation

In applications where fixed frequency operation is more

critical than low current efficiency, and where the lowest

output ripple is desired, forced continuous operation

should be used. Forced continuous operation can be

enabled by tying the MODE/PLLIN pin to ground. In this

mode, inductor current is allowed to reverse during low

output loads, the COMP voltage is in control of the current

comparator threshold throughout, and the top MOSFET

alwaysturnsonwitheachoscillatorpulse.Duringstart-up,

forced continuous mode is disabled and inductor current

is prevented from reversing until the LTM4633 output

voltage is in regulation.

Burst ꢁode Operation

The LTM4633 is capable of Burst Mode operation in

which the power MOSFETs operate intermittently based

on load demand, thus saving quiescent current. For ap-

plications where maximizing the efficiency at very light

loads is a high priority, Burst Mode operation should be

applied. To enable Burst Mode operation, simply float

the MODE/PLLIN pin. During Burst Mode operation, the

peak current of the inductor is set to approximately 30%

of the maximum peak current value in normal operation

4633f

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For more information www.linear.com/LTM4633

LTM4633

applicaTions inForMaTion

PLL, Frequency Synchronization

The LTM4633 regulators are inherently current mode

controlled devices, so the paralleling of V

and V

OUT1

OUT2

The LTM4633 device operates up to 750kHz. It can also be

synchronizedwithaninputclockthathasahighlevelabove

2V and a low level below 0.8V at the MODE/PLLIN pin. The

FREQ/PLLLPF pin must be floating when synchronized to

an incoming clock. Once the LTM4633 is synchronized to

an external clock frequency, it will always be running in

forced continuous operation. The synchronizing range is

channels will have good current sharing. This will balance

the thermals in the design. Tie the COMP, V , TK/SS

FB

and RUN pins together for these two channels to share

the current evenly. Figure 18 shows a schematic of the

parallel design.

ꢁiniꢂuꢂ On-Tiꢂe

from 600kHz to 750kHz. For V

≤ 1.5V use 600kHz,

OUT1,2,3

Minimum on-time, t , is the smallest time duration that

and for V

≥ 1.5V use ≥700kHz. These frequencies

ON

OUT1,2,3

anyofthethreeregulatorchannelsiscapableofturningon

the top MOSFET. It is determined byinternaltimingdelays,

and the gate charge required to turn-on the top MOSFET.

Low duty cycle applications may approach this minimum

on-time limit and care should be taken to ensure that:

optimize efficiency, eliminate minimum on-time issues

for less than 1V output, and control the inductor ripple

currents over the input and output voltage ranges.

A DC voltage should be applied to the FREQ/PLLLPF pin

tosettheoperatingfrequencywhenclocksynchronization

V_OUT

is not used. A voltage divider from the INTV pin (5V) to

CC

> t_ON(MIN)

ground can be used to set the frequency to 600kHz (set

V •FREQ

IN

to 1.4V), 700kHz (set to 1.6V), or tie the FREQ/PLLLPF

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles.Theoutputvoltagewillcontinuetoberegulated,but

the output ripple and inductor ripple current will increase.

The minimum on-time can be increased by lowering the

switching frequency. A good rule of thumb is to use 100ns

for the minimum on-time.

pin to the INTV pin for 750kHz. The top resistor in the

CC

voltage divider should be 50k, and the bottom resistor

should be 19.6k for 600kHz (set to 1.4V), or 23.7k for

700kHz (set to 1.6V). In most cases the FREQ/PLLLPF

pin can be tied to the INTV pin for 750kHz operation

CC

as long as the minimum on-time is not below 100ns. See

Figure 18 for an example.

Output Voltage Tracking

Parallel Channel Operation

Output voltage tracking can be programmed externally

using the TK/SS pins. The output can be tracked up and

downwithanotherregulator.Themasterregulator’soutput

is divided down with an external resistor divider that is the

same as the slave regulator’s feedback divider to imple-

ment coincident tracking. The LTM4633 uses an accurate

60.4k resistor internally for the top feedback resistor for

each channel. Figure 2 shows an example of coincident

For outputs that demand more than 10A of load current,

the LTM4633 device can parallel V

and V

to sup-

OUT1

OUT2

ply 20A of load current. The two channels will operate at

120° of phase shift. The input RMS ripple current can be

calculated using Equation 1. For example, 12V to 1.2V at

20A equates to duty cycle D = 0.1.

20A

0.84

I_CIN(RMS)

=

• 0.1• 1–0.1

(

)

tracking for V

and V

. V is the master and

OUT1

is the slave:

OUT2 OUT1

V

OUT2

I

= 7.14A

, use 4 × 22µF 16V X5R or X7R

RMS

CIN(RMS)

ceramic capacitors rated at 2A

each.







RMS

60.4k

R_TA

V_SLAVE= 1+

V_TRACK







4633f

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For more information www.linear.com/LTM4633

LTM4633

applicaTions inForMaTion

V

is the track ramp applied to the slave’s track pin.

has a control range of 0V to 0.8V, or the internal

RUN pin is below 1.3V or INTV drops below 3.5V. The

TRACK

CC

V

TRACK

total soft-start time can be calculated as:

reference voltage. When the master’s output is divided

down with the same resistor values used to set the slave’s

output, then the slave will coincident track with the master

until it reaches its final value. The master will continue to

its final value from the slave’s regulation point. Voltage

 0.8V •C_SS

t_SS

=









1.5µA

Regardless of the mode selected by the MODE/PLLIN pin,

the regulator channels will always start in pulse-skipping

mode up to TK/SS = 0.64V. Between TK/SS = 0.64V and

0.74V, it will operate in forced continuous mode and revert

totheselectedmodeonceTK/SS>0.74V.Theoutputripple

is minimized during the 100mV forced continuous mode

window ensuring a clean PGOOD signal.

tracking is disabled when V

is more than 0.8V. R in

TRACK

TA

Figure 2 will be equal to the R for coincident tracking.

FB2

The TK/SS pin of the master can be controlled by a capaci-

tor placed on the master regulator TK/SS pin to ground. A

1.5µA current source will charge the TK/SS pin up to the

referencevoltageandthenproceeduptoINTV . Afterthe

CC

When the channel is configured to track another supply,

the feedback voltage of the other supply is duplicated by

a resistor divider and applied to the TK/SS pin. Therefore,

thevoltageramprateonthispinisdeterminedbytheramp

rate of the other supply’s voltage. Note that the small soft-

0.8V ramp, the TK/SS pin will no longer be in control, and

the internal voltage reference will control output regula-

tion from the feedback divider. Foldback current limit is

disabled during this sequence of turn-on during tracking

or soft-starting. The TK/SS pins are pulled low when the

4.7V TO 16V

C

22µF

16V

C

22µF

16V

C

22µF

16V

C

22µF

16V

IN4

IN3

IN2

IN1

4.7µF

6.3V

V

IN1

SW1

V

IN2

SW2

V

SW3 INTV EXTV

CC CC

IN3

CNTL_PWR

MODE/PLLIN

RUN1

FREQ/PLLLPF

COMP1

UVLO SET AT 6V ON RUN PINS.

RUN PINS CAN BE SEQUENCED OR

ENABLED FROM LOGIC CONTROL

10k

13.3k

COMP2

RUN2

COMP3

60.4k

LTM4633

V

RUN3

PGOOD12

PGOOD3

TEMP1

OUT3

TK/SS1

R

60.4k

TB

V

TK/SS2

TK/SS3

OUT3

MASTER

69.8k

TEMP2

R

C

TA

SS3

OUTPUT RAMP

FED TO SLAVE

121k

0.1µF

V

GND SGND

OUT1

FB1

OUT2

FB2

OUT3

FB3

4633 F02

V

FB3

FB1

FB2

C

, SEE TABLE 5

OUT

R

FB3

19.1k

FB1

FB2

69.8k

121k

SOFT-START MASTER

RAMP SET BY C OR

C

OUT4

100µF

OUT1

SS1

100µF

EXTERNAL RAMP

100pF

3.3V

C

OUT7

100µF

V

OUT2

OUT5

FB3

1.5V

1.2V

100µF

220pF

V

FB1

C

OUT8

100µF

OUT3

OUT6

470µF

220pF 470µF

V

FB2

Figure 2. Triple Outputs, 1.5V and 1.2V Tracking to 3.3V

4633f

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LTM4633

applicaTions inForMaTion

startcapacitorchargingcurrentisalwaysflowing,produc-

ing a small offset error. To minimize this error, select the

trackingresistivedividervaluetobesmallenoughtomake

thiserrornegligible.Inordertotrackdownanotherchannel

or supply after the soft-start phase expires, the LTM4633

is forced into continuous mode of operation as soon as

Power Good

The PGOOD12 pin is an open-drain pin that can be used

to monitor valid output voltage regulation for V and

OUT1

. These pins

V

, and PGOOD3 for monitoring V

OUT2

OUT3

monitor a 7.5% window around the 0.8V feedback volt-

age on either V from the output regulation point. A

FB1,2,3

V

is below the undervoltage threshold of 0.74V regard-

FB

resistor can be pulled up to a particular supply voltage

no greater than 6V maximum for monitoring. Any of the

PGOOD pins are pulled low when the RUN pin of the cor-

responding channel is pulled low.

less of the setting of the MODE/PLLIN pin. However, the

LTM4633 should always be set in force continuous mode

tracking down when there is no load. After TK/SS drops

below0.1V,itschannelwilloperateindiscontinuousmode.

Overcurrent and Overvoltage Protection

The master’s TK/SS pin slew rate is directly equal to the

master’s output slew rate in Volts/Time. The equation:

Each of the regulator channels senses the peak inductor

current on a cycle-by-cycle basis as current mode opera-

tion. When current limit is reached the output voltage will

begin to fall and the internal current limit threshold will

begin fold back as the output voltage falls below 50% of

itsvalue. Foldback current limitis disabled during start-up

or track-up. Under a short-circuit condition at low duty

cycle operation, each of the regulator channels will begin

to skip cycles to limit the short-circuit current.

MR

SR





R =

•60.4k









TB

where MR is the master’s output slew rate and SR is the

slave’s output slew rate in Volts/Time. When coincident

tracking is desired, then MR and SR are equal, thus R

TB

is equal the 60.4k. R is derived from equation:

TA

0.8V

R_TA

=

Overvoltage protection is implemented by monitoring

V

V_TRACK

R_TB

FB

+

–

each one of the regulator’s V pins. When the V voltage

FB

60.4k R_FB

exceeds ~7.5% above the 0.8V reference value, then an

internal comparator monitor will turn off the top power

switch, andturnonthebottompowerswitchtoprotectthe

load. If the top power switch faults as a short, then a fuse

or circuit breaker would be recommended to protect the

system. This is due to the top switch being shorted while

the bottom switch is turning on to protect the output from

over voltage. High currents will flow and could damage

the bottom switch.

where V is the feedback voltage reference of the regula-

FB

tor, and V

is 0.8V. Since R is equal to the 60.4k top

TRACK

TB

feedback resistor of the slave regulator in equal slew rate

or coincident tracking, then R is equal to R with V

=

FB

TA

FB

V

.ThereforeR =60.4k,andR =60.4kinFigure2.

TRACK

TB TA

Inratiometrictracking, adifferentslewratemaybedesired

for the slave regulator. R can be solved for when SR is

TB

slower than MR. Make sure that the slave supply slew

rate is chosen to be fast enough so that the slave output

voltage will reach it final value before the master output.

4633f

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Stability Coꢂpensation

If the stray inductance or capacitance can be measured

or approximated then a somewhat analytical technique

can be used to select the snubber values. The inductance

is usually easier to predict. It combines the PowerPath™

board inductance in combination with the MOSFET inter-

connect inductance.

TheLTM4633hasalreadybeeninternallycompensatedfor

all output voltages. Table 5 is provided for most applica-

tion requirements with verified stability. LTpowerCAD is

available for other control loop optimization.

Run Enable

First, the SW pin can be monitored using a wide band-

width scope with a high frequency scope probe. The ring

frequency can be measured for its value. The impedance,

Z, can be calculated:

The RUN 1, 2, 3 pins have an enable threshold of 1.4V

maximum, typically 1.3V with 175mV of hysteresis. They

control the turn-on of their respective channel. There is

a 10k resistor on each pin to ground. The RUN pins can

be pulled up to V for 5V operation, or a resistor can be

placed on the pins and connected to V for higher than 5V

Z

(L)

= 2π • f • L

IN

where f is the resonant frequency of the ring, and L is the

total parasitic inductance in the switch path. If a resistor

is selected that is equal to Z, then the ringing should be

dampened. The snubber capacitor value is then chosen

so that its impedance is equal to the resistor at the ring

frequency:

IN

input. This resistor can be set along with the onboard 10k

resistor such that an undervoltage lockout (UVLO) level

can be programmed to shut down a particular regulator

channel if V falls below a set value. Use the equation:

IN

10k UVLO–1.3V

(

)

1

R=

Z_(C)

=

1.3V

2π •f•C

where R is the resistor from the RUN pin to V to set the

UVLO trip point. For example, if the UVLO point is to be

6.25V while operating at 12V input:

IN

Thesevaluesareagoodplacetostartwith. Modificationto

these components should be made to attenuate the ring-

ing without lowering the regulator’s conversion efficiency.

10k 6.25V –1.3V

(

)

≈ 38.3k

R=

INTV and EXTV

CC

1.3V

The LTM4633 has an onboard linear regulator fed by

CNTL_PWR which delivers a roughly 5V output at INTV

See the Typical Application circuits in Figure 17. The RUN

pins must not go above 6V maximum voltage. The RUN

pins have to be pulled up to enable the regulators.

CC

to power the internal controller and MOSFET drivers for all

three regulator channels. CNTL_PWR requires a voltage

between 4.7V to 16V. Apply a 4.7µF ceramic capacitor

SW Pins

between INTV and ground for decoupling. If the volt-

CC

The SW pins are generally used for testing purposes by

monitoring the pin of interest. The SW pins can also be

used to dampen out switch node ringing caused by LC

parasiticsintheswitchedcurrentpath.UsuallyaseriesR-C

combination is used called a snubber circuit. The resistor

will dampen the resonance and the capacitor is chosen to

only affect the high frequency ringing across the resistor.

age supplied to CNTL_PWR is ≤ 5.5V, connect INTV to

CC

CNTL_PWR. Otherwise, INTV should be left floating. To

CC

eliminate power loss in the onboard linear regulator and

improve efficiency connect a supply from 4.7V to 6V at

EXTV . Biasing EXTV will reduce the power loss in the

CC

internal LDO by (VCNTL_PWR – 5V) • 70mA. If EXTV is

CC

usedadda1µFceramiccapacitortogroundatEXTV and

CC

4633f

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ensure the voltage at CNTL_PWR is always greater than

1. θ :Thethermalresistancefromjunctiontoambient, is

JA

thevoltageatEXTV atalltimesincludingduringstart-up

the natural convection junction-to-ambient air thermal

resistance measured in a one cubic foot sealed enclo-

sure. This environment is sometimes referred to as

“still air” although natural convection causes the air to

move.Thisvalueisdeterminedwiththepartmountedto

a JESD 51-9 defined test board, which does not reflect

an actual application or viable operating condition.

CC

and shutdown. Connecting V

to EXTV may present

OUT3

CC

a convenient way to meet the sequencing requirement if

is a 5V output. Otherwise float EXTV if not used.

V

OUT3

CC

Therꢂal Considerations and Output Current Derating

The thermal resistances reported in the Pin Configura-

tion section of the data sheet are consistent with those

parameters defined by JESD 51-12 and are intended for

use with finite element analysis (FEA) software modeling

tools that leverage the outcome of thermal modeling,

simulation, and correlation to hardware evaluation per-

formed on a µModule package mounted to a hardware

test board defined by JESD 51-9 (“Test Boards for Area

Array Surface Mount Package Thermal Measurements”).

The motivation for providing these thermal coefficients is

foundinJESD51-12(“GuidelinesforReportingandUsing

Electronic Package Thermal Information”).

2. θ

: The thermal resistance from the junction to

JCbottom

the bottom of the product case, is determined with all

of the internal power dissipation flowing through the

bottom of the package. In a typical µModule regulator,

the bulk of the heat flows out the bottom of the pack-

age, but there is always heat flow out into the ambient

environment. As a result, this thermal resistance value

may be useful for comparing packages but the test

conditions don’t generally match the user’s application.

3. θ

: The thermal resistance from junction to top of

JCtop

the product case, is determined with nearly all of the

componentpowerdissipationflowingthroughthetopof

the package. As the electrical connections of the typical

µModule regulator are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of θ

for comparing packages but the test conditions don’t

generally match the user’s application.

Many designers in lieu or to compliment any FEA activities

may opt to use laboratory equipment and a test vehicle

such as the demo board to anticipate the µModule regula-

tor’s thermal performance in their application at various

electricalandenvironmentaloperatingconditions.Without

FEA software, the thermal resistances reported in the Pin

Configurationsectionarein-and-ofthemselvesnotrelevant

toprovidingguidanceofthermalperformance;instead,the

deratingcurvesprovidedlaterinthedatasheetcanbeused

in a manner that yields insight and guidance pertaining to

one’s application usage, and can be adapted to correlate

thermal performance to one’s own application.

, this value may be useful

JCbottom

4. θ : The thermal resistance from junction to the printed

JB

circuitboard,isthejunction-to-boardthermalresistance

where almost all of the heat flows through the bottom

oftheµModulepackageandintotheboard, andisreally

The Pin Configuration section provides values based on

four thermal coefficients explicitly defined in JESD 51-12;

these coefficients are quoted or paraphrased:

the sum of the θ

and the thermal resistance of

JCbottom

the bottom of the part through the solder joints and

through a portion of the board. The board temperature

is measured at a specified distance from the package,

using a 2-sided, 2-layer board. This board is described

in JESD 51-9.

4633f

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A graphical representation of the aforementioned ther-

mal resistances is given in Figure 3; blue resistances are

contained within the μModule regulator, whereas green

resistances are external to the µModule package.

laboratory testing in a controlled environment chamber

to reasonably define and correlate the thermal resistance

valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware

is used to accurately build the mechanical geometry of

the LTM4633 and the specified PCB with all of the cor-

rect material coefficients along with accurate power loss

source definitions; (2) this model simulates a software-

defined JEDEC environment consistent with JSDE 51-12

to predict power loss heat flow and temperature readings

at different interfaces that enable the calculation of the

JEDEC-defined thermal resistance values; (3) the model

and FEA software is used to evaluate the LTM4633 with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled environment

chamber while operating the device at the same power

loss as that which was simulated. The outcome of this

process and due diligence yields a set of derating curves

provided in other sections of this data sheet.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD 51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a μModule regulator. For example,

in normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally con-

duct exclusively through the top or exclusively through

bottom of the µModule package—as the standard defines

for θ

and θ , respectively. In practice, power

JCbottom

JCtop

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4633, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to different

junctions of components or die are not exactly linear with

respect to total package power loss. To reconcile this

complication without sacrificing modeling simplicity—

but also, not ignoring practical realities—an approach

has been taken using FEA software modeling along with

After these laboratory tests have been performed and cor-

related to the LTM4633 model, then the θ and θ are

JB

BA

summed together to correlate quite well with the device

modelconditionsofnoairfloworheatsinkinginaproperly

JUNCTION-TO-AMBIENT RESISTANCE COMPONENTS

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION

AMBIENT

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

4633 F03

µMODULE DEVICE

Figure 3. Graphical Representations of JESD51-12 Therꢂal Coefficients

4633f

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defined chamber. This θ + θ value should accurately

at a particular output voltage and output current for each

output are taken and multiplied by 1.4 for increased power

loss at 125°C junction. Thermal models are derived from

JB

BA

equaltheθ valuebecauseapproximately100%ofpower

JA

loss flows from the junction through the board into ambi-

ent with no air-flow or top mounted heat sink.

-

several temperature measurements in a controlled tem

perature chamber along with thermal modeling analysis.

The junction temperatures are monitored while ambient

temperature is increased with and without airflow. The

power loss increase with ambient temperature change

is factored into the derating curves. The junctions are

maintained at 125°C maximum while lowering output

current or power with increasing ambient temperature.

The decreased output current will decrease the internal

module loss as ambient temperature is increased. The

monitoredjunctiontemperatureof125°Cminustheambi-

entoperatingtemperaturespecifieshowmuchtemperature

rise can be allowed. For example, in Figure 11, the 1V

load current is derated to ~20A at ~85°C with no air and

with heat sink. In Figure 9, the 12V to 1.0V power loss

at 6.66A per channel is 1.4W. The total power loss would

be 3 times 1.4W or 4.2W. The 4.2W is then multiplied by

the 1.4 multiplier for 125°C junction. This 5.88W value is

used with the total temperature rise of 125°C minus the

LTꢁ4633 Therꢂal Considerations and Output Current

Derating

The power loss curves at 5V input, 8V input, and 12V

input are in Figures 7 to 9. These power loss curves can

be used in coordination with the load current derating

curves in Figures 10 to 15 for calculating an approximate

θ

JA

thermal resistance for the LTM4633 with various heat

sinking and airflow conditions. The power loss curves

are taken at room temperature, and are increased with a

multiplicative factor of 1.4 at 125°C junction. This factor

comes from the fact that the power loss of the regulator

increases about 50% from 25°C to 150°C, thus a 50%

spread over 125°C delta equates to ~0.4%/°C power loss

increase. A 125°C maximum junction minus 25°C room

temperature equates to a 100°C increase. This 100°C

increase multiplied by 0.4%/°C equals a 40% power loss

increase at the 125°C junction, thus the 1.4 multiplier.

85°C ambient to calculate θ thermal resistance. If the

JA

The derating curves are plotted with the output current

starting at 30A and the ambient temperature at 40°C.

The 30A come from each of the three channels operating

at 10A each. This simplifies the loading for this thermal

testing. The output voltages are 1.0V and 1.8V when all

three channels are loaded together in parallel. Channel 1

and Channel 2 are designed to operate with outputs up

to 1.8V. Two additional derating curves are shown with

Channel 1 and Channel 2 operating at 1.8V at 10A each

for a total of 20A while Channel 3 is at 5V with 10A load

current derated over ambient temperature. This is done

to look at some of the different output power conditions

to correlate thermal resistance numbers that can be used

for derating the LTM4633 power module with different

output power requirements. The power loss curve values

85°C ambient temperature is subtracted from the 125°C

junction temperature, then the difference of 40°C divided

by 5.88W equals a 6.8°C/W θ thermal resistance. Table

JA

2 specifies a 6°C/W value which is very close. Tables 2 to

4 provide equivalent thermal resistances for 1.0V, 1.8V,

and combination 1.8V and 5V outputs with and without air

flow and heat sinking. The derived thermal resistances in

Tables 2 and 4 for the various conditions can be multiplied

by the calculated power loss as a function of the 125°C

maximum junction temperature to determine if the tem-

perature rise plus ambient is below the 125°C maximum

junction temperature. Thermal or infrared imaging should

be performed to validate the calculated results. Room

temperature power loss can be derived from the power

4633f

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0.8

0.7

0.6

0.5

0.4

0.3

loss curves in Figures 8 to 10 and adjusted with the 1.4

multiplier. The printed circuit board is a 1.6mm thick four

layer board with two ounce copper for the two outer layers

and one ounce copper for the two inner layers. The PCB

dimensions are 95mm x 76mm. The BGA heat sinks are

listed below Table 4.

I

= 100µA

D

Teꢂperature ꢁonitoring (TEꢁP1 and TEꢁP2)

A diode connected PNP transistor is used for the TEMP

monitor function by monitoring its voltage over tempera-

ture. The temperature dependence of this diode can be

understood in the equation:

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

4633 F04

Figure 4. TEꢁP Pin Diode Voltage vs Teꢂperature

 

I_D

D= nV_Tln

 

I

 

S

where V is the thermal voltage (kT/q), and n, the ideality

T

factor is 1 for the two diode connected PNPs being used

in the LTM4633. Since I has an exponential temperature

D

dependence that can be understood from the typical em-

pirical equation for I :

S













–V_GO

V_T

I_S= I_Oexp

whereI issomeprocessandgeometry-dependentcurrent

O

(I is typically around 20 orders of magnitude larger than

O

I at room temperature, so I is much larger than typical

S

O

values of I ), and V is the band gap voltage of 1.2V

D

G0

extrapolated to absolute zero of –273°C Kelvin. Figure 4

shows a plot of the diode temperature characteristic of

the diode connected PNP transistor biased with a 100ua

current source. This plot would extend to the left back to

1.2V at –273°C Kelvin. This curve is stop at –55°C due to

the test system limits.

Figure 5. Therꢂal Plot for 12V Input to 1.8V at 10A Output 1,

1.8V at 10A Output 2, and 5V at 8A Output 3 with 200LFꢁ of

Airflow

The expression shows that the junction voltage of the PNP

connected diode decreases linearly if I were constant

O

from a value V of 1.2V at absolute zero to a decreasing

G0

If we take the I equation and substitute into the V equa-

S

D

value with increased temperature.

tion, then we get:













 kT

10

kT

q

V_D= V_GO–

ln

, V_T=









q

I

D

4633f

20

For more information www.linear.com/LTM4633

LTM4633

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If we take this equation an differentiate it with respect

temperature T, then:

the unit in case of a catastrophic failure. An inline circuit

breaker function can also be used instead of a fuse.

dV_D

dt

V_GO– V_D

T

The fuse or circuit breaker should be selected to limit the

current to the regulator during overvoltage in case of an

internaltopMOSFETfault. IftheinternaltopMOSFETfails,

then turning it off will not resolve the overvoltage, thus

the internal bottomMOSFET willturn on indefinitely trying

to protect the load. Under this fault condition, the input

voltage will source very large currents to ground through

the failed internal top MOSFET and enabled internal bot-

tom MOSFET. This can cause excessive heat and board

damage depending on how much power the input voltage

can deliver to this system. A fuse or circuit breaker can

be used as a secondary fault protector in this situation.

= –

This dVD/dT change as a function of temperature is the

typical ~–2.0mV/°C. This equation is simplified for the

first order derivation.

SolvingforT,T=–(V –V )/dV providethetemperature.

G0

D

1st Example: Figure 4 for 27°C, or 300°C Kelvin the diode

voltage is 0.598V, thus, 300°C = –(1200mV – 598mV)/

–2.0 mV/°C)

2nd Example: Figure 4 for 75°C, or 350°C Kelvin the diode

voltage is 0.50V, thus, 350°C = –(1200mV – 500mV)/

–2.0mV/°C)

Layout Checklist/Exaꢂple

The high integration of LTM4633 makes the PCB board

layoutverysimpleandeasy.However,tooptimizeitselectri-

cal and thermal performance, some layout considerations

are still necessary.

Converting the Kelvin scale to Celsius is simply taking the

Kelvin temp and subtracting –273°C Kelvin from it.

A typical forward voltage is measured and placed in the

electrical characteristics section of the data sheet, and

Figure 4 is the plot of this forward voltage. Measure this

forward voltage at 27°C to establish a reference point.

Then use the above expression while measuring the

forward voltage over temperature will provide a general

temperature monitor.

Use large PCB copper areas for high current paths, in-

cluding V , GND, V

, V

, and V . It helps to

OUT3

IN

OUT1 OUT2

minimize the PCB conduction loss and thermal stress.

Place high frequency ceramic input and output capacitors

next to the V , GND and the V

pins to minimize high

IN

OUT

frequency noise.

The diode connected PNP transistor at the TEMP pins can

beusedtomonitortheinternaltemperatureoftheLTM4633.

A general temperature monitor can be implemented by

Place a dedicated powerground layerunderneaththe unit.

To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection be-

tween top layer and other power layers.

connecting a resistor between TEMP and V to set the

IN

current to 100µA, and then monitoring the diode voltage

drop with temperature. See Figure 19 for an example.

Donotputviasdirectlyonthepads,unlesstheyarecapped

or plated over. Use a separated SGND ground copper area

for components connected to signal pins. Connect the

SGND to GND underneath the unit. Bring out test points

on the signal pins for monitoring. Figure 6 gives a good

example of the recommended layout.

Safety Considerations

The LTM4633 module does not provide galvanic isolation

from V to any of the three V s. There is no internal

IN

OUT

fuse. If required, a slow blow fuse with a rating higher

than the maximum input current can be used to protect

4633f

21

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FARSIDE COMPONENTS

FB1 FB2 FB3

R

, R , R

CONTROL

GND

R

FB1

FB2

FB3

M

L

C

INTVCC

GND

C

IN3

K

J

FARSIDE COMPONENTS

IN1 IN2

IN1

C

IN2

C

, C

H

C

V

G

F

IN3

GND

C

OUT6

C

OUT4

FARSIDE COMPONENTS

E

C

, C

C

OUT4 OUT5, OUT6

GND

D

C

B

A

C

OUT1

OUT3

V

OUT3

V

OUT1

1

2

3

4

5

6

7

8

9

10 11 12

“A1” INDICATOR

4633 F06

V

GND

V

GND

V

OUT1

OUT3

OUT2

LTM4633Y BGA TOP VIEW

Figure 6. Recoꢂꢂended PCB Layout

4633f

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3.0

2.5

2.0

1.5

1.0

0.5

0

3.0

2.5

2.0

1.5

1.0

0.5

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5V TO 1V

8V TO 1V

12V TO 1V

5V TO 1.2V

5V TO 1.5V

5V TO 1.8V

5V TO 2.5V

5V TO 3.3V

8V TO 1.2V

8V TO 1.5V

8V TO 1.8V

8V TO 2.5V

8V TO 3.3V

8V TO 5V

12V TO 1.2V

12V TO 1.5V

12V TO 1.8V

12V TO 2.5V

12V TO 3.3V

12V TO 5V

5

6

5

6

5

6

0

1

2

3

4

7

8

9

10

0

1

2

3

4

7

8

9

10

0

1

2

3

4

7

8

9

10

LOAD CURRENT (A)

4633 F07

4633 F08

4633 F09

Figure 7. 5V Input Power Loss

Figure 8. 8V Input Power Loss

Figure 9. 12V Input Power Loss

35

30

35

30

35

30

25

20

15

10

5

20

15

10

5

20

15

10

5

400LFM

200LFM

0LFM

400LFM

200LFM

0LFM

400LFM

200LFM

0LFM

0

50 60

120

50 60

120

50 60

120

40

70 80 90 100 110

TEMPERATURE (°C)

40

70 80 90 100 110

TEMPERATURE (°C)

40

70 80 90 100 110

TEMPERATURE (°C)

4633 F10

4633 F11

4633 F12

Figure 10. 12V_IN, 1V_OUT, No Heat

Sink, All Channels at 10A Each

Figure 11. 12V_IN, 1V_OUT, With Heat

Sink, All Channels at 10A Each

Figure 12. 12V_IN, 1.8V_OUT, No Heat

Sink, All Channels at 10A Each

35

30

12

10

8

12

10

8

400LFM

200LFM

0LFM

400LFM

200LFM

0LFM

25

20

15

10

5

6

4

400LFM

200LFM

0LFM

2

0

90 100

50 60

120

40 50 60 70 80

110 120

40

70 80 90 100 110

TEMPERATURE (°C)

90 100

AMBIENT TEMPERATURE (°C)

40 50 60 70 80

110 120

AMBIENT TEMPERATURE (°C)

4633 F13

4633 F15

4633 F14

Figure 13. 12V_IN, 1.8V_OUT, With Heat

Sink, All Channels at 10A Each

Figure 14. 12V_IN, 1.8V_OUTat 20A,

5V_OUTDerating, No Heat Sink

Figure 15. 12V_IN, 1.8V_OUTat 20A,

5V_OUTDerating, with Heat Sink

4633f

23

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Table 2. 1.0V Output

DERATING CURVE

V

(V)

POWER LOSS CURVE

Figure 7 to 9

AIR FLOW (LFꢁ)

HEAT SINK

None

θ

(°C/W)

IN

JA

Figures 10

12

0

7.5

6

Figures 10

12

Figure 7 to 9

200

400

0

None

Figures 10

Figure 7 to 9

None

5

Figures 11

Figure 7 to 9

BGA Heat Sink

6

Figures 11

Figure 7 to 9

200

400

4.75

4.0

Figures 11

Figure 7 to 9

Table 3. 1.8V Output

DERATING CURVE

Figures 12

V

IN

(V)

POWER LOSS CURVE

Figure 7 to 9

AIR FLOW (LFꢁ)

HEAT SINK

None

(°C/W)

JA

12

0

7.5

6

Figures 12

Figure 7 to 9

200

400

0

None

Figures 12

Figure 7 to 9

None

5

Figures 13

Figure 7 to 9

BGA Heat Sink

6

Figures 13

Figure 7 to 9

200

400

4.75

4.0

Figures 13

Figure 7 to 9

Table 4. 5V Output, 1.8V Output at 20A on Ch1 and Ch2

DERATING CURVE

V

IN

(V)

POWER LOSS CURVE

AIR FLOW (LFꢁ)

HEAT SINK

None

(°C/W)

JA

Figures 14

12

Figure 7 to 9

0

7.5

6

Figures 14

12

Figure 7 to 9

200

400

0

None

Figures 14

Figure 7 to 9

None

5

Figures 15

Figure 7 to 9

BGA Heat Sink

6

Figures 15

Figure 7 to 9

200

400

4.75

4.0

Figures 15

Figure 7 to 9

Heat Sink ꢁanufacturer Part Nuꢂber Website

Aavid Thermalloy

Cool Innovations

375424B00034G

4-050503P to 4-050508P

www.aavid.com

www.coolinnovations.com

4633f

24

For more information www.linear.com/LTM4633

LTM4633

applicaTions inForMaTion

Table 5. Output Voltage Response Versus Coꢂponent ꢁatrix (Refer to Figure 16) 0 to 5A Load Step Typical ꢁeasured Values

C

CERAꢁIC

C

BULK

C BULK

IN

PART

OUT1

OUT2

VENDORS

VALUE

PART NUꢁBER

VENDORS

VALUE

PART NUꢁBER

ESR VENDORS

9mΩ Sanyo

9mΩ

VALUE

NUꢁBER

TDK

100µF 6.3V C4532X5R0J107MZ Sanyo POSCAP 470µF 2.5V 2R5TPD470M5

100µF 6.3V GRM32ER60J107M Sanyo POSCAP 470µF 6.3V 6TPD470M

100µF 6.3V 18126D107MAT

56µF 25V

25SVP56M

Murata

AVX

PEAK-TO-PEAK

C

OUT2

DEVIATION AT 7A ~RECOVERY LOAD

IN

OUT1

V

(CERAꢁIC) (BULK)* (CERAꢁIC) (BULK)

C

V

DROOP

39mV

LOAD STEP

TIꢁE

100µs

STEP

5A/µs

R

FB

FREQ

OUT

FF

IN

1V

56µF

470µF 220pF 5V, 12V

220µF 220pF 5V, 12V

470µF 220pF 5V, 12V

220µF 220pF 5V, 12V

470µF 220pF 5V, 12V

220µF 220pF 5V, 12V

220µF 100pF 5V, 12V

80mV

242kΩ

121kΩ

69.8kΩ

48.7kΩ

28.7kΩ

19.1kΩ

11.5kΩ

700kHz

22µF × 3

100µF × 2

100µF × 3

100µF × 2

100µF × 3

100µF × 2

100µF × 3

100µF × 2

100uF × 4

100µF

1V

38mV

78mV

1.2V

1.5V

1.8V

2.5V

3.3V

5V

40mV

90mV

43mV

88mV

50mV

100mV

120mV

130mV

240mV

300mV

320mV

400mV

63mV

65mV

None

100pF 5V, 12V

67mV

220µF 220pF 5V, 12V

121mV

120mV

140mV

180mV

220mV

None

100pF 5V, 12V

47pF 5V, 12V

100µF × 2

100µF

100pF

330pF

12V

100µF × 2

100µF × 3

5V

*Bulk capacitance is optional if V has very low input impedance.

IN

4633f

25

For more information www.linear.com/LTM4633

LTM4633

Typical applicaTions

12V INPUT

C

22µF

16V

C

22µF

16V

C

22µF

16V

C

22µF

16V

IN4

IN1

IN2

IN3

4.7µF

6.3V

V

IN1

SW1

V

SW2

V

IN3

SW3 INTV EXTV

CC CC

IN2

CNTL_PWR

MODE/PLLIN

RUN1

FREQ/PLLLPF

COMP1

10k

COMP2

RUN2

COMP3

13.3k

LTM4633

RUN3

PGOOD12

PGOOD3

TEMP1

TK/SS1

TK/SS2

TK/SS3

TEMP2

C

SS1

SS2

SS3

0.1µF

V

FB3

GND SGND

0.1µF

OUT1

FB1

OUT2

FB2

OUT3

4633 F16

V

FB1

V

FB2

V

FB3

R

FB3

19.1k

FB1

FB2

FOR C , R , COMP AND C

OUT FB

69.8k

121k

FF

C

OUT1

OUT4

SEE TABLE 5

100µF

100pF

3.3V

1.5V

C

1.2V

C

OUT7

100µF

V

OUT2

OUT5

FB3

100µF

V

FB1

C

220pF

OUT3

OUT6

OUT8

470µF

220pF 470µF

100µF

V

FB2

Figure 16. LTꢁ4633 Typical 12V Input to 1.5V at 10A, 1.2V at 10A, 3.3V at 10A

4633f

26

For more information www.linear.com/LTM4633

LTM4633

Typical applicaTions

12V INPUT

C

22µF

16V

C

22µF

16V

C

22µF

16V

IN1

IN2

IN3

5V INPUT

C

22µF

6.3V

C

22µF

6.3V

C

22µF

6.3V

4.7µF

6.3V

IN4

IN5

IN6

3.3V INPUT

C

22µF

6.3V

C

22µF

6.3V

C

22µF

6.3V

IN7

IN8

IN9

V

IN1

SW1

V

SW2

V

IN3

SW3 INTV EXTV

CC CC

IN2

CNTL_PWR

MODE/PLLIN

RUN1

FREQ/PLLLPF

COMP1

10k

COMP2

5V INPUT

RUN2

COMP3

3.3V INPUT

38.3k

LTM4633

RUN3

PGOOD12

PGOOD3

TEMP1

TK/SS1

TK/SS2

TK/SS3

C

TEMP2

C

SS1

SS2

SS3

0.1µF

V

OUT1

V

GND SGND

FB1

OUT2

FB2

OUT3

FB3

4633 F17

V

FB1

V

FB2

V

FB3

R

FB3

11.5k

FB1

FB2

243k

121k

C

OUT1

OUT4

100µF

100pF

5V

1.0V

C

1.2V

C

OUT7

100µF

V

OUT2

OUT5

FB3

100µF

V

FB1

C

220pF

OUT3

OUT6

OUT8

470µF

220pF 470µF

100µF

V

FB2

Figure 17. LTꢁ4633 Triple Input and Triple Output (1.0V, 1.2V and 5V) at 10A

4633f

27

For more information www.linear.com/LTM4633

LTM4633

Typical applicaTions

2.5V INPUT

C

22µF

6.3V

C

22µF

6.3V

C

22µF

6.3V

IN5

IN6

IN7

3.3V INPUT

C

22µF

6.3V

C

22µF

6.3V

C

22µF

6.3V

C

22µF

6.3V

IN4

IN3

IN2

IN1

50k

4.7µF

V

IN1

SW1

V

SW2

V

IN3

SW3 INTV EXTV

CC CC

IN2

19.6k

5V

BIAS

CNTL_PWR

FREQ/PLLLPF

COMP1

MODE/PLLIN

10k

COMP2

RUN1

RUN2

COMP3

LTM4633

RUN3

PGOOD12

PGOOD3

TEMP1

RUN3

TK/SS1

TK/SS2

TK/SS3

TEMP2

C

SS3

SS1

V

FB3

GND SGND

0.22µF

0.1µF

OUT1

FB1

OUT2

C

FB2

OUT3

4633 F18

V

FB3

FB1

R

FB3

121k

FB1

121k

C

OUT

, SEE TABLE 5

C

R

= (60.4k/2)/((V /0.8) – 1)

OUT

OUT1

100µF

OUT4

100µF

FB1

C

OUT7

220pF

1.2V

V

FB3

C

OUT2

OUT5

OUT8

330pF

100µF

1V

V

FB1

C

OUT9

470µF

OUT3

OUT6

470µF

1V AT 20A

Figure 18. 3.3V Input to 1V at 20A, and 2.5V to 1.2V at 10A

3.3V_IN, 1V_OUTEfficiency

92

90

88

86

84

82

80

2

8

14

20

LOAD CURRENT (A)

4633 F22b

4633f

28

For more information www.linear.com/LTM4633

LTM4633

Typical applicaTions

4.7V TO 5.5V

C

22µF

6.3V

C

22µF

6.3V

C

22µF

6.3V

IN3

IN2

IN1

4.7µF

6.3V

V

IN1

SW1

V

IN2

SW2

V

SW3 INTV EXTV

CC CC

IN3

CNTL_PWR

MODE/PLLIN

RUN1

FREQ/PLLLPF

COMP1

10k

COMP2

2.5V

6.04k

RUN2

COMP3

LTM4633

6.04k

RUN3

PGOOD12

PGOOD3

TEMP1

TK/SS1

TK/SS2

TK/SS3

TEMP2

24.3k

4.87k

C

SS3

V

IN

V

GND SGND

0.22µF

R =

T

OUT1

FB1

OUT2

FB2

OUT3

FB3

V

IN

100µA

V

FB1

V

FB3

FB2

R

FB3

28.7k

T

FB1

FB2

REDUCED TRACKING FEEDBACK

DIVIDER BY A FACTOR OF 10 TO

REDUCE TK/SS CURRENT ERROR

242k

48.7k

C

OUT2

100µF

C

OUT1

OUT3

2.5V

A/D

100µF

C

OUT4

OUT6

OUT7

4633 F19

1V

1.8V

100µF

100pF

V

FB1

FB3

220pF

C

OUT8

OUT5

470µF

220pF 470µF

V

FB2

Figure 19. 5V Input, 1V, 1.8V and 2.5V at 10A with Tracking

4633f

29

For more information www.linear.com/LTM4633

LTM4633

package DescripTion

LTꢁ4633 Coꢂponent BGA Pinout

PIN ID FUNCTION PIN ID FUNCTION

PIN ID FUNCTION

PIN ID

B1

FUNCTION

PIN ID

E1

FUNCTION

GND

PIN ID FUNCTION

A1

A2

V

C1

C2

V

OUT3

V

OUT3

V

OUT3

V

OUT3

D1

D2

GND

F1

F2

V

OUT3

OUT2

OUT1

IN3

B2

E2

GND

A3

B3

C3

D3

E3

GND

F3

SW3

GND

A4

GND

B4

C4

D4

E4

GND

F4

A5

V

B5

C5

TEMP2

D5

E5

GND

F5

V

OUT2

IN2

A6

V

B6

C6

V

OUT2

V

OUT2

V

OUT2

D6

E6

GND

F6

A7

B7

C7

D7

E7

GND

F7

SW2

GND

A8

GND

B8

C8

D8

E8

GND

F8

A9

B9

C9

TEMP1

D9

E9

GND

F9

V

IN1

A10

A11

A12

V

B10

B11

B12

C10

C11

C12

V

OUT1

V

OUT1

V

OUT1

D10

D11

D12

E10

E11

E12

GND

F10

F11

F12

OUT1

V

GND

SW1

GND

PIN ID FUNCTION

PIN ID

H1

FUNCTION

PIN ID

J1

FUNCTION

GND

PIN ID FUNCTION

PIN ID

L1

FUNCTION

GND

PIN ID FUNCTION

G1

G2

V

IN3

V

IN3

V

IN3

V

IN3

K1

K2

GND

M1

M2

GND

H2

J2

GND

L2

GND

PGOOD12

PGOOD3

COMP1

G3

GND

H3

GND

J3

GND

K3

GND

L3

EXTV

M3

CC

G4

H4

J4

GND

K4

COMP3

L4

COMP2

M4

G5

V

H5

V

J5

GND

K5

V

L5

V

M5

V

FB1

IN2

FB3

FB2

G6

H6

J6

CNTL_PWR

GND

K6

SGND

GND

L6

SGND

M6

GND

G7

GND

H7

GND

J7

K7

L7

M7

G8

H8

J8

INTV

K8

L8

FREQ/PLLLPF

MODE/PLLIN

RUN1

M8

GND

CC

G9

V

IN1

V

IN1

H9

V

IN1

V

IN1

J9

GND

K9

GND

L9

M9

TK/SS1

TK/SS2

TK/SS3

GND

G10

G11

G12

H10

H11

H12

J10

J11

J12

K10

K11

K12

GND

L10

L11

L12

M10

M11

M12

GND

RUN3

GND

RUN2

GND

package phoTo

4633f

30

For more information www.linear.com/LTM4633

LTM4633

package DescripTion

Please refer to http://www.linear.coꢂ/designtools/packaging/ for the ꢂost recent package drawings.

Z

/ / b b b

Z

6 . 9 8 2 0

2 . 7 1 2 0

4 . 4 4 2 0

3 . 1 7 2 0

1 . 9 0 2 0

0 . 6 3 2 0

0 . 0 0 0 0

0 . 6 3 2 0

1 . 9 0 2 0

3 . 1 7 2 0

4 . 4 4 2 0

2 . 7 1 2 0

6 . 9 8 2 0

a a a

Z

4633f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

For more information www.linear.com/LTM4633

LTM4633

Typical applicaTion

LTꢁ4633 Typical 12V Input to 0.9V at 10A, 1.0V at 10A, 1.2V at 10A with 0.9V and 1.0V Tracking 1.2V

12V INPUT

C

22µF

16V

C

22µF

16V

C

22µF

16V

C

22µF

16V

IN4

IN1

IN2

IN3

4.7µF

6.3V

30k

10k

FREQ = 500kHz

V

SW1

V

SW2

V

IN3

SW3 INTV EXTV

CC CC

IN1

IN2

CNTL_PWR

MODE/PLLIN

RUN1

FREQ/PLLLPF

COMP1

COMP2

10k

RUN2

COMP3

13.3k

LTM4633

RUN3

PGOOD12

PGOOD3

TEMP1

TK/SS1

6.04k

TK/SS2

TK/SS3

48.7k

24.3k

0.1µF

TEMP2

V

FB3

GND SGND

OUT1

FB1

OUT2

FB2

OUT3

4633 F20

6.04k

V

FB1

V

FB2

V

FB3

1.2V

R

FB1

487k

R

FB2

243k

R

FB3

121k

FOR C , R , COMP AND C

OUT FB

FF

C

OUT1

OUT4

SEE TABLE 5

100µF

100pF

1.2V

0.9V

C

1.0V

C

V

OUT2

OUT5

OUT7

FB3

100µF

V

FB1

C

220pF

OUT6

OUT8

*

C

220pF 470µF

470µF

OUT3

*1000µF, 2.5V

POSCAP (2R5TPE1000MF)

V

FB2

Design resources

SUBJECT

DESCRIPTION

µModule Design and Manufacturing Resources

Design:

Manufacturing:

• Selector Guides

• Quick Start Guide

• Demo Boards and Gerber Files

• Free Simulation Tools

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

TechClip Videos

Quick videos detailing how to bench test electrical and thermal performance of µModule products.

relaTeD parTs

PART NUꢁBER DESCRIPTION

COꢁꢁENTS

LTM4630

Dual 15V , 18A or Single 36A Step-Down µModule

4.5V ≤ V ≤ 15V, 0.6V ≤ V

≤ 1.8V, PLL Input, Remote Sense Amplifier,

OUT

IN

Regulator with V

Up to 1.8V

V

Tracking, PGOOD, CLKOUT, Internal Temperature Monitor,

OUT

16mm × 16mm × 4.41mm LGA

LTM4624

LTM8028

14V , 4A Step-Down µModule Regulator in Tiny

4V ≤ V ≤ 14V, 0.6V ≤ V

≤ 5.5V, V

Tracking, PGOOD, Light Load Mode,

OUT

IN

OUT

2

6.25mm × 6.25mm × 5.01mm BGA

Complete Solution in 1cm (Single-Sided PCB)

36V , UltraFast™, Low Output Noise 5A µModule

6V ≤ V ≤ 36V, 0.8V ≤ V

≤ 1.8V Set Via 3-Pin Three-State Interface,

IN

OUT

Regulator

<1mV V

Ripple, 10% Accurate Current Limit, PGOOD,

OUT

15mm × 15mm × 4.9mm BGA

LTM4637

20V , 20A DC/DC µModule Step-Down Regulator

4.5V ≤ V ≤ 20V, 0.6V ≤ V

≤ 5.5V, PLL Input, V

Tracking,

IN

OUT

Remote Sense Amplifier, PGOOD, 15mm × 15mm × 4.32mm LGA

4633f

LT 1013 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

For more information www.linear.com/LTM4633

●

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4633

 LINEAR TECHNOLOGY CORPORATION 2013


型号：	LTM4633_15
厂家：	Linear
描述：	Triple 10A Step-Down DC/DC Module Regulator
文件：	总32页 (文件大小：519K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4633_15 [Linear]

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