LTM4634EY#PBF [Linear]
LTM4634 - Triple Output 5A/5A/4A Step-Down DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 144; Temperature Range: -40°C to 85°C;
| 型号： | LTM4634EY#PBF |
| 厂家： | 
Linear |
| 描述： | LTM4634 - Triple Output 5A/5A/4A Step-Down DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 144; Temperature Range: -40°C to 85°C |
| 文件： | 总32页 (文件大小：737K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4634
Triple Output 5A/5A/4A
Step-Down DC/DC
®
µModule Regulator
FeaTures
DescripTion
The LTM®4634 integrates three complete 5A/5A/4A high
efficiencyswitchingmodeDC/DCconvertersintoonesmall
package.Switchingcontrollers,powerFETs,inductors,and
mostsupportcomponentsareincluded.Operatingoveran
inputvoltagerangeof4.75Vto28V, theLTM4634provides
n
Three Independent High Efficiency Regulator
Channels
OUT1,2
n
I
= 5A, I
= 4A
OUT3
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Input Voltage Range: 4.75V to 28V
Independent V for Each Channel
IN
V
V
Voltage Range: 0.8V to 5.5V
three independent output voltages. V
adjustable from 0.8V to 5.5V, while V
from 0.8V to 13.5V. Each output voltage is set by a single
external resistor.
and V
OUT3
are
OUT1,2
OUT1
OUT2
is adjustable
Voltage Range: 0.8V to 13.5V
OUT3
1.5ꢀ ꢁaꢂiꢃuꢃ Total DC Output Error
Current ꢁode Control/Fast Transient Response
Frequency Synchronization
Highswitchingfrequencyandacurrentmodearchitecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequency synchronization, multiphase parallel opera-
tion, soft-start and output voltage tracking for supply rail
sequencing.
Output Overvoltage and Overcurrent Protection
PolyPhase® Operation with Current Sharing
General Purpose Teꢃperature ꢁonitors
Soft-Start/Voltage Tracking
Power Good Monitors
SnPb or RoHS Compliant Finish
15mm × 15mm × 5.01mm BGA Package
Fault protection features include overvoltage protection,
overcurrent protection and temperature monitoring. The
power module is offered in a space saving, thermally
enhanced 15mm × 15mm × 5.01mm BGA package. The
LTM4634 is available with SnPb (BGA) or RoHS compliant
terminal finish.
applicaTions
n
Telecom, Networking and Industrial Equipment
High Density Point of Load Voltage Regulation
n
L, LT, LTC, LTM, µModule, PolyPhase, Burst Mode, Linear Technology and the Linear logo
are registered trademarks and PowerPath, LTpowerCAD and UltraFast are trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194,
6177787, 6304066, 6580258 and 8163643. Other patents pending.
Typical applicaTion
24V Input to 3.3V, 5V and 12V Output Regulator
24V Input Efficiency
100
95
90
85
80
75
70
65
60
5V
24V
IN
4.7µF
6.3V
2Ω
40k
10k
10k
V
V
V
IN3
EXTV
INTV
FREQ/PLLLPF
CC
IN1
IN2
CC
CNTL_PWR
RUN1
PGOOD12
PGOOD3
3.3V
5V
V
V
V
OUT1
RUN2
19.1k
1µF
V
RUN3
FB1
LTM4634
TK/SS1
TK/SS2
TK/SS3
OUT2
11.5k
4.32k
V
= 5V
EXTVCC
V
FB2
24V to 3.3V EFF (750kHz) CH1
24V to 5V EFF (750kHz) CH2
24V to 12V EFF (750kHz) CH3
12V
OUT3
V
FB3
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
MODE/PLLIN GND SGND
LOAD CURRENT (A)
4634 TA01a
4634 TA01b
4634f
1
For more information www.linear.com/LTM4634
LTM4634
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
CNTL_PWR ............................................... –0.3V to 30V
FREQ/PLLLPF
TKSS2
TK/SS1 TK/SS3
V
V
V
V
, V , V ........................................... –0.3V to 30V
OUT1 OUT2
COMP1
COMP2
FB1 GND
IN1 IN2 IN3
M
L
PGOOD12
PGOOD3
, V
........................................... –0.3V to 5.75V
MODE/PLLIN
RUN1
RUN2
RUN3
V
FB2
......................................................... –0.3V to 14V
OUT3
EXTV
CC
V
FB3
SGND
COMP3
K
J
Switch Voltage (SW1, SW2 and SW3) ...........–1V to 30V
GND
GND
MODE/PLLIN, TK/SS1, TK/SS2, TK/SS3,
INTV
CC
CNTL_PWR
H
G
F
FREQ/PLLLPF .......................................–0.3V to INTV
CC
V
IN3
V
V
IN1
GND
GND
IN2
COMP1, COMP2, COMP3, V , V , V
FB1 FB2 FB3
(Note 3).................................................–0.3V to INTV
CC
SW3
SW1
SW2
E
RUN1, RUN2, RUN3, INTV , EXTV ,
CC
CC
GND
D
C
B
A
PGOOD12, PGOOD3..................................... –0.3V to 6V
TEMP1, TEMP2......................................... –0.3V to 0.8V
V
OUT2
TEMP2
TEMP1
INTV Peak Output Current................................100mA
CC
V
V
OUT1
OUT3
Operating Junction Temperature Range
1
2
3
4
5
6
7
8
9
10 11 12
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Body Temperature................. 245°C
GND
GND
BGA PACKAGE 144 LEAD (15mm × 15mm × 5.01mm)
= 125°C, θ = 7.5°C/W, θ = 4°C/W, θ = 5°C/W
T
JMAX
JA
JCbottom
JCtop
θ
DERIVED FROM 95mm × 76mm PCB WITH 4-LAYER, WEIGHT = 3.2g
JA
θ VALUES DETERMINED PER JESD51-12
orDer inForMaTion
PART ꢁARKING*
PACKAGE
TYPE
ꢁSL
TEꢁPERATURE RANGE
(See Note 2)
PART NUꢁBER
LTM4634EY#PBF
LTM4634IY#PBF
LTM4634IY
PAD OR BALL FINISH
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
DEVICE
FINISH CODE
RATING
LTM4634Y
LTM4634Y
LTM4634Y
e1
e1
e0
BGA
BGA
BGA
4
4
4
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
• Terminal Finish Part Markings:
www.linear.com/leadfree
4634f
2
For more information www.linear.com/LTM4634
LTM4634
elecTrical characTerisTics The ldenotes the specifications which apply over the specified internal
operating teꢃperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 24V, per the typical application for each regulator
channel.
SYꢁBOL
PARAꢁETER
CONDITIONS
ꢁIN
TYP
ꢁAX UNITS
l
V
V
Input DC Voltage
CNTL_PWR Powered Tied to Input Supply
4.75
28
V
IN
l
l
Output Voltage Range V
Output Voltage Range V
, V
OUT3
0.8
0.8
5.5
13.5
V
V
OUT(RANGE)
OUT1 OUT2
l
V
Output Voltage, Total Variation with Line
and Load, V , V , V
4.925
5.0
5.075
V
C
= 22µF × 3, C
= 100µF Ceramic × 3,
OUT(DC)
IN
FB
OUT
R
= 11.5k, MODE/PLLIN = 0V, V = 5.5V to 28V,
IN
OUT1 OUT2 OUT3
I
= 0A to 5A, I
= 0A to 4A (Note 4)
OUT1,2
OUT3
Input Specifications
V
V
RUN1, RUN2, RUN3 Pin ON Threshold
RUN Pin Hysteresis
V
Rising
1.15
1.3
1.4
V
RUN
RUN
175
mV
RUN(HYS)
Q(VIN)
I
Input Supply Bias Current Each Channel
V
V
V
= 5V, Burst Mode Operation, I
= 0A
= 0A
= 0A
0.5
1.6
45
mA
mA
mA
µA
OUT
OUT
OUT
OUT
OUT
OUT
= 5V, Pulse-Skipping Mode, I
= 5V, Switching Continuous, I
Shutdown, RUN = 0V, V = 24V
10
IN
I
Input Supply Current Each Channel
V
V
= 12V, EXTV = 5V
I = 5A
OUT1,2
2.21
1.76
A
A
S(VIN)
IN
CC
OUT
= 5V, V
= 5V
OUT1,2
OUT3
I
= 4A
OUT3
Output Specifications (Note 4)
I
Output Continuous Current Range Each
Channel
V
V
= 5V
0
0
5
4
A
A
OUT(DC)
OUT1,2
OUT3
= 5V
l
l
Line Regulation Accuracy per Channel
V
OUT
= V from 5.5V to 28V
0.015 0.02
%/V
∆V
∆V
V
OUT1
IN
OUT(LINE)
I
= 0A, CNTL_PWR Tie to V
IN
V
OUT
Load Regulation Accuracy per Channel
V
= 5V, I
= 0A to 5A
OUT1,2
0.3
0.5
%
OUT
OUT(LOAD)
Ch1, Ch2, I
= 0A to 4A
OUT3
V
OUT
Output Ripple Voltage per Channel
Turn-On Overshoot per Channel
Turn-On Time per Channel
75
50
6
mV
mV
ms
mV
I
= 0A, C
= 100µF Ceramic × 3,
= 5V
OUT(AC)
OUT
OUT
OUT
V
= 24V, V
IN
∆V
OUT(START)
C
= 100µF Ceramic × 3, V
= 5V,
= 5V,
OUT
OUT
OUT
I
= 0A, TK/SS = 0.01µF
t
C
= 100µF Ceramic × 3, V
START
OUT
OUT
OUT
I
= 0A, TK/SS = 0.01µF
V
OUTLS
Peak Deviation for Dynamic Load per
Channel
Load: 0% to 50% to 0% of Full Load,
C
V
200
= 100µF Ceramic × 3,
= 5V Typical Bench Data
OUT
OUT
t
I
Settling Time for Dynamic Load Step per Load: 0% to 50% to 0% of Full Load,
50
8
µs
A
SETTLE
Channel
C
V
= 100µF Ceramic × 3,
OUT
OUT
= 5V Typical Bench Data
Output Current Limit per Channel
V
= 5V
OUT(PK)
OUT
Control Specifications
V
Voltage at V Pin per Channel
I
= 0A, V = 5V
OUT
0.794 0.80 0.806
0.792 0.80 0.808
V
V
FB
FB
OUT
l
l
I
Current at V Pin per Channel
(Note 3)
–10
–50
nA
V
FB
FB
V
Feedback Overvoltage Lockout per
Channel
0.84
1.1
0.86
0.88
OVL
I
Track Pin Soft-Start Pull-Up Current per TK/SS = 0V
Channel
1.5
1.9
µA
TK/SS
t
Minimum On-Time
(Note 3)
90
95
ns
%
ON(MIN)
Max DC
Maximum Duty Cycle
5.5V to 5V at 5A (Note 5)
R
FBHI
Resistor Between V
and V Pins
60.0
60.4
60.8
kΩ
OUT
FB
4634f
3
For more information www.linear.com/LTM4634
LTM4634
elecTrical characTerisTics The ldenotes the specifications which apply over the specified internal
operating teꢃperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 24V, per the typical application for each regulator
channel.
SYꢁBOL
PARAꢁETER
CONDITIONS
ꢁIN
TYP
ꢁAX UNITS
V
PGOOD Trip Level
PGOOD12
PGOOD3
V
With Respect to Set Output
FB
FB
PGOOD
FB
V
V
Ramping Negative
Ramping Positive
–7.5
7.5
%
%
V
PGOOD Voltage Low
I
= 2mA
0.1
0.3
5.2
V
PGL
PGOOD
INTV Linear Regulator
CC
V
V
V
V
V
Internal V Voltage
6V < V < 28V, I = 0mA
4.8
4.5
5
1
V
%
INTVCC
LDOINT
EXTVCC
LDOEXT
LDOHYS
CC
IN
CC
INTV Load Regulation
I
= 0mA to 100mA
CC
CC
Float
MODE/PLLIN
l
EXTV Switchover Voltage
EXTV Ramping Positive
4.7
30
200
V
CC
CC
EXTV Voltage Drop
I
= 20mA, V = 5V
EXTVCC
75
mV
mV
CC
CC
EXTV Hysteresis
CC
Oscillator and Phase-Locked Loop
f
f
SYNC Capture Range
Clock Input Duty Cycle = 50%
250
700
750
825
kHz
kHz
kΩ
V
SYNC
S
Switching Frequency
V
= INTV
750
250
FREQ/PLLLPF
CC
R
MODE/PLLIN Input Resistance
Clock Input Level High
Clock Input Level Low
MODE/PLLIN
V
V
2.0
IH(MODE/PLLIN)
IL(MODE/PLLIN)
0.8
V
Clock Phase
V
OUT2
V
OUT3
V
OUT1
to V
to V
to V
Phase
Phase
Phase
V
= 1.2V (Note 3)
120
120
120
Deg
Deg
Deg
OUT1
OUT2
OUT3
FREQ/PLLLPF
V
Temperature Diode Forward Voltage
Temperature Coefficient
I
= 100µA
TEMP
0.598
–2.0
V
TEMP1,2
TC V
mV/°C
TEMP
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: 100% tested at wafer level.
Note 4: See output current derating curves for different V , V
Note 5: High duty designs need to be validated based on maximum
and T .
IN OUT
A
temperature rise and derating in ambient conditions.
Note 2: The LTM4634 is tested under pulsed load conditions such that
T ≈ T . The LTM4634E is guaranteed to meet performance specifications
J
A
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4634I is guaranteed to meet specifications over the
–40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
4634f
4
For more information www.linear.com/LTM4634
LTM4634
Typical perForMance characTerisTics
5V Input Efficiency (Ch3)
12V Input Efficiency (Ch1 and Ch2)
5V Input Efficiency (Ch1 and Ch2)
100
95
90
85
80
75
70
65
60
55
50
45
40
100
95
90
85
80
75
70
65
60
55
50
45
40
100
95
90
85
80
75
70
65
60
55
50
45
40
V
= 5V
EXTVCC
12V TO 1.0V EFF (250kHz)
12V TO 1.2V EFF (250kHz)
12V TO 1.5V EFF (250kHz)
12V TO 1.8V EFF (250kHz)
12V TO 2.5V EFF (250kHz)
12V TO 3.3V EFF (250kHz)
12V TO 5.0V EFF (250kHz)
5V TO 1.0V EFF (250kHz)
5V TO 1.2V EFF (250kHz)
5V TO 1.5V EFF (250kHz)
5V TO 1.8V EFF (250kHz)
5V TO 2.5V EFF (250kHz)
5V TO 3.3V EFF (250kHz)
5V TO 1.OV EFF (250kHz)
5V TO 1.2V EFF (250kHz)
5V TO 1.5V EFF (250kHz)
5V TO 1.8V EFF (250kHz)
5V TO 2.5V EFF (250kHz)
5V TO 3.3V EFF (250kHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
2.0 2.5
0.5 1.0 1.5
LOAD CURRENT (A)
0
3.0 3.5 4.0
0
0.5 1.0 1.5
3.0 3.5 4.0 4.5
5.0
2.0 2.5
LOAD CURRENT (A)
LOAD CURRENT (A)
4634 G01
4634 G02
4634 G03
12V Input Efficiency (Ch3)
24V Input Efficiency (Ch1 and Ch2)
24V Input Efficiency (Ch3)
100
95
100
95
90
85
80
75
70
65
60
55
50
45
40
100
95
90
90
85
80
75
85
80
75
V
= 5V
EXTVCC
70
65
60
55
50
45
40
70
65
60
55
50
45
40
V
= 5V
V
= 5V
EXTVCC
24 TO 1.0V EFF (250kHz)
24 TO 1.2V EFF (250kHz)
24 TO 1.5V EFF (250kHz)
24 TO 1.8V EFF (300kHz)
24 TO 2.5V EFF (300kHz)
24 TO 3.3V EFF (350kHz)
24 TO 5.0V EFF (500kHz)
24 TO 12V EFF (750kHz)
EXTVCC
12V TO 1.0V EFF (250kHz)
12V TO 1.2V EFF (250kHz)
12V TO 1.5V EFF (250kHz)
12V TO 1.8V EFF (250kHz)
12V TO 2.5V EFF (250kHz)
12V TO 3.3V EFF (250kHz)
12V TO 5.0V EFF (250kHz)
24V TO 1.0V EFF (250kHz)
24V TO 1.2V EFF (250kHz)
24V TO 1.5V EFF (300kHz)
24V TO 1.8V EFF (350kHz)
24V TO 2.5V EFF (350kHz)
24V TO 3.3V EFF (600kHz)
24V TO 5.0V EFF (750kHz)
2.0 2.5
0.5 1.0 1.5
LOAD CURRENT (A)
0
3.0 3.5 4.0
2.0 2.5
0.5 1.0 1.5
LOAD CURRENT (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
3.0 3.5 4.0
LOAD CURRENT (A)
4634 G04
4634 G05
4634 G06
24V Input Continuous, Pulse-
Skipping and Burst ꢁode Operation
24V to 5V Load Step Response
24V to 3.3V Load Step Response
100
95
90
85
80
75
70
65
60
55
50
45
40
OUTPUT
OUTPUT
100mV/DIV
100mV/DIV
LOAD
STEP
1A/DIV
LOAD
STEP
1A/DIV
4634 G08
4634 G09
100µs/DIV
100µs/DIV
0A TO 2.5A, 2.5A/µs LOAD STEP
OUT
0A TO 2.5A, 2.5A/µs LOAD STEP
OUT
C
= 2 × 100µF CERAMIC CAPACITOR
C
= 2 × 100µF CERAMIC CAPACITOR
5.0V
5.0V
5.0V
(750kHz) BURST
(750kHz) PULSE
(750kHz) CONT
OUT
OUT
OUT
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
4634 G07
4634f
5
For more information www.linear.com/LTM4634
LTM4634
Typical perForMance characTerisTics
24V to 12V Load Step Response
12V to 1V Load Step Response
12V to 1.2V Load Step Response
OUTPUT
50mV/DIV
OUTPUT
50mV/DIV
OUTPUT
100mV/DIV
LOAD
STEP
1A/DIV
LOAD
STEP
1A/DIV
LOAD
STEP
1A/DIV
4634 G10
4634 G11
4634 G12
100µs/DIV
100µs/DIV
100µs/DIV
0A TO 2A, 2A/µs LOAD STEP
OUT
0A TO 2.5A, 2.5A/µs LOAD STEP
OUT
0A TO 2.5A, 2.5A/µs LOAD STEP
OUT
C
= 2 × 100µF CERAMIC CAPACITOR
C
= 2 × 100µF CERAMIC CAPACITOR
C
= 2 × 100µF CERAMIC CAPACITOR
AND 100µF 16V 16TQC100MYF POS CAPACITOR
AND 470µF 2V 2TPE470MAJB POS CAPACITOR
AND 470µF 2V 2TPE470MAJB POS CAPACITOR
12V to 1.5V Load Step Response
12V to 1.8V Load Step Response
12V to 2.5V Load Step Response
OUTPUT
50mV/DIV
OUTPUT
50mV/DIV
OUTPUT
50mV/DIV
LOAD
STEP
1A/DIV
LOAD
STEP
1A/DIV
LOAD
STEP
1A/DIV
4634 G13
4634 G14
4634 G15
100µs/DIV
100µs/DIV
100µs/DIV
0A TO 2.5A, 2.5A/µs LOAD STEP
OUT
0A TO 2.5A, 2.5A/µs LOAD STEP
OUT
0A TO 2.5A, 2.5A/µs LOAD STEP
OUT
C
= 2 × 100µF CERAMIC CAPACITOR
C
= 2 × 100µF CERAMIC CAPACITOR
C
= 2 × 100µF CERAMIC CAPACITOR
AND 470µF 2V 2TPE470MAJB POS CAPACITOR
24V to 5V No Load Start-Up
24V to 5V No Load Short
24V to 5V Full Load Start-Up
V
OUT
V
V
OUT
OUT
2V/DIV
1V/DIV
1V/DIV
I
I
I
IN
OUT
OUT
1A/DIV
1A/DIV
1A/DIV
4634 G16
4634 G17
4634 G18
V
V
I
= 24V
= 5V
OUT
20ms/DIV
20ms/DIV
V
V
I
= 24V
= 5V
OUT
20µs/DIV
V
V
I
= 24V
= 5V
OUT
IN
OUT
IN
OUT
IN
OUT
= 0A
= 5A
= 0A
C
= 2 × 100µF X5R 1210
C
= 2 × 100µF X5R 1210
C
= 2 × 100µF X5R 1210
OUT
OUT
OUT
4634f
6
For more information www.linear.com/LTM4634
LTM4634
Typical perForMance characTerisTics
24V to 5V Full Load Short
Start-Up into Pre-Bias
Steady-State Output Ripple
RUN
5V/DIV
V
OUT
V
OUT
RIPPLE
V
OUT1
2V/DIV
10mV/DIV
1V/DIV
SW NODE
5V/DIV
I
SW
10V/DIV
IN
1A/DIV
4634 G19
4634 G20
4634 G21
V
V
I
= 24V
= 5V
OUT
20µs/DIV
20ms/DIV
2µs/DIV
12V TO 3.3V AT 5A LOAD
IN
OUT
PREBIAS 1.5V OUTPUT STARTING AT 0.5V BIAS
12V INPUT
= 5A
C
= 2 × 100µF X5R 1210
OUT
pin FuncTions
PACKAGE ROW AND COLUꢁN LABELING ꢁAY VARY
AꢁONG µꢁodule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
V
,V ,V
(F9-F10,G9-G10,H9-H10);(F5-F6,G5-
IN1 IN2 IN3
G6,H5-H6);(F1-F2,G1-G2,H1-H2): Power Input Pins.
Apply input voltage between these pins and the GND pins.
Recommendplacinginputdecouplingcapacitancedirectly
between the V pins and the GND pins. The V paths
GND (A4, A8-A9, D1- D12, E1-E12, F4, F8, F12, G3-G4,
G7-G8, G11-G12, H3-H4, H7-H8, H11-H12, J1-J5, J7,
J9-J12, K1-K3, K8-K10, K12,L1-L2,L12, ꢁ1, ꢁ6-ꢁ8,
ꢁ12): Ground Pins for Both Input and Output Returns.
All ground pins need to connect with large copper areas
underneath the unit.
IN
IN
can be all combined from one power source, or powered
from independent power sources. See the Applications
Information section.
SW1 (F11), SW2 (F7), SW3 (F3): The internal switch
node for each of the regulator channels for monitoring
the switching waveform. An R-C snubber circuit can be
placed on these pins to ground to eliminate switch node
ringing noise.
V
, V
, V
(A10-A12, B9-B12, and C10-C12);
OUT1 OUT2 OUT3
(A5-A7, B5-B8, C6-C8); (A1-A3, B1-B4, C1-C4): Power
Output Pins. Apply output load between these pins and
the GND pins. Recommend placing output decoupling
capacitance directly between these pins and the GND
pins. See Table 4.
CNTL_PWR (J6): Input Supply to an Internal Bias LDO to
Power the Internal Controller and MOSFET Drivers. The
operating voltage range is 4.75V to 28V under all condi-
TEꢁP1 AND TEꢁP2 (C9, C5): Two Onboard Temperature
Diodes for Monitoring the VBE Junction Voltage Change
with Temperature. Each of these two temperature diode
connected PNP transistors is placed in the middle of
channel 1 and channel 2, and in the middle of channel 2
and channel 3. See the Applications Information section
and an example in Figure 25. Leave floating if not used.
tions. If the voltage at CNTL_PWR is ≤5.8V, the INTV
CC
pin should be tied to CNTL_PWR for optimum efficiency.
If the voltage at CNTL_PWR is >5.8V, leave INTV float-
CC
ing with the recommended decoupling capacitor. To
eliminate power loss in the onboard linear regulator and
improve efficiency connect a 5V supply at EXTV . Ensure
CC
CNTL_PWR > EXTV at all times to avoid reverse polarity
CC
on the internal bias LDO.
4634f
7
For more information www.linear.com/LTM4634
LTM4634
pin FuncTions
INTV (J8): Output of the Internal Bias LDO for Powering
RUN1,RUN2,RUN3(L10,L11,K11):RunControlInputs.
A voltage above 1.3V on any RUN pin turns on that par-
ticular channel. However, forcing any of these RUN pins
below 1.15V causes that channel to shut down. Each of
the RUN pins has an internal 10k resistor to ground. This
resistor can be used with an external pull-up resistor to
the input voltage to set a UVLO for that channel, or simply
to turn on the channel. The RUN pins have a maximum
voltage of 6V. See the Applications Information section.
CC
InternalControlCircuitry.Connecta4.7µFceramiccapaci-
tor to ground for decoupling. If the voltage at CNTL_PWR
is ≤5.8V, tie the INTV pin to CNTL_PWR for optimum
CC
efficiency. If the voltage at CNTL_PWR is >5.8V, leave
INTV floating. See the Applications Information section.
CC
SGND (K6-K7, L6-L7): Signal Ground Connections. The
signal ground connection in the module is separated from
normal power ground (GND) by an internal 2.2Ω resistor.
This allows the designer to connect the signal ground pin
close to GND near the external output capacitors on the
regulatorchannel’soutputs.Theentireinternalsmall-signal
feedback circuitry is referenced to SGND, thus allowing
for better output regulation. See the recommended layout
in the Applications Information section.
PGOOD12, PGOOD3 (ꢁ2, ꢁ3): Output Voltage Power
Good Indicator for V
and V Combined, and V
OUT2 OUT3
OUT1
Separate. The open-drain logic output is pulled to ground
when the output voltage is not within 7.5% of the regula-
tion point.
COꢁP1, COꢁP2, COꢁP3 (ꢁ4, L4, K4): Current Control
Threshold and Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. The LTM4634 regulator channels are all internally
compensatedforproperstability. COMP1andCOMP2can
be tied together for PolyPhase 10A parallel operation. See
the Applications Information section.
EXTV (L3): External Bias Power Input. The internal bias
CC
LDO is bypassed whenever the voltage at EXTV is above
CC
4.7V. Never exceed 6V at this pin and ensure CNTL_PWR >
EXTV atalltimestoavoidreversepolarityontheinternal
CC
bias LDO. Connect a 1µF capacitor to ground when used
otherwise leave floating. Use a 5V bias or 5V output to
power this pin to improve efficiency.
V
, V , V (ꢁ5, L5, K5): The Negative Input of the
FB1 FB2 FB3
FREQ/PLLLPF(L8):FrequencySetandPLLLowpassFilter
Pin. This pin is driven with a DC voltage to set the oper-
ating frequency. The recommended operating frequency
will be supplied in the efficiency graphs for optimal per-
formance. A specific frequency can be chosen as long as
the minimum on-time is not violated, and inductor ripple
current is optimized. When an external clock is used, then
the FREQ/PLLLPF pin must not be connected to any DC
voltage. The pin must be floating and will have the proper
internal compensation for the internal loop filter. See the
Applications Information section.
Error Amplifier for Each of the Three Channels. Internally,
each of these pins is connected to their respective output
with a 60.4k precision resistor. Different output voltages
can be programmed with an additional resistor between
eachindividualV pinandground.InPolyPhaseoperation,
FB
tying the V and V pins together allows for parallel
FB1
FB2
operation up to 10A. See the Applications Information
section for details.
TK/SS1,TK/SS2,TK/SS3(ꢁ9,ꢁ10,ꢁ11):OutputVoltage
TrackingandSoft-StartInputs.Whenoneparticularchannel
is configured to be the master, a capacitor to ground at
this pin sets the ramp rate for the master channel’s output
voltage. When the channel is configured to be the slave,
ꢁODE/PLLIN(L9):ForcedContinuousMode,BurstMode,
or Pulse-Skipping Mode Selection Pin and External Syn-
chronization Input to Phase Detector Pin. Connect this pin
to SGND to force all channels into the continuous mode
the V voltage of the master channel is reproduced by a
FB
resistor divider and applied to this pin. Internal soft-start
currents of 1.5μA are charging the soft-start capacitors.
In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to
be shorted externally.
of operation. Connect to INTV to enable pulse-skipping
CC
mode of operation. Leave floating to enable Burst Mode
operation. A clock on the pin will force the controller into
continuousmodeofoperationandsynchronizetheinternal
oscillator. See the Applications Information section.
4634f
8
For more information www.linear.com/LTM4634
LTM4634
block DiagraM
INTERNAL BLOCK DIAGRAM
MODE/PLLIN
CNTL_PWR
1µF
50V
2Ω
C
4.7µF
50V
V
IN1
FREQ/PLLLPF
24V
INTV
24V
CC
IN1
1µF
INTERNAL
FILTER
GND
SW1
MTOP1
MBOT1
R1
150k
1.5µH
V
OUT1
V
=
V
OUT1
IN(UVLO)
SGND
RUN1
3.3V
5A
(R1 + 10k)1.3V
10k
+
R
RUN1
10k
R
FBHI1
0.1µF
C
OUT1
60.4k
TK/SS1
COMP1
GND
SS
CAP1
V
FB1
SGND
R
V
FB1
19.1k
FB1
INTERNAL
COMP
SGND
LOCATED NEAR POWER STAGES
SGND
SGND
TEMP1
PNP
SGND
INTV
CC
R4
10k
V
IN2
PGOOD12
C
4.7µF
50V
+
IN3
100µF
50V
1µF
GND
SW2
INTV
CC
MTOP2
MBOT2
4.7µF
1.5µH
V
5V
5A
OUT2
V
EXTV
OUT2
CC
5V
+
24V
R
FBHI2
60.4k
0.1µF
C
OUT2
R2
150k
GND
3-CHANNEL
POWER CONTROL
RUN2
R
RUN2
10k
SGND
TK/SS2
SS
CAP2
TEMP2
PNP
INTV
CC
SGND
V
FB2
V
FB2
R5
10k
R
FB2
LOCATED NEAR
POWER STAGES
PGOOD3
COMP2
11.5k
V
SGND
IN3
C
IN5
INTERNAL
COMP
1µF
4.7µF
50V
GND
SW3
OUT3
24V
R3
MTOP3
MBOT3
SGND
3.3µH
V
12V
4A
OUT3
V
150k
RUN3
+
R
FBHI3
60.4k
R
0.1µF
RUN3
10k
C
OUT3
GND
TK/SS3
COMP3
SS
CAP3
V
FB3
SGND
R
V
FB3
FB3
SGND
INTERNAL
COMP
4.32k
SGND
2.2Ω
SGND
SGND
4634 F01
Figure 1. Siꢃplified LTꢁ4634 Block Diagraꢃ
4634f
9
For more information www.linear.com/LTM4634
LTM4634
operaTion
Power ꢁodule Description
is cleared. There are two temperatures monitors in the
LTM4634. TEMP1 monitors the close relative tempera-
ture of channels 1 and 2, and TEMP2 monitors the close
relative temperature of channels 2 and 3. The two diode
connected PNP transistors are grounded in the module
andcanbeusedasgeneralpurposetemperaturemonitors
usingadevicethatisdesignedtomonitorthesingle-ended
connection.
The LTM4634 µModule regulator is a high performance
triple output nonisolated switching mode DC/DC power
supply. It can provide 5A/5A/4A outputs with a few ex-
ternal input and output capacitors. This module provides
precisely regulated output voltages programmable via
external resistors from 0.8V DC to 5.5V DC (V
and
OUT1
). When apply-
V
), and 0.8V DC to 13.5V DC (V
OUT2
OUT3
ing control bias in the range from 4.75V to 5.8V, then
Pulling any of the RUN pins below 1.15V forces that
regulator channel into a shutdown state. The TK/SS pins
are used for programming the output voltage ramp and
voltage tracking during start-up for each of the channels.
See the Applications Information section.
connect the bias to CNTL_PWR and INTV , otherwise
CC
if >5.8V only the CNTL_PWR pin needs to be biased. The
typical application schematic is shown in Figure 22.
TheLTM4634hasthreeintegratedconstant-frequencycur-
rent mode regulators, power MOSFETs, power inductors,
and other supporting discrete components. The typical
switching frequency is 750kHz. For switching noise-
sensitive applications, it can be externally synchronized
from 250kHz to 750kHz. Operating frequency range will
TheLTM4634isinternallycompensatedtobestableoverall
operatingconditions.Table4providesaguidelineforinput
and output capacitances for several operating conditions.
The LTpowerCAD™ software tool is provided for transient
and stability analysis. The V pin is used to program the
FB
be dependent upon specific V and V
requirements
output voltage with a single external resistor to ground.
IN
OUT
as they pertain to minimum on-time and inductor ripple
current of less than 60% of the load current. See the Ap-
plications Information section.
Each of the channels, operate 120° phase shift for mul-
tiphase operation. V
and V
can be combined to
OUT2
OUT1
provide a single 10A output. The two channels will not be
operating180°phaseshift,but120°phasewhencombined
for a 10A design. So the input RMS current may be higher
than a 180° phase shifted design. See the Applications
Information section for details.
With current mode control and internal feedback loop
compensation, the LTM4634 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation using the MODE/PLLIN
pin. These light load features will accommodate battery
operation. Efficiencygraphsareprovidedforlightloadop-
erationintheTypicalPerformanceCharacteristicssection.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limit in an overcurrent condition. An internal overvoltage
monitor protects the output voltages in the event of an
overvoltage >10%. The top MOSFET is turned off and the
bottom MOSFET is turned on until the output overvoltage
4634f
10
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
The typical LTM4634 application circuit is shown in Fig-
ure 22. External component selection is primarily deter-
mined by the maximum load current and output voltage.
RefertoTable4forspecificexternalcapacitorrequirements
for particular applications.
Input Capacitors
The LTM4634 module should be connected to a low AC
impedance DC source. Additional input capacitors are
neededfortheRMSinputripplecurrentrating.TheI
CIN(RMS)
equation which follows can be used to calculate the input
capacitor requirement for each channel. Typically 4.7µF
to 10µF X7R ceramics are a good choice with RMS ripple
currentratingsof~2Aeach.A47µFto100µFsurfacemount
aluminumelectrolyticcapacitorcanbeusedformoreinput
bulk capacitance. This bulk input capacitor is only needed
if the input source impedance is compromised by long
inductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
V to V
Step-Down Ratios
IN
OUT
There are restrictions in the V to V
step-down ratio
IN
OUT
that can be achieved for a given input voltage. The V to
IN
V
OUT
minimum dropout is a function of load current and
at very low input voltage and high duty cycle applications
output power may be limited as the internal top power
MOSFET is not rated for 5A operation at higher ambient
temperatures. Atverylowdutycyclestheminimum100ns
on-time must be maintained. See the Frequency Adjust-
ment section and temperature derating curves.
For a buck converter, the switching duty cycle can be
estimated as:
Output Voltage Prograꢃꢃing
VOUT
D=
V
The PWM controller has an internal 0.8V 1% reference
voltage. As shown in the Block Diagram, a 60.4k preci-
sion internal feedback resistor connects the V
pins together.
IN
Without considering the inductor ripple current, for each
output, the RMS current of the input capacitor can be
estimated as:
and V
OUT
FB
The output voltage will default to 0.8V with no feedback
I
ICIN(RMS)
=
OUT(MAX) • D• 1–D
resistor. Adding a resistor R from V to ground pro-
FB
FB
(1)
(
)
η%
grams the output voltage:
60.4k+ RFB
48.32k
VOUT –0.8
In the previous equation, η% is the estimated efficiency
VOUT = 0.8V •
or RFB =
of the power module in decimal form (0.nn) for a given
RFB
V
OUT
-to-V ratio.
IN
Table 1. VFB Resistor Table vs Various Output Voltages
(V) 0.8 1.0 1.2 1.5 1.8 2.5 3.3 5.0 12.0
The selection of C is simplified by the 3-phase architec-
IN
V
OUT
ture and its impact on the worst-case RMS current draw
occurs when only one channel is operating. This is true
when the three channels are powered from a common
R
(kΩ) Open 243 121 69.8 48.7 28.7 19.1 11.5 4.32
FB
In the parallel operation the following pins should be tied
together, V and V pins, COMP1 and COMP2 pins,
V . The channel with the highest duty cycle D peaking at
IN
FB1
FB2
0.5 and maximum load current needs to be used in the
aboveformula. ThiswillgivethemaximumRMScapacitor
current requirement. Increasing the output current drawn
from the other channels will actually decrease the input
RMS ripple current from its maximum value. The out-of-
phase technique typically reduces the input capacitor’s
RMS ripple current by a factor of 50% when compared to
asinglephasepowersupplysolution. Ifthethreechannels
are powered from independent input sources, then each
TK/SS1 and TK/SS2, and RUN1 and RUN2.
For parallel operation of V and V , connect V
FB1
OUT1
OUT2
and V together with a single resistor to ground whose
FB2
value is determined by:
60.4k
2
RFB =
VOUT
–1
0.8
4634f
11
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
of the input RMS current ratings will need to be calculated
specific to that channel.
sleep line goes low, and the LTM4634 resumes normal
operation. The next oscillator cycle will turn on the top
power MOSFET and the switching cycle repeats.
Output Capacitors
Pulse-Skipping ꢁode Operation
The LTM4634 is designed for low output voltage ripple
noise. The bulk output capacitors defined as C
are
Inapplicationswherelowoutputrippleandhighefficiency
OUT
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient require-
at intermediate currents are desired, pulse-skipping
mode should be used. Pulse-skipping operation allows
the LTM4634 to skip cycles at low output loads, thus
increasing efficiency by reducing switching loss. Tying
ments. C
can be a low ESR tantalum capacitor, low
OUT
ESR Polymer capacitor or ceramic capacitor. The typical
outputcapacitancerangeisfrom200µFto470µF.Additional
output filtering may be required by the system designer
if further reduction of output ripple or dynamic transient
spikesisrequired.Table4showsamatrixofdifferentoutput
voltages and output capacitors to minimize the voltage
droop and overshoot during a 5A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to optimize the transient performance. Stability criteria
are considered in the Table 4 matrix, and LTpowerCAD is
available for stability analysis. LTpowerCAD can calculate
the output ripple reduction as the number of implemented
phases increases by N times.
the MODE/PLLINpin to INTV enables pulse-skipping
CC
operation. With pulse-skipping mode at light load, the
internalcurrentcomparatormayremaintrippedforseveral
cycles, thus skipping operation cycles. This mode has
lower ripple than Burst Mode operation and maintains a
higher frequency operation than Burst Mode operation.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE/PLLIN pin to ground. In this
mode, inductor current is allowed to reverse during low
output loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
alwaysturnsonwitheachoscillatorpulse.Duringstart-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4634 output
voltage is in regulation.
Burst ꢁode Operation
The LTM4634 is capable of Burst Mode operation in
which the power MOSFETs operate intermittently based
on load demand, thus saving quiescent current. For ap-
plications where maximizing the efficiency at very light
loads is a high priority, Burst Mode operation should be
applied. To enable Burst Mode operation, simply float
the MODE/PLLIN pin. During Burst Mode operation, the
peak current of the inductor is set to approximately 30%
of the maximum peak current value in normal operation
even though the voltage at the COMP pin indicates a
lower value. The voltage at the COMP pin drops when
the inductor’s average current is greater than the load
requirement. As the COMP voltage drops below 0.5V, the
burst comparator trips, causing the internal sleep line to
go high and turn off both power MOSFETs.
Frequency Synchronization
The LTM4634 device operates up to 750kHz. It can also be
synchronizedwithaninputclockthathasahighlevelabove
2V and a low level below 0.8V at the MODE/PLLIN pin. The
FREQ/PLLLPF pin must be floating when synchronized to
an incoming clock. Once the LTM4634 is synchronized to
an external clock frequency, it will always be running in
forced continuous operation. The synchronizing range is
from 250kHz to 750kHz. For V
≤ 1.5V use 250kHz
In sleep mode, the internal circuitry is partially turned
off, reducing the quiescent current. The load current is
now being supplied from the output capacitors. When the
output voltage drops, causing COMP to rise, the internal
OUT1,2,3
≤ 2.5V use 400kHz, 2.5V ≤
to 300kHz, 1.5V ≤ V
OUT1,2,3
V
≤ 5V use 600kHz. If V
is greater than 5V
up to 12V set the operating frequency to 750kHz. These
OUT1,2,3
OUT3
4634f
12
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
frequencies optimize efficiency, eliminate minimum on-
timeissuesforlessthan1Voutput,andcontroltheinductor
ripple currents over the input and output voltage ranges.
where FREQV is the voltage at the FREQ/PLLLPF pin in
Figure 2 that corresponds to a particular frequency. See
Figure 25 for an example.
800
700
600
500
400
300
200
24Vinputapplicationsthatconverttooutputvoltagesequal
to 5V (V
) and up to 12V (V
) will be required to
OUT1,2
OUT3
set the LTM4634 switching frequency to 750kHz. This is
required to maintain less than 60% inductor ripple current
at the higher output voltages. The 750kHz requirement
for these higher output conversions from 24V will limit
outputvoltagesonotherchannelstobenolowerthan1.5V
due to minimum on-time considerations. There is a way
around this issue by taking one of these outputs, either
5V or 12V, and using it as the source for the 0.8V to 1.5V
output. An example circuit is shown in Figure 26. 5V and
12V input conversions on all three channels can be oper-
ated at lower frequencies across the output ranges so that
minimum on-time is not an issue at low output voltages.
The minimum on-time equation on the next page can be
used to verify that no switching frequency is violating this
0
0.5
1
1.5
2
2.5
FREQ/PLLLPF PIN VOLTAGE (V)
4634 F02
Figure 2. Relationship Between Oscillator Frequency
and Voltage at the FREQ/PLLLPF Pin
Parallel Channel Operation
parameter. The equations for checking I
%:
For outputs that demand more than 5A of load current,
the LTM4634 device can parallel V
ply 10A of load current. The two channels will operate at
120° of phase shift. The input RMS ripple current can be
calculated using Equation 1. For example, 12V to 1.2V at
10A equates to duty cycle D = 0.1.
RIPPLE
and V
to sup-
OUT1
OUT2
V – V
V
(
)
IRIPPLE
CH#MaxLoad
IN
OUT OUT
= FREQ,
= IRIPPLE
%
L•IRIPPLE •V
IN
This verifies that the operating frequencies are selected to
limitinductorripplecurrentstobebelow60%ofmaximum
10A
0.85
load, where FREQ is selected frequency in Hertz, I
RIPPLE
ICIN(RMS)
=
• 0.1• 1–0.1
(
)
and maximum load current in amps, and L is inductance
in Henrys. Ch1, Ch2 L = 1.5µH, and Ch3 L = 3.3µH. Maxi-
I
=3.5A
capacitors rated at 2A
,use2× 22µF16VX5RorX7Rceramic
RMS
CIN(RMS)
mum load current I
RIPPLE
= 5A, and I
= 4A, therefore
OUT1,2
OUT3
each.
RMS
I
should try to stay below 2.5A for Ch1, Ch2, and
2A for Ch3, except for 12V output. The efficiency curves
will show the recommended optimal operating frequency
for the different conversions
The LTM4634 regulators are inherently current mode
controlled devices, so the paralleling of V and V
OUT1
OUT2
channels will have good current sharing. This will balance
the thermals in the design. Tie the COMP, V , TK/SS
FB
A DC voltage should be applied to the FREQ/PLLLPF pin
to set the operating frequency when clock synchroniza-
tion is not used. Figure 2 shows the frequency selection
as a function of the applied DC voltage. This can be done
and RUN pins together for these two channels to share
the current evenly. Figure 24 shows a schematic of the
parallel design.
with a voltage divider from the INTV (5V) pin to SGND.
CC
ꢁiniꢃuꢃ On-Tiꢃe
A 10k resistor can be selected as the bottom resistor. The
Minimum on-time, t , is the smallest time duration that
top resistor, R
, can be determined by using equation:
FREQ
ON
anyofthethreeregulatorchannelsiscapableofturningon
the top MOSFET. It is determined byinternaltimingdelays,
and the gate charge required to turn on the top MOSFET.
4634f
5V •10k
FREQV
RFREQ
=
–10k
13
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
60.4k resistor internally for the top feedback resistor for
each channel. Figure 3 shows an example of coincident
tracking for V
and V
. V
is the master and
OUT1
is the slave:
OUT2 OUT1
VOUT
> tON(MIN)
V
OUT2
V •FREQ
IN
60.4k
RTA
VSLAVE = 1+
VTRACK
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles.Theoutputvoltagewillcontinuetoberegulated,but
the output ripple and inductor ripple current will increase.
The minimum on-time can be increased by lowering the
switching frequency. A good rule of thumb is to use a
100ns on-time.
V
V
is the track ramp applied to the slave’s track pin.
has a control range of 0V to 0.8V, or the internal
TRACK
TRACK
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
tracking is disabled when V
Figure 3 will be equal to the R for coincident tracking.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TK/SS pins. The output can be tracked up and
downwithanotherregulator.Themasterregulator’soutput
is divided down with an external resistor divider that is the
same as the slave regulator’s feedback divider to imple-
ment coincident tracking. The LTM4634 uses an accurate
is more than 0.8V. R in
TRACK TA
FB2
The TK/SS pin of the master can be controlled by a capaci-
tor placed on the master regulator TK/SS pin to ground. A
1.5µA current source will charge the TK/SS pin up to the
5.5V TO 16V
C
22µF
16V
C
22µF
16V
C
22µF
16V
C
22µF
16V
IN4
IN3
IN2
IN1
4.7µF
6.3V
V
IN1
SW1
V
IN2
SW2
V
SW3 INTV EXTV
CC CC
IN3
CNTL_PWR
MODE/PLLIN
RUN1
FREQ/PLLLPF
COMP1
UVLO SET AT 4.7V ON RUN PINS.
RUN PINS CAN BE SEQUENCED OR
ENABLED FROM LOGIC CONTROL
10k
10k
7.87k
COMP2
RUN2
COMP3
LTM4634
RUN3
PGOOD12
PGOOD3
TEMP1
60.4k
V
TK/SS1
OUT3
R
60.4k
TB
69.8k
V
TK/SS2
TK/SS3
OUT3
TEMP2
R
C
TA
SS3
121k
0.1µF
V
V
V
V
V
V
GND SGND
OUT1
FB1
OUT2
FB2
OUT3
FB3
4633 F03
V
V
V
FB3
FB1
FB2
C
OUT
, SEE TABLE 5
R
R
R
FB3
19.1k
FB1
FB2
69.8k
121k
SOFT-START MASTER
RAMP SET BY C OR
C
C
OUT4
220µF
OUT1
SS3
220µF
EXTERNAL RAMP
47pF
3.3V
1.2V
C
C
C
OUT7
100µF
V
OUT2
OUT5
FB3
220pF
220µF
220µF
47pF
1.5V
MASTER
V
V
FB2
FB1
C
OUT8
100µF
Figure 3. Triple Outputs (1.5V and 1.2V) with Tracking and 3.3V
4634f
14
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
referencevoltageandthenproceeduptoINTV . Afterthe
tracking is desired, then MR and SR are equal, thus R
TB
CC
0.8V ramp, the TK/SS pin will no longer be in control, and
the internal voltage reference will control output regula-
tion from the feedback divider. Foldback current limit is
disabled during this sequence of turn-on during tracking
or soft-starting. The TK/SS pins are pulled low when the
is equal the 60.4k. R is derived from equation:
TA
0.8V
RTA
=
V
V
VTRACK
RTB
FB
FB
+
–
60.4k RFB
RUN pin is below 1.15V or INTV drops below 3.5V. The
CC
where V is the feedback voltage reference of the regula-
FB
total soft-start time can be calculated as:
tor, and V
is 0.8V. Since R is equal to the 60.4k top
TRACK
TB
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then R is equal to R with V
0.8V •C
1.5µA
SS
tSS
=
=
FB
TA
FB
V
.ThereforeR =60.4k,andR =60.4kinFigure3.
TRACK
TB TA
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator channels will always start in pulse-skipping
mode up to TK/SS = 0.64V. Between TK/SS = 0.64V and
0.74V, it will operate in forced continuous mode and revert
totheselectedmodeonceTK/SS>0.74V.Theoutputripple
is minimized during the 100mV forced continuous mode
window ensuring a clean PGOOD signal.
Inratiometrictracking, adifferentslewratemaybedesired
for the slave regulator. R can be solved for when SR is
TB
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
Power Good
When the channel is configured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TK/SS pin. Therefore,
thevoltageramprateonthispinisdeterminedbytheramp
rate of the other supply’s voltage. Note that the small soft-
startcapacitorchargingcurrentisalwaysflowing,produc-
ing a small offset error. To minimize this error, select the
trackingresistivedividervaluetobesmallenoughtomake
thiserrornegligible.Inordertotrackdownanotherchannel
orsupplyafterthesoft-startphaseexpires,theLTM4634is
The PGOOD12 pin is an open-drain pin that can be used
to monitor valid output voltage regulation for V
and
OUT1
. These pins
V
, and PGOOD3 for monitoring V
OUT2
OUT3
monitor a 7.5% window around the 0.8V feedback volt-
age on either V from the output regulation point. A
FB1,2,3
resistor can be pulled up to a particular supply voltage
no greater than 6V maximum for monitoring. Any of the
PGOOD pins are pulled low when the RUN pin of the cor-
responding channel is pulled low.
forced into continuous mode of operation as soon as V
Overcurrent and Overvoltage Protection
FB
isbelowtheundervoltagethresholdof0.74Vregardlessof
thesettingoftheMODE/PLLINpin. However, theLTM4634
should always be set in forced continuous mode tracking
downwhenthereisnoload. AfterTK/SSdropsbelow0.1V,
its channel will operate in discontinuous mode.
Each of the regulator channels senses the peak inductor
current on a cycle-by-cycle basis in current mode opera-
tion. When current limit is reached the output voltage will
begin to fall and the internal current limit threshold will
begin fold back as the output voltage falls below 50% of
its value. Foldback current limit is disabled during start-
up or track-up. Under short-circuit condition at low duty
cycle operation, each of the regulator channels will begin
to skip cycles to limit the short-circuit current.
The master’s TK/SS pin slew rate is directly equal to the
master’s output slew rate in Volts/Time. The equation:
MR
SR
R =
•60.4k
TB
Overvoltage protection is implemented by monitoring
each one of the regulator’s V pins. When the V volt-
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
FB
FB
age exceeds ~7.5% of the 0.8V reference value, then an
4634f
15
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
switched current path. Usually a series R-C combination
is used called a snubber circuit. The resistor will dampen
the resonance and the capacitor is chosen to only affect
the high frequency ringing across the resistor.
internal comparator monitor will turn off the top power
switch, andturnonthebottompowerswitchtoprotectthe
load. If the top power switch faults as a short, then a fuse
or circuit breaker would be recommended to protect the
system. This is due to the top switch being shorted while
the bottom switch is turning on to protect the output from
over voltage. High currents will flow and could damage
the bottom switch.
If the stray inductance or capacitance can be measured
or approximated then a somewhat analytical technique
can be used to select the snubber values. The inductance
is usually easier to predict. It combines the PowerPath™
board inductance in combination with the MOSFET inter-
connect inductance.
Stability Coꢃpensation
First the SW pin can be monitored with a wide bandwidth
scope with a high frequency scope probe. The ring fre-
quency can be measured for its value. The impedance, Z,
can be calculated:
The module has already been internally compensated for
all output voltages. Table 4 is provided for most applica-
tion requirements with verified stability. LTpowerCAD is
available for other control loop optimization.
Z
(L)
= 2π • f • L
Run Enable
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by:
The RUN 1, 2, 3 pins have an enable threshold of 1.4V
maximum, typically 1.3V with 175mV of hysteresis. They
control the turn-on of their respective channel. There is
a 10k resistor on each pin to ground. The RUN pins can
be pulled up to V for 5V operation, or a resistor can be
IN
placed on the pins and connected to V for higher than 5V
IN
1
input. This resistor can be set along with the onboard 10k
resistor such that an undervoltage lockout (UVLO) level
can be programmed to shut down a particular regulator
Z(C)
=
2π •f•C
these values are a good place to start with. Modification to
these components should be made to attenuate the ring-
ing without lowering the regulator’s conversion efficiency.
channel if V falls below a set value. Use the equation:
IN
10k UVLO–1.3V
(
)
R=
1.3V
INTV and EXTV
CC
CC
where R is the resistor from the RUN pin to V to set the
IN
The LTM4634 has an onboard linear regulator fed by
CNTL_PWR which delivers a roughly 5V output at INTV
UVLO trip point. For example, if the UVLO point is to be
CC
6.25V while operating at 12V input:
to power the internal controller and MOSFET drivers for all
10k 6.25V –1.3V
(
)
≈ 38k
three regulator channels. Apply a 4.7µF ceramic capacitor
R=
1.3V
between INTV and ground for decoupling. CNTL_PWR
CC
requires a voltage between 4.75V to 28V. If the voltage
See the Block Diagram in Figure 1. The RUN pins must
never exceed 6V maximum voltage. The RUN pins have
to be pulled up to enable the regulators.
supplied to CNTL_PWR is ≤ 5.8V, connect INTV to
CC
CNTL_PWR. Otherwise, INTV should be left floating.
CC
To eliminate power loss in the onboard linear regulator
and improve efficiency connect a supply from 4.7V to 6V
SW Pins
at EXTV . Biasing EXTV at 5V will reduce the power
CC
CC
The SW pins are generally for testing purposes by moni-
toring the pin. The SW pin can also be used to dampen
out switch node ringing caused by LC parasitics in the
loss in the internal LDO by (V
and is recommended for V
– 5V) • 90mA
≥ 12V when all
CNTL_PWR
CNTRL_POWER
three channels are operating. If EXTV is used add a 1µF
CC
4634f
16
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
ceramic capacitor to ground at EXTV and ensure the
2. θ
: The thermal resistance from the junction to
CC
JCbottom
voltage at CNTL_PWR is always greater than the voltage
the bottom of the product case, is determined with all
of the internal power dissipation flowing through the
bottom of the package. In a typical µModule regulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
at EXTV at all times during start-up and shutdown.
CC
Connecting V
to EXTV may present a convenient
OUT3
CC
way to meet the sequencing requirement. Otherwise float
EXTV if not used.
CC
Therꢃal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients is
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
3. θ
: The thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetopof
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
for comparing packages but the test conditions don’t
generally match the user’s application.
, this value may be useful
JCbottom
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to predict the
µModule regulator’s thermal performance in their appli-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are, in and of themselves, not relevant
to providing guidance of thermal performance; instead,
the derating curves provided in the data sheet can be used
in a manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.
4. θ : The thermal resistance from junction to the printed
JB
circuitboard,isthejunction-to-boardthermalresistance
where almost all of the heat flows through the bottom
oftheµModulepackageandintotheboard, andisreally
the sum of the θ
and the thermal resistance of
JCbottom
the bottom of the part through the solder joints and
through a portion of the board. The board temperature
is measured at a specified distance from the package.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 4; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule package.
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD51-12. These coefficients
are quoted or paraphrased as follows:
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal oper-
ating conditions of a μModule regulator. For example, in
normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally con-
duct exclusively through the top or exclusively through
1. θ :Thethermalresistancefromjunctiontoambient, is
JA
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
4634f
17
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
JUNCTION-TO-AMBIENT RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4633 F04
µMODULE DEVICE
Figure 4. Graphical Representations of JESD51-12 Therꢃal Coefficients
bottom of the µModule package—as the standard defines
for θ and θ , respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow; a majority of the heat flow is into the board.
conditions in the software model, a thorough laboratory
evaluation replicates the simulated conditions with ther-
mocoupleswithinacontrolledenvironmentchamberwhile
operating the device at the same power loss as that which
was simulated. The outcome of this process and due
diligence yields the set of derating curves shown in this
data sheet.
JCtop
JCbottom
Within the LTM4634, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled environment chamber
to reasonably define and correlate the thermal resistance
valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware
is used to accurately build the mechanical geometry of
the LTM4634 and the specified PCB with all of the cor-
rect material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
andFEAsoftwareisusedtoevaluatetheLTM4634withheat
sink and airflow; (4) having solved for and analyzed these
thermalresistancevaluesandsimulatedvariousoperating
After these laboratory tests have been performed and cor-
related to the LTM4634 model, then the θ and θ are
JB
BA
summed together to correlate quite well with the device
modelconditionsofnoairfloworheatsinkinginaproperly
define chamber. This θ + θ value should accurately
JB
BA
equaltheθ valuebecauseapproximately100%ofpower
JA
loss flows from the junction through the board into ambi-
ent with no air-flow or top mounted heat sink.
LTꢁ4634 Therꢃal Considerations and Output Current
Derating
Thepowerlosscurvesat5Vinput,12Vinput,and24Vinput
are shown in Figures 8 to 13. These power loss curves
can be used in coordination with the load current derating
curves in Figures 14 to 21 for calculating an approximate
θ
thermal resistance for the LTM4634 with various heat
JA
sinking and airflow conditions. The power loss curves
are taken at room temperature, and are increased with a
multiplicative factor of 1.4 at 120°C junction.
4634f
18
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
The derating curves are plotted with the output current
starting at 15A (5A/CH) and the ambient temperature at
~40°C. The 15A comes from each of the three channels
operating at 5A each. This simplifies the loading for this
thermal testing. The output voltages are 3.3V, and 5V
when all three channels are loaded together in parallel.
Channel 1 and Channel 2 are designed to operate with
outputs up to 5V, and Channel 3 is designed for 12V. The
power loss curve values at a particular output voltage and
output current for each output are taken and multiplied by
1.4 for increased power loss at 120°C junction. Thermal
models are derived from several temperature measure-
ments in a controlled temperature chamber along with
thermal modeling analysis. The junction temperatures
are monitored while ambient temperature is increased
with and without airflow. The power loss increase with
ambient temperature change is factored into the derating
curves. The junctions are maintained at 120°C maximum
while lowering output current or power with increasing
ambient temperature. The decreased output current will
decrease the internal module loss as ambient tempera-
ture is increased. The monitored junction temperature of
120°Cminustheambientoperatingtemperaturespecifies
how much module temperature rise can be allowed. As
an example, in Figure 17 the 5.0V load current is derated
to ~12.6A at ~71°C with no air and with no heat sink. In
Figure 10, the 12V to 5.0V power loss at 4.2A per chan-
nel is 1.25W. The total loss would be 3 times 1.25W for
3.75W total power loss. The 3.75W is then multiplied by
the 1.4 multiplier for 120°C junction. This 5.25W value is
used with the total temperature rise of 120°C minus the
belowthe120°Cmaximumjunctiontemperature.Thermal
measurements or infrared analysis should be performed
to validate the values. Ambient temperature power loss
can be derived from the power loss curves in Figures 8 to
13 and adjusted with the 1.4 multiplier. The printed circuit
board is a 1.6mm thick four-layer board with two ounce
copper for the two outer layers and 1 ounce copper for
the two inner layers. The PCB dimensions are 95mm ×
76mm. The BGA heat sinks are listed in Table 3.
Teꢃperature ꢁonitoring (TEꢁP1 and TEꢁP2)
Diode connected PNP transistors are used for the TEMP1,
TEMP2monitoringfunctionsincethediodeforwardvoltage
varies with temperature. The temperature dependence of
the diodes can be understood in the equation:
ID
VD = nVT ln
I
S
where V is the thermal voltage (kT/q), and n, the ideality
T
factor, is 1 for the two diode connected PNPs being used
in the LTM4634. I is expressed by the typical empirical
S
equation:
–VG0
VT
IS = I0 exp
where I is a process and geometry-dependent current (I
0
0
is typically around 20 orders of magnitude larger than I
S
at room temperature), and V is the band gap voltage of
G0
1.2V extrapolated to absolute zero or –273°C.
71°C ambient to calculate θ thermal resistance. If the
JA
If we take the I equation and substitute into the V equa-
S
D
71°C ambient temperature is subtracted from the 120°C
tion, then we get:
junction temperature, then the difference of 49°C divided
kT
q
I0
kT
q
5.25W equals a 9.3°C/W θ thermal resistance. Table 2
JA
VD = VG0 –
ln
, VT =
I
specifies a 9.0°C/W value which is very close. Tables 2
and 3 provide equivalent thermal resistances for 3.3V and
5V outputs with and without air flow and heat sinking. The
derivedthermalresistancesinTables2and3forthevarious
conditions can be multiplied by the calculated power loss
as a function of the 120°C maximum junction tempera-
ture to determine if the temperature rise plus ambient is
D
The expression shows that the diode voltage decreases
(linearly if I were constant) with increasing temperature
0
and constant diode current. Figure 5 shows a plot of V
D
vs Temperature over the operating temperature range of
the LTM4634.
4634f
19
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
If we take this equation and differentiate it with respect to
temperature T, then:
0.8
0.7
0.6
0.5
0.4
0.3
I
D
= 100µA
dVD
dT
VG0 – VD
T
= –
This dV /dT term is the temperature coefficient equal to
D
about –2mV/K or –2mV/°C. The equation is simplified for
the first order derivation.
Solving for T, T = –(V – V )/(dV /dT) provides the
G0
D
D
temperature.
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
4634 F05
1st Example: Figure 5 for 27°C, or 300K the diode
voltage is 0.598V, thus, 300K = –(1200mV – 598mV)/
–2.0 mV/K)
Figure 5. Diode Voltage VD vs Teꢃperature T(°C)
2nd Example: Figure 5 for 75°C, or 350K the diode
voltage is 0.50V, thus, 350K = –(1200mV – 500mV)/
–2.0mV/K)
Converting the Kelvin scale to Celsius is simply taking the
Kelvin temp and subtracting 273 from it.
A typical forward voltage is given in the electrical charac-
teristics section of the data sheet, and Figure 5 is the plot
of this forward voltage. Measure this forward voltage at
27°C to establish a reference point. Then using the above
expression while measuring the forward voltage over
temperature will provide a general temperature monitor.
Connect resistors between TEMP1, TEMP2 and V to set
IN
the currents to 100µA each. See Figure 25 for an example.
Figure 6. Therꢃal Plot 24V to 3.3V at 5A, 5V at 5A, and 12V
at 4A, Airflow = 200LFꢁ, Aꢃbient = 25°C
Safety Considerations
The LTM4634 module does not provide galvanic isolation
from V to any of the three V s. There is no internal
IN
OUT
the internal bottomMOSFET willturn on indefinitely trying
to protect the load. Under this fault condition, the input
voltage will source very large currents to ground through
the failed internal top MOSFET and enabled internal bot-
tom MOSFET. This can cause excessive heat and board
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker can
be used as a secondary fault protector in this situation.
fuse. If required, a slow blow fuse with a rating higher
than the maximum input current can be used to protect
the unit in case of a catastrophic failure. An inline circuit
breaker function can also be used instead of a fuse.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internaltopMOSFETfault. IftheinternaltopMOSFETfails,
then turning it off will not resolve the overvoltage, thus
4634f
20
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
Layout Checklist/Eꢂaꢃple
Place a dedicated powerground layerunderneaththe unit.
To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection be-
tween top layer and other power layers.
The high integration of LTM4634 makes the PCB board
layoutverysimpleandeasy.However,tooptimizeitselectri-
cal and thermal performance, some layout considerations
are still necessary.
Donotputviasdirectlyonthepads,unlesstheyarecapped
or plated over. Use a separated SGND ground copper area
for components connected to signal pins. Connect the
SGND to GND underneath the unit. Bring out test points
on the signal pins for monitoring. Figure 7 gives a good
example of the recommended layout.
Use large PCB copper areas for high current paths, in-
cluding V , GND, V
, V
, and V . It helps to
OUT3
IN
OUT1 OUT2
minimize the PCB conduction loss and thermal stress.
Place high frequency ceramic input and output capacitors
next to the V , GND and the V
pins to minimize high
IN
OUT
frequency noise.
FARSIDE COMPONENTS
R
, R , R
FB1 FB2 FB3
CONTROL
CONTROL
INTVCC
GND
R
R
R
FB1
FB2
FB3
M
L
C
GND
GND
C
IN3
K
J
FARSIDE COMPONENTS
IN1 IN2
IN1
C
IN2
C
, C
H
C
V
G
F
IN3
GND
C
C
OUT6
OUT4
FARSIDE COMPONENTS
E
C
, C
C
OUT4 OUT5, OUT6
GND
D
C
B
A
C
C
OUT1
OUT3
V
OUT3
V
OUT1
1
2
3
4
5
6
7
8
9
10 11 12
“A1” INDICATOR
4634 F07
V
GND
V
GND
V
OUT1
OUT3
OUT2
LTM4634Y BGA TOP VIEW
Figure 7. Recoꢃꢃended PCB Layout
4634f
21
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
1.4
1.3
1.2
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5V TO 3.3V POWER
LOSS CURVE
5V TO 2.5V POWER
LOSS CURVE
5V TO 1.8V POWER
LOSS CURVE
5V TO 1.5V POWER
LOSS CURVE
5V TO 1.2V POWER
LOSS CURVE
5V TO 1V POWER
LOSS CURVE
5V TO 3.3V POWER
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
LOSS CURVE
5V TO 2.5V POWER
LOSS CURVE
5V TO 1.8V POWER
LOSS CURVE
5V TO 1.5V POWER
LOSS CURVE
5V TO 1.2V POWER
LOSS CURVE
5V TO 1V POWER
LOSS CURVE
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
4634 F08
4634 F09
Figure 8. 5V Input Power Loss
(Ch1 and Ch2)
Figure 9. 5V Input Power Loss (Ch3)
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
12V TO 5V POWER
LOSS CURVE
12V TO 3.3V POWER
LOSS CURVE
12V TO 2.5V POWER
LOSS CURVE
12V TO 1.8V POWER
LOSS CURVE
12V TO 1.5V POWER
LOSS CURVE
12V TO 1.2V POWER
LOSS CURVE
12V TO 1V POWER
LOSS CURVE
12V TO 5V POWER
LOSS CURVE
12V TO 3.3V POWER
LOSS CURVE
12V TO 2.5V POWER
LOSS CURVE
12V TO 1.8V POWER
LOSS CURVE
12V TO 1.5V POWER
LOSS CURVE
12V TO 1.2V POWER
LOSS CURVE
12V TO 1V POWER
LOSS CURVE
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
4634 F10
4634 F11
Figure 10. 12V Input Power Loss
(Ch1 and Ch2)
Figure 11. 12V Power Loss (Ch3)
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
24V TO 12V POWER
LOSS CURVE
24V TO 5V POWER
LOSS CURVE
24V TO 3.3V POWER
LOSS CURVE
24V TO 2.5V POWER
LOSS CURVE
24V TO 1.8V POWER
LOSS CURVE
24V TO 1.5V POWER
LOSS CURVE
24V TO 1.2V POWER
LOSS CURVE
24V TO 1V POWER
LOSS CURVE
24V TO 5V POWER
LOSS CURVE
24V TO 3.3V POWER
LOSS CURVE
24V TO 2.5V POWER
LOSS CURVE
24V TO 1.8V POWER
LOSS CURVE
24V TO 1.5V POWER
LOSS CURVE
24V TO 1.2V POWER
LOSS CURVE
24V TO 1V POWER
LOSS CURVE
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOAD CURRENT (A)
4634 F12
4634 F12
Figure 12. 24V Power Loss
(Ch1 and Ch2)
Figure 13. 24V Power Loss (Ch3)
4634f
22
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
16
14
12
10
8
16
14
12
10
8
16
14
12
10
8
6
6
6
4
4
4
0 LFM AIR FLOW
200 LFM AIR FLOW
400 LFM AIR FLOW
0 LFM AIR FLOW
200 LFM AIR FLOW
400 LFM AIR FLOW
0 LFM AIR FLOW
200 LFM AIR FLOW
400 LFM AIR FLOW
2
2
2
0
0
0
40
60
80
100
40
60
80
100
40
60
80
100
0
20
120
0
20
120
0
20
120
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4634 F14
4634 F15
4634 F16
Figure 14. 12VIN, 3.3VOUT, with Heat
Sink, All Channels at 5A Each
Figure 15. 12VIN, 3.3VOUT, without
Heat Sink, All Channels at 5A Each
Figure 16. 12VIN, 5V, with Heat
Sink, All Channels at 5A Each
16
14
12
10
8
16
16
14
12
10
8
14
12
10
8
6
6
6
4
4
4
0 LFM AIR FLOW
200 LFM AIR FLOW
400 LFM AIR FLOW
0 LFM AIR FLOW
200 LFM AIR FLOW
400 LFM AIR FLOW
0 LFM AIR FLOW
200 LFM AIR FLOW
400 LFM AIR FLOW
2
0
2
2
0
0
40
60
80
100
40
60
80
100
40
60
80
100
0
20
120
0
20
120
0
20
120
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4634 F17
4634 F18
4634 F19
Figure 18. 24VIN, 3.3V, with Heat
Sink, All Channels at 5A Each
Figure 19. 24VIN, 3.3V, without
Heat Sink, All Channels at 5A Each
Figure 17. 12VIN, 5V, without Heat
Sink, All Channels at 5A Each
16
14
12
10
8
16
14
12
10
8
6
6
4
4
0 LFM AIR FLOW
200 LFM AIR FLOW
400 LFM AIR FLOW
0 LFM AIR FLOW
200 LFM AIR FLOW
400 LFM AIR FLOW
2
0
2
0
40
60
80
100
40
60
80
100
0
20
120
0
20
120
TEMPERATURE (°C)
TEMPERATURE (°C)
4634 F20
4634 F21
Figure 20. 24VIN, 5V, with Heat
Sink, All Channels at 5A Each
Figure 21. 24VIN, 5V, without Heat
Sink, All Channels at 5A Each
4634f
23
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
Table 2. 3.3V Output
DERATING CURVE
Figures 15, 19
Figures 15, 19
Figures 15, 19
Figures 14, 18
Figures 14, 18
Figures 14, 18
V
(V)
POWER LOSS CURVE
Figures 8 to 13
Figures 8 to 13
Figures 8 to 13
Figures 8 to 13
Figures 8 to 13
Figures 8 to 13
AIR FLOW (LFꢁ)
HEAT SINK
None
θ
(°C/W)
9.0
IN
JA
12, 24
12, 24
12, 24
12, 24
12, 24
12, 24
0
200
400
0
None
7.5
None
6.5
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
9.0
200
400
6.5
6.0
Table 3. 5V Output
DERATING CURVE
Figures 17, 20
Figures 17, 20
Figures 17, 20
Figures 16, 21
Figures 16, 21
Figures 16, 21
V
(V)
POWER LOSS CURVE
Figures 8 to 13
Figures 8 to 13
Figures 8 to 13
Figures 8 to 13
Figures 8 to 13
Figures 8 to 13
AIR FLOW (LFꢁ)
HEAT SINK
None
θ
(°C/W)
9.0
IN
JA
12, 24
12, 24
12, 24
12, 24
12, 24
12, 24
0
200
400
0
None
7.5
None
6.5
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
9.0
200
400
6.5
6.0
Heat Sink ꢁanufacturer Part Nuꢃber Website
Aavid Thermalloy
Cool Innovations
375424B00034G
www.aavid.com
www.coolinnovations.com
4-050503P to
4-050508P
4634f
24
For more information www.linear.com/LTM4634
LTM4634
applicaTions inForMaTion
Table 4. Output Voltage Response Versus Coꢃponent ꢁatriꢂ
(Refer to Figure 26) 0 to 2.5A Load Step Typical ꢁeasured Values
C
CERAꢁIC
OUT
VENDORS
Murata
TDK
VALUE
PART NUꢁBER
220µF, 4V, X5R 1206 Case Size
GRM31CR60G277M
100µF, 6.3V, X5R 1210 Case Size C3225X5R0J107M
22µF, 25V, X7R, 1210 Case Size GRM32ER71E226K
Murata
Panasonic
Poscap
100µF, 16V, D2 Case Size
150µF, 16V, D3L Case Size
4.7µF, 50V
16TQC100M
16TQC100M
Murata
GRU55ER71H475K
GRM32ER71H06KA12L
10µF, 50V
PEAK-TO-PEAK
V
,
C
C
C
C
OUT2
DEVIATION AT RECOVERY LOAD
OUT1
IN
IN
OUT1
V
(CERAꢁIC) (BULK)* (CERAꢁIC) (BULK)
C
FF
C
C
V
DROP 2.5A LOAD STEP
TIꢁE
STEP
R
FB
FREQ
OUT2
BOT
COꢁP
IN
1V
1V
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
None
None
47pF None None 12V 50mV
47pF None None 12V 40mV
100mV
80mV
90µs
2.5A/µs 243kΩ 500kHz
2.5A/µs 243kΩ 500kHz
2.5A/µs 121kΩ 500kHz
2.5A/µs 69.8kΩ 500kHz
2.5A/µs 48.7kΩ 500kHz
2.5A/µs 28.7kΩ 500kHz
2.5A/µs 28.7kΩ 500kHz
2.5A/µs 19.1kΩ 500kHz
2.5A/µs 19.1kΩ 750kHz
2.5A/µs 19.1kΩ 500kHz
2.5A/µs 19.1kΩ 750kHz
2.5A/µs 11.5kΩ 750kHz
2.5A/µs 11.5kΩ 750kHz
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
22µF × 3
100µF × 2
220µF × 2
220µF × 2
220µF × 2
220µF × 2
220µF × 2
220µF × 3
220µF × 2
220µF × 2
220µF × 3
100µF × 2
100µF × 2
100µF × 3
90µs
1.2V
1.5V
1.8V
2.5V
2.5V
3.3V
3.3V
3.3V
3.3V
5V
None 47pF None None 12V 48mV
None 47pF None None 12V 50mV
96mV
90µs
100mV
100mV
150mV
140mV
200mV
200mV
180mV
200mV
340mV
280mV
100µs
100µs
100µs
100µs
120µs
120µs
120µs
120µs
100µs
100µs
None
None
None
None
None
None
None
None
None
47pF None None 12V 50mV
47pF None None 12V 75mV
47pF None None 12V 70mV
47pF None None 12V 100mV
47pF None None 12V 100mV
47pF None None 12V 90mV
47pF None None 12V 100mV
47pF None None 12V 170mV
47pF None None 12V 140mV
5V
PEAK-TO-PEAK
C **
C
C
C
OUT2
DEVIATION AT RECOVERY LOAD
IN
IN
OUT1
V
OUT3
(CERAꢁIC) (BULK)* (CERAꢁIC) (BULK)
C
C
C
V
DROP 2.5A LOAD STEP
TIꢁE
120µs
120µs
120µs
120µs
120µs
120µs
120µs
200µs
200µs
200µs
200µs
200µs
200µs
STEP
R
FB
FREQ
FF
BOT
COꢁP
IN
5
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
150µF
None
None
47pF None None 24V 170mV
47pF None None 24V 140mV
47pF None None 24V 120mV
47pF None None 24V 120mV
47pF None None 24V 120mV
47pF None None 24V 110mV
47pF None None 24V 110mV
47pF None None 24V 300mV
47pF None None 24V 300mV
47pF None None 24V 250mV
47pF None None 24V 240mV
47pF None None 24V 230mV
47pF None None 24V 220mV
340mV
280mV
240mV
240mV
240mV
220mV
220mV
600mV
600mV
500mV
480mV
460mV
440mV
2.5A/µs 11.5kΩ 600kHz
2.5A/µs 11.5kΩ 600kHz
2.5A/µs 11.5kΩ 600kHz
2.5A/µs 11.5kΩ 600kHz
2.5A/µs 11.5kΩ 600kHz
2.5A/µs 11.5kΩ 600kHz
2.5A/µs 11.5kΩ 600kHz
2.5A/µs 4.32kΩ 600kHz
2.5A/µs 4.32kΩ 600kHz
2.5A/µs 4.32kΩ 600kHz
2.5A/µs 4.32kΩ 600kHz
2.5A/µs 4.32kΩ 600kHz
2.5A/µs 4.32kΩ 600kHz
4.7µF × 3
4.7µF × 3
4.7µF × 3
4.7µF × 3
4.7µF × 3
4.7µF × 3
4.7µF × 3
4.7µF × 3
4.7µF × 3
4.7µF × 3
4.7µF × 3
4.7µF × 3
4.7µF × 3
100µF × 2
100µF × 3
5
5
100µF × 1 100µF × 1
22µF × 1 100µF × 1
22µF × 2 100µF × 1
22µF × 1 100µF × 1
22µF × 2 100µF × 1
5
5
5
5
12
12
12
12
12
12
None
None
22µF × 2
22µF × 3
22µF × 1 100µF × 1
22µF × 2 100µF × 1
22µF × 1 100µF × 1
22µF × 2 100µF × 1
*Bulk capacitor is optional if VIN has very low input impedance. Slew rate: 2.5A/µs. **50V
4634f
25
For more information www.linear.com/LTM4634
LTM4634
Typical applicaTions
5V
24V INPUT
+
C
4.7µF
50V
C
4.7µF
50V
C
4.7µF
50V
C
IN3
4.7µF
50V
100µF
50V
IN4
IN1
IN2
4.7µF
6.3V
V
IN1
SW1
V
SW2
V
IN3
SW3 INTV EXTV
CC CC
IN2
2Ω
CNTL_PWR
MODE/PLLIN
RUN1
FREQ/PLLLPF
COMP1
1µF
10k
10k
COMP2
RUN2
COMP3
50k
LTM4634
RUN3
PGOOD12
PGOOD3
TEMP1
TK/SS1
TK/SS2
TK/SS3
TEMP2
C
C
C
SS1
SS2
SS3
0.1µF
V
V
V
V
V
V
FB3
GND SGND
0.1µF
0.1µF
OUT1
FB1
OUT2
FB2
OUT3
4634 F22
V
V
V
FB3
FB1
FB2
R
R
R
FB3
4.32k
FB1
FB2
FOR C , R , COMP AND C
OUT FB
FF
19.1k
11.5k
SEE TABLE 4
C
22µF
16V
OUT9
C
C
C
47pF
3.3V
47pF
5V
47pF
12V
OUT2
OUT7
22µF
OUT4
100µF
100µF
V
FB1
V
FB2
V
FB3
6.3V
16V
6.3V
C
C
22µF
6.3V
C
OUT3
OUT5
OUT8
22µF
100µF
6.3V
16V
Figure 22. LTꢁ4634 Typical 24V Input to 3.3V at 5A, 5V at 5A, 12V at 4A
4634f
26
For more information www.linear.com/LTM4634
LTM4634
Typical applicaTions
24V
+
C
4.7µF
50V
C
IN2
4.7µF
50V
IN1
56µF
50V
12V
C
22µF
16V
C
IN6
IN5
22µF
16V
5V
C
22µF
6.3V
C
22µF
6.3V
IN8
IN9
V
IN1
SW1
V
SW2
V
SW3 INTV EXTV
CC CC
IN2
IN3
CNTL_PWR
MODE/PLLIN
RUN1
FREQ/PLLLPF
COMP1
4.7µF
6.3V
10k
10k
COMP2
5V INPUT
12V INPUT
50k
RUN2
COMP3
120k
C
LTM4634
RUN3
PGOOD12
PGOOD3
TEMP1
TK/SS1
TK/SS2
TK/SS3
C
TEMP2
C
SS1
SS2
0.1µF
SS3
0.1µF
0.1µF
V
OUT1
V
V
V
V
V
FB3
GND SGND
FB1
OUT2
FB2
OUT3
4634 F23
V
V
V
FB3
FB1
FB2
R
R
R
FB1
FB2
FB3
28.7k
69.8k
19.1k
C
C
OUT4
C
OUT1
OUT7
220µF
220µF
100µF
4V
4V
6.3V
2.5V
47pF
1.5V
47pF
3.3V
47pF
C
C
C
OUT8
OUT2
OUT5
100µF
6.3V
220µF
4V
220µF
4V
V
V
V
FB3
FB1
FB2
Figure 23. LTꢁ4634 Triple Input and Triple Output (2.5V, 1.5V and 3.3V) at 5A, 5A and 4A
4634f
27
For more information www.linear.com/LTM4634
LTM4634
Typical applicaTions
24V INPUT
+
C
4.7µF
50V
C
IN7
4.7µF
50V
IN6
56µF
50V
12V
AT 1.2A
OUT
C
22µF
16V
C
22µF
16V
IN4
IN3
5V BIAS
SW3 INTV EXTV
CC
4.7µF
10k
V
SW1
V
SW2
V
IN3
IN1
IN2
CC
2Ω
24V
10k
CNTL_PWR
FREQ/PLLLPF
COMP1
1µF
MODE/PLLIN
10k
COMP2
RUN1
RUN2
COMP3
120k
LTM4634
RUN3
PGOOD12
PGOOD3
TEMP1
24V
TK/SS1
TK/SS2
TK/SS3
TEMP2
C
C
SS3
SS1
V
V
V
V
V
V
FB3
GND SGND
0.22µF
0.1µF
OUT1
FB1
OUT2
C
FB2
OUT3
4634 F24
V
V
FB3
FB1
R
R
FB3
FB1
121k
C
OUT
, SEE TABLE 4
4.32k
C
OUT7
C
R
= (60.4k/2)/(V /0.8) – 1
OUT
OUT1
100µF
6.3V
OUT4
100µF
6.3V
FB1
22µF
16V
C
C
C
OUT2
OUT5
OUT8
22µF
100µF
6.3V
100µF
6.3V
47pF
47pF
16V
1V
V
V
FB1
FB3
C
C
OUT6
100µF
6.3V
OUT3
100µF
6.3V
12V
OUT
12V AT 2.8A
FOR OTHER CIRCUITS
1V AT 10A
Figure 24. 24V to 12V at 2.8A, Then 12V to 1V at 10A
4634f
28
For more information www.linear.com/LTM4634
LTM4634
Typical applicaTions
7V TO 28V INPUT
+
C
4.7µF
50V
C
4.7µF
50V
C
IN1
4.7µF
50V
IN3
IN2
4.7µF
6.3V
35.7k
(400kHz)
5V BIAS
56µF
50V
2Ω
V
IN1
SW1
V
IN2
SW2
V
SW3 INTV EXTV
CC CC
IN3
CNTL_PWR
MODE/PLLIN
RUN1
FREQ/PLLLPF
COMP1
1µF
10k 10k 10k
13.3k
COMP2
3.3V
3.3V
6.04k
RUN2
COMP3
LTM4634
6.04k
RUN3
PGOOD12
PGOOD3
TEMP1
TK/SS1
TK/SS2
TK/SS3
V
V
IN
TEMP2
6.98k
4.87k
C
SS3
0.22µF
R
V
V
V
V
V
V
FB3
GND SGND
T
OUT1
FB1
OUT2
C
FB2
OUT3
C
TO ADC
TO ADC
R
R
R
FB3
19.1k
FB1
FB2
IN
69.8k
48.7k
C
REDUCED TRACKING FEEDBACK
DIVIDER BY A FACTOR OF 10 TO
REDUCE TK/SS CURRENT ERROR
OUT1
OUT2
100µF
6.3V
OUT3
100µF
100µF
R
T
3.3V
6.3V
6.3V
4634 F25
V
IN
C
C
C
OUT4
OUT6
OUT7
R
=
T
1.5V
1.8V
100µA
100µF
6.3V
100µF
6.3V
100µF
6.3V
Figure 25. 7V to 28V Input, 1.5V, 1.8V and 3.3V at 5A,5A, 4A with Tracking
4634f
29
For more information www.linear.com/LTM4634
LTM4634
package DescripTion
LTꢁ4634 Coꢃponent BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION
PIN ID FUNCTION
PIN ID
B1
FUNCTION
PIN ID
E1
FUNCTION
GND
PIN ID FUNCTION
A1
A2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
C1
C2
V
OUT3
V
OUT3
V
OUT3
V
OUT3
D1
D2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
F1
F2
V
V
OUT3
OUT3
OUT3
OUT3
OUT3
OUT3
OUT3
OUT2
OUT2
OUT2
OUT2
OUT1
OUT1
OUT1
OUT1
IN3
IN3
B2
E2
GND
A3
B3
C3
D3
E3
GND
F3
SW3
GND
A4
GND
B4
C4
D4
E4
GND
F4
A5
V
B5
C5
TEMP2
D5
E5
GND
F5
V
V
OUT2
OUT2
OUT2
IN2
IN2
A6
V
V
B6
C6
V
OUT2
V
OUT2
V
OUT2
D6
E6
GND
F6
A7
B7
C7
D7
E7
GND
F7
SW2
GND
A8
GND
GND
B8
C8
D8
E8
GND
F8
A9
B9
C9
TEMP1
D9
E9
GND
F9
V
V
IN1
IN1
A10
A11
A12
V
B10
B11
B12
C10
C11
C12
V
OUT1
V
OUT1
V
OUT1
D10
D11
D12
E10
E11
E12
GND
F10
F11
F12
OUT1
OUT1
OUT1
V
V
GND
SW1
GND
GND
PIN ID FUNCTION
PIN ID
H1
FUNCTION
PIN ID
J1
FUNCTION
GND
PIN ID FUNCTION
PIN ID
L1
FUNCTION
GND
PIN ID FUNCTION
G1
G2
V
IN3
V
IN3
V
IN3
V
IN3
K1
K2
GND
GND
M1
M2
GND
H2
J2
GND
L2
GND
PGOOD12
PGOOD3
COMP1
G3
GND
GND
H3
GND
GND
J3
GND
K3
GND
L3
EXTV
M3
CC
G4
H4
J4
GND
K4
COMP3
L4
COMP2
M4
G5
V
V
H5
V
V
J5
GND
K5
V
L5
V
M5
V
FB1
IN2
IN2
IN2
IN2
FB3
FB2
G6
H6
J6
CNTL_PWR
GND
K6
SGND
SGND
GND
L6
SGND
SGND
M6
GND
GND
G7
GND
GND
H7
GND
GND
J7
K7
L7
M7
G8
H8
J8
INTV
K8
L8
FREQ/PLLLPF
MODE/PLLIN
RUN1
M8
GND
CC
G9
V
IN1
V
IN1
H9
V
IN1
V
IN1
J9
GND
GND
GND
GND
K9
GND
L9
M9
TK/SS1
TK/SS2
TK/SS3
GND
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
GND
L10
L11
L12
M10
M11
M12
GND
GND
GND
GND
RUN3
GND
RUN2
GND
package phoTo
4634f
30
For more information www.linear.com/LTM4634
LTM4634
package DescripTion
Please refer to http://www.linear.coꢃ/designtools/packaging/ for the ꢃost recent package drawings.
Z
/ / b b b
Z
6 . 9 8 2 0
2 . 7 1 2 0
4 . 4 4 2 0
3 . 1 7 2 0
1 . 9 0 2 0
0 . 6 3 2 0
0 . 0 0 0 0
0 . 6 3 2 0
1 . 9 0 2 0
3 . 1 7 2 0
4 . 4 4 2 0
2 . 7 1 2 0
6 . 9 8 2 0
a a a
Z
4634f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
31
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTM4634
Typical applicaTion
24V INPUT
+
C
4.7µF
50V
C
IN7
4.7µF
50V
IN6
56µF
50V
5V
AT 3A
OUT
C
22µF
6.3V
C
22µF
6.3V
IN4
IN3
5V
OUT
4.7µF
30k
V
SW1
V
SW2
V
SW3 INTV EXTV
CC CC
IN1
IN2
IN3
2Ω
24V
CNTL_PWR
FREQ/PLLLPF
COMP1
1µF
MODE/PLLIN
10k 10k
RUN3
10k
COMP2
RUN1
RUN2
COMP3
120k
LTM4634
RUN3
PGOOD12
PGOOD3
TEMP1
24V
TK/SS1
TK/SS2
TK/SS3
TEMP2
C
SS1
0.1µF
C
SS3
0.1µF
V
V
V
V
V
V
GND SGND
OUT1
FB1
OUT2
FB2
OUT3
FB3
4634 F26
V
V
FB1
FB3
C
OUT
SEE TABLE 4
R
FB1
60.4k
R
FB3
11.5k
C
OUT7
C
OUT1
C
OUT4
220µF
4V
100µF
6.3V
220µF
4V
+
C
C
C
22µF
6.3V
OUT2
OUT5
OUT8
220µF
4V
220µF
4V
1.2V
47pF
47pF
V
V
FB3
FB1
5V
OUT
5V AT 1A
FOR OTHER CIRCUITS
Figure 26. 24V to 5V at 1A, Then 5V Output to 1.2V at 10A
relaTeD parTs
PART NUꢁBER DESCRIPTION
COꢁꢁENTS
LTM4633
LTM4630
LTM4644
LTM4676
Triple 10A, 16V Step-Down DC/DC µModule 4.7V ≤ V ≤ 16V, 0.8V ≤ V
≤ 1.8V, 0.8V ≤ V
≤ 5.5V, PLL Input, V
Soft-Start
IN
IN
OUT1,2
OUT3
OUT
Regulator
and Tracking, PGOOD, Internal Temperature Monitor, 15mm × 15mm × 5.01mm BGA
Dual 15V , 18A or Single 36A Step-Down
4.5V ≤ V ≤ 15V, 0.6V ≤ V ≤ 1.8V, PLL Input, Remote Sense Amplifier, V Tracking,
IN
IN
OUT
OUT
µModule Regulator with V
Up to 1.8V
PGOOD, CLKOUT, Internal Temperature Monitor, 16mm × 16mm × 4.41mm LGA
OUT
Quad 4A, 14V Step-Down µModule Regulator 4V ≤ V ≤ 14V, 0.6V ≤ V
≤ 5.5V, CLK Input and Output, V Tracking, PGOOD,
IN
OUT
OUT
with Configurable Output Array
9mm × 15mm × 5.01mm BGA
Dual 13A or Single 26A µModule Regulator
with Digital Power System Management
4.5V ≤ V ≤ 26V, 0.5V ≤ V
≤ 4.0V, 0.5V ≤ V
≤ 5.4V, Digital I/F for Control and
IN
OUT0
OUT1
2
Monitoring, Integrated 16-Bit ADC, PMBus Compliant I C Interface, Remote Sense
Amplifiers, 16mm × 16mm × 5.01mm BGA
LTM8028
LTM4637
LTM8045
36V , UltraFast™, Low Output Noise 5A
6V ≤ V ≤ 36V, 0.8V ≤ V
≤ 1.8V Set Via 3-Pin Three-State Interface, <1mV V
IN
IN
OUT OUT
µModule Regulator
Ripple, 10% Accurate Current Limit, PGOOD, 15mm × 15mm × 4.9mm BGA
20V , 20A DC/DC µModule Step-Down
4.5V ≤ V ≤ 20V, 0.6V ≤ V ≤ 5.5V, PLL Input, V Tracking, Remote Sense Amplifier,
IN
IN
OUT
OUT
Regulator
PGOOD, 15mm × 15mm × 4.32mm LGA and 15mm × 15mm × 4.92mm BGA
Inverting or SEPIC _Module DC/DC Converter 2.8V ≤ V ≤ 18V, 2.5V ≤ V
with Up to 700mA Output Current
≤
15V, Synchronizable, No Derating or Logic-Level Shift
IN
OUT
for Control Inputs When Inverting, 6.25mm × 11.25mm × 4.92mm BGA
0.25% TUE 16-Bit ADC, Voltage/Temperature Monitoring and Supervision
0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision
LTC2977
LTC2974
8-Channel PMBus Power System Manager
4-Channel PMBus Power System Manager
4634f
LT 0814 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4634
LINEAR TECHNOLOGY CORPORATION 2014
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明