LTM4637_技术文档

LTM4645

25A DC/DC Step-Down

µModule Regulator

FeaTures

DescripTion

TheLTM^®4645isa25Aoutputswitchingmodestep-down

DC/DC µModule^®(power module) regulator. Included in

the package are the switching controller, power FETs, in-

ductor and all supporting components. Operating over an

input voltage range of 4.7V to 15V, the LTM4645 supports

an output voltage range of 0.6V to 1.8V, set by a single

external resistor. Only a few input and output capacitors

are needed.

n

4.7V to 15V Input Voltage Range

n

0.6V to 1.8V Output Voltage Range

n

25A DC Output Current

n

1.2ꢀTotalDCOutputVoltageError(–40°Cto125°C)

n

HighReliabilityN+1PhaseRedundancySupported

n

InternalorExternalControlLoopCompensation

n

Differential Remote Sense Amplifier for Precision

Regulation

n

Current Mode Control/Fast Transient Response

Its high efficiency design delivers about 86% efficiency

from 12V input to 1.0V output with 25A continuous load

current. High switching frequency and a current-mode

architecture enable a very fast transient response to line

and load changes without sacrificing stability. The device

supports frequency synchronization, programmable

multiphase operation, N+1 phase redundancy, and output

voltage tracking for supply rail sequencing.

n

Multiphase Current Sharing Up to 150A

n

Built-In Temperature Monitoring

Selectable Pulse-Skipping, Burst Mode^®Operation

n

Soft-Start/Voltage Tracking

n

Frequency Synchronization

n

Output Overvoltage Protection

n

Output Overcurrent Foldback Protection

n

9mm × 15mm × 3.51mm BGA Package

Fault protection features include overvoltage and overcur-

rent protection. The power module is offered in a space

saving 9mm × 15mm × 3.51mm BGA package. The

LTM4645 is available with SnPb (BGA) or RoHS compli-

ant terminal finish.

applicaTions

n

Telecom, Networking and Industrial Equipment

Point of Load Regulation

n

L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, µModule, LTpowerCAD

and PolyPhase are registered trademarks of Analog Devices, Inc. All other trademarks are the

property of their respective owners.

Typical applicaTion

Efficiency vs Output Current

at 1V Output

12V_IN, 1V_OUT, 25A DC/DC µModule Regulator

100

95

4.7µF

1µF

6.3V

2.2Ω

SV

DRV

INTV

90

85

IN

CC

V

IN

V

IN

6V TO 15V

22µF

25V

×2

HIZB

FREQ

LTM4645

80

75

70

65

60

V

OUT

1V

V

OUT

+

25A

43.2k

V

47pF

COMPa

COMPb

OSNS

V

FB

–

100µF

6.3V

×4

TRACK/SS

OSNS

90.9k

5V INPUT

12V INPUT

0.1µF

SGND GND

4645 TA01a

10

15

20

25

0

5

PINS NOT USED IN THIS CIRCUIT:

LOAD CURRENT (A)

CLKOUT, MODE/PLLIN, PGOOD,

+

–

4645 TA01b

PHASMD, PWM, RUN, SW, TEMP , TEMP

4645f

1

For more information www.linear.com/LTM4645

LTM4645

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

TOP VIEW

V , SV , HIZB .......................................... –0.3V to 16V

OUT

IN

1

2

3

4

5

6

7

V

,......................................................... –0.3V to 3.5V

GND GND RUN GND

A

B

C

D

E

F

CLKOUT

INTV , DRV , PGOOD, RUN ..................... –0.3V to 6V

CC

V

IN

PWM

TEST1

+

–

MODE/PLLIN

MODE/PLLIN, TRACK/SS, V

CLKOUT, COMPa, COMPb, V , PHASMD,

, V

,

OSNS

FB

OSNS

DRV

INTV

CC

PHASMD

TEST2

SV

IN

FREQ

FREQ ....................................................–0.3V to INTV

CC

–

GND

HIZB

GND

V

FB

TEMP

TRACK/SS

TEMP

Operating Junction Temperature (Note 2)..–40 to 125°C

Storage Temperature Range ...................... –55 to 125°C

Peak Solder Reflow Body Temperature .................250°C

SGND

SW

+

TEST3

–

+

V

OSNS

PGOOD

G

H

J

+

–

GND

COMPa

TEMP , TEMP .......................................... –0.3V to 0.8V

COMPb

V

GND

OUT

K

L

BGA PACKAGE

77-LEAD (9mm × 15mm × 3.51mm)

= 125°C, θ = 9.5°C/W, θ = 4°C/W, θ

T

= 6.7°C/W, θ = 4.5°C/W

JB

J(MAX)

JA

JCbottom

JCtop

θ

DERIVED FROM 95mm × 76mm PCB WITH SIX LAYERS; WEIGHT = 1.3g

JA

θ VALUES DETERMINED PER JESD51-12

orDer inForMaTion ^{http://www.linear.com/product/LTM4645#orderinfo}

PART MARKING*

PACKAGE

MSL

TEMPERATURE RANGE

(Note 2)

PART NUMBER

LTM4645EY#PBF

LTM4645IY#PBF

LTM4645IY

PAD OR BALL FINISH

SAC305 (RoHS)

SnPb (63/37)

DEVICE

FINISH CODE

TYPE

BGA

RATING

LTM4645Y

e1

e0

3

–40°C to 125°C

Consult Marketing for parts specified with wider operating temperature

ranges. *Device temperature grade is indicated by a label on the shipping

container. Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Recommended LGA and BGA PCB Assembly and Manufacturing

Procedures:

www.linear.com/umodule/pcbassembly

• LGA and BGA Package and Tray Drawings:

www.linear.com/packaging

• Terminal Finish Part Marking:

www.linear.com/leadfree

4645f

2

For more information www.linear.com/LTM4645

LTM4645

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified internal

operating temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 12V, per the typical application.

SYMBOL

PARAMETER

CONDITIONS

MIN

4.7

TYP

MAX

15

UNITS

l

V

Input DC Voltage

Output Voltage Range

V

IN

V

C

= 4.7V to 15V

0.6

1.8

OUT(RANGE)

OUT(DC)

IN

Output Voltage, Total Variation

with Line and Load

= 22µF × 4, C

= 60.4k, MODE = GND,V = 4.7V to 15V, I

= 100µF Ceramic, 470µF POSCAP,

IN

OUT

l

1.186 1.200 1.214

V

R

FB

= 0A to 25A

IN

OUT

Input Specifications

I

Input Supply Bias Current

V

= 12V, V

= 1.2V, Burst Mode Operation, I

= 0A

11

25

170

90

mA

µA

Q(VIN)

IN

OUT

= 1.2V, Pulse-Skipping Mode, I

= 1.2V, Switching Continuous, I

OUT

Shutdown, RUN = 0, V = 12V

IN

I

Input Supply Current

V

= 12V, V

= 1.2V, I = 25A

OUT

3.0

A

S(VIN)

IN

OUT

Output Specifications

I

Output Continuous Current

Range

= 1.2V (Note 4)

0

25

A

OUT(DC)

IN

OUT

l

Line Regulation Accuracy

Load Regulation Accuracy

Output Ripple Voltage

V

= 1.2V, V from 4.7V to 15V, I = 0A

OUT

0.005

0.1

0.05

0.3

%/V

%

∆V

V

/V

OUT

IN

OUT(LINE) OUT

= 1.2V, I

= 0A to 25A, V = 12V (Note 4)

IN

/ V

OUT

OUT(LOAD) OUT

15

mV

C

V

= 100µF Ceramic × 6,

= 1.2V, I

OUT

OUT(AC)

= 12V, V

= 0A

IN

OUT

Turn-On Overshoot

Turn-On Time

20

5

mV

ms

mV

µs

∆V

C

IN

= 100µF Ceramic × 6,

OUT

OUT(START)

OUTLS

V

= 12V, V

= 1.2V, I

OUT

t

C

V

= 100µF Ceramic × 6

START

OUT

IN

= 12V, V

= 1.2V, No Load, TRACK/SS = 0.01µF

OUT

Peak Deviation for Dynamic

Load

Load: 0% to 50% to 0% of Full Load,

= 100µF Ceramic × 6, V = 12V, V

36

15

35

∆V

C

OUT

= 1.2V

IN

OUT

t

Settling Time for Dynamic

Load Step

Load: 0% to 50% to 0% of Full Load,

SETTLE

C

OUT

= 100µF Ceramic × 6, V = 12V, V

IN

I

Output Current Limit

V

IN

= 12V, V

= 1.2V

A

OUTPK

OUT

Control Specifications

Voltage at V Pin

l

V

I

= 0A, V

= 1.2V

594

600

–30

1.25

606

FB

OUT

I

Current at V Pin

(Note 7)

–100

nA

µA

FB

Track Pin Soft-Start Pull-Up

Current

TRACK/SS = 0V

TRACK/SS

t

Minimum On-Time

(Note 3)

90

ns

ON(MIN)

R

FBHI

Resistor Between V

60.05 60.40 60.75

kΩ

OUT_LCL

and V Pins

FB

V

RUN Pin On Threshold

RUN Pin On Hysteresis

Undervoltage Lockout

UVLO Hysteresis

V

Rising

1.2

1.35

180

4

1.45

V

mV

V

RUN

RUNHYS

UVLO

Falling

INTVCC

400

2.3

800

mV

V

HYS

V

HIZB Pin On Threshold

HIZB Pin On Hysteresis

Rising

HIZB

HIZBHYS

mV

4645f

3

For more information www.linear.com/LTM4645

LTM4645

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified internal

operating temperature range, otherwise specifications are at T_A= 25°C (Note 2). V_IN= 12V, per the typical application.

SYMBOL

PGOOD

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

R

PGOOD Pull-Down Resistance

PGOOD Trip Level

90

200

Ω

PGOOD

V

With Respect to Set Output

FB

V

Ramping Negative

Ramping Positive

–7.5

7.5

%

V

PGOOD Voltage Low

I

= 2mA

0.1

0.3

5.7

V

PGL

PGOOD

INTV Linear Regulator

CC

V

Internal V Voltage

V

≥ 12V

5.3

5.5

0.5

V

INTVCC

CC

IN

Load Reg INTV Load Regulation

I

= 0mA to 10mA

%

CC

Oscillator and Phase-Locked Loop

f

I

SYNC Capture Range

Switching Frequency

300

540

1000

660

kHz

µA

kΩ

V

SYNC

SW

R

= 47.5kΩ

= 0.8V

600

20

FREQ

FREQ Pin Current

V

FREQ

R

Mode_PLLIN Input Resistance

Clock Input Level High

Clock Input Level Low

CLKOUT to SW Phase Delay

250

MODE_PLLIN

V

θ

2.0

IH_MODE_PLLIN

IL_MODE_PLLIN

1.2

V

= 0V

90

Deg

PHSMD

CLKOUT

= 1/4 INTV

= Float

CC

120

60

= 3/4 INTV

= INTV

180

CC

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: The minimum on-time condition is specified for a peak-to-peak

inductor ripple current of ~40% of I

Information section)

Load. (See the Applications

MAX

Note 4: See output current derating curves for different V , V

and T .

A

IN OUT

Note 2: The LTM4645 is tested under pulsed load conditions such that

Note 5: Limit current into the RUN pin to less than 2mA.

T ≈ T . The LTM4645E is guaranteed to meet performance specifications

J

A

Note 6: Guaranteed by design.

over the 0°C to 125°C internal operating temperature range. Specifications

over the full –40°C to 125°C internal operating temperature range are

assured by design, characterization and correlation with statistical process

controls. The LTM4645I is guaranteed to meet specifications over the

full –40°C to 125°C internal operating temperature range. Note that the

maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board

layout, the rated package thermal resistance and other environmental

factors.

Note 7: 100% tested at wafer level.

4645f

4

For more information www.linear.com/LTM4645

LTM4645

Typical perForMance characTerisTics

CCM, Burst Mode and Pulse-

Efficiency vs Output Current,

V_IN= 5V

Efficiency vs Output Current,

V_IN= 12V

Skipping Mode Efficiency

V_IN= 12V, V_OUT= 1.2V, 750kHz

100

90

80

70

60

50

40

30

20

10

0

100

95

90

85

80

75

70

65

100

95

90

85

80

75

70

65

0.9V

1V

1.2V

1.5V

1.8V

500kHz

600kHz

700kHz

800kHz

900kHz

0.9V

1V

1.2V

1.5V

1.8V

500kHz

600kHz

700kHz

800kHz

900kHz

OUT

CCM

Burst Mode OPERATION

PULSE-SKIPPING MODE

10

15

20

25

0

5

0.01

0.1

1

10

100

10

15

20

25

0

5

LOAD CURRENT (A)

4645 G03

4645 G02

4645 G01

0.9V Output Load Step Transient

Response

1V Output Load Step Transient

Response

1.2V Output Load Step Transient

Response

V

OUT

50mV/DIV

AC-

50mV/DIV

AC-

COUPLED

LOAD STEP

5A/DIV

LOAD STEP

5A/DIV

LOAD STEP

5A/DIV

4645 G04

4645 G05

4645 G06

50µs/DIV

= 0.9V, F = 500kHz

50µs/DIV

= 1.2V, F = 700kHz

V

C

= 12V, V

OUT

= 33pF

V

C

= 12V, V

OUT

= 33pF

= 1V, F = 600kHz

V

C

= 12V, V

OUT

= 33pF

FF

IN

OUT

S

IN

OUT

S

IN

S

= 6 × 100µF CERAMIC

FF

0A TO 6.25A LOAD STEP, 10A/µs

1.8V Output Load Step Transient

Response

1.5V Output Load Step Transient

Response

V

OUT

50mV/DIV

AC-

50mV/DIV

AC-

COUPLED

LOAD STEP

5A/DIV

LOAD STEP

5A/DIV

4645 G07

4645 G08

50µs/DIV

= 1.5V, F = 800kHz

50µs/DIV

= 1.8V, F = 900kHz

V

C

= 12V, V

OUT

= 33pF

V

C

= 12V, V

OUT

= 33pF

FF

IN

OUT

S

IN

S

= 6 × 100µF CERAMIC

FF

0A TO 6.25A LOAD STEP, 10A/µs

4645f

5

For more information www.linear.com/LTM4645

LTM4645

Typical perForMance characTerisTics

Start-Up with No Load Applied

Start-Up with 25A Load Applied

SW

10V/DIV

SW

10V/DIV

V

OUT

500m/DIV

OUT

500m/DIV

I

IN

200mA/DIV

4645 G09

4645 G10

20ms/DIV

V

C

= 12V, V

OUT

= 0.1µF

= 1.2V, F = 700kHz, NO LOAD

V

C

= 12V, V

OUT

= 0.1µF

SS

= 1.2V, F = 700kHz, NO LOAD

IN

OUT

S

IN

S

= 1 × 47µF CERAMIC + 1 × 470µF SPCAP

SS

4645f

6

For more information www.linear.com/LTM4645

LTM4645

pin FuncTions

PACKAGE ROW AND COLUMN LABELING MAY VARY

external supply 4.5V or above through a 2.2Ω plus 1µF

R-C filter. See the Application Information section.

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

INTV (C6): Internal 5.5V LDO for driving the control

CC

V (A1-A3, B1-B2, C1-C2):PowerInputPins. Applyinput

IN

circuitry decouple with pin to GND with a minimum of

2.2µF low ESR ceramic capacitor. The 5.5V LDO has a

50mA current limit.

voltage between these pins and GND pins. Recommend

placing input decoupling capacitance directly between V

pins and GND pins.

IN

PHASMD (C7): This pin determines the relative phases

between the internal controller and the CLKOUT signal.

See Table 2 in the Application Information section.

GND (A4, A7, B3, C3, C4, D1-D4, E2-E4, F2, F4, F6, G1-

G4, H1-H5, J5-J7, K5-K7): Ground Pins for Both Input

and Output Returns. All ground pins need to connect with

large copper areas underneath the unit.

FREQ (D7): Frequency Set Pin. A 20µA current is sourced

from this pin. A resistor from this pin to ground sets a

voltage that in turn programs the operating frequency.

Alternatively, this pin can be driven with a DC voltage

that can set the operating frequency. See the Applications

Information section.

RUN (A6): Run Control Pin. A voltage above 1.35V will

turn on the module. This is a 1µA pull-up current on this

pin. Once the RUN pin rises above the 1.35V threshold

the pull-up current increases to 5µA.

PWM (B4): Control PWM Three-State Output Signal. For

HIZB(E5):PhaseSheddingInputPin.Whenthispinislow,

monitor and test purpose only. Do not drive this pin.

TRACK/SS, COMP and PWM pin go to high impedance.

Tie to INTV or V to disable this function.

CC

IN

CLKOUT (B5): Clock output with phase control using the

PHASMD pin to enable multiphase operation between

devices. See the Applications Information section.

V

(E6): The Negative Input of the Error Amplifier. Inter-

FB

+

nally, this pin is connected to V

with a 60.4k 0.5%

OSNS

precision resistor. Different output voltages can be pro-

TEST1, TEST2, TEST3 (B6, D5, F7): These pins are for

µModule initial test purposes. Please connect these pins

to GND with a large GND copper area.

grammed with an additional resistor between V and

FB

–

V

pins. In PolyPhase^®operation, tying the V pins

SNS

togetherallowsforparalleloperation.SeetheApplications

MODE/PLLIN (B7): Mode Selection Pin and External

Synchronization Pin. Connect this pin to SGND to force

the module into force continuous current mode (CCM) of

Information section for details.

SGND (E7): Signal Ground Pin. Return ground path for all

analog and low power circuitry. Tie a single connection

to the output capacitor GND in the application. See layout

guidelines in Figure 22.

operation. Connect to INTV to enable pulse-skipping

CC

mode of operation. Leaving the pin floating will enable

Burst Mode operation. A clock on the pin will force the

module into continuous current mode of operation and

synchronized to the external clock applied to this pin. See

the Applications Information section.

SW (F3): Switching node of the circuit is used for testing

purposes. Also an R-C snubber network can be applied

to reduce or eliminate switch node ringing, or otherwise

leave floating. See the Applications Information section.

SV (D6): Signal V . Input voltage to the internal 5.5V

IN

regulator for the control circuitry of the regulator. Tie this

TRACK/SS(F5):OutputVoltageTrackingPinandSoft-Start

Inputs. The pin has a 1.25µA pull-up current. A capacitor

from this pin to ground will set a soft-start ramp rate. In

tracking, the regulator output can be tracked to a different

voltage. The voltage ramp rate at his pin sets the voltage

ramp rate of the output. See the Applications Information

section.

pin to V pin through a 2.2Ω plus 1µF R-C filter in most

IN

application. See the Application Information section.

DRV (C5): Power Input Pin for the MOSFET driver cir-

CC

cuitry. Connect to INTV output for the application with

CC

the input voltage 6V and above or connect this pin to an

4645f

7

For more information www.linear.com/LTM4645

LTM4645

pin FuncTions

–

V

(G5): Input to the Remote Sense Amplifier. This

connect an R-C compensation network from COMPa to

SGND. Tie COMPa pins together in parallel operation. See

the Applications Information section.

OSNS

pin connects to the ground remote sense point at the

output load.

+

V

OSNS

(G6): Input to the Remote Sense Amplifier. In-

COMPb(H7):InternalLoopCompensationNetworks.Tieto

COMPatoprovideinternalloopcompensationformajority

ofapplications.Floatthispinifinternalloopcompensation

not used. See COMPa description.

ternally, this pin is connected to V with a 60.4k 0.5%

precision resistor.

FB

PGOOD (G7): Output Voltage Power Good Indicator.

Open-drain logic output that is pulled to ground when the

output voltage is not within 7.5% of the regulation point.

V

OUT

(J1-J4, K1-K4, L1-L7): Power Output Pins. Apply

outputloadbetweenthesepinsandGNDpins.Recommend

placing output decoupling capacitance directly between

these pins and GND pins. See Table 1.

COMPa (H6): Current Control Threshold and Error Am-

plifier Compensation Point. The current comparator

threshold increases with this control voltage. Small filter

capacitor (10pF) internal to LTM4645 on this pin provides

good noise rejection in the control loop. Tie to COMPb

pin to use internal compensation in the vast majority of

applications. Whereas, when more specialized applica-

tions require an optimization of control loop response,

+

TEMP (F1): Temperature Monitor. An internal diode con-

nected PNP transistor. See the Applications Information

section.

–

TEMP (E1):LowSideoftheInternalTemperatureMonitor.

4645f

8

For more information www.linear.com/LTM4645

LTM4645

block DiagraM

2.2Ω

1µF

RUN

HIZB

CLKOUT

INTV

CC

COMPa

COMPb

PGOOD

10pF

3300pF

47pF

2k

V

IN

V

IN

6V TO 15V

+

2.2µF

SV

C

IN

M1

90nH

V

PHASMD

FREQ

OUT

V

OUT

1V

25A

1µF

M2

POWER

CONTROL

C

OUT

R

FREQ

GND

48.7k

SGND

INTV

CC

INTV

CC

–

V

INTV

–

+

SNS

CC

4.7µF

0.1µF

DIFF

AMP

90.9k

DVRV

CC

V

FB

TRACK/SS

60.4k

0.1µF

+

V

SNS

MODE/PLLIN

4645 F01

Figure 1. Simplified LTM4645 Block Diagram

Decoupling requireMenTs

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

C

IN

External Input Capacitor Requirement

IN

I

= 25A

44

µF

OUT

(V = 4.7V to 15V, V

= 1V)

OUT

C

External Output Capacitor Requirement

(V = 4.7V to 15V, V = 1V)

I

= 25A

300

µF

OUT

IN

OUT

4645f

9

For more information www.linear.com/LTM4645

LTM4645

operaTion

Power Module Description

monitor protects the output voltage in the event of an

overvoltage >10%. The top MOSFET is turned off and the

bottom MOSFET is turned on until the output is cleared.

The LTM4645 is a high performance single output stand-

alone nonisolated switching mode DC/DC power supply.

It can provide a 25A output with few external input and

output capacitors. This module provides precisely regu-

lated output voltages programmable via external resistors

from 0.6V DC to 1.8V DC over a 4.7V to 15V input range.

The typical application schematic is shown in Figure 23

and Figure 24.

Pulling the RUN pin below 1.35V forces the regulator into

a shutdown state. The TRACK/SS pin is used for pro-

gramming the output voltage ramp and voltage tracking

during start-up. See the Application Information section.

Multiphase operation can be easily employed by cascad-

ing the MODE/PLLIN input to the CLKOUT output. See the

ApplicationsInformationsectionandFigure25forexample.

The LTM4645 has an integrated constant-frequency cur-

rentmoderegulator,powerMOSFETs, inductor,andother

supportingdiscretecomponents.Theswitchingfrequency

range is optimized from 400kHz to 900kHz, depending on

outputvoltage.Forswitchingnoise-sensitiveapplications,

it can externally program to or be synchronized to a clock

from 300kHz to 1MHz subject to minimum on-time and

inductor ripple current limitations. See the Applications

Information section.

For high reliability environment, N+1 phase redundancy

canbeeasilyimplementedinLTM4645togetherwithahot

swap controller, such as the LTC^®4226, for extra system

protection. By connecting the HIZB pin to the gate of the

hot swap switch, any fault channel can be disconnected

while the rest of the system is not affected. See Applica-

tions Information section and Figure 27 for example.

High efficiency at light loads can be accomplished with

phasesheddinginmultiphaseoperationorwithselectable

pulse-skipping mode or Burst Mode operation in single

phase operation. Efficiency graphs are provided for light

load operation in the Typical Performance Characteristics

section.

The LTM4645 is designed to use either external or internal

controlloopcompensationbyshortingCOMPbandCOMPa

pins together. With current mode control, the internal

loop compensation has sufficient stability margins and

good transient performance with a wide range of output

capacitors, even with all ceramic output capacitors. Table

5 provides a guideline for input and output capacitances

for several different output conditions using the internal

loop compensation. The LTpowerCAD^®design tool is

available to download for optimizing the loop stability and

transient response.

Aremotesenseamplifierisprovidedforaccuratelysensing

output voltages at the load point.

+

–

ATEMP andTEMP pinsareprovidedtoallowtheinternal

device temperature to be monitored using an onboard

diode connected PNP transistor.

Currentmodecontrolprovidescycle-by-cyclefastcurrent

limit in an overcurrent condition. An internal overvoltage

4645f

10

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

In multiphase single output application. Only one set of

differentialsensingamplifierandonesetoffeedbackresis-

The typical LTM4645 application circuit is shown in

Figure 23 and Figure 24. External component selection

is primarily determined by the maximum load current

and output voltage. Refer to Table 5 for specific external

capacitor requirements for particular applications.

tor are required while connecting V , V and COMP of

OUT FB

different channels together. See Figure 25 for paralleling

application.

Input Capacitors

V to V

Step-Down Ratios and Minimum On-Time

IN

OUT

The LTM4645 module should be connected to a low

AC-impedance DC source. Additional input capacitors

are needed for the RMS input ripple current rating. The

There are restrictions in the V to V

that can be achieved for a given input, output voltage

and frequency. The minimum on-time, t , limits

the smallest time duration that the module is capable of

turning on the top MOSFET. It is determined by internal

timing delays, and the gate charge required turning on

the top MOSFET. At very low duty cycles, the minimum

90nson-timemustbemaintainedandsatisfytheequation:

step-down ratio

IN

OUT

ON(MIN)

I

equation which follows can be used to calculate

CIN(RMS)

the input capacitor requirement. Typically 22µF ceramics

are a good choice with RMS ripple current ratings of ~2A

each.A47µFto100µFsurfacemountaluminumelectrolytic

bulkcapacitorcanbeusedformoreinputbulkcapacitance.

This bulk input capacitor is only needed if the input source

impedanceiscompromisedbylonginductiveleads,traces

ornotenoughsourcecapacitance.Iflowimpedancepower

planes are used, then this bulk capacitor is not needed.

V_OUT

t_ON

=

> 90ns

V •FREQ

IN

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the output ripple voltage of inductor ripple and current

will increase. The minimum on-time can be increased by

lowering the switching frequency.

For a buck converter, the switching duty cycle can be

estimated as:

V_OUT

D=

V

IN

Without considering the inductor ripple current, for each

output, the RMS current of the input capacitor can be

estimated as:

Output Voltage Programming

ThePWM controllerhasaninternal0.6V referencevoltage.

As shown in the Block Diagram, a 60.4k, 0.5% accuracy

I

+

^OUT(MAX)• D• 1–D

internal feedback resistor connects from the V

OSNS

I_CIN(RMS)

=

(

)

η%

to the V pin.

FB

The output voltage will default to 0.6V with no feedback

In the previous equation, η% is the estimated efficiency of

the power module. The bulk capacitor can be a switcher-

rated electrolytic aluminum capacitor or a Polymer

capacitor.

–

resistor. Adding a resistor R from V to V

pro-

FB

OSNS

grams the output voltage:

60.4k+ R_FB

V_OUT= 0.6V •

R_FB

Output Capacitors

Table 1. V_FBResistor Table vs Various Output Voltages

The LTM4645 is designed for low output voltage ripple

noise. The bulk output capacitors defined as C

are

V

(V)

0.6

OPEN

400

0.9

121

500

43.2

1.0

90.9

600

48.7

1.2

60.4

700

53.6

1.5

40.2

800

59

1.8

30.1

900

64.9

OUT

chosen with low enough effective series resistance (ESR)

to meet the output voltage ripple and transient require-

R

FB

(kΩ)

Frequency (kHz)

(kΩ)

ments.C

canbealowESRtantalumcapacitor,lowESR

R

37.4

OUT

FREQ

Polymercapacitororceramiccapacitors.Pleasenotesmall

4645f

11

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

22pF to 47pF feedforward capacitor (C ) is necessary for

Pulse-Skipping Mode Operation

FF

all ceramic output application to achieve enough phase

margin.Thetypicaloutputcapacitancerangeisfrom400µF

to 800µF. Additional output filtering may be required by

the system designer if further reduction of output ripple

or dynamic transient spikes is required. Table 5 shows a

matrix of different output voltages and output capacitors

to minimize the voltage droop and overshoot during a 6A/

µstransient(at10A/µsslewrate).Thetableoptimizestotal

equivalent ESR and total output capacitance to optimize

the transient performance. Multiphase operation will re-

duce effective output ripple as a function of the number

of phases. Application Note 77 discusses this reduction

versus output ripple current cancellation. But the output

capacitance should be considered carefully as a function

of stability and transient response. The Linear Technology

LTpowerCAD Design Tool can calculate the output ripple

reductionasthenumberofimplementedphase’sincreases

by N times and provide stability analysis.

Inapplicationswherelowoutputrippleandhighefficiency

at intermediate currents are desired, pulse-skipping

mode should be used. Pulse-skipping operation allows

the LTM4645 to skip cycles at low output loads, thus

increasing efficiency by reducing switching loss. Tying

the MODE_PLLIN pin to INTV enables pulse-skipping

CC

operation. With pulse-skipping mode at light load, the

internalcurrentcomparatormayremaintrippedforseveral

cycles, thus skipping operation cycles. This mode has

lower ripple than Burst Mode operation and maintains a

higher frequency operation than Burst Mode operation.

Forced Continuous Operation

In applications where fixed frequency operation is more

critical than low current efficiency, and where the lowest

output ripple is desired, forced continuous operation

should be used. Forced continuous operation can be

enabled by tying the MODE_PLLIN pin to GND. In this

mode, inductor current is allowed to reverse during low

outputloads,theCOMPavoltageisincontrolofthecurrent

comparator threshold throughout, and the top MOSFET

alwaysturnsonwitheachoscillatorpulse.Duringstart-up,

forced continuous mode is disabled and inductor current

is prevented from reversing until the LTM4645’s output

voltage is in regulation.

Burst Mode Operation

TheLTM4645iscapableofBurstModeoperationinwhich

the power MOSFETs operate intermittently based on load

demand, thus saving quiescent current. For applications

where maximizing the efficiency at very light loads is a

high priority, Burst Mode operation should be applied. To

enableBurstModeoperation,simplyfloattheMODE_PLLIN

pin. During Burst Mode operation, the peak current of the

inductorissettoapproximatelyone-thirdofthemaximum

peak current value in normal operation even though the

voltage at the COMPa pin indicates a lower value. The

voltage at the COMPa pin drops when the inductor’s aver-

age current is greater than the load requirement. As the

COMPa voltage drops below 0.5V, the burst comparator

trips, causing the internal sleep line to go high and turn

off both power MOSFETs.

Frequency Selection

TheLTM4645deviceisoperatedoverarangeoffrequencies

toimprovepowerconversionefficiency.Itisrecommended

to operate the lower output voltages or lower duty cycle

conversions at lower frequencies to improve efficiency by

lowering power MOSFET switching losses. Higher output

voltages or higher duty cycle conversions can be operated

at higher frequencies to limit inductor ripple current. The

efficiencygraphswillshowanoperatingfrequencychosen

for that condition. See Table 1 for optimized frequency for

various output voltages.

In sleep mode, the internal circuitry is partially turned

off, reducing the quiescent current. The load current is

now being supplied from the output capacitors. When the

output voltage drops, causing COMPa to rise, the internal

sleep line goes low, and the LTM4645 resumes normal

operation. The next oscillator cycle will turn on the top

power MOSFET and the switching cycle repeats.

The LTM4645 switching frequency can be set with an

external resistor from the f

pin to SGND. An accurate

SET

20µA current source into the resistor will set a voltage

that programs the frequency or a DC voltage can be

applied.Figure2showsagraphoffrequencysettingverses

programming voltage.

4645f

12

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

1300

1100

900

Multiphase Operation

For outputs that demand more than 25A of load current,

multiple LTM4645 devices can be paralleled to provide

more output current without increasing input and output

voltage ripple.

700

500

300

100

TheMODE_PLLINpinallowstheLTM4645tosynchronize

to an external clock (between 300kHz and 1MHz) and the

internal phase-locked loop allows the LTM4645 to lock

onto an incoming clock phase as well. The CLKOUT signal

can be connected to the MODE_PLLIN pin of the following

stage to line up both the frequency and the phase of the

0.4 0.6

0.8 1.0 1.2

(V)

1.4

1.6

1.8

V

FREQ

4645 F02

Figure 2. Relationship Between Switching Frequency

and FREQ Pin Voltage

entire system. Tying the PHASMD pin to INTV , three-

CC

PLL and Frequency Synchronization

fourths of INTV , floating or, SGND generates a phase

CC

difference (between V

and CLKOUT) of 180 degrees,

OUT

Forsomeswitchingnoisesensitiveapplications,LTM4645

can be synchronized from 300kHz to 1MHz subject to

minimum on-time and inductor current ripple limitation

with an input clock that has a high level above 2V and a

low level below 0.8V at the MODE_PLLIN pin. Once the

LTM4645 is synchronizing to an external clock frequency,

it will always be running in forced continuous current

operation. The 300kHz low end operation frequency limit

is suggested to limit inductor ripple current.

60 degrees, 120 degrees, 90 degrees respectively. A total

of 12 phases can be cascaded to run simultaneously with

respect to each other by programming the PHASMD pin

of each LTM4645 channel to different levels. Figure 3

shows a 2-phase, 3-phase, 4-phase, and 6-phase design

example for clock phasing.

TWO PHASE

PHASE SELECTION

0 PHASE

180 PHASE

V

CLKOUT PHASMD

OUT

MODE_PLLIN CLKOUT

LTM4645

PHASMD

MODE_PLLIN CLKOUT

LTM4645

PHASMD

PHASE PHASE

(V)

0

90

120

60

INTV

V

INTV

CC

V

OUT

CC

OUT

1/4 INTV

FLOAT

3/4 INTV

CC

THREE PHASE

CC

0 PHASE

120 PHASE

240 PHASE

180

INTV

CC

MODE_PLLIN CLKOUT

LTM4645

MODE_PLLIN CLKOUT

LTM4645

MODE_PLLIN CLKOUT

LTM4645

PHASMD

V

PHASMD

V

PHASMD

V

OUT

FOUR PHASE

0 PHASE

90 PHASE

180 PHASE

270 PHASE

MODE_PLLIN CLKOUT

LTM4645

MODE_PLLIN CLKOUT

LTM4645

MODE_PLLIN CLKOUT

LTM4645

MODE_PLLIN CLKOUT

LTM4645

PHASMD

V

PHASMD

V

PHASMD

V

PHASMD

V

OUT

SIX PHASE

60 PHASE

0 PHASE

120 PHASE

INTV

CC

MODE_PLLIN CLKOUT

LTM4645

MODE_PLLIN CLKOUT

LTM4645

MODE_PLLIN CLKOUT

LTM4645

R2

10k

3/4 INTV

CC

PHASMD

V

3/4 INTV

PHASMD

V

OUT

3/4 INTV

PHASMD

V

OUT

CC

R1

30.1k

180 PHASE

240 PHASE

300 PHASE

MODE_PLLIN CLKOUT

LTM4645

MODE_PLLIN CLKOUT

LTM4645

MODE_PLLIN CLKOUT

LTM4645

3/4 INTV

PHASMD

V

PHASMD

V

PHASMD

V

OUT

CC

OUT

4645 F03

Figure 3. Phase Selection Examples

4645f

13

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

The LTM4645 device is an inherently current mode con-

trolled device, so parallel modules will have good current

sharing.Thiswillbalancethethermalsinthedesign.Tiethe

Input RMS Ripple Current Cancellation

Application Note 77 provides a detailed explanation of

multiphase operation. The input RMS ripple current can-

cellation mathematical derivations are presented, and a

graph is displayed representing the RMS ripple current

reductionasafunctionofthenumberofinterleavedphases

(see Figure 4).

COMPa, V , TRACK/SS and RUN pins of each LTM4645

FB

together to share the current evenly. Figures 25 and 28

show a schematic of the parallel design.

Table 2. PHASMD and CLKOUT Signal Relationship

PHASMD

CLKOUT

GND 1/4 INTV

FLOAT

3/4 INTV

INTV

CC

Soft-Start And Output Voltage Tracking

90°

120°

60°

180°

The TRACK/SS pin provides a means to either soft-start

the regulator or track it to a different power supply. A ca-

pacitor on the TRACK/SS pin will program the ramp rate

of the output voltage. An internal 1.25µA current source

will charge up the external soft-start capacitor towards

A multiphase power supply could significantly reduce

the amount of ripple current in both the input and output

capacitors. The RMS input ripple current is reduced by,

and the effective ripple frequency is multiplied by, the

number of phases used (assuming that the input voltage

isgreaterthanthenumberofphasesusedtimestheoutput

voltage). The output ripple amplitude is also reduced by

the number of phases used.

INTV voltage. When the TRACK/SS voltage is below

CC

0.6V, it will take over the internal 0.6V reference voltage

to control the output voltage. The total soft-start time can

be calculated as:

C_SS

t_SS= 0.6•

1.25µA

0.60

1 PHASE

2 PHASE

0.55

3 PHASE

4 PHASE

6 PHASE

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY CYCLE (V /V

)

4645 F04

OUT IN

Figure 4. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six µModule Regulators (Phases)

4645f

14

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

where C is the capacitance on the TRACK/SS pin. Cur-

outputvoltageandthemasteroutputvoltageshouldsatisfy

the following equation during start-up:

SS

rent foldback and forced continuous mode are disabled

during the soft-start process.

R_FB(SL)

V_OUT(SL)

•

=

Outputvoltagetrackingcanalsobeprogrammedexternally

using the TRACK/SS pin. The output can be tracked up

and down with another regulator. Figure 5 and Figure 6

show an example waveform and schematic of ratiometric

tracking where the slave regulator’s output slew rate is

proportional to the master’s.

R_FB(SL)+ 60.4k

R_TR(BOT)

V_OUT(MA)

•

R_TR(TOP)+ R_TR(BOT)

The R

TR(BOT)

is the feedback resistor and the R

/

TR(TOP)

FB(SL)

R

is the resistor divider on the TRACK/SS pin of

the slave regulator, as shown in Figure 6.

MASTER OUTPUT

SLAVE OUTPUT

Following the previous equation, the ratio of the master’s

output slew rate (MR) to the slave’s output slew rate (SR)

is determined by:

R_FB(SL)

R_FB(SL)+ 60.4k

MR

SR

=

R_TR(BOT)

4645 F05

TIME

R_TR(TOP)+ R_TR(BOT)

Figure 5. Output Ratiometric Tracking Waveform

For example, V

OUT(SL)

could solve that R

are a good combination for the ratiometric tracking. The

TRACK/SS pin will have the 2.5μA current source on when

a resistive divider is used to implement tracking on the

= 1.5V, MR = 1.5V/1ms and

OUT(MA)

V

= 1.2V, SR = 1.2V/1ms, from the equation, we

Since the slave regulator’s TRACK/SS is connected to

= 60.4k and R

= 40.2k

TR(TOP)

TR(BOT)

the master’s output through a R

/R

resistor

TR(TOP) TR(BOT)

divider and its voltage used to regulate the slave output

voltage when TRACK/SS voltage is below 0.6V, the slave

V

IN

6V TO 15V

2.2Ω

1µF

4.7µF

6.3V

4.7µF

6.3V

SV

DRV INTV

CC

SV

DRV INTV

CC CC

IN

CC

IN

V

IN

HIZB

IN

HIZB

22µF

25V

×2

22µF

25V

×2

V

1.5V

25A

TR(TOP)

60.4k

V

1.2V

25A

OUT

V

MODE/PLLIN

V

OUT

+

OUT

+

MODE/PLLIN

100µF

6.3V

×2

FB(SL)

60.4k

LTM4645

V

LTM4645

V

OSNS

V

OSNS

V

6.3V

R

×2

TRACK/SS

COMPa

COMPb

FREQ

FB

–

FB

–

+

330µF

6.3V

×2

+

330µF

6.3V

×2

R

FB(MA)

0.1µF

47.5k

TRACK/SS

COMPa

COMPb

FREQ

OSNS

40.2k

R

TR(BOT)

40.2k

4645 F06

SGND GND

47.5k

PINS NOT USED IN THESE CIRCUITS:

CLKOUT, PGOOD, PHASMD, RUN, SW

Figure 6. Example Schematic of Ratiometric Output Voltage Tracking

4645f

15

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

In parallel operation the RUN pins can be tie together and

controlled from a single control. The RUN pin can also be

left floating. The RUN pin has a 1µA pull-up current source

that increases to 5µA during ramp-up. Please note that

the RUN pin has an ABSMAX voltage of 6V.

slave regulator. This will impose an offset on the TRACK/

SS pin input. Smaller value resistors with the same ratios

as the resistor values calculated from the above equation

can be used. For example, where the 60.4k is used then

a 6.04k can be used to reduce the TRACK/SS pin offset

to a negligible value.

Differential Remote Sense Amplifier

The coincident output tracking can be recognized as a

special ratiometric output tracking in which the master’s

output slew rate (MR) is the same as the slave’s output

slew rate (SR), waveform as shown in Figure 7.

Anaccuratedifferentialremotesenseamplifierisbuildinto

the LTM4645 to sense output voltages accurately at the

remote load points. This is especially true for high current

+

–

loads. It is very important that the V

and V

are

OSNS

connected properly at the remote output sense point, and

the feedback resistor R is connected to between V

FB

MASTER OUTPUT

SLAVE OUTPUT

–

pin to V

pin. Review the schematics in Figure 23

OSNS

for reference.

In multiphase single output application. Only one set of

differential sensing amplifier and one set of feedback

resistor are required while connecting RUN, TRACK/SS,

V

, V and COMPa of different channels together. See

OUT FB

Figure 25 for paralleling application.

4645 F07

TIME

Power Good

Figure 7. Output Coincident Tracking Waveform

The PGOOD pins are open-drain pins that can be used to

monitor valid output voltage regulation. This pin monitors

a 7.5% window around the regulation point. A resistor

can be pulled up to a particular supply voltage no greater

than 6V maximum for monitoring.

From the equation, we could easily find that, in coincident

tracking,theslaveregulator’sTRACK/SSpinresistordivider

is always the same as its feedback divider:

R_FB(SL)

R_TR(BOT)

Overvoltage and Overcurrent Protection

=

R_FB(SL)+ 60.4k R_TR(TOP)+ R_TR(BOT)

The LTM4645 has over current protection (OCP) in a

short circuit. The internal current comparator threshold

folds back during a short to reduce the output current. An

overvoltage condition (OVP) above 10% of the regulated

outputvoltagewillforcethetopMOSFEToffandthebottom

MOSFET on until the condition is cleared. Foldback cur-

rent limit is disabled during soft-start or tracking start-up.

For example, R

= 60.4k and R

= 60.4k is a

TR(TOP)

TR(BOT)

good combination for coincident tracking for a V

OUT(MA)

=1 .5V and V

= 1.2V application.

OUT(SL)

Run Enable

The RUN pin has an enable threshold of 1.45V maximum,

typically 1.35V with 180mV of hysteresis. It controls the

turn-on of the µModule. The RUN pin can be pulled up to

Pre-Biased Output Start-Up

In the application that require the power supply to start

up with a pre-bias on the output capacitors, the LTM4645

module can safely power up into a pre-biased output

without discharging it.

V for 5V operation, or a 5V Zener diode can be placed

IN

on the pin and a 10k to 100k resistor can be placed up to

higher than 5V input for enabling the µModule. The RUN

pin can also be used for output voltage sequencing.

4645f

16

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

The LTM4645 accomplishes this by disabling both the top

where f is the resonant frequency of the ring, and L is the

total parasitic inductance in the switch path. If a resistor

is selected that is equal to Z, then the ringing should be

dampened. The snubber capacitor value is chosen so that

itsimpedanceisequaltotheresistorattheringfrequency.

Calculated by:

and bottom MOSFETs until the TRACK/SS pin voltage and

theinternalsoft-startvoltageareabovetheV pinvoltage.

FB

N+1 Phase Redundancy and Hot Swap

The HIZB pin can be used to force both top and bottom

MOSFETtoturnoffwhilenotpullingdowntheCOMPaand

TRACK/SS pins. In a multiphase system N+1 redundancy

can be achieved via the HIZB pin. When combined with a

hot swap controller, such as the LTC4211, the HIZB pin

could be connected to the gate of the hot swap switch.

When a damaged MOSFET triggers the hot swap control-

ler, it also disables the corresponding channel’s power,

disconnecting it. Since COMPa and TRACK/SS pins are

unaffected, it does not affect the rest of the system. The

propagationdelayfromHIZBfallingtobothtopandbottom

MOSFET turned off is <200ns. See Figure 27 for example.

1

Z_C=

2π •f•C

These values are a good place to start. Modification to

these components should be made to attenuate the ring-

ing with the least amount the power loss.

Stability Compensation

The LTM4645 has already been internally optimized and

compensated for all output voltages and capacitor combi-

nations including all ceramic capacitor applications when

COMPb is tied to COMPa. Please note that a 22pF to

SW Pins and Snubbering Circuit

47pF feedforward capacitor (C ) is required connecting

FF

from V

to V pin for all ceramic capacitor application

The SW pin is generally for testing purposes by monitor-

ing the pin. The SW pin can also be used to dampen out

switchnoderingingcausedbyLCparasiticintheswitched

current path. Usually a series R-C combination is used

called a snubber circuit. The resistor will dampen the

resonance and the capacitor is chosen to only affect the

high frequency ringing across the resistor.

OUT

FB

to achieve high bandwidth control loop compensation

with enough phase margin. Table 5 is provided for most

application requirements using the optimized internal

compensation. For specific optimized requirement, dis-

connect COMPb from COMPa and apply a Type II C-R-C

compensation network from COMPa to SGND to achieve

external compensation. The LTpowerCAD design tool is

available to download online to perform specific control

loopoptimizationandanalyzethecontrolstabilityandload

transient performance.

If the stray inductance or capacitance can be measured or

approximated then a somewhat analytical technique can

be used to select the snubber values. The inductance is

usuallyeasiertopredict.Itcombinesthepowerpathboard

inductance in combination with the MOSFET interconnect

bond wire inductance.

SV , PV , INTV AND DRV

CC

IN

CC

SV is the filtered input voltage to the internal 5.5V LDO

IN

First the SW pin can be monitored with a wide bandwidth

scope with a high frequency scope probe. The ring fre-

quency can be measured for its value. The impedance Z

can be calculated:

regulator to power the control circuitry of the regulator.

Connect SV to V through a 2.2Ω and 1µF R-C filter.

IN

INTV is the output of the 5.5V LDO. Decouple it with

CC

a minimum 2.2µF ceramic capacitor. Connect INTV to

CC

Z = 2π • f • L

L

SV directly if SV is less than 6V.

IN

PV is the power input connected to power MOSFETs and

IN

the DRV is the supply voltage for the driver circuity to

CC

drive both power MOSFETs. DRV could connect to an

CC

4645f

17

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

external supply higher than 4.5V or V (V < 6V) directly

and by definition must always be less than I . Combining

IN IN

D

through a 2.2Ω plus 1µF R-C filter. In the application with

all of the constants into one term:

the input voltage 6V or above, DRV could also connect

CC

η •k

K_D=

q

to INTV 5.5V output directly.

CC

See Figure 23 for a typical application circuit for input 6V

or above. See Figure 24 for a typical application circuit for

input from 4.7V to 5.5V.

−5

where K = 8.62 • 10 , and knowing ln(I /I ) is always

D

D S

positive because I is always greater than I , leaves us

with the equation that:

D

S

Please note that INTV and DRV has 6V ABSMAX

CC

I

I_S

voltage rating.

V = T KELVIN •K •In ^D

(

)

D

Temperature Monitoring

where V appears to increase with temperature. It is com-

D

Measuring the absolute temperature of a diode is pos-

sible due to the relationship between current, voltage

and temperature described by the classic diode equation:

mon knowledge that a silicon diode biased with a current

source has an approximate –2mV/°C temperature rela-

tionship (Figure 8), which is at odds with the equation. In













V_D

η •V

fact, the I term increases with temperature, reducing the

S

I_D= I_S•e

ln(I /I ) absolute value yielding an approximate –2mV/°C

D S

T

composite diode voltage slope.

or

To obtain a linear voltage proportional to temperature

we cancel the I variable in the natural logarithm term to

S

I

V_D= η •V_T•In ^D

remove the I dependency from the equation 1. This is

S

I_S

accomplished by measuring the diode voltage at two cur-

rents I , and I , where I = 10 • I ) and subtracting we get:

1

2

1

2

where I is the diode current, V is the diode voltage, η

D

is the ideality factor (typically close to 1.0) and I (satura-

S

I

2

1

∆V_D= T(KELVIN)•K •IN –T(KELVIN)•K •IN

tion current) is a process dependent parameter. V can

T

D

I

S

be broken out to:

0.8

0.7

0.6

0.5

0.4

0.3

k •T

V_T=

q

where T is the diode junction temperature in Kelvin, q is

the electron charge and k is Boltzmann’s constant. V is

T

approximately 26mV at room temperature (298K) and

scales linearly with Kelvin temperature. It is this linear

temperature relationship that makes diodes suitable tem-

perature sensors. The I term in the previous equation is

S

the extrapolated current through a diode junction when

–50 –25

0

25

50

75 100 125

the diode has zero volts across the terminals. The I term

S

TEMPERATURE (°C)

4645 F08

varies from process to process, varies with temperature,

Figure 8. Diode Voltage V_Dvs Temperature T(°C)

4645f

18

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

Combining like terms, then simplifying the natural log

terms yields:

sectionare, inandofthemselves, notrelevanttoproviding

guidance of thermal performance; instead, the derating

curves provided in this data sheet can be used in a man-

ner that yields insight and guidance pertaining to one’s

applicationusage, andcanbeadaptedtocorrelatethermal

performance to one’s own application.

∆V = T(KELVIN) • K • lN(10)

D

and redefining constant

198µV

K' = K •IN(10) =

D

The Pin Configuration section gives four thermal coeffi-

cients explicitly defined in JESD 51-12; these coefficients

are quoted or paraphrased below:

K

yields

∆V = K' • T(KELVIN)

D

1. θ , the thermal resistance from junction to ambient, is

JA

the natural convection junction-to-ambient air thermal

resistance measured in a one cubic foot sealed enclo-

sure. This environment is sometimes referred to as

“still air” although natural convection causes the air to

move. This value is determined with the part mounted

to a 95mm × 76mm PCB with six layers.

Solving for temperature:

∆V_D

T(KELVIN)=

(°CELSIUS)= T(KELVIN)–273.15

K'

D

where

300°K = 27°C

2. θ , the thermal resistance from junction to the

JCbottom

bottom of the product case, is determined with all of

the component power dissipation flowing through the

bottomofthepackage.InthetypicalµModuleregulator,

the bulk of the heat flows out the bottom of the pack-

age, but there is always heat flow out into the ambient

environment. As a result, this thermal resistance value

may be useful for comparing packages but the test

conditionsdon’tgenerallymatchtheuser’sapplication.

means that is we take the difference in voltage across the

diode measured at two currents with a ratio of 10, the

resulting voltage is 198μV per Kelvin of the junction with

a zero intercept at 0 Kelvin.

+

The diode connected PNP transistor between the TEMP

–

and TEMP pin can be used to monitor the internal tem-

perature of the LTM4645. See Figure 23 for an example.

3. θ

, the thermal resistance from junction to top of

JCtop

Thermal Considerations

the product case, is determined with nearly all of the

componentpowerdissipationflowingthroughthetopof

the package. As the electrical connections of the typical

µModule regulator are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of θ

for comparing packages but the test conditions don’t

generally match the user’s application.

The thermal resistances reported in the Pin Configuration

section of the data sheet are consistent with those param-

eters defined by JESD51-12 and are intended for use with

finite element analysis (FEA) software modeling tools that

leverage the outcome of thermal modeling, simulation,

and correlation to hardware evaluation performed on

an µModule package mounted to a hardware test board.

The motivation for providing these thermal coefficients in

foundinJESD51-12(“GuidelinesforReportingandUsing

Electronic Package Thermal Information”).

, this value may be useful

JCbottom

4. θ , the thermal resistance from junction to the printed

JB

circuitboard,isthejunction-to-boardthermalresistance

where almost all of the heat flows through the bottom

oftheµModulepackageandintotheboard, andisreally

Manydesignersmayopttouselaboratoryequipmentanda

testvehiclesuchasthedemoboardtopredicttheµModule

regulator’s thermal performance in their application at

various electrical and environmental operating conditions

to compliment any FEA activities. Without FEA software,

the thermal resistances reported in the Pin Configuration

the sum of the θ

and the thermal resistance of

JCbottom

the bottom of the part through the solder joints and a

portionoftheboard.Theboardtemperatureismeasured

a specified distance from the package.

4645f

19

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 9; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule package. As a

practical matter, it should be clear to the reader that no

individual or sub-group of the four thermal resistance

parameters defined by JESD 51-12 or provided in the

Pin Configuration section replicates or conveys normal

operatingconditionsofaµModuleregulator. Forexample,

in normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the µModule package—as the standard defines

complicationwithoutsacrificingmodelingsimplicity—but

alsonotignoringpracticalrealities—anapproachhasbeen

taken using FEA software modeling along with laboratory

testing in a controlled-environment chamber to reason-

ably define and correlate the thermal resistance values

supplied in this data sheet: (1) Initially, FEA software is

used to accurately build the mechanical geometry of the

LTM4645 and the specified PCB with all of the correct

materialcoefficientsalongwithaccuratepowerlosssource

definitions; (2) this model simulates a software-defined

JEDECenvironmentconsistentwithJESD51-12topredict

powerlossheatflowandtemperaturereadingsatdifferent

interfacesthatenablethecalculationoftheJEDEC-defined

thermalresistancevalues;(3)themodeland FEA software

isusedtoevaluatetheLTM4645withheatsinkandairflow;

(4) having solved for and analyzed these thermal resis-

tance values and simulated various operating conditions

in the software model, a thorough laboratory evaluation

replicates the simulated conditions with thermocouples

within a controlled-environment chamber while operat-

ing the device at the same power loss as that which was

simulated. The outcome of this process and due diligence

yields the set of derating curves shown in this data sheet.

for θ

and θ , respectively. In practice, power

JCbottom

JCtop

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4645, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to different

junctions of components or die are not exactly linear with

respect to total package power loss. To reconcile this

JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION

A

t

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

4645 F09

µMODULE DEVICE

Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

4645f

20

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

Safety Considerations

The LTM4645 has been designed to effectively remove

heat from both the top and bottom of the package. The

bottomsubstratematerialhasverylowthermalresistance

to the printed circuit board. An external heat sink can be

applied to the top of the device for excellent heat sinking

with airflow. Basically all power dissipating devices are

mounted directly to the substrate and the top exposed

metal. This provides two low thermal resistance paths to

remove heat.

The LTM4645 modules do not provide isolation from V

IN

to V . There is no internal fuse. If required, a slow blow

OUT

fuse with a rating twice the maximum input current needs

tobeprovidedtoprotecteachunitfromcatastrophicfailure.

The fuse or circuit breaker should be selected to limit the

current to the regulator during overvoltage in case of an

internaltopMOSFETfault. IftheinternaltopMOSFETfails,

then turning it off will not resolve the overvoltage, thus

the internalbottom MOSFET willturn onindefinitely trying

to protect the load. Under this fault condition, the input

voltage will source very large currents to ground through

the failed internal top MOSFET and enabled internal bot-

tom MOSFET. This can cause excessive heat and board

damage depending on how much power the input voltage

can deliver to this system. A fuse or circuit breaker can be

used as a secondary fault protector in this situation. The

Figures10and11showthethermalimagesoftheLTM4645

with no heat sink and no airflow running at 1V/25A and

1.8V/25A.

+

device does support over current protection. The TEMP

–

and TEMP pins are provided for monitoring internal tem-

perature, and can be used to detect the need for thermal

shutdown that can be done by controlling the HIZB pin.

Output Current Derating

The 1V, 1.5V power loss curves in Figures 12 to 13 can

be used in coordination with the load current derating

curves in Figures 14 to 21 for calculating an approximate

Figure 10. LTM4645 12V_INto 1V_OUTat 25A with No Air Flow

and No Heat Sink

θ thermal resistance for the LTM4645 with various heat

JA

sinking and airflow conditions. The power loss curves

are taken at room temperature and are increased with a

multiplicativefactoraccordingtothejunctiontemperature,

which is 1.3 for 120°C. The derating curves are plotted

with the output current starting at 25A and the ambient

temperature at ~30°C. The output voltages are 1V and

1.5V. These are chosen to include the lower and higher

outputvoltagerangesforcorrelatingthethermalresistance.

Thermal models are derived from several temperature

measurementsinacontrolledtemperaturechamberalong

withthermalmodelinganalysis.Thejunctiontemperatures

are monitored while ambient temperature is increased

with and without airflow. The power loss increase with

Figure 11. LTM4645 12V_INto 1.8V_OUTat 25A with No Air

Flow and No Heat Sink

4645f

21

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

6

5

4

3

2

1

0

6

5

4

3

2

1

0

30

25

20

15

10

5

0LMF

200LMF

400LMF

V

= 5V

= 12V

V

= 5V

= 12V

IN

0

5

10

15

20

25

0

5

10

15

20

25

30 40 50 60 70 80 90 100 110 120

LOAD CURRENT (A)

AMBIENT TEMPERATURE (°C)

4645 F12

4645 F13

4645 F14

Figure 12. 1V Power Loss Curve

Figure 13. 1.5V Power Loss Curve

Figure 14. 12V to 1V Derating Curve,

No Heat Sink

30

25

20

15

10

5

30

25

20

15

10

5

25

20

15

10

5

0LMF

200LMF

400LMF

0LMF

200LMF

400LMF

0LMF

200LMF

400LMF

0

30 40 50 60 70 80 90 100 110 120

AMBIENT TEMPERATURE (°C)

4645 F15

4645 F16

4645 F17

Figure 15. 5V to 1V Derating Curve,

No Heat Sink

Figure 16. 12V to 1V Derating Curve,

BGA Heat Sink

Figure 17. 5V to 1V Derating Curve,

BGA Heat Sink

30

25

20

15

10

30

25

20

15

10

5

0LMF

5

200LMF

400LMF

200LMF

400LMF

0

30 40 50 60 70 80 90 100 110 120

AMBIENT TEMPERATURE (°C)

4645 F19

4645 F18

Figure 18. 12V to 1.5V Derating Curve,

No Heat Sink

Figure 19. 5V to 1.5V Derating Curve,

No Heat Sink

4645f

22

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

30

25

20

15

10

5

30

25

20

15

10

0LMF

5

200LMF

400LMF

200LMF

400LMF

0

30 40 50 60 70 80 90 100 110 120

AMBIENT TEMPERATURE (°C)

4645 F21

4645 F20

Figure 20. 12V to 1.5V Derating Curve, BGA Heat Sink

Figure 21. 5V to 1.5V Derating Curve, BGA Heat Sink

Table 3. 1.0V Output

DERATING CURVE

Figures 14, 15

Figures 16, 17

V

(V)

POWER LOSS CURVE

Figure 12

AIR FLOW (LFM)

HEAT SINK

None

θ

(°C/W)

IN

JA

5, 12

0

9

6.5

6

Figure 12

200

400

0

None

Figure 12

None

Figure 12

BGA Heat Sink

8.5

5.5

5

Figure 12

200

400

Figure 12

Table 4. 1.5V Output

DERATING CURVE

Figures 18, 19

V

(V)

POWER LOSS CURVE

Figure 13

AIR FLOW (LFM)

HEAT SINK

None

θ

(°C/W)

IN

JA

5, 12

0

9

6.5

6

Figures 18, 19

5, 12

Figure 13

200

400

0

None

Figures 18, 19

Figure 13

None

Figures 20, 21

Figure 13

BGA Heat Sink

8.5

5.5

5

Figures 20, 21

Figure 13

200

400

Figures 20, 21

Figure 13

Heat Sink Manufacturer

Aavid Thermalloy

Part Number

Website

375424B00034G

www.aavid.com

Cool Innovations

4-050503P to 4-050508P

www.coolinnovations.com

4645f

23

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

Table 5. Output Voltage Response vs Component Matrix (Refer to Figure 23) 0A to 7A Load Step Typical Measured Values

C

VENDORS VALUE

PART NUMBER

C

VENDORS

OUT

VALUE

PART NUMBER

EEFSX0E471E4

2R5TPD470M5

6TPD470M5

IN

Bulk

Panasonic SP-CAP 470µF 2.5V

Panasonic POSCAP 470µF 2.5V

Panasonic POSCAP 470µF 6.3V

Ceramic Taiyo Yuden

Murata

22µF, 25V, 1206, X7S C3216X7S0J226M

Murata

100µF, 6.3V, 1206, X5R GRM31CR60J107M

100µF, 6.3V, 1206, X5R C3216X5R0G107M

22µF, 25V,1206, X5R GRM31CR61E226KE15L TDK

Murata

220µF, 4V, 1206, X5R

GRM31CR60G227M

Taiyo Yuden

220µF, 2.5V, 1206, X5R PMK316DBJ227MLHT

Ceramic Cap Only

P-P

RECOVERY

TIME

LOAD

STEP

(A)

SLEW

RATE

V

C

DROOP DEVIATION

R

FB

(kΩ)

121

FREQ

(kHz)

IN

OUT

IN

OUT

FF

(V)

0.9

1

(CERAMIC)

22µF × 3

(CERAMIC)

100µF × 6

(BULK)

(pF)

47pF

47µF

(mV)

109

102

97

(µs)

(A/µs)

5, 12

N/A

0

130

140

150

6

10

500

600

700

800

900

N/A

90.9

60.4

40.2

30.1

1.2

1.5

1.8

N/A

100

107

N/A

Bulk and Ceramic Cap

P-P

RECOVERY

TIME

LOAD

STEP

(A)

SLEW

RATE

V

C

DROOP DEVIATION

R

FB

(kΩ)

121

FREQ

(kHz)

IN

OUT

IN

OUT

FF

(V)

0.9

1

(CERAMIC)

22µF × 3

(CERAMIC)

47µF × 2

(BULK)

470µF

(pF)

N/A

(mV)

109

107

122

131

142

(µs)

(A/µs)

5, 12

0

30

40

50

6

10

500

600

700

800

900

90.9

60.4

40.2

30.1

1.2

1.5

1.8

4645f

24

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

ambient temperature change is factored into the derating

curves. Thejunctionsaremaintainedat~120°Cmaximum

while lowering output current or power with increasing

ambient temperature. The decreased output current will

decrease the internal module loss as ambient temperature

isincreased.Themonitoredjunctiontemperatureof120°C

minus the ambient operating temperature specifies how

much module temperature rise can be allowed, as an ex-

ample, in Figure 20 the load current is derated to 15A at

100°C with no air or heat sink and the power loss for the

12V to 1.5V at 15A output is about 3.5W. The 3.5W loss

is calculated with the 2.7W room temperature loss from

the 12V to 1.5V power loss curve at 15A, from Figure 13,

and the 1.3 multiplying factor at 120°C junction. If the

100°C ambient temperature is subtracted from the 120°C

junction temperature, then the difference of 20°C divided

Layout Checklist/Example

The high integration of LTM4645 makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout consid-

erations are still necessary.

• Use large PCB copper areas for high current paths,

including V , GND, and V . It helps to minimize the

IN

OUT

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-

tors next to the V , PGND and V

pins to minimize

IN

OUT

high frequency noise.

• Place a dedicated power ground layer underneath the

unit.

• To minimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

by 3.5W equals a 5.7°C/W θ thermal resistance. Table

JA

4 specifies a 5.5°C/W value which is very close. Tables 3

and 4 provide equivalent thermal resistances for 1.0V and

1.5Voutputswithandwithoutairflowandheatsinking.The

derivedthermalresistancesinTables3and4forthevarious

conditions can be multiplied by the calculated power loss

asafunctionofambienttemperaturetoderivetemperature

rise above ambient, thus maximum junction temperature.

Room temperature power loss can be derived from the ef-

ficiencycurvesintheTypicalPerformanceCharacteristics

section and adjusted with the above ambient temperature

multiplicativefactors.Theprintedcircuitboardisa1.6mm

thick six layer board with two ounce copper for all layers.

The PCB dimensions are 95mm × 76mm. The BGA heat

sinks are listed in Table 4.

• Do not put via directly on the pad, unless they are

capped or plated over.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

• For parallel modules, tie the V , V , and COMP pins

OUT FB

together. Use an internal layer to closely connect these

pins together. The TRACK pin can be tied a common

capacitor for regulator soft-start.

• Bring out test points on the signal pins for monitoring.

Figure22givesagoodexampleoftherecommendedlayout.

4645f

25

For more information www.linear.com/LTM4645

LTM4645

applicaTions inForMaTion

C

OUT

V

OUT

GND

V

IN

C

IN

4645 F22

Figure 22. Recommended PCB Layout

4645f

26

For more information www.linear.com/LTM4645

LTM4645

Typical applicaTions

1µF

2.2Ω

4.7µF

100k

V

IN

V

IN

6V TO 15V

22µF

25V

×2

PGOOD

HIZB

PGOOD

V

OUT

1V

V

OUT

+

25A

TRACK/SS

COMPa

COMPb

FREQ

V

47pF

LTM4645

OSNS

100µF

V

6.3V

0.1µF

FB

–

×4

OSNS

90.9k

48.7k

4645 F23

DIGITAL TELEMETRY FOR

TEMPERATURE MONITORING

PINS NOT USED IN THIS

CIRCUIT: CLKOUT, PHASMD,

PWM, SW

Figure 23. Typical 6V to 15V Input 1.0V at 25A Output Design

1µF

4.7µF

2.2Ω

100k

V

IN

V

IN

4.7V TO 5.5V

22µF

16V

×2

PGOOD

HIZB

DRV

PGOOD

V

1.2V

25A

OUT

V

OUT

CC

+

V

47µF

6.3V

TRACK/SS

COMPa

COMPb

FREQ

LTM4645

OSNS

V

FB

–

0.1µF

+

V

330µF

6.3V

OSNS

60.4k

48.7k

DIGITAL TELEMETRY FOR

TEMPERATURE MONITORING

PINS NOT USED IN THIS

4645 F24

CIRCUIT: CLKOUT, PHASMD,

PWM, SW

Figure 24. Typical 4.7V to 5.5V Input 1.2V at 25A Output Design

4645f

27

For more information www.linear.com/LTM4645

LTM4645

Typical applicaTions

4.7µF

2.2Ω

SV

IN

1µF

100k

V

IN

V

IN

6V TO 15V

22µF

25V

×2

PGOOD

HIZB

PGOOD

V

OUT

1V

LTM4645

U1

RUN

V

OUT

+

47µF

50A

TRACK/SS

COMPa

COMPb

FREQ

V

OSNS

V

6.3V

FB

×2

FB

+

–

330µF

4V

OSNS

90.9k

48.7k

TEMPERATURE

MONITORING

4.7µF

SV

IN

V

IN

22µF

25V

×2

PGOOD

FB

HIZB

PGOOD

RUN

V

OUT

47µF

6.3V

×2

+

TRACK/SS

COMPa

COMPb

FREQ

330µF

4V

LTM4645

U2

V

0.1µF

FB

–

V

OSNS

48.7k

PINS NOT USED IN CIRCUIT

LTM4647 U1: PWM, SW

TEMPERATURE

MONITORING

4645 F25

PINS NOT USED IN CIRCUIT LTM4647 U2:

+

CLKOUT, PHASMD, PWM, SW, V

OSNS

Figure 25. 6V to 15V Input, 1.0V Output at 50A

4645f

28

For more information www.linear.com/LTM4645

LTM4645

Typical applicaTions

4.7µF

2.2Ω

SV

IN

1µF

100k

V

IN

V

IN

6V TO 15V

22µF

25V

×2

PGOOD1

HIZB

PGOOD

V

OUT1

LTM4645

1V

V

OUT

+

25A

TRACK/SS

COMPa

COMPb

FREQ

V

OSNS

47µF

6.3V

×2

+

330µF

4V

V

0.1µF

FB

–

90.9k

OSNS

48.7k

4.7µF

100k

SV

IN

V

IN

22µF

PGOOD2

HIZB

PGOOD

V

1.2V

25A

25V

OUT2

60.4k

90.9k

V

OUT

×2

LTM4645

+

TRACK/SS

COMPa

COMPb

FREQ

V

OSNS

V

47µF

6.3V

×2

+

330µF

4V

FB

–

60.4k

OSNS

53.6k

4645 F25

PINS NOT USED IN LTM4647 U1 AND U2

CIRCUITS: CLKOUT, PHASMD, PWM, SW, TEMP , TEMP

+

–

Figure 26. 6V to 15V Input, 1.0V and 1.2V Output with Tracking

4645f

29

For more information www.linear.com/LTM4645

LTM4645

Typical applicaTions

O U T

T E G A

E P

T E G A

E P

S O U R C E

G N D

R E V

G N D

R E V

G N D

R E V

C P O

I N

V

C C

V

I N

V

C C

V

I N

V

C C

V

I N

V

C C

V

C C

V

C C

V

I N T

R V D

V

I N T

R V D

V

I N T

R V D

I N T

R V D

C C

M O D E / P L L I N

P H A S M D

C L K O U T

M O D E / P L L I N

P H A S M D

C L K O U T

M O D E / P L L I N

P H A S M D

S G N D

G N D

S G N D

G N D

S G N D

G N D

P H A S M D

C L K O U T

S G N D

G N D

4645f

30

For more information www.linear.com/LTM4645

LTM4645

Typical applicaTions

2.2µF

2.2Ω

SV

IN

1µF

100k

V

IN

V

IN

6V TO 15V

22µF

25V

×8

PGOOD

22pF

HIZB

PGOOD

V

OUT

1.0V

RUN

V

OUT

LTM4645

U1

100A

+

TRACK/SS

COMPa

COMPb

FREQ

V

OSNS

100µF

COMP

48.7k

V

FB

6.3V

FB

–

U1 PINS NOT USED: PWM, SW

×6

+

–

TEMP , TEMP

90.9k

OSNS

2.2µF

SV

IN

V

IN

PGOOD

FB

HIZB

PGOOD

RUN

V

OUT

100µF

6.3V

×6

TRACK/SS

COMPa

COMPb

FREQ

V

LTM4645

U2

FB

U2 PINS NOT USED: PWM, SW

+

–

+

TEMP , TEMP , V

OSNS

–

V

OSNS

48.7k

2.2µF

SV

IN

V

IN

PGOOD

FB

HIZB

PGOOD

RUN

V

OUT

100µF

6.3V

×6

TRACK/SS

COMPa

COMPb

FREQ

V

LTM4645

U3

FB

U3 PINS NOT USED: PWM, SW

+

–

+

TEMP , TEMP , V

–

OSNS

V

OSNS

48.7k

2.2µF

SV

IN

V

IN

HIZB4

48.7k

PGOOD

FB

HIZB

PGOOD

RUN

V

OUT

100µF

6.3V

×6

TRACK/SS

COMPa

COMPb

FREQ

V

LTM4645

U4

FB

U4 PINS NOT USED: CLKOUT, PWM, SW

+

–

+

V

TEMP , TEMP , V

OSNS

0.1µF

4645 F28

Figure 28. 4 Phase 1V at 100A Design

4645f

31

For more information www.linear.com/LTM4645

LTM4645

package DescripTion

LTM4645 Component BGA Pinout

PIN ID FUNCTION PIN ID FUNCTION

PIN ID FUNCTION

PIN ID

B1

FUNCTION

PIN ID

E1

FUNCTION

PIN ID

F1

FUNCTION

–

+

A1

A2

A3

A4

A5

A6

A7

V

IN

V

IN

V

IN

V

C1

C2

C3

C4

C5

C6

C7

V

D1

D2

D3

D4

D5

D6

D7

GND

TEMP

IN

B2

E2

GND

HIZB

V_FB

F2

GND

SW

B3

GND

PWM

GND

E3

F3

GND

RUN

GND

B4

GND

E4

F4

GND

B5

CLKOUT

TEST1

DRV

TEST2

E5

F5

TRACK/SS

GND

CC

B6

INTV

SV

IN

E6

F6

CC

B7

MODE/PLLIN

PHASMD

FREQ

E7

SGND

F7

TEST3

PIN ID FUNCTION

PIN ID

H1

FUNCTION

GND

PIN ID

J1

FUNCTION PIN ID FUNCTION

PIN ID

L1

FUNCTION

G1

G2

G3

G4

G5

G6

G7

GND

V

K1

K2

K3

K4

K5

K6

K7

V

OUT

H2

GND

J2

L2

H3

GND

J3

L3

H4

GND

J4

L4

–

+

V

H5

GND

J5

GND

L5

OSNS

V

H6

COMPa

COMPb

J6

L6

PGOOD

H7

J7

L7

4645f

32

For more information www.linear.com/LTM4645

LTM4645

package DescripTion

Please refer to http://www.linear.com/product/LTM4645#packaging for the most recent package drawings.

Z

/ / b b b

Z

3 . 8 1 0

2 . 5 4 0

1 . 2 7 0

0 . 3 1 7 5

1 . 2 7 0

0 . 0 0 0

2 . 5 4 0

3 . 8 1 0

4645f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

33

For more information www.linear.com/LTM4645

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTM4645

package phoTo

Design resources

SUBJECT

DESCRIPTION

µModule Design and Manufacturing Resources

Design:

Manufacturing:

• Selector Guides

• Quick Start Guide

• Demo Boards and Gerber Files

• Free Simulation Tools

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

µModule Regulator Products Search

1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

TechClip Videos

Quick videos detailing how to bench test electrical and thermal performance of µModule products.

Digital Power System Management

Linear Technology’s family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.

relaTeD parTs

PART

NUMBER

DESCRIPTION

COMMENTS

LTM4637

20A µModule Regulator

4.5V ≤ V ≤ 20V, 0.6V ≤ V

≤ 5.5V, 15mm × 15mm × 4.32mm (LGA), 15mm ×

IN

OUT

15mm × 4.92mm (BGA)

LTM4647

LTM4636

LTM4631

30A µModule Regulator, Pin Compatible with LTM4645

4.7V ≤ V ≤ 15V, 0.6V ≤ V

≤ 1.8V. 9mm × 15mm × 5.01mm (BGA)

≤ 3.3V, 16mm × 16mm × 7.12mm (BGA)

IN

OUT

40A µModule Regulator, 1% V

Accuracy

4.75V ≤ V ≤ 15V, 0.6V ≤ V

OUT

IN

OUT

Dual 10A, Single 20A µModule Regulator, 1.91mm

Package Height

4.5V ≤ V ≤ 15V, 0.6V ≤ V

≤ 1.8V, 16mm × 16mm × 1.91mm (LGA)

IN

OUT

LTM4620A Dual 13A or Single 26A µModule Regulator, V

≤ 5.3V

4.5V ≤ V ≤ 15V, 0.6V ≤ V

≤ 5.3V, 15mm × 15mm × 4.41mm (LGA), 15mm ×

≤ 1.8V, 16mm × 16mm × 4.41mm (LGA), 16mm ×

≤ 5.3V, 16mm × 16mm × 4.41mm (LGA)

OUT

IN

OUT

15mm × 5.01mm (BGA)

LTM4630/ Dual 18A or Single 36A µModule Regulator, External

LTM4630-1 Compensation(–1), 0.8V V Accuracy (–1A)

4.5V ≤ V ≤ 15V, 0.6V ≤ V

IN

OUT

16mm × 5.01mm (BGA)

OUT

LTM4630A Dual 18A or Single 36A µModule Regulator, V

≤ 5.3V

4.5V ≤ V ≤ 15V, 0.6V ≤ V

OUT

IN

LTM4650/ Dual 25A or Single 50A µModule Regulator, External

LTM4650-1 Compensation(–1), 0.8V V Accuracy (–1A)

4.5V ≤ V ≤ 15V, 0.6V ≤ V

≤ 1.8V, 16mm × 16mm × 5.01mm (BGA)

IN

OUT

LTM4650A Dual 25A or Single 50A µModule Regulator, V

≤ 5.5V

4.5V ≤ V ≤ 16V, 0.6V ≤ V

≤ 5.5V. 16mm × 16mm × 5.01mm (BGA)

≤ 5.5V, 16mm × 16mm × 5.01mm (BGA)

≤ 1.8V, 16mm × 16mm × 5.01mm (BGA)

OUT

IN

OUT

LTM4676A Dual 13A or Single 26A µModule Regulator with PSM

4.5V ≤ V ≤ 17V, 0.5V ≤ V

IN

LTM4677

Dual 25A or Single 50A µModule Regulator with PSM

4.5V ≤ V ≤ 16V, 0.5V ≤ V

IN

4645f

LT 0917 • PRINTED IN USA

www.linear.com/LTM4645

34

 LINEAR TECHNOLOGY CORPORATION 2017

For more information www.linear.com/LTM4645


型号：	LTM4637
厂家：	Linear
描述：	25A DC/DC Step-Down Î¼Module Regulator
文件：	总34页 (文件大小：695K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM4637 [Linear]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E