LTM4649EY#PBF [Linear]
LTM4649 - 10A Step-Down DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 68; Temperature Range: -40°C to 85°C;
| 型号： | LTM4649EY#PBF |
| 厂家： | 
Linear |
| 描述： | LTM4649 - 10A Step-Down DC/DC µModule (Power Module) Regulator; Package: BGA; Pins: 68; Temperature Range: -40°C to 85°C 开关 输出元件 |
| 文件： | 总30页 (文件大小：1466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4649
10A Step-Down DC/DC
µModule Regulator
FEATURES
DESCRIPTION
n
10A DC Output Current
TheLTM®4649isacomplete10Ahighefficiencyswitching
mode step-down DC/DC µModule® regulator in a 9mm ×
15mm×4.92BGApackage.Includedinthepackagearethe
switching controller, power FETs, inductor, and all support
components.Operatingoveraninputvoltagerangeof4.5V
to 16V, the LTM4649 supports an output voltage range of
0.6V to 3.3V, set by a single external resistor. This high
efficiency design delivers 10A continuous current. Only
bulk input and output capacitors are needed.
n
Input Voltage Range: 4.5V to 16V
n
Output Voltage Range: 0.6V Up to 3.3V
n
No Heat Sink or Current Derating Up to 85°C Ambi-
ent Temperature
n
1.5ꢀ Total DC Voltage Output Error
n
Multiphase Operation with Current Sharing
n
Remote Sense Amplifier
n
Built-In General Purpose Temperature Monitor
Selectable Pulse-Skipping Mode/Burst Mode® Opera-
n
Highswitchingfrequencyandacurrentmodearchitecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequency synchronization, programmable multiphase
operation, and output voltage tracking for supply rail
sequencing.
tion for High Efficiency at Light Load
Soft-Start/Voltage Tracking
Protection: Output Overvoltage and Overcurrent
Foldback
n
n
n
9mm × 15mm × 4.92mm BGA Package
Fault protection features include output overvoltage and
overcurrent protection. The LTM4649 is offered in a small
9mm×15mm×4.92mmBGApackageavailablewithSnPb
or RoHS compliant terminal finish.
L, LT, LTC, LTM, Burst Mode, µModule, PolyPhase, Linear Technology and the Linear logo
are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678,
6144194, 6177787, 6304066, 6580258 and 8163643. Other patents pending.
APPLICATIONS
n
Telecom, Networking and Industrial Equipment
n
Point of Load Regulation
TYPICAL APPLICATION
4.5V to 16V Input, 1.5V Output DC/DC
µModule Regulator
Efficiency and Power Loss
at 12V and 5V Input
Current Derating: 12V Input,
1.5VOUT, No Heat Sink
95
90
3.0
2.5
12
10
8
CLKIN
FREQ
V
1.5V
10A
OUT
V
IN
4.5V TO 16V
V
V
IN
OUT
V
OUT_LCL
22µF
16V
×2
INTV
SW
CC
100µF
6.3V
×2
DIFFOUT
DIFFP
85
80
2.0
1.5
RUN
LTM4649
MODE
DIFFN
6
PHMODE
TRACK/SS
V
FB
COMP
75
70
65
1.0
0.5
0
4
6.65k
TEMP
GND
PGOOD
CLKOUT
0.1µF
400LFM
200LFM
0LFM
2
V
V
= 12V
= 5V
IN
IN
4649 TA01a
0
0
2
4
6
8
10
0
40
60
80
100
120
20
LOAD CURRENT (A)
4649 TA01b
AMBIENT TEMPERATURE (°C)
4649 TA01c
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For more information www.linear.com/LTM4649
LTM4649
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
A
B
C
D
E
F
G
V ............................................................. –0.3V to 18V
OUT
IN
RUN
GND
GND
V
IN
V
.......................................................... –0.3V to 3.6V
1
2
3
4
5
6
7
8
9
CLKOUT
INTV , PGOOD, RUN.................................. –0.3V to 6V
CC
NC
FREQ
CLKIN
PHMODE
MODE
MODE, CLKIN, TRACK/SS, DIFFP, DIFFN,
INTV
CC
DIFFOUT, PHMODE ...............................–0.3V to INTV
FB
CC
TRACK/SS
V ............................................................ –0.3V to 2.7V
COMP (Note 3).......................................... –0.3V to 2.7V
COMP
DIFFN
SW
TEMP
NC
V
FB
INTV Peak Output Current................................100mA
CC
PGOOD
DIFFP
DIFFOUT
Internal Operating Temperature Range
(Note 2).................................................. –55°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Package Body Temperature ... 245°C
V
OUT_LCL
10
11
V
GND
OUT
BGA PACKAGE
68-LEAD (9mm × 15mm × 4.92mm)
T
JMAX
= 125°C, θ = 14°C/W, θ = 5°C/W, θ
= 20°C/W
JA
JCbottom
JCtop
θ
JB
+ θ = 14°C/W, WEIGHT = 1.7g
BA
ORDER INFORMATION
http://www.linear.com/product/LTM4649#orderinfo
PART NUMBER
PAD OR BALL FINISH
PART MARKING*
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(Note 2)
DEVICE
FINISH CODE
LTM4649EY#PBF
LTM4649IY#PBF
LTM4649IY
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
LTM4649Y
LTM4649Y
LTM4649Y
e1
e1
e0
BGA
BGA
BGA
3
3
3
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Pb-free and Non-Pb-free Part Markings:
www.linear.com/leadfree
• LGA and BGA Package and Tray Drawings:
www.linear.com/packaging
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For more information www.linear.com/LTM4649
LTM4649
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V per typical application.
SYMBOL
PARAMETER
CONDITIONS
MIN
4.5
TYP
MAX
16
UNITS
l
l
l
V
V
V
Input DC Voltage
Output Voltage Range
V
V
V
IN
0.6
3.3
OUT(RANGE)
OUT(DC)
Output Voltage, Total Variation with
Line and Load
C
= 10µF × 1,C
= 100µF Ceramic,
1.477
1.50
1.523
IN
OUT
100µF POSCAP, R = 6.65k, MODE = GND,
FB
V
= 4.5V to 16V, I
= 0A to 10A
IN
OUT
Input Specifications
V
V
RUN Pin On Threshold
RUN Pin On Hysteresis
Input Supply Bias Current
V
Rising
1.1
1.25
150
1.4
V
RUN
RUN
mV
RUN(HYS)
Q(VIN)
I
V
V
V
= 12V, V
= 12V, V
= 12V, V
= 1.5V, Burst Mode Operation
= 1.5V, Pulse-Skipping Mode
= 1.5V, Switching Continuous
5
mA
mA
mA
µA
IN
IN
IN
OUT
OUT
OUT
15
75
70
Shutdown, RUN = 0, V = 12V
IN
I
Input Supply Current
V
= 12V, V
= 1.5V, I = 10A
OUT
1.5
A
S(VIN)
IN
OUT
Output Specifications
I
Output Continuous Current Range
Line Regulation Accuracy
V
V
= 12V, V
= 1.5V (Note 4)
0
10
A
OUT(DC)
IN
OUT
l
l
ΔV
= 1.5V, V from 4.5V to 16V I = 0A
OUT
0.010
0.15
15
0.04
%/V
OUT(LINE)
OUT
IN
V
OUT
ΔV
Load Regulation Accuracy
Output Ripple Voltage
Turn-On Overshoot
V
= 1.5V, I
= 0A to 10A, V = 12V
0.5
%
mV
mV
ms
mV
OUT(LOAD)
OUT
OUT
IN
(Note 4)
V
OUT
V
I
= 0A, C
= 100µF Ceramic, 100µF
OUT
OUT(AC)
OUT
POSCAP, V = 12V, V
= 1.5V
IN
OUT
ΔV
C
V
= 100µF Ceramic, 100µF POSCAP,
= 1.5V, I
20
OUT(START)
OUTLS
OUT
OUT
= 0A, V = 12V
OUT
IN
t
Turn-On Time
C
= 100µF Ceramic, 100µF POSCAP,
5
START
OUT
No Load, TRACK/SS = 0.01µF, V = 12V
IN
ΔV
Peak Deviation for Dynamic Load
Load: 0% to 50% to 0% of Full Load,
60
C
V
= 100µF Ceramic, 100µF POSCAP,
OUT
= 12V, V
= 1.5V
IN
OUT
t
Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load,
20
µs
A
SETTLE
C
V
= 100µF Ceramic, 100µF POSCAP,
OUT
= 12V, V =1.5V
IN
OUT
I
Output Current Limit
V
= 12V, V
= 1.5V (Note 4)
= 0A, V = 1.5V
OUT
12
OUTPK
IN
OUT
Control Specifications
l
l
V
Voltage at V Pin
I
0.593
0.60
–12
0.66
1.2
90
0.607
–25
V
nA
V
FB
FB
OUT
I
Current at V Pin
(Note 3)
FB
FB
V
Feedback Overvoltage Lockout
Track Pin Soft-Start Pull-Up Current
Minimum On-Time
0.64
1.0
0.68
1.4
OVL
I
t
TRACK/SS = 0V
(Note 3)
µA
ns
kΩ
TRACK/SS
ON(MIN)
R
Resistor Between V
Pins
and V
FB
9.90
0
10
10.10
3.6
FBHI
OUT_LCL
DIFFP, DIFFN CM Common Mode Input Range
RANGE
V
= 12V, Run > 1.4V
V
IN
V
V
A
Maximum DIFFOUT Voltage
Input Offset Voltage
Differential Gain
I
= 300µA
INTV -1.4
V
mV
V/V
DIFFOUT(MAX)
DIFFOUT
CC
V
= V
= 1.5V, I = 100µA
DIFFOUT
4
OS
V
DIFFP
DIFFOUT
(Note 3)
1
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For more information www.linear.com/LTM4649
LTM4649
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V per typical application.
SYMBOL
SR
PARAMETER
CONDITIONS
(Note 5)
MIN
TYP
2
MAX
UNITS
V/µs
MHz
dB
Slew Rate
GBP
Gain Bandwidth Product
Common Mode Rejection
DIFFOUT Current
Input Resistance
PGOOD Trip Level
(Note 5)
3
CMRR
(Note 3)
60
I
Sourcing
2
mA
DIFFOUT
R
DIFFP, DIFFN to GND
80
kΩ
IN
V
V
With Respect to Set Output
FB
PGOOD
V
V
Ramping Negative
Ramping Positive
–10
10
%
%
FB
FB
V
PGOOD Voltage Low
I
I
= 2mA
PGOOD
0.1
0.3
5.2
V
PGL
INTV Linear Regulator
CC
V
V
Internal V Voltage
4.8
5
V
INTVCC
INTVCC
CC
Load Reg INTV Load Regulation
= 0mA to 50mA
CC
0.9
%
CC
Oscillator and Phase-Locked Loop
f
f
Frequency Sync Capture Range
Nominal Switching Frequency
MODE Input Resistance
Clock Input Level High
250
400
800
500
kHz
kHz
kΩ
V
SYNC
S
450
250
R
MODE
V
V
2.0
IH_CLKIN
IL_CLKIN
Clock Input Level Low
0.8
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Notes are automatically numbered when you apply
the note style.
Note 3: 100% tested at wafer level.
Note 4: See output current derating curves for different V , V
Note 5: Guaranteed by design.
and T .
IN OUT
A
Note 2: The LTM4649 is tested under pulsed load conditions such that
T ≈ T . The LTM4649E is guaranteed to meet performance specifications
J
A
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4649I is guaranteed to meet specifications over the
–40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
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For more information www.linear.com/LTM4649
LTM4649
TYPICAL PERFORMANCE CHARACTERISTICS
CCM, Burst Mode and Pulse-
Skipping Mode Efficiency
12VIN Efficiency
5VIN Efficiency
100
90
100
95
100
95
V
V
= 12V
IN
OUT
= 1.5V
80
90
85
80
75
70
65
90
85
80
75
70
65
70
60
50
40
30
20
10
0
V
V
V
V
V
= 1V, 450kHz
V
V
V
V
V
= 1V, 450kHz
OUT
OUT
OUT
OUT
OUT
CCM
OUT
OUT
OUT
OUT
OUT
= 1.2V, 450kHz
= 1.5V, 450kHz
= 2.5V, 450kHz
= 3.3V, 450kHz
= 1.2V, 450kHz
= 1.5V, 450kHz
= 2.5V, 750kHz
= 3.3V, 750kHz
PULSE-
SKIPPPING
Burst Mode
OPERATION
2
4
6
10
2
4
6
10
0
8
0
8
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4649 G03
4649 G02
4649 G01
5VIN, 1VOUT Load Transient
12VIN, 1VOUT Load Transient
5VIN, 1.5VOUT Load Transient
I
I
I
OUT
5A/DIV
AC
OUT
OUT
5A/DIV
AC
5A/DIV
AC
V
V
V
OUT
100mV/DIV
AC
OUT
OUT
100mV/DIV
AC
100mV/DIV
AC
4649 G04
4649 G05
4649 G06
50µs/DIV
50µs/DIV
50µs/DIV
5V , 1V , 5A TO 10A LOAD STEP
12V , 1V , 5A TO 10A LOAD STEP
5V , 1.5V , 5A TO 10A LOAD STEP
IN
OUT
IN
OUT
IN
OUT
C
= 2 • 220µF 4V CERAMIC CAPACITOR
C
= 2 • 220µF 4V CERAMIC CAPACITOR
C
= 2 • 220µF 4V CERAMIC CAPACITOR
OUT
OUT
OUT
NO C CAPACITOR
NO C CAPACITOR
NO C CAPACITOR
FF
FF
FF
12VIN, 1.5VOUT Load Transient
5VIN, 2.5VOUT Load Transient
12VIN, 2.5VOUT Load Transient
I
I
I
OUT
OUT
OUT
5A/DIV
AC
5A/DIV
AC
5A/DIV
AC
V
V
V
OUT
OUT
OUT
100mV/DIV
AC
100mV/DIV
AC
100mV/DIV
AC
4649 G07
4649 G08
4649 G09
50µs/DIV
50µs/DIV
50µs/DIV
12V , 1.5V , 5A TO 10A LOAD STEP
5V , 2.5V , 5A TO 10A LOAD STEP
12V , 2.5V , 5A TO 10A LOAD STEP, 750kHz
IN
OUT
IN
OUT
IN
OUT
C
= 2 • 220µF 4V CERAMIC CAPACITOR
C
= 2 • 220µF 4V CERAMIC CAPACITOR
C
= 2 • 220µF 4V CERAMIC CAPACITOR
OUT
OUT
OUT
NO C CAPACITOR
NO C CAPACITOR
FF
NO C CAPACITOR
FF
FF
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For more information www.linear.com/LTM4649
LTM4649
TYPICAL PERFORMANCE CHARACTERISTICS
5VIN, 3.3VOUT Load Transient
12VIN, 3.3VOUT Load Transient
Soft-Start with No Load
I
I
OUT
5A/DIV
AC
OUT
I
IN
5A/DIV
AC
1A/DIV
V
V
OUT
100mV/DIV
AC
OUT
V
OUT
100mV/DIV
AC
0.5V/DIV
V
SW
10V/DIV
4649 G10
4649 G11
4649 G12
50µs/DIV
50µs/DIV
20ms/DIV
5V , 3.3V , 5A TO 10A LOAD STEP
12V , 3.3V , 5A TO 10A LOAD STEP, 750kHz
12V , 1.5V
IN OUT
IN
OUT
IN
OUT
C
= 2 • 220µF 4V CERAMIC CAPACITOR
C
= 2 • 220µF 4V CERAMIC CAPACITOR
I = 0A START-UP
O
OUT
OUT
NO C CAPACITOR
NO C CAPACITOR
C
= 0.1µF
SS
FF
FF
Short-Circuit Protection
with No Load
Short-Circuit Protection
with Full Load
Soft-Start with Full Load
I
IN
I
I
IN
IN
1A/DIV
V
1A/DIV
1A/DIV
V
OUT
1V/DIV
OUT
0.5V/DIV
V
OUT
0.5V/DIV
V
V
SW
V
SW
SW
10V/DIV
10V/DIV
10V/DIV
4649 G13
4649 G15
4649 G14
20ms/DIV
20µs/DIV
20µs/DIV
12V , 1.5V
12V , 1.5V
OUT
12V , 1.5V
IN
OUT
IN
IN
OUT
I
= 10A START-UP
= 0.1µF
SHORT CIRCUIT WITH FULL LOAD
SHORT CIRCUIT WITH NO LOAD
O
C
C
= 2 • 220µF 4V CERAMIC CAPACITOR
C
= 2 • 220µF 4V CERAMIC CAPACITOR
SS
OUT
OUT
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For more information www.linear.com/LTM4649
LTM4649
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
PGOOD(C7):OutputVoltagePowerGoodIndicator.Open-
drain logic output that is pulled to ground when the output
voltage is not within 10% of the regulation point.
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
GND (A1-A5, A7-A11, B1, B9-B11, E1, F3, F5, G1-G7):
GroundPinsforBothInputandOutputReturns.Allground
pins need to connect with large copper areas underneath
the unit.
V
(G9): This pin is connected to the top of the
OUT_LCL
internal top feedback resistor for the output. When the
remote sense amplifier is used, connect the remote sense
amplifier output DIFFOUT to V
to drive the 10k top
OUT_LCL
feedback resistor. When the remote sense amplifier is not
used, connect V to V directly.
TEMP (A6): Onboard Temperature Diode for Monitoring
the V Junction Voltage Change with Temperature. See
OUT_LCL
OUT
BE
the Applications Information section.
FREQ (E3): Frequency Set Pin. A 10µA current is sourced
from this pin. A resistor from this pin to ground sets a
voltage, that in turn, programs the operating frequency.
Alternatively, this pin can be driven with a DC voltage that
can set the operating frequency. See the Applications In-
formation section. The LTM4649 has an internal resistor
to program the frequency to 450kHz.
CLKIN (B3): External Synchronization Input to Phase De-
tector Pin. A clock on this pin will enable synchronization
with forced continuous operation. See the Applications
Information section.
PHMODE (B4): This pin can be tied to GND, tied to INTV
CC
or left floating. This pin determines the relative phases
between the internal controllers and the phasing of the
CLKOUT signal. See Table 2 in the Operation section.
TRACK/SS (E5): Output Voltage Tracking Pin and Soft-
Start Inputs. The pin has a 1.2µA pull-up current source.
A capacitor from this pin to ground will set a soft-start
ramp rate. In tracking, the regulator output can be tracked
to a different voltage. The different voltage is applied to
a voltage divider then the slave output’s track pin. This
voltage divider is equal to the slave output’s feedback
divider for coincidental tracking. See the Applications
Information section.
MODE (B5): Mode Select Input. Connect this pin to
INTV toenableBurstModeoperation.Connecttoground
CC
to enable forced continuous mode of operation. Floating
this pin will enable pulse-skipping mode.
NC(B7-B8, C3-C4):NoConnectionPins. Eitherfloatthese
pins or connect them to GND for thermal purpose.
V (C1, C8, C9, D1, D3-D5, D7-D9 and E8): Power Input
V
(E7): The Negative Input of the Error Amplifier. Inter-
IN
FB
Pins. Apply input voltage between these pins and GND
nally,thispinisconnectedtoV
witha10kprecision
OUT_LCL
pins. Recommend placing input decoupling capacitance
resistor. Different output voltages can be programmed
directly between V pins and GND pins.
with an additional resistor between V and ground pins.
IN
FB
In PolyPhase operation, tying the V pins together allows
FB
V
(C10-C11, D10-D11, E9-E11, F9-F11, G10-G11):
OUT
for parallel operation. See the Applications Information
Power Output Pins. Apply output load between these pins
and GND pins. Recommend placing output decoupling
capacitance directly between these pins and GND pins.
section for details.
RUN(F1):RunControlPin.Avoltageabove1.25Vwillturn
on the module. The RUN pin has a 1µA pull-up current,
and then once the RUN pin reaches 1.2V an additional
4.5µA pull-up current is added to this pin.
SW (C5): Switching Node of the Circuit. This pin is used
to check the switching frequency. Leave pin floating. A
resistor-capacitor snubber can be placed from SW to GND
to eliminate high frequency switch node ringing. See the
Applications Information section.
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LTM4649
PIN FUNCTIONS
CLKOUT (F2): Output Clock Signal for PolyPhase Opera-
tion. The phase of CLKOUT is determined by the state of
the PHMODE pin.
DIFFN (F7): Input to the Remote Sense Amplifier. This pin
connects to the ground remote sense point. Connect to
ground when not used.
DIFFP (F8): Input to the Remote Sense Amplifier. This
pin connects to the output remote sense point. Connect
to ground when not used.
INTV (F4): Internal 5V LDO for Driving the Control Cir-
CC
cuitry and the Power MOSFET Drivers. The 5V LDO has
an absolute maximum 100mA peak current limit.
DIFFOUT (G8): Output of the Remote Sense Amplifier.
COMP(F6):CurrentControlThresholdandErrorAmplifier
Compensation Point. The current comparator threshold
increases with this control voltage. Tie all COMP pins
together in parallel operation.
This pin connects to the V
pin for remote sense
OUT_LCL
applications. Otherwise float when not used.
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LTM4649
BLOCK DIAGRAM
INTV
CC
V
OUT_LCL
V
OUT
1M
10k
V
IN
PGOOD
> 1.4V = ON
< 1.1V = OFF
MAX = 6V
R1
R2
V
IN
RUN
V
IN
4.5V TO 16V
+
1µF
C
IN
CLKOUT
COMP
10k
SW
M1
M2
INTERNAL
COMP
0.35µH
V
1.5V
10A
OUT
V
OUT
GND
POWER
CONTROL
+
V
FB
C
OUT
FREQ
GND
6.65k
R
115k
fSET
INTERNAL
LOOP
FILTER
PHMODE
TRACK/SS
INTV
CC
DIFFN
DIFFP
–
+
+
C
SS
CLKIN
DIFF
AMP
MODE
–
250k
DIFFOUT
INTV
CC
1µF
TEMP
4649 F01
Figure 1. Simplified LTM4649 Block Diagram
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LTM4649
OPERATION
Power Module Description
The LTM4649 is internally compensated to be stable over
all operating conditions. Table 3 provides a guideline for
inputandoutputcapacitancesforseveraloperatingcondi-
tions. LTpowerCAD™isavailablefortransientandstability
The LTM4649 is a high performance single output stand-
alone nonisolated switching mode DC/DC power supply.
It can provide up to 10A output current with few exter-
nal input and output capacitors. This module provides
precisely regulated output voltage programmable via
an external resistor from 0.6VDC to 3.3VDC over a 4.5V
to 16V input range. The typical application schematic is
shown in Figure 17.
analysis.TheV pinisusedtoprogramtheoutputvoltage
FB
with a single external resistor to ground.
A remote sense amplifier is provided in the LTM4649 for
accuratelysensingoutputvoltages≤3.3Vattheloadpoint.
Multiphase operation can be easily employed with the
synchronization inputs using an external clock source.
See application examples.
The LTM4649 has an integrated constant-frequency cur-
rent mode regulator, power MOSFETs, inductor, and other
supporting discrete components. The typical switching
frequency is 450kHz. For switching noise-sensitive ap-
plications, it can be externally synchronized from 400kHz
to 800kHz. See the Applications Information section.
High efficiency at light loads can be accomplished with
selectableBurstModeoperationusingtheMODEpin.These
light load features will accommodate battery operation.
Efficiency graphs are provided for light load operation in
the Typical Performance Characteristics section.
With current mode control and internal feedback loop
compensation, the LTM4649 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, especially with all ceramic
output capacitors.
A TEMP pin is provided to allow the internal device tem-
peraturetobemonitoredusinganonboarddiodeconnected
PNP transistor. This diode connected PNP transistor is
grounded in the module and can be used as a general
temperature monitor using a device that is designed to
monitor the single-ended connection.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limit in an overcurrent condition. An internal overvoltage
monitor protects the output voltage in the event of an
overvoltage >10%. The top MOSFET is turned off and the
bottom MOSFET is turned on until the output is cleared.
The switching node pin is available for functional opera-
tion monitoring. A resistor-capacitor snubber circuit can
be carefully placed from the switching node pin to ground
to dampen any high frequency ringing on the transition
edges.SeetheApplicationsInformationsectionfordetails.
Pulling the RUN pin below 1.1V forces the regulator into a
shutdown state. The TRACK/SS pin is used for program-
ming the output voltage ramp and voltage tracking during
start-up. See the Application Information section.
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LTM4649
APPLICATIONS INFORMATION
The typical LTM4649 application circuit is shown in
Figure 17. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 3 for specific external capacitor
requirements for particular applications.
error due to this current, an additional V
pin can
OUT_LCL
be tied to V , and an additional R resistor can be used
OUT
FB
to lower the total Thevenin equivalent resistance seen by
this current.
Input Capacitors
V to V
Step-Down Ratios
IN
OUT
The LTM4649 module should be connected to a low AC
impedance DC source. Additional input capacitors are
neededfortheRMSinputripplecurrentrating.TheI
There are restrictions in the V to V
step-down ratio
IN
OUT
that can be achieved for a given input voltage. The V to
IN
CIN(RMS)
V
OUT
minimum dropout is a function of load current and
equation which follows can be used to calculate the input
capacitor requirement. Typically 22µF X7R ceramics are a
good choice with RMS ripple current ratings of ~2A each.
A47µFto100µFsurfacemountaluminumelectrolyticbulk
capacitor can be used for more input bulk capacitance.
This bulk input capacitor is only needed if the input source
impedanceiscompromisedbylonginductiveleads,traces
ornotenoughsourcecapacitance.Iflowimpedancepower
planes are used, then this bulk capacitor is not needed.
at very low input voltage and high duty cycle applications
output power may be limited as the internal top power
MOSFET is not rated for 10A operation at higher ambient
temperatures. At very low duty cycles a minimum 110ns
on-time should be maintained. See the Frequency Adjust-
ment section and temperature derating curves.
Output Voltage Programming
ThePWMcontrollerhasaninternal0.6Vreferencevoltage.
As shown in the Block Diagram, a 10k internal feedback
For a buck converter, the switching duty cycle can be
estimated as:
resistor connects the V
and V pins together.
OUT_LCL
FB
VOUT
When the remote sense amplifier is used, then DIFFOUT
D =
V
IN
is connected to the V pin. If the remote sense
OUT_LCL
amplifier isnotused, thenV
connects to V . The
OUT
OUT_LCL
Without considering the inductor ripple current, for each
output, the RMS current of the input capacitor can be
estimated as:
output voltage will default to 0.6V with no feedback resis-
tor. Adding a resistor R from V to ground programs
FB
FB
the output voltage:
IOUT(MAX)
ICIN(RMS)
=
• D• 1−D
(
)
10k+RFB
η%
VOUT = 0.6V •
RFB
In the previous equation, η% is the estimated efficiency of
thepowermodule.Thebulkcapacitorcanbeaswitcher-rated
aluminum electrolytic capacitor or a polymer capacitor.
Table 1. VFB Resistor Table vs Various Output Voltages
V
(V)
OUT
0.6
1.0
1.2
1.5
1.8
2.5
3.3
R
(k)
FB
OPEN
15
10
6.65
4.99
3.16
2.21
Output Capacitors
For parallel operation of N LTM4649, the following equa-
The LTM4649 is designed for low output voltage ripple
tion can be used to solve for R :
FB
noise. The bulk output capacitors defined as C
are
OUT
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient require-
10k
N
RFB =
ments. C
can be a low ESR tantalum capacitor, low
VOUT
0.6
OUT
– 1
ESR Polymer capacitor or ceramic capacitors. The typical
outputcapacitancerangeisfrom200µFto470µF.Additional
output filtering may be required by the system designer
if further reduction of output ripple or dynamic transient
In parallel operation the V pins have an I current of
25nA maximum each channel. To reduce output voltage
FB
FB
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LTM4649
APPLICATIONS INFORMATION
spikesisrequired.Table3showsamatrixofdifferentoutput
voltages and output capacitors to minimize the voltage
droop and overshoot during a 5A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to optimize the transient performance. Stability criteria
are considered in the Table 3 matrix, and LTpowerCAD is
available for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the num-
ber of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
afunctionofstabilityandtransientresponse.LTpowerCAD
can calculate the output ripple reduction as the number of
implemented phase’s increases by N times.
should be used. Pulse-skipping operation allows the
LTM4649toskipcyclesatlowoutputloads,thusincreasing
efficiency by reducing switching loss. Floating the MODE
pinenablespulse-skippingoperation.Withpulse-skipping
mode at light load, the internal current comparator may
remain tripped for several cycles, thus skipping opera-
tion cycles. This mode has lower ripple than Burst Mode
operationandmaintainsahigherfrequencyoperationthan
Burst Mode operation.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation
should be used. Forced continuous operation can be
enabled by tying the MODE pin to ground. In this mode,
inductor current is allowed to reverse during low output
loads, the COMP voltage is in control of the current
comparator threshold throughout, and the top MOSFET
alwaysturnsonwitheachoscillatorpulse.Duringstart-up,
forced continuous mode is disabled and inductor current
is prevented from reversing until the LTM4649’s output
voltage is in regulation.
Burst Mode Operation
TheLTM4649iscapableofBurstModeoperationinwhich
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
where maximizing the efficiency at very light loads is a
high priority, Burst Mode operation should be applied. To
enable Burst Mode operation, simply tie the MODE pin to
INTV . During Burst Mode operation, the peak current
CC
of the inductor is set to approximately 30% of the maxi-
mum peak current value in normal operation even though
the voltage at the COMP pin indicates a lower value. The
voltage at the COMP pin drops when the inductor’s aver-
age current is greater than the load requirement. As the
COMP voltage drops below 0.5V, the burst comparator
trips, causing the internal sleep line to go high and turn
off both power MOSFETs.
Frequency Selection
The LTM4649 device is internally programmed to 450kHz
switching frequency to improve power conversion ef-
ficiency. It is recommended for all applications with low
V
or low V . For applications with high V (V
≥
IN
OUT
IN
IN
12V) and high V
(V
≥ 1.8V), 750kHz is the rec-
OUT
OUT
ommended operating frequency to limit inductor ripple
current. Simply tie FREQ to INTV . Table 3 lists different
In sleep mode, the internal circuitry is partially turned
off, reducing the quiescent current. The load current is
now being supplied from the output capacitors. When the
output voltage drops, causing COMP to rise, the internal
sleep line goes low, and the LTM4649 resumes normal
operation. The next oscillator cycle will turn on the top
power MOSFET and the switching cycle repeats.
CC
frequency and FREQ pin recommendations for different
V , V
conditions.
IN OUT
If desired, a resistor can be connected from the FREQ pin
toINTV toadjusttheFREQpinDCvoltagetoincreasethe
CC
switching frequency between the default 450kHz and the
maximum 750kHz. Figure 2 shows a graph of frequency
versus FREQ pin DC voltage. Figure 18 shows an example
where the frequency is programmed to 650kHz. Please be
aware the FREQ pin has an internal 10µA current sourced
from this pin when calculating the resistor value.
Pulse-Skipping Mode Operation
Inapplicationswherelowoutputrippleandhighefficiency
atintermediatecurrentsaredesired, pulse-skippingmode
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LTM4649
APPLICATIONS INFORMATION
900
800
700
600
500
400
300
200
100
0
Multiphase Operation
For outputs that demand more than 10A of load current,
multiple LTM4649 devices can be paralleled to provide
more output current and reduced input and output volt-
age ripple.
The CLKOUT signal together with CLKIN pin can be used
tocascadeadditionalpowerstagestoachieveamultiphase
power supply solution. Tying the PHMODE pin to INTV ,
CC
GND, or leaving it floating generates a phase difference
(between CLKIN and CLKOUT) of 180°, 120°, or 90°
respectively as shown in Table 2. A total of 4 phases can
be cascaded to run simultaneously with respect to each
other by programming the PHMODE pin of each LTM4649
channel to different levels. Figure 3 shows a 3-phase de-
sign and 4-phase design example for clock phasing with
the PHMODE table.
0
0.5
1
1.5
2
2.5
FREQ PIN VOLTAGE (V)
4649 F02
Figure 2. Operating Frequency vs FREQ Pin Voltage
PLL and Frequency Synchronization
The LTM4649 device operates over a range of frequen-
cies to improve power conversion efficiency. The nominal
switchingfrequencyis450kHz.Itcanalsobesynchronized
from 400kHz to 800kHz with an input clock that has a high
level above 2V and a low level below 0.8V at the CLKIN pin.
Once the LTM4649 is synchronizing to an external clock
frequency, it will always be running in Forced Continuous
operation.Althoughsynchronizationto250kHzispossible,
400kHz is the lowest recommended operating frequency
to limit inductor ripple current.
Table 2. PHMODE and CLKOUT Signal Relationship
PHMODE
GND
FLOAT
INTV
CC
CLKOUT
120°
90°
180°
The LTM4649 device is an inherently current mode con-
trolled device, so parallel modules will have good current
sharing. This will balance the thermals in the design. Tie
theCOMP, V , TRACK/SSandRUNpinsofeachLTM4649
FB
together to share the current evenly. Figures 19 and 20
each show a schematic of a parallel design.
3-PHASE DESIGN
120 DEGREE
CLKOUT
120 DEGREE
CLKOUT
CLKOUT
CLKIN
CLKIN
CLKIN
0 PHASE
GND
120 PHASE
GND
240 PHASE
V
OUT
V
OUT
V
OUT
GND
PHMODE
PHMODE
PHMODE
4-PHASE DESIGN
90 DEGREE
90 DEGREE
90 DEGREE
CLKOUT
CLKOUT
CLKOUT
CLKOUT
CLKIN
CLKIN
CLKIN
CLKIN
0 PHASE
FLOAT
90 PHASE
180 PHASE
FLOAT
270 PHASE
V
OUT
V
OUT
V
OUT
V
OUT
FLOAT
FLOAT
PHMODE
PHMODE
PHMODE
PHMODE
4649 F03
Figure 3. Examples of 3-Phase, 4-Phase Operation with PHMODE Table
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LTM4649
APPLICATIONS INFORMATION
A multiphase power supply could significantly reduce
the amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by,
and the effective ripple frequency is multiplied by, the
number of phases used (assuming that the input voltage
isgreaterthanthenumberofphasesusedtimestheoutput
voltage). The output ripple amplitude is also reduced by
the number of phases used.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
VOUT
> tON(MIN)
V •FREQ
IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the output ripple and current will increase. The mini-
mum on-time can be increased by lowering the switching
frequency. A good rule of thumb is to assume a 110ns
minimum on-time.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reductionasafunctionofthenumberofinterleavedphases
(see Figure 4).
Soft-Start
The TRACK/SS pin of the master can be controlled by a
capacitorplacedfromthemasterregulatorTRACK/SSpinto
ground. A 1.2µA current source will charge the TRACK/SS
pin up to the reference voltage and then proceed up to
Minimum On-Time
Minimum on-time t is the smallest time duration that
the LTM4649 is capable of turning on the top MOSFET.
ON
0.60
1-PHASE
2-PHASE
0.55
3-PHASE
4-PHASE
6-PHASE
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
IN
O
4649 F04
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
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LTM4649
APPLICATIONS INFORMATION
INTV . After ramping to 0.6V, the TRACK/SS pin will no
as soon as V is below 0.54V regardless of the setting
CC
FB
longer be in control, and the internal voltage reference
will control output regulation from the feedback divider.
Foldback current limit is disabled during this sequence of
turn-on during tracking or soft-starting. The TRACK/SS
pin is pulled low when the RUN pin is below 1.2V. The
total soft-start time can be calculated as:
on the MODE pin.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up
and down with another regulator. The master regulator’s
output is divided down with an external resistor divider
that is the same as the slave regulator’s feedback divider
to implement coincident tracking. The LTM4649 uses an
accurate 10k resistor internally for the top feedback resis-
tor. Figure 6 shows the coincident tracking characteristic.
CSS
1.2µA
tSS
=
• 0.6V
Regardless of the mode selected by the MODE pin, the
regulator will always start in pulse-skipping mode up to
TRACK/SS = 0.5V. Between TRACK/SS = 0.5V and 0.54V,
it will operate in forced continuous mode and revert to the
selected mode once TRACK/SS > 0.54V. In order to track
with another regulator once in steady state operation,
the LTM4649 is forced into continuous mode operation
10k
VSLAVE = 1+
• V
TRACK
R
TA
V
V
is the track ramp applied to the slave’s track pin.
has a control range of 0V to 0.6V, or the internal
TRACK
TRACK
reference voltage. When the master’s output is divided
V
IN
C7
22µF
16V
C10
22µF
16V
SOFT-START
CAPACITOR
INTV
PGOOD
V
IN
CC
V
1.5V
10A
OUT2
COMP
V
C
OUT
OUT_LCL
R2
10k
SS
C11
TRACK/SS
V
100µF
6.3V
×2
LTM4649
RUN
DIFFOUT
DIFFP
FREQ
MODE
DIFFN
V
FB
GND
R
FB1
6.65k
V
IN
C3
C2
MASTER RAMP
OR OUTPUT
22µF
16V
22µF
16V
PGOOD
V
INTV
CC
IN
V
1.2V
10A
OUT1
R
TB
R
TA
COMP
V
OUT
OUT_LCL
10k
C6
10k
R1
10k
TRACK/SS
RUN
V
100µF
6.3V
×2
LTM4649
DIFFOUT
DIFFP
FREQ
MODE
DIFFN
4649 F05
V
FB
GND
R
FB
10k
Figure 5. Dual Outputs (1.5V and 1.2V) with Tracking
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LTM4649
APPLICATIONS INFORMATION
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
MASTER OUTPUT
Each of the TRACK/SS pins will have the 1.3µA current
source on when a resistive divider is used to implement
trackingonthatspecificchannel.Thiswillimposeanoffset
on the TRACK/SS pin input. Smaller value resistors with
the same ratios as the resistor values calculated from the
previous equations can be used. For example, where the
10k value is calculated then a 1.0k can be used to reduce
the TRACK/SS pin offset to a negligible value.
SLAVE OUTPUT
TIME
4649 F06
Figure 6. Output Coincident Tracking Characteristic
Power Good
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point. A pull-up
resistor can be connected from PGOOD to a supply volt-
age no greater than 6V.
tracking is disabled when V
is more than 0.6V. RTA
TRACK
in Figure 5 will be equal to R for coincident tracking.
FB
Ratiometric tracking can be achieved by a few simple
calculations and the slew rate value applied to the mas-
ter’s TRACK/SS pin. As mentioned above, the TRACK/SS
pin has a control range from 0V to 0.6V. The master’s
TRACK/SS pin slew rate is directly equal to the master’s
Stability Compensation
The module has already been internally compensated for
alloutputvoltages.Table3isprovidedformostapplication
requirements. LTpowerCAD is available for other control
loop optimization.
output slew rate in Volts/Time. The equation for R :
TB
MR
SR
Run Enable
•10k =RTB
The RUN pin has an enable threshold of 1.4V maximum,
typically 1.25V with 150mV of hysteresis. It controls the
turn-on of the µModule. The RUN pin can be pulled up to
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus R
is equal to 10k. R is derived from equation:
V for 5V operation, or a 5V Zener diode can be placed
IN
TB
on the pin and a 10k to 100k resistor can be placed up to
higher than 5V input for enabling the µModule. The RUN
pin can also be used for output voltage sequencing.
TA
0.6V
RTA
=
V
V
VTRACK
RTB
FB
FB
In parallel operation the RUN pins can be tied together and
controlled from a single control. See the Typical Applica-
tion circuits in Figures 19 and 20. The RUN pin can also
be left floating. The RUN pin has a 1µA pull-up current
source that increases to 4.5µA during ramp-up.
+
−
10k RFB
where V is the feedback voltage reference of the regula-
tor, and V
FB
TRACK
is 0.6V. Since R is equal to the 10k top
TB
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then R is equal to R with V
TA
FB
FB
Differential Remote Sense Amplifier
= V
. Therefore R = 10k, and R = 10k in Figure 5.
TRACK
TB TA
Anaccuratedifferentialremotesenseamplifierisprovided
in the LTM4649 to sense low output voltages accurately
at the remote load points. This is especially applicable for
Inratiometrictracking, adifferentslewratemaybedesired
for the slave regulator. R can be solved for when SR is
TB
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LTM4649
APPLICATIONS INFORMATION
high current loads. It is very important that the DIFFP and
DIFFN are connected properly at the output, and DIFFOUT
Temperature Monitoring
A diode connected PNP transistor is used for the TEMP
monitor function by monitoring its voltage over tempera-
ture. The temperature dependence of this diode voltage
can be understood in the equation:
is connected to V
. Review the parallel schematics
OUT_LCL
in Figures 19 and 20.
SW Pins
ID
The SW pin is generally used for testing purposes. The
SW pin can also be used to dampen out switch node ring-
ing caused by LC parasitic in the switched current path.
Usually a series R-C combination is used, referred to as a
snubbercircuit.Theresistorwilldampentheresonanceand
the capacitor is chosen to only affect the high frequency
ringing across the resistor.
V = nV ln
D
T
I
S
where V is the thermal voltage (kT/q), and n, the ideality
T
factor, is 1 for the diode connected PNP transistor be-
ing used in the LTM4649. I is expressed by the typical
S
empirical equation:
If the stray inductance or capacitance can be measured
or approximated then a somewhat analytical technique
can be used to select the snubber values. The inductance
is usually easier to determine. It combines the power
path board inductance in combination with the MOSFET
interconnect bond wire inductance.
–V
G0
VT
I =I exp
0
S
where I is a process and geometry dependent current, (I
0
0
S
is typically around 20k orders of magnitude larger than I
at room temperature) and V is the band gap voltage of
G0
1.2V extrapolated to absolute zero or –273°C.
First the SW pin can be monitored using a wide band-
width scope with a high frequency scope probe. The ring
frequency can be measured for its value. The impedance
Z can be calculated:
If we take the I equation and substitute into the V equa-
tion, then we get:
S
D
kT
q
I0
kT
q
V = V –
ln
,V =
D
T
G0
Z = 2π • f • L
L
I
D
where f is the resonant frequency of the ring, and L is the
total parasitic inductance in the switch path. If a resistor
is selected that is equal to Z, then the ringing should be
dampened. The snubber capacitor value is chosen so that
its impedance is equal to the resistor at the ring frequency.
Calculated by:
The expression shows that the diode voltage decreases
(linearly if I were constant) with increasing temperature
0
and constant diode current. Figure 7 shows a plot of V
D
vs Temperature over the operating temperature range of
the LTM4649.
If we take this equation and differentiate it with respect to
temperature T, then:
1
ZC =
2π • f •C
dVD
dT
VG0 − VD
These values are a good place to start. Modification to
these components should be made to attenuate the ring-
ing with the least amount of power loss.
= −
T
This dV /dT term is the temperature coefficient equal to
D
about –2mV/K or –2mV/°C. The equation is simplified for
the first order derivation.
Solving for T, T = –(V – V )/(dV /dT) provides the
G0
D
D
temperature.
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LTM4649
APPLICATIONS INFORMATION
0.8
to compliment any FEA activities. Without FEA software,
the thermal resistances reported in the Pin Configuration
section are, in and of themselves, not relevant to provid-
ing guidance of thermal performance; instead, the derat-
ing curves provided in this data sheet can be used in a
manner that yields insight and guidance pertaining to
one’s application usage, and can be adapted to correlate
thermal performance to one’s own application.
I
= 100µA
D
0.7
0.6
0.5
0.4
0.3
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD51-12; these coef-
ficients are quoted or paraphrased below:
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
4649 F07
1. θ : the thermal resistance from junction to ambient, is
Figure 7. Diode Voltage VD vs Temperature T(°C)
JA
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
1st Example: Figure 7 for 27°C, or 300K the diode voltage
is 0.598V, thus, 300K = –(1200mV – 598mV)/–2.0mV/K).
2nd Example: Figure 7 for 75°C, or 350K the diode voltage
is 0.5V, thus, 350K = –(1200mV – 500mV)/–2.0mV/K).
Converting the Kelvin scale to Celsius is simply taking the
Kelvin temperature and subtracting 273 from it.
2. θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottomofthepackage.InthetypicalµModuleregulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditionsdon’tgenerallymatchtheuser’sapplication.
Measure the forward voltage at 27°C to establish a refer-
ence point. Then using the above expression while mea-
suring the forward voltage over temperature will provide a
general temperature monitor. Connect a resistor between
TEMP and V to set the current to 100µA. See Figure 21
IN
for an example.
Thermal Considerations and Output Current Derating
3. θ
: the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
component power dissipation flowing through the top
of the package. As the electrical connections of the
typical µModule are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-12 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients is
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
As in the case of θ
, this value may be useful
JCbottom
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θ : the thermal resistance from junction to the printed
JB
circuitboard,isthejunction-to-boardthermalresistance
where almost all of the heat flows through the bottom
oftheµModulepackageandintotheboard, andisreally
Manydesignersmayopttouselaboratoryequipmentanda
testvehiclesuchasthedemoboardtopredicttheµModule
regulator’s thermal performance in their application at
various electrical and environmental operating conditions
the sum of the θ
and the thermal resistance of
JCbottom
4649fc
18
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
the bottom of the part through the solder joints and
through a portion of the board. The board temperature
is measured a specified distance from the package.
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware
is used to accurately build the mechanical geometry of
the LTM4649 and the specified PCB with all of the cor-
rect material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4649 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamber while operating the device at the same power
loss as that which was simulated. The outcome of this
processandduediligenceyieldsthesetofderatingcurves
shown in this data sheet. After these laboratory tests have
been performed and correlated to the LTM4649 model,
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 8; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal oper-
ating conditions of a μModule regulator. For example, in
normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
for θ
and θ , respectively. In practice, power
JCbottom
JCtop
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4649, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
then the θ and θ values are summed together to
JB
BA
correlate quite well with the µModule model for θ with
JA
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4649 F08
µMODULE DEVICE
Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients
4649fc
19
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
curves are taken at room temperature, and are increased
with a multiplicative factor according to the ambient
temperature. This approximate factor is: 1.4 for 120°C.
The derating curves are plotted with the output current
starting at 10A and the ambient temperature at 40°C. The
output voltages are 1.5V and 3.3V. These are chosen to
include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derived from several temperature measurements in a
controlled temperature chamber along with thermal mod-
eling analysis. The junction temperatures are monitored
no airflow or heat sinking in a properly defined chamber.
This θ + θ value is shown in the Pin Configuration
JB
BA
section and should accurately equal the θ value because
JA
approximately 100% of power loss flows from the junc-
tion through the board into ambient with no airflow or top
mounted heat sink.
The 5V and 12V power loss curves in Figures 9 and 10
IN
IN
can be used in coordination with the load current derating
curves in Figures 11 to 14 for calculating an approximate
θ
thermal resistance for the LTM4649 with various
JA
heat sinking and airflow conditions. The power loss
3.0
2.5
3.0
2.5
12
10
8
2.0
1.5
2.0
1.5
6
1.0
0.5
0
1.0
0.5
0
4
400LFM
2
200LFM
0LFM
V
V
= 3.3V
= 1.5V
V
V
= 3.3V
= 1.5V
OUT
OUT
OUT
OUT
0
0
2
4
6
8
10
0
2
4
6
8
10
0
40
60
80
100
120
20
LOAD CURRENT (A)
LOAD CURRENT (A)
AMBIENT TEMPERATURE (°C)
4649 F09
4649 F10
4649 F11
Figure 9. 5VIN, 3.3VOUT and
1.5VOUT Power Loss
Figure 10. 12VIN, 3.3VOUT
and 1.5VOUT Power Loss
Figure 11. No Heat Sink with 5VIN
to 1.5VOUT
12
10
8
12
10
8
12
10
8
6
6
6
4
4
4
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
400LFM
200LFM
0LFM
2
2
2
0
0
0
0
40
60
80
100
120
0
40
60
80
100
120
0
40
60
80
100
120
20
20
20
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4649 F12
4649 F13
4649 F14
Figure 12. No Heat Sink with
12VIN to 1.5VOUT
Figure 13. No Heat Sink with
5VIN to 3.3VOUT
Figure 14. No Heat Sink with
12VIN to 3.3VOUT
4649fc
20
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
and 3.3V outputs with and without airflow. The derived
thermal resistances in Tables 4 and 5 for the various con-
ditions can be multiplied by the calculated power loss as
a function of ambient temperature to derive temperature
rise above ambient, thus maximum junction temperature.
Room temperature power loss can be derived from the ef-
ficiencycurvesintheTypicalPerformanceCharacteristics
section and adjusted with the above ambient temperature
multiplicativefactors.Theprintedcircuitboardisa1.6mm
thick four layer board with two ounce copper for the two
outerlayersandoneouncecopperforthetwoinnerlayers.
The PCB dimensions are 95mm × 76mm.
while ambient temperature is increased with and without
airflow.Thepowerlossincreasewithambienttemperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
currentorpowerwithincreasingambienttemperature.The
decreasedoutputcurrentwilldecreasetheinternalmodule
loss as ambient temperature is increased. The monitored
junctiontemperatureof120°Cminustheambientoperating
temperaturespecifieshowmuchmoduletemperaturerise
canbeallowed.AsanexampleinFigure12theloadcurrent
is derated to ~8A at ~90°C with no air or heat sink and
the power loss for the 12V to 1.5V at 8A output is about
2.24W. The 2.24W loss is calculated with the 1.6W room
temperature loss from the 12V to 1.5V power loss curve
at 8A, and the 1.40 multiplying factor at 120°C junction. If
the90°Cambienttemperatureissubtractedfromthe120°C
junction temperature, then the difference of 30°C divided
Safety Considerations
The LTM4649 module does not provide galvanic isolation
from V to V . There is no internal fuse. If required,
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
by 2.24W equals a 13°C/W θ thermal resistance. Table 4
JA
specifies a 14°C/W value which is very close. Table 4 and
Table 5 provide equivalent thermal resistances for 1.5V
48.1°C
48.8°C
4649 F15
Figure 15. Thermal Image 12V to 1.5V at 10A
(No Heat Sink, No Air Flow. At Room Temperature Ambient)
4649fc
21
For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
Layout Checklist/Example
• Place a dedicated power ground layer underneath the
unit.
The high integration of LTM4649 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout con-
siderations are still necessary.
• Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Use large PCB copper areas for high current path,
• Do not put vias directly on the pads, unless they are
capped.
including V , GND and V . It helps to minimize the
IN
OUT
PCB conduction loss and thermal stress.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
• Place high frequency ceramic input and output capaci-
tors next to the V , GND and V
pins to minimize
IN
OUT
high frequency noise.
Figure16givesagoodexampleoftherecommendedlayout.
V
OUT
GND
C
OUT
C
IN
GND
V
IN
4649 F16
Figure 16. Recommended PCB Layout
4649fc
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For more information www.linear.com/LTM4649
LTM4649
APPLICATIONS INFORMATION
Table 3. Output Voltage Response vs Component Matrix (Refer to Figure 18) 0A to 5A Load Step Typical Measured Values
C
C
C
OUT
IN
IN
(BULK)*
VENDORS
PART NUMBER (CERAMIC) VENDORS
PART NUMBER
(CERAMIC) VENDORS
PART NUMBER
150µF, SANYO OSCON 25HVH150MT 22µF, 16V
16V
MURATA GRM32ER71C226KE18L 100µF, 6.3V MURATA GRM32ER60J107ME20L
220µF, 4V MURATA
GRM31CR60G227M
C
C
C
OUT
RECOVERY LOAD STEP
FREQ
SW FREQ PIN
IN
IN
V
V
(BULK)* (CERAMIC) (CERAMIC)
C
FF
LOAD STEP
V
V
TIME
40µs
50µs
60µs
70µs
70µs
70µs
70µs
30µs
40µs
40µs
50µs
50µs
60µs
60µs
SPEED
1A/µs
1A/µs
1A/µs
1A/µs
1A/µs
1A/µs
1A/µs
1A/µs
1A/µs
1A/µs
1A/µs
1A/µs
1A/µs
1A/µs
R
FB
OUT
IN
DROOP
P-P
1V 5V, 12V 120µF* 22µF × 2
1.2V 5V, 12V 120µF* 22µF × 2
1.5V 5V, 12V 120µF* 22µF × 2
100µF × 3 None 75% to 100% 45mV
90mV
15kΩ 450kHz
10kΩ 450kHz
6.65kΩ 450kHz
3.16kΩ 450kHz
Float
Float
Float
Float
100µF × 3 None 75% to 100% 50mV 100mV
100µF × 3 None 75% to 100% 57mV 114mV
100µF × 3 None 75% to 100% 75mV 150mV
100µF × 3 None 75% to 100% 75mV 150mV
100µF × 3 None 75% to 100% 95mV 190mV
100µF × 3 None 75% to 100% 95mV 190mV
220µF × 2 None 50% to 100% 70mV 140mV
220µF × 2 None 50% to 100% 75mV 150mV
220µF × 2 None 50% to 100% 90mV 180mV
220µF × 2 None 50% to 100% 135mV 270mV
220µF × 2 None 50% to 100% 135mV 270mV
220µF × 2 None 50% to 100% 175mV 350mV
220µF × 2 None 50% to 100% 175mV 350mV
2.5V
2.5V
3.3V
3.3V
5V
12V
5V
120µF* 22µF × 2
120µF* 22µF × 2
120µF* 22µF × 2
120µF* 22µF × 2
3.16kΩ 750kHz INTV
CC
2.21kΩ 450kHz
Float
12V
2.21kΩ 750kHz INTV
CC
1V 5V, 12V 120µF* 22µF × 2
1.2V 5V, 12V 120µF* 22µF × 2
1.5V 5V, 12V 120µF* 22µF × 2
15kΩ 450kHz
10kΩ 450kHz
6.65kΩ 450kHz
3.16kΩ 450kHz
Float
Float
Float
Float
2.5V
2.5V
3.3V
3.3V
5V
12V
5V
120µF* 22µF × 2
120µF* 22µF × 2
120µF* 22µF × 2
120µF* 22µF × 2
3.16kΩ 750kHz INTV
CC
2.21kΩ 450kHz
Float
12V
2.21kΩ 750kHz INTV
CC
*Bulk capacitor is optional if V has very low input impedance.
IN
Table 4. 1.5V Output
DERATING CURVE
Figures 11, 12
Figures 11, 12
Figures 11, 12
V
(V)
POWER LOSS CURVE
Figure 9
AIR FLOW (LFM)
HEAT SINK
None
θ
θ
(°C/W)
14
IN
JA
5, 12
5, 12
5, 12
0
Figure 9
200
400
None
12
Figure 9
None
10
Table 5. 3.3V Output
DERATING CURVE
Figures 13, 14
VIN (V)
5, 12
5, 12
5, 12
POWER LOSS CURVE
Figure 10
AIR FLOW (LFM)
HEAT SINK
None
(°C/W)
14
JA
0
Figures 13, 14
Figure 10
200
400
None
12
Figures 13, 14
Figure 10
None
10
4649fc
23
For more information www.linear.com/LTM4649
LTM4649
TYPICAL APPLICATIONS
FREQ
CLKIN
V
V
1.5V
10A
OUT
V
IN
V
IN
OUT
4.5V TO 16V
C
C
22µF
16V
OUT1
IN
INTV
SW
V
CC
OUT_LCL
DIFFOUT
C
100µF
6.3V
OUT2
100µF
6.3V
RUN
DIFFP
LTM4649
MODE
DIFFN
PHMODE
TRACK/SS
V
FB
COMP
R
FB
TEMP
GND
PGOOD
CLKOUT
6.65k
C1
0.1µF
4649 F17
Figure 17. 4.5V to 16VIN, 1.5V at 10A Design
1M
FREQ
CLKIN
V
V
3.3V
8A
OUT
V
IN
V
IN
OUT
4.5V TO 16V
100µF
6.3V
×2
C
22µF
16V
C
IN
22µF
16V
IN
INTV
SW
V
OUT_LCL
CC
DIFFOUT
RUN
DIFFP
DIFFN
LTM4649
MODE
PHMODE
TRACK/SS
V
FB
COMP
R
FB
TEMP
GND
PGOOD
CLKOUT
2.21k
C1
0.1µF
4649 F18
Figure 18. 4.5V to 16V VIN, 3.3VOUT at 8A Design with Increased 650kHz Frequency
4649fc
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For more information www.linear.com/LTM4649
LTM4649
TYPICAL APPLICATIONS
FREQ
CLKIN
V
V
1.5V
30A
OUT
V
IN
V
IN
OUT
4.5V TO 16V
C
22µF
16V
C
IN1
OUT1
INTV
SW
V
CC
OUT_LCL
DIFFOUT
100µF
6.3V
C
OUT2
100µF
6.3V
RUN
RUN
DIFFP
LTM4649
MODE
DIFFN
PHMODE
TRACK/SS
V
FB
R
COMP
FB
C1
0.1µF
6.65k
TEMP
GND
PGOOD
CLKOUT
FREQ
IN
CLKIN
OUT
V
OUT_LCL
V
V
C
C
C
22µF
16V
OUT3
OUT4
IN2
INTV
SW
CC
100µF
6.3V
100µF
6.3V
DIFFOUT
RUN
DIFFP
DIFFN
LTM4649
MODE
PHMODE
TRACK/SS
V
FB
COMP
TEMP
GND
PGOOD
CLKOUT
FREQ
IN
CLKIN
V
V
OUT
V
OUT_LCL
C
C
C
22µF
16V
OUT5
OUT6
IN3
INTV
SW
CC
100µF
6.3V
100µF
6.3V
DIFFOUT
RUN
DIFFP
DIFFN
LTM4649
MODE
4649 F19
PHMODE
TRACK/SS
V
FB
COMP
TEMP
GND
PGOOD
CLKOUT
PGOOD
Figure 19. Three LTM4649 in Parallel, 1.5V at 30A Design
4649fc
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For more information www.linear.com/LTM4649
LTM4649
TYPICAL APPLICATIONS
FREQ
CLKIN
V
FREQ
CLKIN
V
OUT
V
3.3V
8A
V
1.8V
10A
OUT1
OUT3
V
IN
V
V
IN
OUT
IN
4.5V TO 16V
C
C
OUT5
C
22µF
16V
C
22µF
16V
OUT1
IN1
IN3
INTV
SW
V
INTV
SW
V
CC
OUT_LCL
DIFFOUT
CC
OUT_LCL
DIFFOUT
100µF
6.3V
100µF
6.3V
C
OUT6
100µF
6.3V
C
OUT2
100µF
6.3V
RUN
DIFFP
RUN
DIFFP
V
LTM4649
LTM4649
OUT1
MODE
DIFFN
MODE
DIFFN
R6
10k
PHMODE
TRACK/SS
V
PHMODE
TRACK/SS
V
FB
FB
COMP
COMP
R1
2.21k
R5
4.99k
R7
4.87k
TEMP
GND
PGOOD
CLKOUT
TEMP
GND
PGOOD
CLKOUT
C1
0.1µF
FREQ
CLKIN
FREQ
CLKIN
V
2.5V
10A
V
1.5V
10A
OUT2
OUT4
V
V
OUT
V
V
OUT
IN
IN
C
C
OUT7
C
22µF
16V
C
22µF
16V
OUT3
IN2
IN4
INTV
SW
V
INTV
SW
V
OUT_LCL
CC
OUT_LCL
CC
C
100µF
6.3V
100µF
6.3V
OUT8
C
OUT4
DIFFOUT
DIFFP
DIFFOUT
DIFFP
100µF
6.3V
100µF
6.3V
RUN
RUN
V
V
LTM4649
LTM4649
OUT1
OUT1
MODE
DIFFN
MODE
DIFFN
R3
10k
R9
10k
PHMODE
TRACK/SS
V
PHMODE
TRACK/SS
V
FB
FB
COMP
COMP
R2
3.09k
R2
6.65k
R4
3.09k
R10
6.65k
TEMP
GND
PGOOD
CLKOUT
TEMP
GND
PGOOD
CLKOUT
4649 F20
Figure 20. Quad Outputs 4-Phase LTM4649 Regulator with Tracking Function
FREQ
CLKIN
V
V
1.5V
10A
OUT
V
IN
V
IN
OUT
4.5V TO 16V
C
22µF
16V
C
IN
OUT1
INTV
SW
V
CC
OUT_LCL
DIFFOUT
C
100µF
6.3V
OUT2
0.1µF
100µF
6.3V
RUN
DIFFP
LTM4649
MODE
DIFFN
PHMODE
TRACK/SS
V
FB
COMP
V
– 0.6V
100µA
R
IN
FB
TEMP
GND
PGOOD
CLKOUT
R7 =
6.65k
C1
V
IN
0.1µF
UC
R7
A/D
4649 F21
Figure 21. Single LTM4649 10A Design with Temperature Monitoring
4649fc
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For more information www.linear.com/LTM4649
LTM4649
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4649#packaging/ for the most recent package drawings.
Z
Z
/ / b b b
Z
3 . 8 1 0
2 . 5 4 0
1 . 2 7 0
0 . 3 1 7 5
0 . 3 1 7 5
1 . 2 7 0
0 . 0 0 0
2 . 5 4 0
3 . 8 1 0
4649fc
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For more information www.linear.com/LTM4649
LTM4649
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4649 BGA Pin Assignment Table
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1
A2
GND
GND
GND
GND
GND
TEMP
GND
GND
GND
GND
GND
B1
B2
GND
–
C1
C2
VIN
–
D1
D2
VIN
–
E1
E2
E3
E4
GND
–
F1
F2
RUN
CLCKOUT
GND
G1
G2
GND
GND
A3
B3
CLKIN
PHMODE
MODE
–
C3
NC
D3
VIN
VIN
VIN
–
FREQ
–
F3
G3
GND
A4
B4
C4
NC
D4
F4
INTVCC
GND
G4
GND
A5
B5
C5
SW
–
D5
E5 TRACK/SS
F5
G5
GND
A6
B6
C6
D6
E6
E7
–
F6
COMP
DIFFN
DIFFP
VOUT
G6
GND
A7
B7
NC
C7
PGOOD
VIN
D7
VIN
VIN
VIN
VOUT
VOUT
FB
F7
G7
GND
A8
B8
NC
C8
D8
E8
VIN
F8
G8
DIFFOUT
VOUT_LCL
VOUT
A9
B9
GND
GND
GND
C9
VIN
D9
E9
VOUT
VOUT
VOUT
F9
G9
A10
A11
B10
B11
C10
C11
VOUT
VOUT
D10
D11
E10
E11
F10
F11
VOUT
G10
G11
VOUT
VOUT
PACKAGE PHOTO
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For more information www.linear.com/LTM4649
LTM4649
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
2/14
Added SnPb (lead) BGA package.
Figures 9 and 10 changed Y-Axis to Power Loss (W).
1, 2
20
11
17
9
B
C
12/15 Corrected R (k) for 2.5V from 3.06 to 3.16.
FB
Revised Temperature Monitoring discussion.
Added CLKOUT, PHMODE and SW pins on Block Diagram.
7/17
Corrected note number to COMP from Note 6 to Note 3.
2
4649fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconne tion f i s circui s a scribed reinill n in rin n existing patent rights.
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LTM4649
TYPICAL APPLICATION
CLOCK
CLKIN
V
1.2V
10A
OUT
CLKIN
FREQ
FREQ
V
1.8V
10A
OUT
V
IN
4.5V TO 16V
V
V
V
V
IN
OUT
IN
OUT
V
OUT_LCL
C
22µF
16V
C
22µF
16V
IN1
IN2
C
C
C
C
OUT4
100µF
6.3V
OUT1
OUT2
OUT3
INTV
SW
V
INTV
SW
CC
OUT_LCL
CC
100µF
6.3V
100µF
6.3V
100µF
6.3V
DIFFOUT
DIFFP
DIFFOUT
DIFFP
RUN
RUN
LTM4649
LTM4649
MODE
DIFFN
MODE
DIFFN
R2
INTV
INTV
CC
PHMODE
TRACK/SS
V
PHMODE
TRACK/SS
V
CC
FB
FB
10k
MASTER
SLOPE
COMP
COMP
R1
10k
R4
4.99k
R3
10k
TEMP
GND
PGOOD
TEMP
GND
PGOOD
CLKOUT
CLKOUT
4649 F22
Figure 22. Dual Output 1.2V, 1.8V 2-Phase LTM4649 Regulator with Tracking
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM4627
20V, 15A Step-Down µModule Regulator
4.5V ≤ V ≤ 20V, 0.6V ≤ V
≤ 5V, PLL input, Remote Sense Amplifier,
IN
OUT
V
Tracking, 15mm × 15mm × 4.3mm LGA and 15mm × 15mm × 4.9mm
OUT
BGA
LTM4620A
LTM4613
LTM8045
LTM8061
Dual 16V, 13A or Single 26A Step-Down µModule
Regulator
4.5V ≤ V ≤ 16V, 0.6V ≤ V
≤ 5.3V, PLL Input, Remote Sense Amplifier,
IN
OUT
V
Tracking, 15mm × 15mm × 4.41mm LGA
OUT
36V , 8A EN55022 Class B Certified DC/DC Step-Down 5V ≤ V ≤ 36V, 3.3V ≤ V
≤ 15V, PLL Input, V
Tracking and Margining,
IN
IN
OUT
OUT
µModule Regulator
15mm × 15mm × 4.32mm LGA
Inverting or SEPIC µModule DC/DC Converter with Up to 2.8V ≤ V ≤ 18V, 2.5V ≤ V
700mA Output Current
32V, 2A Step-Down µModule Battery Charger with
Programmable Input Current Limit
≤
15V, Synchronizable,
6.25mm × 11.25mm × 4.92mm BGA
CC-CV Charging Single and Dual Cell Li-Ion or Li-Poly Batteries,
IN
OUT
4.95V ≤ V ≤ 32V, C/10 or Adjustable Timer Charge Termination,
IN
9mm × 15mm × 4.32mm LGA
LTM8048
LTC2974
1.5W, 725VDC Galvanically Isolated µModule Converter
with LDO post regulator
Quad Digital Power Supply Manager with EEPROM
3.1V ≤ V ≤ 32V, 2.5V ≤ V
≤ 12V, 1mV Output Ripple, Internal Isolated
IN
OUT PP
Transformer, 9mm × 11.25mm × 4.92mm BGA
2
I C/PMBus Interface, Configuration EEPROM, Fault Logging, Per Channel
Voltage, Current and Temperature Measurements
4649fc
LT 0717 REV C • PRINTED IN USA
www.linear.com/LTM4649
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LINEAR TECHNOLOGY CORPORATION 2013
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