LTM8048MPY [Linear]
LTM8048 - 3.1VIN to 32VIN Isolated µModule (Power Module) DC/DC Converter with LDO Post Regulator; Package: BGA; Pins: 45; Temperature Range: -55°C to 125°C;
| 型号： | LTM8048MPY |
| 厂家： | 
Linear |
| 描述： | LTM8048 - 3.1VIN to 32VIN Isolated µModule (Power Module) DC/DC Converter with LDO Post Regulator; Package: BGA; Pins: 45; Temperature Range: -55°C to 125°C 开关 |
| 文件： | 总20页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM8048
3.1V to 32V Isolated
IN
IN
µModule DC/DC Converter
with LDO Post Regulator
FEATURES
DESCRIPTION
n
Complete Switch Mode Power Supply
The LTM®8048 is an isolated flyback µModule DC/DC
converter with LDO post regulator. The LTM8048 has an
isolation rating of 725VDC. Included in the package are
theswitchingcontroller, powerswitches, transformer, and
all support components. Operating over an input voltage
range of 3.1V to 32V, the LTM8048 supports an output
voltage range of 2.5V to 13V, set by a single resistor. There
is also a linear post regulator whose output voltage is ad-
justable from 1.2V to 12V as set by a single resistor. Only
output, input, and bypass capacitors are needed to finish
the design. Other components may be used to control the
soft-start control and biasing.
n
725VDC Isolation
n
Wide Input Voltage Range: 3.1V to 32V
n
V
Output:
OUT1
Up to 440mA (V
= 2.5V, 24V )
IN
OUT1
2.5V to 13V Output Range
OUT2
n
V
Low Noise Linear Post Regulator:
Up to 300mA
1.2V to 12V Output Range
n
n
n
n
n
Current Mode Control
Programmable Soft-Start
User Configurable Undervoltage Lockout
SnPb or RoHS Compliant Finish
Low Profile (11.25mm × 9mm × 4.92mm) Surface
Mount BGA Package
The LTM8048 is packaged in a thermally enhanced, com-
pact (11.25mm × 9mm × 4.92mm) over-molded ball grid
array (BGA) package suitable for automated assembly by
standardsurfacemountequipment.TheLTM8048isavail-
able with SnPb (BGA) or RoHS compliant terminal finish.
APPLICATIONS
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
n
Industrial Sensors
n
Industrial Switches
n
Ground Loop Mitigation
TYPICAL APPLICATION
Total Output Current vs VIN
725V DC Isolated Low Noise µModule Regulator
330
LTM8048
5.7V
V
IN
V
V
V
280
IN
OUT1
3.1V TO 29V
V
2.2µF
OUT2
RUN
BIAS
OUT2
BYP
5V
230
180
130
80
4.7µF
6.19k
22µF
10µF
ADJ1
SS
ADJ2
–
162k
GND
V
OUT
8048 TA01
725VDC ISOLATION
0
5
10
15
20
25
30
INPUT VOLTAGE (V)
8048 TA01b
8048fg
1
For more information www.linear.com/LTM8048
LTM8048
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V , RUN, BIAS ........................................................32V
IN
ADJ1, SS.....................................................................5V
A
–
ADJ2
B
V
Relative to V
OUT1
Relative to V
............................................16V
OUT
..........................................+20V
OUT1
OUT
–
(V – GND) + (V
– V
).................................36V
IN
C
–
–
V
OUT2
BANK 3
OUT2
BANK 2
–
BANK 1
OUT
BYP
D
E
V
V
V
OUT
OUT1
ADJ2 Relative to V
.............................................+7V
............................................+0.6V
OUT
OUT
–
BANK 4
GND
BYP Relative to V
BANK 5
IN
F
BIAS Above V ........................................................ 0.1V
V
IN
RUN
–
G
H
ADJ1
GND to V
Isolation (Note 2) ........................725VDC
OUT
Maximum Internal Temperature (Note 3).............. 125°C
Maximum Solder Temperature..............................250°C
Storage Temperature.............................. –55°C to 125°C
BIAS SS
1
2
3
4
5
6
7
BGA PACKAGE
45-LEAD (11.25mm × 9mm × 4.92mm)
= 125°C, θ = 23.2°C/W, θ = 5.8°C/W, θ = 23.2°C/W, θ = 6.7°C/W
T
JMAX
JA
JCbottom
JCtop
JB
WEIGHT = 1.1g, θ VALUES DETERMINED PER JEDEC 51-9, 51-12
ORDER INFORMATION
PART MARKING*
PAD OR BALL
PART NUMBER
LTM8048EY#PBF
LTM8048IY#PBF
LTM8048IY
FINISH
DEVICE
FINISH CODE
PACKAGE TYPE
MSL RATING TEMPERATURE RANGE (NOTE 3)
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
SAC305 (RoHS)
SnPb (63/37)
LTM8048Y
LTM8048Y
LTM8048Y
LTM8048Y
LTM8048Y
e1
e1
e0
e1
e0
BGA
BGA
BGA
BGA
BGA
3
3
3
3
3
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–55°C to 125°C
LTM8048MPY#PBF
LTM8048MPY
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Pb-free & Non-Pb-free Part Markings:
www.linear.com/leadfree
• BGA Package and Tray Drawings:
www.linear.com/packaging/
8048fg
2
For more information www.linear.com/LTM8048
LTM8048
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, RUN = 12V (Note 3).
PARAMETER
CONDITIONS
BIAS = V
MIN
TYP
MAX
UNITS
l
l
Minimum Input DC Voltage
3.1
V
IN
V
DC Voltage
R
ADJ1
R
ADJ1
R
ADJ1
= 12.4k
= 6.98k
= 3.16k
2.5
5
12
V
V
V
OUT1
4.75
5.25
1
V
IN
Quiescent Current
V
= 0V
µA
µA
RUN
Not Switching
850
1.7
1.5
20
V
OUT1
V
OUT1
V
OUT1
Line Regulation
Load Regulation
Ripple (RMS)
6V ≤ V ≤ 31V, I = 0.15A
OUT
%
%
IN
0.05A ≤ I
≤ 0.2A
OUT
I
= 0.1A
mV
mA
V
OUT
Input Short Circuit Current
RUN Pin Input Threshold
RUN Pin Current
V
Shorted
30
OUT1
RUN Pin Rising
1.18
1.24
1.30
V
RUN
V
RUN
= 1V
= 1.3V
2.5
0.1
µA
µA
SS Threshold
0.7
–10
8
V
µA
mA
V
SS Sourcing Current
BIAS Current
SS = 0V
V
= 12V, BIAS = 5V, I
= 100mA
LOAD1
IN
Minimum BIAS Voltage (Note 4)
I
= 100mA
3.1
2.3
LOAD1
LDO (V
) Minimum Input DC Voltage
OUT2
(Note 5)
1.8
V
V
OUT2
Voltage Range
V
OUT1
V
OUT1
= 16V, R
= 16V, R
Open, No Load (Note 5)
= 41.2k, No Load (Note 5)
1.22
15.8
V
V
ADJ2
ADJ2
ADJ2 Pin Voltage
V
OUT1
V
OUT1
V
OUT1
= 2V, I
= 2V, I
= 2V, I
= 1mA (Note 5)
= 1mA, E- and I-Grades (Note 5)
= 1mA, MP-Grade (Note 5)
1.22
V
V
V
OUT2
OUT2
OUT2
l
l
1.19
1.15
1.25
1.29
V
V
Line Regulation
Load Regulation
2V < V
< 16V, I = 1mA (Note 5)
OUT2
1
2
5
mV
mV
OUT2
OUT2
OUT1
V
OUT1
= 5V, 10mA < I
= 300mA (Note 5)
OUT2
10
LDO Dropout Voltage
I
I
I
= 10mA (Note 5)
= 100mA (Note 5)
= 300mA (Note 5)
0.25
0.34
0.43
V
V
V
OUT2
OUT2
OUT2
V
Ripple (RMS)
C
BYP
= 0.01µF, I
= 300mA, BW = 100Hz to 100kHz (Note 5)
20
µV
RMS
OUT2
OUT2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
range. The LTM8048MP is guaranteed to meet specifications over the
full –55°C to 125°C internal operating temperature range. Note that
the maximum internal temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 2: The LTM8048 isolation is tested at 725VDC for one second in each
polarity.
Note 4: This is the BIAS pin voltage at which the internal circuitry is
powered through the BIAS pin and not the integrated regulator. See BIAS
Pin Considerations for details.
Note 3: The LTM8048E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C internal
temperature range are assured by design, characterization and correlation
with statistical process controls. LTM8048I is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
Note 5: V
powered by applying a voltage to V
= 0V (Flyback not running), but the V
post regulator is
RUN
OUT2
.
OUT1
8048fg
3
For more information www.linear.com/LTM8048
LTM8048
Unless otherwise noted, operating conditions are
TYPICAL PERFORMANCE CHARACTERISTICS
as in Table 1 (TA = 25°C).
Efficiency vs Load
Efficiency vs Load
Efficiency vs Load
90
80
70
60
50
90
80
70
60
50
90
V
= 2.5V
V
= 3.3V
V
= 5V
OUT1
OUT1
OUT1
BIAS = 5V
BIAS = 5V
BIAS = 5V
12V
IN
12V
80
70
60
50
IN
12V
IN
24V
IN
24V
IN
24V
IN
0
100
200
300
400
500
0
100
200
300
400
0
50 100 150 200 250 300 350
CURRENT (mA)
V
CURRENT (mA)
V
CURRENT (mA)
V
OUT1
OUT1
OUT1
8048 G01
8048 G02
8048 G03
Efficiency vs Load
Efficiency vs Load
BIAS Current vs VOUT1 Load
100
90
80
70
60
100
90
80
70
60
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
V
= 8V
V
= 12V
V
= 2.5V
OUT1
OUT1
OUT1
12V
IN
BIAS = 5V
BIAS = 5V
BIAS = 5V
12V
12V
IN
IN
24V
IN
24V
IN
24V
IN
0
50 100 150 200 250 300 350
CURRENT (mA)
0
50
100
150
200
250
0
100
200
300
400
500
V
V
CURRENT (mA)
V
OUT1
CURRENT (mA)
OUT1
OUT1
8048 G04
8048 G05
8048 G06
BIAS Current vs VOUT1 Load
BIAS Current vs VOUT1 Load
BIAS Current vs VOUT1 Load
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
10
9
12
11
10
9
V
= 3.3V
V
= 5V
V
= 8V
OUT1
OUT1
12V
OUT1
IN
12V
IN
BIAS = 5V
BIAS = 5V
BIAS = 5V
12V
IN
8
24V
IN
24V
24V
IN
IN
7
8
7
6
6
5
5
4
4
0
100
200
300
400
0
50 100 150 200 250 300 350
CURRENT (mA)
0
50 100 150 200 250 300 350
V
CURRENT (mA)
V
V
CURRENT (mA)
OUT1
OUT1
OUT1
8048 G07
8048 G08
8048 G09
8048fg
4
For more information www.linear.com/LTM8048
LTM8048
Unless otherwise noted, operating conditions are
TYPICAL PERFORMANCE CHARACTERISTICS
as in Table 1 (TA = 25°C).
BIAS Current vs VOUT1 Load
Maximum Load vs VIN
Maximum Load vs VIN
13
12
11
10
9
500
450
400
350
300
250
200
150
100
350
V
= 12V
BIAS = V IF V ≤ 5V
BIAS = V IF V ≤ 5V
IN IN
BIAS = 5V IF V > 5V
IN
OUT1
IN
IN
BIAS = 5V
BIAS = 5V IF V > 5V
12V
IN
IN
300
250
200
150
100
50
24V
IN
8
7
6
2.5V
3.3V
OUT1
OUT1
OUT1
8V
5
OUT1
OUT1
5V
12V
4
0
0
50
100
150
200
250
0
5
10
15
(V)
20
25
30
0
5
10
V
IN
15
(V)
20
25
V
CURRENT (mA)
V
OUT1
IN
8048 G10
8048 G11
8048 12
Input Current vs VIN
VOUT1 Shorted
Minimum Load vs VIN
Minimum Load vs VIN
40
35
30
25
20
15
10
5
15
12
9
80
70
60
50
40
30
20
10
2.5V
3.3V
OUT1
8V
OUT1
OUT1
OUT1
12V
OUT1
5V
6
3
0
0
0
5
10
15
(V)
20
25
30
0
5
10
15
(V)
20
25
30
0
4
8
12 16 20 24 28 32
(V)
V
V
V
IN
IN
IN
8048 G13
8048 G14
8048 G15
Input Current vs VIN
VOUT2 Shorted
VOUT2 Output Ripple and Noise
VOUT2 Dropout Voltage vs Load
225
200
175
150
125
100
75
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
V
V
= 12V
V
= 3.3V
OUT2
IN
= 5.7V
= 5V
OUT1
OUT2
125°C
500µV/DIV
25°C
–40°C
8048 G26
1µs/DIV
MEASURED PER AN70,
USING HP461A AMPLIFIER,
150MHz BW
50
0
10
20
(V)
30
40
0
50
100
150
200
250
300
V
V
OUT2
LOAD CURRENT (mA)
IN
8048 G16
8048 G17
8048fg
5
For more information www.linear.com/LTM8048
LTM8048
Unless otherwise noted, operating conditions are
TYPICAL PERFORMANCE CHARACTERISTICS
as in Table 1 (TA = 25°C).
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
10
V
= 1.2V
V
= 1.5V
V
= 1.8V
OUT2
OUT2
OUT2
9
8
7
6
5
4
3
2
1
0
3.3V
5V
12V
24V
3.3V
5V
12V
24V
3.3V
IN
5V
12V
24V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
0
50
100
150
200
250
300
0
50
100
150
200
250
300
0
50
100
150
200
250
300
V
LOAD CURRENT (mA)
V
LOAD CURRENT (mA)
V
OUT2
LOAD CURRENT (mA)
OUT2
OUT2
8048 G18
8048 G19
8048 G20
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
12
10
8
14
12
10
8
10
9
8
7
6
5
4
3
2
1
0
V
= 3.3V
V
= 5V
OUT2
V
= 2.5V
OUT2
OUT2
6
6
4
4
3.3V
5V
12V
24V
3.3V
IN
5V
12V
24V
3.3V
5V
12V
24V
IN
IN
IN
IN
IN
IN
IN
IN
2
IN
IN
IN
2
0
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
0
50
100
150
200
250
300
V
LOAD CURRENT (mA)
V
OUT2
LOAD CURRENT (mA)
V
LOAD CURRENT (mA)
OUT2
OUT2
8048 G22
8048 G23
8048 G21
Junction Temperature Rise vs
Load Current
Junction Temperature Rise vs
Load Current
16
14
12
10
8
16
V
= 8V
V
= 12V
OUT2
OUT2
14
12
10
8
6
6
4
4
3.3V
IN
3.3V
IN
IN
5V
5V
IN
2
2
12V
24V
12V
24V
IN
IN
IN
IN
0
0
0
50
100
150
200
250
300
0
50
100
150
200
250
V
LOAD CURRENT (mA)
V
OUT2
LOAD CURRENT (mA)
OUT2
8048 G24
8048 G25
8048fg
6
For more information www.linear.com/LTM8048
LTM8048
PIN FUNCTIONS
–
V
(Bank 1): V
and V comprise the isolated
BYP (Pin B2): The BYP pin is used to bypass the refer-
OUT1
OUT1
OUT
output of the LTM8048 flyback stage. Apply an external
ence of the LDO to achieve low noise performance from
–
–
capacitor between V
to exceed V
and V
. Do not allow V
the linear post regulator. The BYP pin is clamped internally
OUT1
OUT
OUT
–
.
to 0.6V relative to V
. A small capacitor from V
OUT1
OUT
OUT2
to this pin will bypass the reference to lower the output
–
–
V
(Bank 2): V
is the return for both V
and
OUT1
OUT
V
OUT
and V
voltage noise. A maximum value of 0.01µF can be used
–
. V
comprise the isolated output of
OUT2 OUT1
OUT
for reducing output voltage noise to a typical 20µV
RMS
the LTM8048. In most applications, the bulk of the heat
over a 100Hz to 100kHz bandwidth. If not used, this pin
–
flow out of the LTM8048 is through the GND and V
OUT
must be left unconnected.
pads, so the printed circuit design has a large impact on
the thermal performance of the part. See the PCB Layout
RUN (Pin F3): A resistive divider connected to V and this
IN
and Thermal Considerations sections for more details.
pin programs the minimum voltage at which the LTM8048
will operate. Below 1.24V, the LTM8048 does not deliver
power to the secondary. Above 1.24V, power will be de-
livered to the secondary and 10µA will be fed into the SS
pin. When RUN is less than 1.24V, the pin draws 2.5µA,
allowing for a programmable hysteresis. Do not allow a
negative voltage (relative to GND) on this pin.
–
Apply an external capacitor between V
and V
.
OUT1
OUT
V
(Bank 3): The output of the secondary side linear
OUT2
postregulator.Applytheloadandoutputcapacitorbetween
–
V
OUT2
andV
.SeetheApplicationsInformationsection
OUT
for more information on output capacitance and reverse
output characteristics.
ADJ1 (Pins G7): Apply a resistor from this pin to GND to
GND (Bank 4): This is the primary side local ground of the
–
set the output voltage V
relative to V
, using the
OUT1
OUT
LTM8048primary.Inmostapplications,thebulkoftheheat
recommended value given in Table 1. If Table 1 does not
–
flow out of the LTM8048 is through the GND and V
OUT
list the desired V
value, the equation
OUT1
pads, so the printed circuit design has a large impact on
the thermal performance of the part. See the PCB Layout
and Thermal Considerations sections for more details.
–0.879
kΩ
RADJ1 = 28.4 V
OUT1
may be used to approximate the value. To the seasoned
designer,thisexponentialequationmayseemunusual.The
equation is exponential due to non-linear current sources
that are used to temperature compensate the regulation.
V (Bank 5): V supplies current to the LTM8048’s inter-
IN
IN
nal regulator and to the integrated power switch. These
pins must be locally bypassed with an external, low ESR
capacitor.
BIAS (Pin H5): This pin supplies the power necessary to
operate the LTM8048. It must be locally bypassed with a
low ESR capacitor of at least 4.7μF. Do not allow this pin
ADJ2(pinA2):Thisistheinputtotheerroramplifierofthe
secondary side LDO post regulator. This pin is internally
clamped to 7V. The ADJ2 pin voltage is 1.22V referenced
–
voltage to rise above V .
to V
and the output voltage range is 1.22V to 12V. Ap-
IN
OUT
–
ply a resistor from this pin to V
, using the equation
OUT
SS(PinH6):Placeasoft-startcapacitorheretolimitinrush
current and the output voltage ramp rate. Do not allow a
negative voltage (relative to GND) on this pin.
R
= 608.78/(V
– 1.22)kΩ. If the post regulator
ADJ2
OUT2
is not used, leave this pin floating.
8048fg
7
For more information www.linear.com/LTM8048
LTM8048
BLOCK DIAGRAM
V
V
V
OUT1
IN
OUT2
•
499k
0.1µF
•
ADJ2
BYP
1µF
LOW NOISE
LDO
RUN
BIAS*
SS
–
V
OUT
CURRENT
MODE
CONTROLLER
ADJ1
GND
8048 BD
*DO NOT ALLOW BIAS VOLTAGE TO BE ABOVE V
IN
8048fg
8
For more information www.linear.com/LTM8048
LTM8048
OPERATION
The LTM8048 is a stand-alone isolated flyback switching
DC/DC power supply that can deliver up to 440mA of
output current. This module provides a regulated output
voltage programmable via one external resistor from 2.5V
to 13V. It is also equipped with a high performance linear
post regulator. The input voltage range of the LTM8048 is
3.1V to 32V. Given that the LTM8048 is a flyback converter,
the output current depends upon the input and output
voltages, so make sure that the input voltage is high
enough to support the desired output voltage and load
current. The Typical Performance Characteristics section
An internal regulator provides power to the control cir-
cuitry. The bias regulator normally draws power from the
IN
V
pin, but if the BIAS pin is connected to an external
voltage higher than 3.1V, bias power will be drawn from
the external source, improving efficiency. V
must not
BIAS
exceed V . The RUN pin is used to turn on or off the
IN
LTM8048,disconnectingtheoutputandreducingtheinput
current to 1μA or less.
The LTM8048 is a variable frequency device. For a fixed
input and output voltage, the frequency increases as the
load increases. For light loads, the current through the
internal transformer may be discontinuous.
gives several graphs of the maximum load versus V for
several output voltages.
IN
The post regulator is a high performance 300mA low
dropout regulator with micropower quiescent current and
shutdown. The device is capable of supplying 300mA at
a dropout voltage of 300mV. Output voltage noise can be
Asimplifiedblockdiagramisgiven.TheLTM8048contains
acurrentmodecontroller,powerswitchingelement,power
transformer, power Schottky diode, a modest amount of
input and output capacitance and a high performance
linear post regulator.
lowered to 20µV
over a 100Hz to 100kHz bandwidth
RMS
with the addition of a 0.01μF reference bypass capacitor.
Additionally, this reference bypass capacitor will improve
transient response of the regulator, lowering the settling
time for transient load conditions. The linear regulator is
protected against both reverse input and reverse output
voltages.
The LTM8048 has a galvanic primary to secondary isola-
tion rating of 725VDC. This is verified by applying 725VDC
between the primary to secondary for 1 second and then
applying –725VDC for 1 second. For details please refer
to the Isolation and Working Voltage section.
8048fg
9
For more information www.linear.com/LTM8048
LTM8048
APPLICATIONS INFORMATION
For most applications, the design process is straight
indicated in Table 1 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
forward, summarized as follows:
1. Look at Table 1a (or Table 1b, if the post linear regula-
tor is used) and find the row that has the desired input
range and output voltage.
2. Apply the recommended C , C
, C
, R
,
IN
OUT1
OUT2
ADJ1
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and ap-
plied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application cir-
cuit they may have only a small fraction of their nominal
capacitanceresultinginmuchhigheroutputvoltageripple
than expected.
R
and C
if required.
ADJ2
BYP
3. Connect BIAS as indicated, or tie to an external source
up to 15V or V , whichever is less.
IN
Whilethesecomponentcombinationshavebeentestedfor
proper operation, it is incumbent upon the user to verify
proper operation over the intended system’s line, load and
environmentalconditions. Bearinmindthatthemaximum
output current may be limited by junction temperature,
the relationship between the input and output voltage
magnitude and polarity and other factors. Please refer
to the graphs in the Typical Performance Characteristics
section for guidance.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8048. A
ceramic input capacitor combined with trace or cable
inductance forms a high-Q (underdamped) tank circuit. If
the LTM8048 circuit is plugged into a live supply, the input
voltage can ring to much higher than its nominal value,
possibly exceeding the device’s rating. This situation is
easily avoided; see the Hot-Plugging Safely section.
Capacitor Selection Considerations
The C , C
and C
capacitor values in Table 1 are
IN OUT1
OUT2
the minimum recommended values for the associated op-
erating conditions. Applying capacitor values below those
LTM8048 Table 1a. Recommended Component Values and Configuration for Specific VOUT1 Voltages (TA = 25°C)
V
V
V
C
C
R
ADJ1
IN
OUT1
BIAS
IN
OUT1
3.1V to 32V
3.1V to 32V
3.1V to 29V
3.1V to 26V
3.1V to 24V
9V to 15V
2.5V
3.3V
5V
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 25V, 0805
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 25V, 0805
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
100µF, 6.3V, 1210
100µF, 6.3V, 1210
22µF, 16V, 1210
22µF, 10V, 1206
10µF, 16V, 1210
100µF, 6.3V, 1210
47µF, 6.3V, 1210
22µF, 16V, 1210
22µF, 10V, 1206
10µF, 16V, 1210
100µF, 6.3V, 1210
47µF, 6.3V, 1210
22µF, 16V, 1210
22µF, 10V, 1206
10µF, 16V, 1210
12.4k
10k
6.98k
8V
4.53k
12V
2.5V
3.3V
5V
3.16k/12pF*
12.4k
V
V
V
V
V
IN
IN
IN
IN
IN
9V to 15V
10k
9V to 15V
6.98k
9V to 15V
8V
4.53k
9V to 15V
12V
2.5V
3.3V
5V
3.16k
18V to 32V
18V to 32V
18V to 29V
18V to 26V
18V to 24V
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
12.4k
10k
6.98k
8V
4.53k
12V
3.16k/12pF*
Note: Do not allow BIAS to exceed V , a bulk input capacitor is required.
IN
*Connect 3.16k in parallel with 12pF from ADJ to GND.
8048fg
10
For more information www.linear.com/LTM8048
LTM8048
APPLICATIONS INFORMATION
LTM8048 Table 1b. Recommended Component Values and Configuration for Specific VOUT2 Voltages (TA = 25°C)
V
V
V
V
C
IN
C
OUT1
C
OUT2
R
ADJ1
R
ADJ2
IN
OUT1
OUT2
BIAS
3.1V to 32V
3.1V to 32V
3.1V to 32V
3.1V to 32V
3.1V to 32V
3.1V to 29V
3.1V to 26V
3.1V to 21V
9V to 15V
1.71V
2.02V
2.34V
3.08V
3.92V
5.7V
1.2V
1.5V
1.8V
2.5V
3.3V
5V
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 25V, 0805
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 25V, 0805
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
2.2µF, 50V, 1206
100µF, 6.3V, 1210
100µF, 6.3V, 1210
100µF, 6.3V, 1210
100µF, 6.3V, 1210
47µF, 6.3V, 1210
22µF, 16V, 1210
22µF, 10V, 1206
10µF, 16V, 1210
100µF, 6.3V, 1210
100µF, 6.3V, 1210
100µF, 6.3V, 1210
100µF, 6.3V, 1210
47µF, 6.3V, 1210
22µF, 16V, 1210
22µF, 10V, 1206
10µF, 16V, 1210
100µF, 6.3V, 1210
100µF, 6.3V, 1210
100µF, 6.3V, 1210
100µF, 6.3V, 1210
47µF, 6.3V, 1210
22µF, 16V, 1210
22µF, 10V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 10V, 1206
10µF, 16V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 10V, 1206
10µF, 16V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 6.3V, 1206
10µF, 10V, 1206
16.5k
14.7k
Open
2.32M
1.07M
487k
13.3k
10.5k
8.66k
294k
6.19k
162k
8.85V
13V
8V
4.12k
88.7k
56.2k
Open
2.32M
1.07M
487k
12V
1.2V
1.5V
1.8V
2.5V
3.3V
5V
2.94k/12pF*
16.5k
1.71V
2.02V
2.34V
3.08V
3.92V
5.7V
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
9V to 15V
14.7k
9V to 15V
13.3k
9V to 15V
10.5k
9V to 15V
8.66k
294k
9V to 15V
6.19k
162k
9V to 15V
8.85V
13V
8V
4.12k
88.7k
56.2k
Open
2.32M
1.07M
487k
9V to 15V
12V
1.2V
1.5V
1.8V
2.5V
3.3V
5V
2.94k/12pF*
16.5k
18V to 32V
18V to 32V
18V to 32V
18V to 32V
18V to 32V
18V to 29V
18V to 26V
1.71V
2.02V
2.34V
3.08V
3.92V
5.7V
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
3.1V to 15V or Open
14.7k
13.3k
10.5k
8.66k
294k
6.19k
162k
8.85V
8V
4.12k
88.7k
Note: Do not allow BIAS to exceed V , a bulk input capacitor is required.
IN
*Connect 2.94k in parallel with 12pF from ADJ to GND.
BIAS Pin Considerations
regulator. This has the added advantage of keeping the
physical size of the BIAS capacitor small. Do not allow
The BIAS pin is the output of an internal linear regulator
that powers the LTM8048’s internal circuitry. It is set to
3V and must be decoupled with a low ESR capacitor of at
least 4.7μF. The LTM8048 will run properly without apply-
ing a voltage to this pin, but will operate more efficiently
and dissipate less power if a voltage greater than 3.1V is
BIAS to rise above V .
IN
Soft-Start
For many applications, it is necessary to minimize the
inrush current at start-up. The built-in soft-start circuit
significantly reduces the start-up current spike and output
voltageovershootbyapplyingacapacitorfromSStoGND.
applied. At low V , the LTM8048 will be able to deliver
IN
more output current if BIAS is 3.1V or greater. Up to 32V
may be applied to this pin, but a high BIAS voltage will
causeexcessivepowerdissipationintheinternalcircuitry.
For applications with an input voltage less than 15V, the
When the LTM8048 is enabled, whether from V reaching
IN
a sufficiently high voltage or RUN being pulled high, the
LTM8048 will source approximately 10µA out of the SS
pin. As this current gradually charges the capacitor from
SS to GND, the LTM8048 will correspondingly increase
the power delivered to the output, allowing for a graceful
turn-on ramp.
BIAS pin is typically connected directly to the V pin. For
IN
input voltages greater than 15V, it is preferred to leave the
BIAS pin separate from the V pin, either powered from
IN
a separate voltage source or left running from the internal
8048fg
11
For more information www.linear.com/LTM8048
LTM8048
APPLICATIONS INFORMATION
Isolation and Working Voltage
resistor from the R
pin to GND; the value of R
ADJ2 ADJ2
can be calculated by the equation:
The LTM8048 isolation is tested by tying all of the primary
pins together, all of the secondary pins together and
subjecting the two resultant circuits to a differential of
725VDC for one second. This establishes the isolation
voltage rating, but it does not determine the working volt-
age rating, which is subject to the application board layout
and possibly other factors. The metal to metal separation
of the primary and secondary throughout the LTM8048
substrate is 0.44mm.
608.78
VOUT2 – 1.22
RADJ2
=
kΩ
–
V
to V
Reverse Voltage
OUT1
OUT
TheLTM8048cannottolerateareversevoltagefromV
OUT1
OUT1
–
–
to V
during operation. If V
raises above V
OUT
OUT
duringoperation,theLTM8048maybedamaged.Toprotect
against this condition, a low forward drop power Schottky
ADJ and Line Regulation
diode has been integrated into the LTM8048, anti-parallel
–
to V
/V
. This can protect the output against many
OUT1 OUT
For V
greater than 8V, a capacitor connected from ADJ
OUT
reverse voltage faults. Reverse voltage faults can be both
steady state and transient. An example of a steady state
voltage reversal is accidentally misconnecting a powered
LTM8048 to a negative voltage source. An example of
transient voltage reversals is a momentary connection to
to GND improves line regulation. Figure 1 shows the ef-
fect of three capacitance values applied to ADJ for a load
of 15mA. No capacitance has poor line regulation, while
12pF has improved line regulation. As the capacitance
increases, the line regulation begins to degrade again, but
in the opposite direction as having too little capacitance.
Furthermore,toomuchcapacitancefromADJtoGNDmay
increasetheminimumloadrequiredforproperregulation.
a negative voltage. It is also possible to achieve a V
OUT1
reversal if the load is short-circuited through a long cable.
The inductance of the long cable forms an LC tank circuit
with the V
capacitance, which drive V
negative.
OUT1
OUT1
12.50
Avoid these conditions.
NO CAP
12pF
12.25
18pF
V
Post Regulator Bypass Capacitance and Low
OUT2
12.00
Noise Performance
11.75
11.50
11.25
11.00
10.75
The V linear regulator may be used with the addition
OUT2
of a 0.01μF bypass capacitor from V
to the BYP pin
OUT
to lower output voltage noise. A good quality low leakage
capacitor,suchasaX5RorX75ceramic,isrecommended.
This capacitor will bypass the reference of the regulator,
lowering the output voltage noise to as low as 20µV
.
RMS
0
5
10
V
15
(V)
20
25
Using a bypass capacitor has the added benefit of improv-
IN
8048 F01
ing transient response.
Figure 1. For Higher Output Voltages, the LTM8048 Requires
Some Capacitance from ADJ to GND for Proper Line Regulation
Safety Rated Capacitors
Some applications require safety rated capacitors, which
are high voltage capacitors that are specifically designed
and rated for AC operation and high voltage surges. These
capacitorsareoftencertifiedtosafetystandardssuchasUL
60950, IEC 60950 and others. In the case of the LTM8048,
V
Post Regulator
OUT2
V
is produced by a high performance low dropout
OUT2
300mA regulator. At full load, its dropout is less than
430mV over temperature. Its output is set by applying a
8048fg
12
For more information www.linear.com/LTM8048
LTM8048
APPLICATIONS INFORMATION
a common application of a safety rated capacitor would
ADJ1
–
V
C
be to connect it from GND to V
. To provide maximum
OUT1
OUT
LTM8048
flexibility, the LTM8048 does not include any components
–
between GND and V
added externally.
. Any safety capacitors must be
OUT
SS
OUT1
V
The specific capacitor and circuit configuration for any
application depends upon the safety requirements of
the system into which the LTM8048 is being designed.
Table 2 provides a list of possible capacitors and their
manufacturers.
BIAS
GND
–
OUT
RUN
ADJ2 BYP
C
V
OUT2
OUT2
Table 2. Safety Rated Capacitors
MANUFACTURER
PART NUMBER
DESCRIPTION
Murata Electronics GA343DR7GD472KW01L
4700pF, 250VAC, X7R,
4.5mm × 3.2mm
Capacitor
C
IN
V
IN
THERMAL/INTERCONNECT VIAS
Johanson Dielectrics 302R29W471KV3E-****-SC 470pF, 250VAC,
8048 F02
X7R, 4.5mm × 2mm
Capacitor
Figure 2. Layout Showing Suggested External Components,
Planes and Thermal Vias
Syfer Technology
1808JA250102JCTSP
100pF, 250VAC, C0G,
1808 Capacitor
4. Place the C and C
capacitors such that their
OUT
IN
–
ground current flow directly adjacent or underneath
the LTM8048.
The application of a capacitor from GND to V
alsoreducethehighfrequencyoutputnoiseontheoutput.
may
OUT
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8048.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8048. The LTM8048 is neverthe-
less a switching power supply, and care must be taken to
minimizeelectricalnoisetoensureproperoperation. Even
with the high level of integration, you may fail to achieve
specified operation with a haphazard or poor layout. See
Figure 2 for a suggested layout. Ensure that the grounding
and heat sinking are acceptable.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 2. The LTM8048 can benefit from
theheatsinkingaffordedbyviasthatconnecttointernal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
A few rules to keep in mind are:
1. PlacetheR
andR
resistorsascloseaspossible
ADJ2
ADJ1
to their respective pins.
2. Place the C capacitor as close as possible to the V
IN
IN
and GND connections of the LTM8048.
3. Place the C
capacitor as close as possible to V
OUT1
OUT1
Hot-Plugging Safely
–
and V
. Likewise, place the C
capacitor as close
OUT
OUT2
.
–
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
8048fg
as possible to V
and V
OUT2
OUT
13
For more information www.linear.com/LTM8048
LTM8048
APPLICATIONS INFORMATION
Forincreasedaccuracyandfidelitytotheactualapplication,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration section of the data sheet
typically gives four thermal coefficients:
bypass capacitor of the LTM8048. However, these capaci-
tors can cause problems if the LTM8048 is plugged into a
live supply (see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt-
ꢀ θ : Thermal resistance from junction to ambient
JA
ꢀ θ
: Thermal resistance from junction to the bot-
JCbottom
tom of the product case
age at the V pin of the LTM8048 can ring to more than
IN
twice the nominal input voltage, possibly exceeding the
LTM8048’s rating and damaging the part. A similar phe-
nomenon can occur inside the LTM8048 module, at the
output of the integrated EMI filter, with the same potential
of damaging the part. If the input supply is poorly con-
trolled or the user will be plugging the LTM8048 into an
energized supply, the input network should be designed
to prevent this overshoot. This can be accomplished by
ꢀ θ : Thermal resistance from junction to top of the
JCtop
product case
ꢀ θ
:Thermalresistancefromjunctiontotheprinted
JCboard
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confu-
sion and inconsistency. These definitions are given in
JESD 51-12, and are quoted or paraphrased as follows:
installing a small resistor in series to V , but the most
IN
popular method of controlling input voltage overshoot is
adding an electrolytic bulk capacitor to the V or f net.
IN
IN
θ
is the natural convection junction-to-ambient air
JA
Thiscapacitor’srelativelyhighequivalentseriesresistance
damps the circuit and eliminates the voltage overshoot.
The extra capacitor improves low frequency ripple filter-
ing and can slightly improve the efficiency of the circuit,
though it can be a large component in the circuit.
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as still air although natural convection causes the air to
move. This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect an
actual application or viable operating condition.
Thermal Considerations
θ
is the junction-to-board thermal resistance with
JCbottom
The LTM8048 output current may need to be derated if it
is required to operate in a high ambient temperature. The
amount of current derating is dependent upon the input
voltage, output power and ambient temperature. The
temperature rise curves given in the Typical Performance
Characteristicssectioncanbeusedasaguide.Thesecurves
allofthecomponentpowerdissipationflowingthroughthe
bottom of the package. In the typical µModule converter,
the bulk of the heat flows out the bottom of the package,
but there is always heat flow out into the ambient envi-
ronment. As a result, this thermal resistance value may
be useful for comparing packages but the test conditions
don’t generally match the user’s application.
2
were generated by the LTM8048 mounted to a 58cm
4-layer FR4 printed circuit board. Boards of other sizes
and layer count can exhibit different thermal behavior, so
it is incumbent upon the user to verify proper operation
over the intended system’s line, load and environmental
operating conditions.
θ
isdeterminedwithnearlyallofthecomponentpower
JCtop
dissipation flowing through the top of the package. As the
electricalconnectionsofthetypicalµModuleconverterare
8048fg
14
For more information www.linear.com/LTM8048
LTM8048
APPLICATIONS INFORMATION
on the bottom of the package, it is rare for an application
to operate such that most of the heat flows from the junc-
correlate to the junction temperature vs load graphs given
in the product’s data sheet. The only appropriate way to
use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
tion to the top of the part. As in the case of θ
, this
JCbottom
value may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
θ
isthejunction-to-boardthermalresistancewhere
A graphical representation of these thermal resistances
is given in Figure 3.
JCboard
almost all of the heat flows through the bottom of the
µModule converter and into the board, and is really the
sum of the θ
bottom of the part through the solder joints and through a
portion of the board. The board temperature is measured
a specified distance from the package, using a two-sided,
two-layer board. This board is described in JESD 51-9.
The blue resistances are contained within the µModule
converter, and the green are outside.
and the thermal resistance of the
JCbottom
The die temperature of the LTM8048 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM8048. The bulk of the heat flow out of the LTM8048
is through the bottom of the module and the BGA pads
into the printed circuit board. Consequently a poor printed
circuit board design can cause excessive heating, result-
ing in impaired performance or reliability. Please refer to
the PCB Layout section for printed circuit board design
suggestions.
Giventhesedefinitions,itshouldnowbeapparentthatnone
of these thermal coefficients reflects an actual physical
operating condition of a µModule converter. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
BOARD-TO-AMBIENT
RESISTANCE
RESISTANCE
8048 F03
µMODULE DEVICE
Figure 3.
8048fg
15
For more information www.linear.com/LTM8048
LTM8048
TYPICAL APPLICATIONS
V
OUT2 Output Current vs VIN
3.3V Flyback Converter
340
320
300
280
260
240
220
200
LTM8048
3.9V
V
IN
V
V
V
IN
OUT1
OUT2
9V TO 15V
V
OUT2
RUN
2.2µF
3.3V
BIAS
BYP
4.7µF
8.66k
47µF
10µF
ADJ1
SS
ADJ2
–
294k
GND
V
OUT
8048 TA02
725VDC ISOLATION
9
10
11
12
(V)
13
14
15
V
IN
8048 TA02b
VOUT2 Output Current vs VIN
12V Flyback Converter with Low Noise Bypass
250
230
210
190
170
150
130
110
90
LTM8048
13V
V
IN
V
V
OUT1
IN
5VDC TO 23VDC
V
OUT2
RUN
V
OUT2
12V
0.01µF
56.2k
5V
BIAS
BYP
10µF
4.7µF
2.94k
ADJ1
SS
ADJ2
–
10µF
GND
V
OUT
70
8048 TA03
725VDC ISOLATION
50
5
10
15
(V)
20
25
V
IN
8048 TA03b
Total Output Current vs VIN
500
450
400
350
300
250
200
150
100
3.3V and 2.5V Flyback Converter
LTM8048
V
V
OUT1
IN
V
V
V
IN
OUT1
3.3V
3.5VDC TO 32VDC
V
OUT2
2.2µF
RUN
BIAS
OUT2
BYP
2.5V
4.7µF
100µF
10µF
10k
ADJ1
SS
ADJ2
–
487k
GND
V
OUT
0
8
16
(V)
24
32
8048 TA04
725VDC ISOLATION
V
IN
8048 TA04b
8048fg
16
For more information www.linear.com/LTM8048
LTM8048
PACKAGE DESCRIPTION
Pin Assignment Table
(Arranged by Pin Number)
PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION
A1
A2
A3
A4
A5
A6
A7
V
ADJ2
B1
B2
B3
B4
B5
B6
B7
V
BYP
C1
C2
C3
C4
C5
C6
C7
V
V
V
V
V
V
V
D1
D2
D3
D4
D5
D6
D7
-
-
-
-
-
-
-
E1
E2
E3
E4
E5
E6
E7
GND
GND
GND
GND
GND
GND
GND
F1
F2
F3
F4
F5
F6
F7
-
-
G1
G2
G3
G4
G5
G6
G7
V
V
-
GND
GND
GND
ADJ1
H1
H2
H3
H4
H5
H6
H7
V
V
-
GND
BIAS
SS
OUT2
OUT2
OUT2
IN
IN
OUT2
IN
IN
–
–
–
V
V
V
V
V
V
RUN
GND
GND
GND
GND
OUT
OUT
OUT
OUT
OUT
OUT
OUT
–
–
–
–
–
V
V
V
V
OUT
–
OUT
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
GND
PACKAGE PHOTO
8048fg
17
For more information www.linear.com/LTM8048
LTM8048
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
/ / b b b
Z
3 . 8 1 0
2 . 5 4 0
1 . 2 7 0
0 . 3 1 7 5
0 . 0 0 0
0 . 3 1 7 5
1 . 2 7 0
2 . 5 4 0
3 . 8 1 0
8048fg
18
For more information www.linear.com/LTM8048
LTM8048
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
6/12
Added storage temperature range.
2
Clarify V
Clarify R
and ADJ1 pin function description.
equation.
8
OUT2
ADJ2
13
20
12
Updated Related Parts table.
B
C
D
8/12
9/12
3/13
Add Safety Rated Capacitors section.
Correct Pin Assignment Table.
17
Updated Typical Application schematic.
Added Operating Conditions to Output Ripple graph.
Updated Related Parts table.
1
5
20
3
E
1/14
Revised R
Revised R
value for 5V
value for 5V
and added minimum and maximum limits.
in Table 1a.
ADJ1
ADJ1
OUT
OUT
10
1, 2
F
1/14
7/15
Added SnPb Terminal Finish Option.
G
Added ADJ and Line Regulation discussion.
12
8048fg
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTM8048
TYPICAL APPLICATION
Total Output Current vs VIN
400
380
360
340
320
300
280
260
240
220
200
5V Flyback Converter with Low Noise Bypass
LTM8048
5.7V
V
IN
V
V
V
IN
OUT1
15VDC TO 30VDC
V
OUT2
2.2µF
RUN
OUT2
5V
0.01µF
162k
BIAS
BYP
4.7µF
22µF
10µF
6.19k
ADJ1
SS
ADJ2
–
GND
V
OUT
8048 TA05
725VDC ISOLATION
15
20
25
30
V
(V)
IN
8048 TA05b
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
EN55022 Class B Compliant, 3.6V ≤ V ≤ 36V; 0.8V ≤ V
LTM8031
LTM8032
LTM8033
LTM4612
LTM8061
LTM4613
LTM8047
LTC2978
Ultralow EMI 1A µModule Regulator
Ultralow EMI 2A µModule Regulator
Ultralow EMI 3A µModule Regulator
Ultralow EMI 5A µModule Regulator
Li-Ion/Polymer µModule Battery Charger
Ultralow EMI 8A µModule Regulator
725VDC Isolated µModule Converter
≤ 10V
≤ 10V
≤ 24V
IN
OUT
OUT
OUT
EN55022 Class B Compliant, 3.6V ≤ V ≤ 36V; 0.8V ≤ V
IN
EN55022 Class B Compliant, 3.6V ≤ V ≤ 36V; 0.8V ≤ V
IN
EN55022 Class B Compliant, 5V ≤ V ≤ 36V; 3.3V ≤ V
≤ 15V
OUT
IN
4.95V ≤ V ≤ 32V, 2A Charge Current, 1-Cell and 2-Cell, 4.1V or 4.2V per Cell
IN
EN55022 Class B Compliant, 5V ≤ V ≤ 36V; 3.3V ≤ V
≤ 15V
OUT
IN
3.1V ≤ V ≤ 32V; 2.5V ≤ V
≤ 12V
OUT
IN
2
Octal Digital Power Supply Manager with EEPROM I C/PMBus Interface, Configuration EEPROM, Fault Logging, 16-Bit ADC with
0.25% TUE, 3.3V to 15V Operation
2
LTC2974
Quad Digital Power Supply Manager with EEPROM I C/PMBus Interface, Configuration EEPROM, Fault Logging, Per Channel Voltage,
Current and Temperature Measurements
8048fg
LT 0715 REV G • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM8048
●
●
ꢀLINEAR TECHNOLOGY CORPORATION 2011
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