LTM8062EVPBF_技术文档

LTM8062

32V , 2A µModule Power

IN

Tracking Battery Charger

FEATURES

DESCRIPTION

The LTM^®8062 is a complete 32V , 2A μModule^®power

n

Complete Battery Charger System

Input Supply Voltage Regulation Loop for Peak

IN

n

tracking battery charger. The LTM8062 provides a con-

stant-current/constant-voltagechargecharacteristic,a2A

maximumchargecurrent,andemploysa3.3Vfloatvoltage

feedbackreference, soanydesiredbatteryfloatvoltageup

to 14.4V can be programmed with a resistor divider.

Power Tracking in MPPT (Maximum Peak Power

Tracking) Solar Applications

n

Wide Input Voltage Range: 4.95V to 32V

(40V Abs Max)

2A Charge Current

Resistor Programmable Float Voltage Up to 14.4V

Accommodates Li-Ion/Polymer, LiFePO , SLA

Integrated Input Reverse Voltage Protection

User Selectable Termination: C/10 or Termination

Timer

0.75% Float Voltage Reference Accuracy

9mm × 15mm × 4.32mm LGA Package

n

The LTM8062 employs an input voltage regulation loop,

whichreduceschargecurrentiftheinputvoltagefallsbelow

a programmed level, set with a resistor divider. When the

LTM8062ispoweredbyasolarpanel, thisinputregulation

loop is used to maintain the panel at peak output power.

TheLTM8062alsofeaturespreconditioningtricklecharge,

bad battery detection, a choice of termination schemes

and automatic restart.

n

4

n

The LTM8062 is packaged in a thermally enhanced, com-

pact (9mm × 15mm × 4.32mm) over-molded land grid

array (LGA) package suitable for automated assembly

by standard surface mount equipment. The LTM8062 is

RoHS compliant.

APPLICATIONS

n

Industrial Handheld Instruments

n

12V to 24V Automotive and Heavy Equipment

n

Desktop Cradle Chargers

L, LT, LTC, LTM, Linear Technology, the Linear logo and μModule are registered trademarks of

n

Solar Power Battery Charging

Linear Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

2A LiFePO₄μModule Battery Charger

Charge Current vs Battery Voltage

2500

LTM8062

V

IN

V

BAT

BIAS

INA

NORMAL CHARGING

2000

6V TO 32V

IN

CHRG

FAULT

ADJ

INREG

274k

1500

1000

1-CELL

RUN

TMR

NTC

LiFePO

(3.6V)

4

4.7μF

2.87M

GND

500

PRECONDITION

8062 TA01a

TERMINATION

0

1

3

4

2

BATTERY VOLTAGE (V)

8062 TA01b

8062f

1

LTM8062

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

V

, V ...................................................................40V

INA IN

BIAS ADJ FAULT CHRG GND

, RUN, CHRG, FAULT ......................V + 0.5, 40V

INREG

IN

7

6

5

4

3

2

1

V

BAT

BANK 2

NTC TMR RUN

INREG

TMR, NTC ................................................................2.5V

BAT ...........................................................................15V

BIAS..........................................................................10V

ADJ.............................................................................5V

Maximum Internal Operating Temperature

(Note 2)................................................................. 125°C

Maximum Body Solder Temperature..................... 245°C

V

BANK 3

BANK 4

INA

BANK 1

GND

V

IN

A

B

C

D

E

F

G

H

J

K

L

LGA PACKAGE

77-LEAD (15mm s 9mm s 4.32mm)

T

= 125°C, θ = 17.0°C/W, θ = 6.1°C/W,

JMAX

θ

JA

JCbottom

= 16.2°C/W, θ = 11.2°C/W, WEIGHT = 1.7g

JCtop

JB

θ VALUES DETERMINED PER JEDEC 51-9, 51-12

ORDER INFORMATION

LEAD FREE FINISH

LTM8062EV#PBF

LTM8062IV#PBF

TRAY

PART MARKING*

LTM8062V

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTM8062EV#PBF

LTM8062IV#PBF

77-Lead (15mm × 9mm × 4.32mm) LGA

LTM8062V

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

8062f

2

LTM8062

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full internal

operating temperature range, otherwise specifications are at T_A= 25°C. RUN = 2V.

PARAMETER CONDITIONS

MIN

TYP

MAX

UNITS

V

Maximum Operating Voltage

Start Voltage

32

V

IN

INA

l

7.5

32

OVLO Threshold

OVLO Hysteresis

UVLO Threshold

UVLO Hysteresis

V

Rising

35

1

40

IN

4.6

0.3

0.55

to V Diode Forward Voltage Drop

Current = 2A

= 2A

IN

INA

BAT

Maximum BAT Float Voltage

Input Supply Current

I

14.7

2.1

Standby Mode

RUN = 0, V Reg Open

85

18

μA

IN

Maximum BAT Charging Current

ADJ Float Reference Voltage

(Note 3)

(Note 4)

1.8

A

3.275

3.25

3.3

3.325

3.34

V

l

ADJ Recharge Threshold Voltage

ADJ Precondition Threshold Voltage

ADJ Precondition Threshold Hysteresis Voltage

ADJ Input Bias Current

Threshold Relative to ADJ Float Reference (Note 3)

ADJ Rising (Note 4)

82.5

2.3

95

mV

V

Relative to ADJ Precondition Threshold (Note 4)

mV

Charging Terminated

CV Operation (Note 5)

65

110

nA

l

V

Reference Voltage

Bias Current

ADJ = 3V, I = 1A

2.61

2.7

35

2.83

100

V

nA

V

INREG

BAT

V

= V

Reference

INREG

NTC Range Limit (High) Voltage

NTC Range Limit (Low) Voltage

NTC Disable Impedance

Rising

Falling

1.25

0.27

250

45

1.36

0.29

500

1.45

0.315

NTC

V

kΩ

μA

%

NTC Bias Current

V

= 0.8V

53

NTC

NTC Threshold Hysteresis

RUN Threshold Voltage

For Both High and Low Range Limits

Rising

20

V

1.15

1.20

120

–10

1.25

V

RUN

RUN Hysteresis Voltage

mV

nA

V

RUN Input Bias Current

CHRG, FAULT Output Low Voltage

TMR Charge/Discharge Current

TMR Disable Threshold Voltage

Operating Frequency

10mA Load

0.4

25

0.25

1

μA

V

0.85

1.15

MHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

125°C internal operating temperature range. Note that the maximum

internal temperature is determined by specific operating conditions in

conjunction with board layout, the rated package thermal resistance and

other environmental factors.

Note 2: The LTM8062E is guaranteed to meet performance specifications

from 0°C to 125°C internal. Specifications over the full –40°C to

125°C internal operating temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTM8062I is guaranteed to meet specifications over the full –40°C to

Note 3: The maximum BAT charging current is reduced by thermal

foldback. See the Typical Performance Characteristics for details.

Note 4: ADJ voltages measured through 250k equivalent series resistance.

Note 5: Output battery float voltage programming resistor divider

equivalent resistance = 250k compensates for input bias current.

8062f

3

LTM8062

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs I_BAT, 4.2V Float

Efficiency vs I_BAT, 7.2V Float

Efficiency vs I_BAT, 8.4V Float

84

82

80

78

76

74

72

70

87

86

85

84

83

82

81

80

88

87

86

85

84

83

82

81

V

= 12V

INA

V

= 12V

INA

V

= 24V

INA

V

= 24V

INA

V

= 24V

INA

V

= 12V

INA

0

500

1500

2000

0

500

1500

2000

1000

(mA)

1000

I (mA)

BAT

0

500

1500

2000

2500

1000

I

(mA)

BAT

8062 G01

8062 G02

8062 G03

Efficiency vs I_BAT, 14.4V Float

ADJ Float Voltage vs Temperature

I_BIASvs I_BAT, 4.2V Float

25

20

15

10

5

3.280

3.275

3.270

3.265

90

89

88

87

86

85

84

83

82

V

= 24V

INA

V

= 12V

INA

V

= 24V

INA

0

500

1500

2000

1000

(mA)

–50 –25

25

50

75 100 125

0

500

1500

2000

1000

(mA)

I

TEMPERATURE (°C)

I

BAT

8062 G06

8062 G05

8062 G04

I_BIASvs I_BAT, 7.2V Float

I_BIASvs I_BAT, 8.4V Float

I_BIASvs I_BAT, 14.4V Float

50

45

40

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

V

= 12V

INA

V

= 24V

INA

V

= 12V

INA

V

= 24V

1500

INA

V

= 24V

INA

0

500

1500

2000

1000

(mA)

0

500

2000

1000

(mA)

0

500

1500

2000

1000

(mA)

I

BAT

8062 G08

8062 G07

8062 G09

8062f

4

LTM8062

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Input Current vs I_BAT, 4.2V Float

Input Current vs I_BAT, 7.2V Float

Input Current vs I_BAT, 8.4V Float

900

800

700

600

500

400

300

200

100

0

1400

1200

1000

800

600

400

200

0

1600

1400

1200

1000

800

600

400

200

0

V

= 12V

INA

V

= 12V

INA

V

= 12V

INA

V

= 24V

INA

V

= 24V

INA

V

= 24V

INA

0

500

1500

2000

0

500

1500

2000

0

500

1500

(mA)

2000

2500

1000

(mA)

1000

(mA)

1000

I

BAT

I

BAT

8062 G10

8062 G11

8062 G12

Maximum I_BATvs ADJ

Input Current vs I_BAT, 14.4V Float

I_Qvs V_INA, RUN = 0V, V_INREGOpen

2500

2000

1500

1000

500

1400

1200

1000

800

600

400

200

0

250

200

150

100

50

V

= 24V

INA

0

0.5

1

1.5

ADJ VOLTAGE (V)

3

3.5

0

500

1500

2000

0

10

30

40

2

2.5

1000

(mA)

20

(V)

I

V

BAT

INA

8062 G15

8062 G13

8062 G14

Maximum Charge Current

vs Temperature

Temperature Rise vs I_BAT

,

Maximum I_BATvs V_INREG

4.2V Float Voltage

2000

1600

1200

800

400

0

25

20

15

10

5

2500

2000

1500

1000

500

V

INA

= 24V

V

INA

= 12V

0

–40 –20

0

40

80 100 120

0

500

1500

2000

20

60

1000

(mA)

2

3

3.5

2.5

TEMPERATURE (°C)

I

V

(V)

BAT

INREG

8062 G17

8062 G18

8062 G16

8062f

5

LTM8062

T_A= 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS

Temperature Rise vs I_BAT

,

Temperature Rise vs I_BAT

,

7.2V Float Voltage

8.4V Float Voltage

30

25

20

15

10

5

30

25

20

15

10

5

V

= 12V

INA

V

= 24V

V

INA

= 24V

= 12V

1500

INA

0

500

1500

2000

0

500

2000

1000

(mA)

1000

(mA)

I

BAT

8062 G20

8062 G19

Temperature Rise vs I_BAT

,

V_INStandby Mode Current

vs Temperature

14.4V Float Voltage

40

35

30

25

20

15

10

5

6

5

4

3

2

1

0

V

= 24V

V

= 12V

INA

V

= 24V

INA

0

500

1500

2000

1000

(mA)

–50

0

100

50

I

TEMPERATURE (°C)

BAT

8062 G21

8062 G22

PIN FUNCTIONS

GND (Bank 1, Pin L7): Power and Signal Ground Return.

V

(Bank 4): Charger Input Supply. Decouple with at least

IN

4.7μFtoGND.Connecttheinputpowerhereifnoinputreverse

voltage protection is needed.

BAT(Bank2):BatteryChargeCurrentOutputBus. Thecharge

function operates to achieve the final float voltage at this pin.

The auto-restart feature initiates a new charging cycle when

the voltage at the ADJ pin falls 2.5% below the float voltage.

Once the charge cycle is terminated, the input bias current of

the BAT pin is reduced to minimize battery discharge while

the charger remains connected.

BIAS(PinG7):TheBIASpinconnectstotheinternalpowerbus.

In most cases connect to V . If this is not desirable, connect

BAT

to a power source greater than 2.8V and less than 10V.

CHRG (Pin K7): Open-Collector Charger Status Output; typi-

cally pulled up through a resistor to a reference voltage. This

V

(Bank 3): Anode of input reverse protection Schottky

status pin can be pulled up to voltages as high as V and can

INA

IN

diode. Connect the input power here if input reverse voltage

protection is desired.

sink currents up to 10mA. During a battery charging cycle,

CHRGispulledlow.WhenthechargecurrentfallsbelowC/10,

8062f

6

LTM8062

PIN FUNCTIONS

the CHRG pin becomes high impedance. If the internal timer

is used for termination, the pin stays low during the charg-

ing cycle until the charge current drops below a C/10 rate,

approximately 200mA, even though the charger will continue

to top off the battery until the end-of-charge timer terminates

the charge cycle. A temperature fault also causes this pin to

be pulled low (see the Applications Information section).

pin can be pulled up to voltages as high as V and can sink

IN

currents up to 10mA. This pin indicates charge cycle fault

conditions during a battery charging cycle. A temperature

fault causes this pin to be pulled low. If the internal timer is

used for termination, a bad battery fault also causes this pin

to be pulled low. If no fault conditions exist, the FAULT pin

remains high impedance (see the Applications Information

section).

NTC (Pin H6): Battery Temperature Monitor Pin. This pin

is the input to the NTC (negative temperature coefficient)

thermistor temperature monitoring circuit. This function is

enabled by connecting a 10kꢀ, B = 3380 NTC thermistor

from the NTC pin to ground. The pin sources 50ꢁA, and

monitors the voltage across the 10kꢀ thermistor. When the

voltage on this pin is above 1.36V (T < 0°C) or below 0.29V

(T > 40°C), charging is disabled and the CHRG and FAULT

pins are both pulled low. If the internal timer termination is

being used, the timer is paused, suspending the charging

cycle. Charging resumes when the voltage on NTC returns to

withinthe0.29Vto1.36Vactiveregion.Thereisapproximately

5°C of temperature hysteresis associated with each of the

temperature thresholds. The temperature monitoring func-

tion remains enabled while thermistor resistance to ground

is less than 250kꢀ. If this function is not desired, leave the

NTC pin unconnected.

TMR(PinJ6):End-Of-CycleTimerProgrammingPin.Ifatimer-

basedchargeterminationisdesired,connectacapacitorfrom

this pin to ground. Full charge end-of cycle time (in hours) is

programmed with this capacitor following the equation:

6

t

= C

• 4.4 • 10

TIMER

EOC

A bad battery fault is generated if the battery does not reach

the precondition threshold voltage within one-eighth of t

or:

,

EOC

5

t

= C

• 5.5 • 10

TIMER

PRE

A0.68ꢁFcapacitorisoftenused,whichgeneratesatimerEOC

at three hours, and a precondition limit time of 22.5 minutes.

If a timer-based termination is not desired, the timer function

canbedisabledbyconnectingtheTMRpintoground.Withthe

timerfunctiondisabled,chargingterminateswhenthecharge

current drops below a C/10 rate, approximately 200mA.

ADJ(PinH7):BatteryFloatVoltageFeedbackInput.Thecharge

V

(Pin L6): Input Voltage Regulation Reference. The

INREG

functionoperatestoachieveafinalfloatvoltageof3.3Vonthis

maximum charge current is reduced when this pin is below

pin.Theoutputbatteryfloatvoltage(V

)isprogrammed

BAT(FLT)

2.7V. Connecting a resistor divider from V to this sets the

IN

using a resistor divider. V

can be programmed up to

BAT(FLT)

minimum operational V voltage. This is typically used to

IN

14.4V. The auto-restart feature initiates a new charging cycle

when the voltage at the ADJ pin falls 2.5% below the float

voltage reference. The ADJ pin input bias current is 110nA.

Using a resistor divider with an equivalent input resistance

at the ADJ pin of 250k compensates for input bias current

programthepeakpowervoltageforasolarpanel.TheLTM8062

servos the maximum charge current required to maintain the

programmedoperationalV voltage,throughmaintainingthe

IN

voltage on V

at or above 2.7V. If the voltage regulation

INREG

feature is not used, connect the pin to V .

IN

error. Required resistor values to program desired V

follow the equations:

BAT(FLT)

RUN (Pin K6): Precision Threshold Enable Input Pin. The

RUN threshold is 1.25V (rising), with 120mV of input hys-

teresis. When in shutdown mode, all charging functions are

disabled. The precision threshold allows use of the RUN pin

to incorporate UVLO functions. If the RUN pin is pulled below

0.4V, the IC enters a low current shutdown mode where the

V

_BAT(FLT)•2.5•10⁵

R1=

R2 =

(Ω)

3.3

R1•2.5•10⁵

R1−(2.5•10⁵)

(Ω)

V

pin current is reduced to 15ꢁA. Typical RUN pin input

IN

R1 is connected from BAT to ADJ, and R2 is connected from

ADJ to ground.

bias current is 10nA. If the shutdown function is not desired,

connect the pin to the V pin.

IN

FAULT (Pin J7): Open-Collector Fault Status Output; typically

pulledupthrougharesistortoareferencevoltage.Thisstatus

8062f

7

LTM8062

BLOCK DIAGRAM

V

IN

INA

SENSE

RESISTOR

BAT

8.2μH

0.1μF

10μF

BIAS

V

INREG

INTERNAL

COMPENSATION

ADJ

RUN

ADJ

TMR

NTC

CURRENT

MODE

BATTERY

MANAGEMENT

CONTROLLER

GND

FAULT

CHRG

8062 BD

OPERATION

The LTM8062 is a complete monolithic, mid-power, power

trackingbatterycharger,addressinghighinputvoltageap-

plications with solutions that use a minimum of external

components. The product can be programmed for float

voltages between 3.3V and 14.4V with just two external

resistors,operatingundera1MHzfixedfrequency,average

currentmodestep-downarchitecture.A2ApowerSchottky

diode is integrated within the ꢁModule for reverse input

voltageprotection.Awideinputrangeallowstheoperation

to full charge from an input voltage up to 32V. A precision

threshold on the RUN pin allows the implementation of

a UVLO feature by using a simple resistor network. The

chargercanalsobeputintoalowcurrentshutdownmode,

in which the input supply bias is reduced to only 15ꢁA.

is used to maintain the panel at peak output power. The

LTM8062automaticallyentersabatterypreconditionmode

if the sensed battery voltage is very low. In this mode,

the charge current is reduced to 300mA. Once the bat-

tery voltage climbs above the internally set precondition

threshold (2.3V at the ADJ pin), the ꢁModule automati-

cally increases the maximum charge current to the full

programmed value.

TheLTM8062canuseachargecurrentbasedC/10termina-

tion scheme, which ends a charge cycle when the battery

charge current falls to one-tenth the programmed charge

current.TheLTM8062alsocontainsaninternalchargecycle

controltimer, fortimer-basedtermination. Whenusingthe

internal timer, the charge cycle can continue beyond the

C/10leveltotop-offthebattery.Thechargecycleterminates

whentheprogrammedtimeelapses, aboutthreehoursfor

a 0.68μF timer capacitor. The CHRG status pin continues

to signal charging at a C/10 or greater rate, regardless of

The LTM8062 employs an input voltage regulation loop,

which reduces charge current if a monitored input volt-

age falls below a programmed level. When the LTM8062

is powered by a solar panel, the input regulation loop

8062f

8

LTM8062

OPERATION

which termination scheme is used. When the timer-based

scheme is used, the LTM8062 also supports bad battery

detection, which triggers a system fault if a battery stays

in precondition mode for more than one-eighth of the total

programmed charge cycle time.

battery is removed and replaced with another battery.

The LTM8062 contains a battery temperature monitoring

circuit. This feature, using a thermistor, monitors battery

temperature and will not allow charging to begin, or will

suspend charging, and signal a fault condition if the bat-

tery temperature is outside a safe charging range. The

LTM8062 contains two digital open-collector outputs,

CHRGandFAULT, whichprovidechargerstatusandsignal

fault conditions. These binary coded pins signal battery

charging,standbyorshutdownmodes,batterytemperature

faults and bad battery faults. For reference, C/10 and TMR

based charging cycles are shown in Figures 1 and 2.

Once charging terminates and the LTM8062 is not actively

charging, the charger automatically enters a low current

standby mode in which supply bias currents are reduced

to 85ꢁA. If the battery voltage drops 2.5% from the full

charge float voltage, the LTM8062 engages an automatic

charge cycle restart. The IC also automatically restarts a

new charge cycle after a bad-battery fault once the failed

FLOAT VOLTAGE

RECHARGE THRESHOLD

BATTERY VOLTAGE

PRECONDITION THRESHOLD

MAXIMUM CHARGE CURRENT

BATTERY CHARGE

CURRENT

PRECONDITION CURRENT

C/10

0 AMPS

1

CHRG

FAULT

0

1

0

1

RUN

0

8062 F01

Figure 1. Typical C/10 Terminated Charge Cycle (TMR Grounded, Time Not to Scale)

FLOAT VOLTAGE

RECHARGE THRESHOLD

BATTERY VOLTAGE

PRECONDITION THRESHOLD

MAXIMUM CHARGE CURRENT

BATTERY CHARGE

CURRENT

PRECONDITION CURRENT

C/10 CURRENT

1

CHRG

FAULT

0

1

0

1

RUN

0

< t /8

EOC

t

EOC

AUTOMATIC

RESTART

8062 F02

Figure 2. Typical EOC (Timer-Based) Terminated Charge Cycle

(Capacitor Connected to TMR, Time Not to Scale)

8062f

9

LTM8062

APPLICATIONS INFORMATION

For most applications, the design process is straight

forward, summarized as follows:

Reverse Protection Diode

The LTM8062 integrates a high voltage power Schottky

diode to provide input reverse voltage protection. The

1. Look at Table 1 and find the row that has the desired

input voltage range and battery float voltage.

anode of this diode is connected to V , and the cathode

INA

is connected to V . There is a small mount of capacitance

IN

2. Apply the recommended C and R

values.

ADJ

IN

at each end; please see the Block Diagram.

3. Connect BIAS as indicated.

Input Supply Voltage Regulation

While these component combinations have been tested

for proper operation, it is incumbent upon the user to

verify proper operation over the intended system’s line,

load and environmental conditions. Bear in mind that the

maximum output current is limited by junction tempera-

ture, therelationshipbetweentheinputandoutputvoltage

magnitude and polarity and other factors. Please refer to

the graphs in the Typical Performance Characteristics

section for guidance.

The LTM8062 contains a voltage monitor pin that enables

programming a minimum operational voltage. Connect-

ing a resistor divider from V to the V

programming of minimum input supply voltage, typically

used to program the peak power voltage for a solar panel.

Maximum charge current is reduced when the V

is below the regulation threshold of 2.7V.

pin enables

IN

INREG

If the V

function is not used, and if the input supply

INREG

cannot provide enough power to satisfy the requirements

of an LTM8062 charger, the input supply voltage will col-

lapse. A minimum operating supply voltage can thus be

programmed by monitoring the supply through a resistor

divider,suchthatthedesiredminimumvoltagecorresponds

Table 1. Recommended Component Values and Configuration

(T_A= 25°C)

R

ADJ2

BOTTOM

(kΩ)

ADJ1

TOP

V

RANGE (V)*

6 to 32

V

(V)

C

IN

(kΩ)

IN

BAT

3.6

4.7μF 1206 X7R 50V

274

312

320

357

530

549

626

642

715

942

965

1020

1090

1110

2870

1260

1150

835

464

459

417

412

383

344

340

328

332

328

to 2.7V at the V

pin. The LTM8062 servos the maxi-

INREG

6 to 32

4.1

4.2

mum output charge current to maintain the voltage on

at or above 2.7V.

6 to 32

V

INREG

6.25 to 32

9.5 to 32

4.7

Programming of the desired minimum voltage is ac-

complished by connecting a resistor divider as shown in

7.05

7.2

9.75 to 32

11 to 32

Figure 3. The ratio of R /R for a desired minimum

IN1 IN2

8.2

voltage (V ) is:

IN(MIN)

11.5 to 32

12.75 to 32

16.5 to 32

17 to 32

8.4

R

/R = (V

/2.7) – 1

9.4

IN1 IN2

IN(MIN)

12.3

12.6

13.5

If the voltage regulation feature is not used, connect the

V

INREG

pin to V .

IN

18.25 to 32

19 to 32

LTM8062

14.08

14.42

INPUT SUPPLY

V

IN

R

19.5 to 32

IN1

IN2

* Input bulk capacitance is required.

INREG

8062 F03

V Input Supply

IN

TheLTM8062isbiaseddirectlyfromthechargerinputsup-

Figure 3. Resistive Divider Sets Minimum V_IN

ply through the V pin. This pin provides large switched

IN

currents,soahighqualitylowESRdecouplingcapacitoris

BIAS Pin Considerations

recommended to minimize voltage glitches on V . 4.7ꢁF

IN

The BIAS pin is used to provide drive power for the in-

ternal power switching stage and operate other internal

8062f

is typically adequate for most charger applications.

10

LTM8062

APPLICATIONS INFORMATION

circuitry. For proper operation, it must be powered by at

least 2.8V and no more than the absolute maximum rat-

ing of 10V. In most applications, connect BIAS to BAT. If

there is no BIAS supply available or the battery voltage is

below 2.8V, the internal switch requires more headroom

MPPT Temperature Compensation

Atypicalsolarpaneliscomprisedofanumberofseries-con-

nectedcells,eachcellbeingaforward-biasedp-njunction.

As such, the open-circuit voltage (V ) of a solar cell has

OC

a temperature coefficient that is similar to a common p-n

from V for proper operation. Please refer to the Typical

IN

diode, or about –2mV/°C. The peak power point voltage

PerformanceCharacteristicscurvesforminimumstartand

running requirements under various battery conditions.

Whencharginga2-cellbatteryusingarelativelyhighinput

voltage,theLTM8062powerdissipationcanbereducedby

connecting BIAS to a voltage between 2.8V and 3.3V.

(V ) for a crystalline solar panel can be approximated as

MP

a fixed voltage below V , so the temperature coefficient

OC

for the peak power point is similar to that of V .

OC

Panel manufacturers typically specify the 25°C values for

V , V , and the temperature coefficient for V , making

OC MP

OC

Output Capacitance

determination of the temperature coefficient for V of

MP

a typical panel straight forward. The LTM8062 employs

In many applications, the internal BAT capacitance of the

LTM8062issufficientforproperoperation.Therearecases,

however, where it may be necessary to add capacitance or

otherwise modify the output impedance of the LTM8062.

Case 1: the μModule is physically located far from the

battery and the added line impedance may interfere with

the control loop. Case 2: the battery ESR is very small or

very large; the LTM8062 controller is designed for a wide

range, but some battery packs have an ESR outside of this

range. Case 3: there is no battery at all. As the charger is

designed to work with the ESR of the battery, the output

may oscillate if no battery is present.

a feedback network to program the V input regulation

IN

voltage. Manipulation of the network makes for efficient

implementation of various temperature compensation

schemes for a maximum peak power tracking (MPPT)

application. As the temperature characteristic for a typical

solar panel V voltage is highly linear, a simple solution

MP

fortrackingthatcharacteristiccanbeimplementedusinga

Linear Technology LM234 3-terminal temperature sensor.

This creates an easily programmable, linear temperature

dependent characteristic.

In the circuit shown in Figure 4,

The optimum ESR is about 100mΩ, but ESR values both

higher and lower will work. Table 2 shows a sample of

parts successfully tested by Linear Technology:

R_IN1= –R_SET•(TC • 4405), and

R_IN1

R_IN2

=

V_MP(25°C)+R_IN1•(0.0674 /R_SET

)

Table 2

V_INREG−1

PART NUMBER

DESCRIPTION

MANUFACTURER

Sanyo

16TQC22M

22μF, 16V, POSCAP

18μF, 35V, OS-CON

22μF, 25V Tantalum

22μF, 25V, Tantalum

68μF, 6V, Tantalum

47μF, 6V, Tantalum

68μF, 10V Aluminum

68μF, 25V Aluminum

where TC = temperature coefficient (in V/°C), and

(25°C) = maximum power voltage at 25°C.

35SVPD18M

Sanyo

V

MP

TPSD226M025R0100

T495D226K025AS

TPSC686M006R0150

TPSB476M006R0250

APXE100ARA680ME61G

APS-150ELL680MHB5S

AVX

V

IN

Kemet

LINEAR

TECHNOLOGY

LM234

AVX

+

–

V

R

AVX

R

IN1

V

IN

V

R

SET

Nippon Chemicon

V

INREG

IN2

LTM8062

If system constraints preclude the use of electrolytic ca-

pacitors, aseriesR-Cnetworkmaybeused. Useaceramic

capacitor of at least 22μF and an equivalent resistance of

100mΩ. An example of this is shown in the Typical Ap-

plications section.

8062 F04

Figure 4. MPPT Temperature Compensation Network

8062f

11

LTM8062

APPLICATIONS INFORMATION

For example, given a common 36-cell solar panel that has

the following specified characteristics:

In a manner similar to the MPPT temperature correction

outlinedpreviously,implementationoflinearbatterycharge

voltagetemperaturecompensationcanbeaccomplishedby

incorporating a Linear Technology LM234 into the output

feedback network. For example, a 6-cell lead acid battery

has a float charge voltage that is commonly specified at

2.25V/cell at 25°C, or 13.5V, and a –3.3mV/°C per cell

temperaturecoefficient,or–19.8mV/°C.Usingthefeedback

network shown in Figure 5, with the desired temperature

Open Circuit Voltage (V ) = 21.7V

OC

Maximum Power Voltage (V ) = 17.6V

MP

Open-Circuit Voltage Temperature Coefficient (V )

= –78mV/°C

OC

As the temperature coefficient for V is similar to that

MP

of V , the specified temperature coefficient for V

OC

coefficient (TC) and 25°C float voltage (V

(25°C))

FLOAT

(TC) of –78mV/°C and the specified peak power voltage

specified, and using a convenient value of 2.4k for R

necessary resistor values follow the relations:

,

SET

(V (25°C)) of 17.6V can be inserted into the equations

MP

to calculate the appropriate resistor values for the tem-

R

= –R • (TC • 4405)

perature compensation network in Figure 4. With R

FB1

SET

= –2.4k • (–0.0198 • 4405) = 210k

equal to 1k, then:

R_SET=1k

R_FB1

R_FB2

=

R_IN1= −1k • (−0.078 • 4405)= 344k

V

_FLOAT(25°C)+R_FB1•(0.0674 /R_SET)

−1

V

FB

344k

R_IN2

=

= 24.4k

17.6+ 344k •(0.0674 / 1k)

210k

−1

=

13.5+ 210k •(0.0674 / 2.4k)

2.7

−1

3.3

Battery Voltage Temperature Compensation

= 43k

Some battery chemistries have charge voltage require-

ments that vary with temperature. Lead-acid batteries in

particular experience a significant change in charge volt-

age requirements as temperature changes. For example,

manufacturers of large lead-acid batteries recommend a

floatchargeof2.25V/cellat25°C.Thisbatteryfloatvoltage,

however, has a temperature coefficient which is typically

specified at –3.3mV/°C per cell.

R

= 250k – R ||R

= 250k – 210k||43k = 215k

(see the Battery Float Voltage Programming section)

FB3

FB1 FB2

While the circuit in Figure 5 creates a linear tempera-

ture characteristic that follows a typical –3.3mV/°C per

cell lead-acid specification, the theoretical float charge

14.3

14.2

14.0

BAT

–19.8mV/°C

13.8

+

V

LINEAR

R

FB1

TECHNOLOGY

LM234

6-CELL

LEAD-ACID

BATTERY

LTM8062

R

13.6

210k

–

R

SET

V

R

FB3

2.4k

13.4

13.2

13.0

12.8

12.6

215k

ADJ

R

FB2

43k

8062 F05a

–10

0

10

20

30

40

50

60

TEMPERATURE (°C)

8062 F05b

Figure 5. Lead-Acid 6-Cell Float Charge Voltage vs Temperature with a –19.8mV/°C

Temperature Coefficient Using LM234 with the Feedback Network

8062f

12

LTM8062

APPLICATIONS INFORMATION

14.8

14.6

14.4

14.2

BAT

+

6-CELL

LEAD-ACID

BATTERY

196k

69k

14.0

13.8

13.6

13.4

13.2

THEORETICAL V

BAT(FLOAT)

FLOAT

LTM8062

22k

B = 3380

198k

ADJ

PROGRAMMED V

69k

8062 F06a

13.0

12.8

–10

0

10

20

30

40

50

60

TEMPERATURE (°C)

8062 F06b

Figure 6. Thermistor-Based Temperature Compensation Network Programs V_FLOAT

to Closely Match Ideal Lead-Acid Float Charge Voltage for 6-Cell Charger

voltage characteristic is slightly nonlinear. This nonlinear

characteristic follows the relation:

results in pulsing at the CHRG output. An LED connected

to this pin will exhibit a blinking pattern, indicating to the

user that a battery is not present. The frequency of this

blinking pattern is dependent on the output capacitance.

–5

2

–3

V

= 4 • 10 (T ) – 6 • 10 (T) + 2.375

FLOAT

(with a 2.18V minimum)

where T = temperature in °C. A thermistor-based network

can be used to approximate the nonlinear ideal tempera-

ture characteristic across a reasonable operating range,

as shown in Figure 6.

C/10 Charge Termination

The LTM8062 supports a low current based termination

scheme, where a battery charge cycle terminates when

the charge current falls below one-tenth the programmed

chargecurrent,orapproximately200mA.Thistermination

modeisengagedbyshortingtheTMRpintoground.When

C/10 termination is used, an LTM8062 charger sources

battery charge current as long as the average current level

remains above the C/10 threshold. As the full-charge float

voltage is achieved, the charge current falls until the C/10

thresholdisreached, atwhichtimethechargerterminates

and the LTM8062 enters standby mode. The CHRG status

pin follows the charger cycle and is high impedance when

the charger is not actively charging. There is no provision

for bad-battery detection if C/10 termination is used.

Status Pins

The LTM8062 reports charger status through two open-

collector outputs, the CHRG and FAULT pins. These pins

can be pulled up as high as V , and can sink up to 10mA.

IN

The CHRG pin indicates that the charger is delivering

current at greater than a C/10 rate, or one-tenth of the

programmed charge current. The FAULT pin signals bad-

battery and NTC faults. These pins are binary coded, as

shown in Table 3.

Table 3. Status Pin State

CHRG FAULT

STATUS

Timer Charge Termination

High

Low

High

Low

High

Low

Not Charging—Standby or Shutdown Mode

Bad-Battery Fault (Precondition Timeout/EOC Failure)

Normal Charging at C/10 or Greater

NTC Fault (Pause)

TheLTM8062supportsatimer-basedterminationscheme,

where a battery charge cycle terminates after a specific

amount of time elapses. Timer termination is engaged

when a capacitor (C

) is connected from the TMR pin

TIMER

If the battery is removed from an LTM8062 charger that is

configuredforC/10termination,alowamplitudesawtooth

waveform appears at the charger output, due to cycling

between termination and recharge events. This cycling

to ground. The timer cycle time span (t ) is determined

EOC

by C

in the equation:

TIMER

–7

C

= t

• 2.27 • 10 (Hours)

TIMER

EOC

8062f

13

LTM8062

APPLICATIONS INFORMATION

When charging at a 1C rate, t

is commonly set to three

a new timer charge cycle initiates if the BAT pin exceeds

the precondition threshold voltage. During a bad-battery

fault,asmallcurrentissourcedfromthecharger;removing

the failed battery allows the charger output voltage to rise

above the preconditioning threshold voltage and initiate a

charge cycle reset. A new charge cycle is started by con-

necting another battery to the charger output.

EOC

hours, which requires a 0.68ꢁF capacitor.

TheCHRGstatuspincontinuestosignalcharging, regard-

less of which termination scheme is used. When timer

termination is used, the CHRG status pin is pulled low

during a charge cycle until the charge current falls below

the C/10 threshold. The charger continues to top off the

battery until timer EOC, when the LTM8062 terminates the

charge cycle and enters standby mode.

Battery Temperature Fault: NTC

The LTM8062 can accommodate battery temperature

monitoring by using an NTC (negative temperature

coefficient) thermistor close to the battery pack. The

temperature monitoring function is enabled by connect-

ing a 10kꢀ, β ≈ 3380 NTC thermistor from the NTC pin

to ground. If the NTC function is not desired, leave the

pin open. The NTC pin sources 50ꢁA, and monitors the

voltage dropped across the 10kꢀ thermistor. When the

voltage on this pin is above 1.36V (0°C) or below 0.29V

(40°C), the battery temperature is out of range, and the

LTM8062 triggers an NTC fault. The NTC fault condition

remains until the voltage on the NTC pin corresponds to

a temperature within the 0°C to 40°C range. Both hot and

coldthresholdsincorporate20%hysteresis,whichequates

to about 5°C. If higher operational charging temperatures

are desired, the temperature range can be expanded by

adding series resistance to the 10k NTC resistor. Adding

a 909ꢀ resistor will increase the effective temperature

threshold to 45°C, for example.

Termination at the end of the timer cycle only occurs if the

charge cycle was successful. A successful charge cycle

occurs when the battery is charged to within 2.5% of the

full-charge float voltage. If a charge cycle is not success-

ful at EOC, the timer cycle resets and charging continues

for another full timer cycle. When V drops 2.5% from

BAT

the full-charge float voltage, whether by battery loading

or replacement of the battery, the charger automatically

resets and starts charging.

Preconditioning and Bad-Battery Fault

The LTM8062 has a precondition mode, where the charge

currentislimitedto15%ofthemaximumchargecurrent,or

approximately300mA.Preconditionmodeisengagedifthe

voltage on the BAT pin is below the precondition threshold,

or approximately 70% of the float voltage. Once the BAT

voltagerisesabovethepreconditionthreshold, normalfull-

currentchargingcancommence.TheLTM8062incorporates

90mV hysteresis to avoid spurious mode transitions.

During an NTC fault, charging is halted and both status

pins are pulled low. If timer termination is enabled, the

timer count is suspended and held until the fault condi-

tion is cleared.

Bad-battery detection is engaged when the internal timer

is used for termination (capacitor tied to TMR). This fault

detection feature is designed to identify failed cells. A

bad-battery fault is triggered when the voltage on BAT

remains below the precondition threshold for greater than

one-eighth of a full timer cycle (one-eighth EOC). A bad-

batteryfaultisalsotriggeredifanormallychargingbattery

re-enters precondition mode after one-eighth EOC.

Thermal Foldback

TheLTM8062containsathermalfoldbackprotectionfeature

thatreduceschargecurrentastheICjunctiontemperature

approaches 125°C. In most cases, on-chip temperatures

servosuchthatanyovertemperatureconditionsarerelieved

with only slight reductions in maximum charge current.

In some cases, the thermal foldback protection feature

can reduce charge currents below the C/10 threshold.

In applications that use C/10 termination (TMR = 0V), the

LTM8062 will suspend charging and enter standby mode

When a bad-battery fault is triggered, the charge cycle

is suspended, and the CHRG status pin becomes high

impedance. The FAULT pin is pulled low to signal that a

fault has been detected.

Cyclingthecharger’spowerorshutdownfunctioninitiates

a new charge cycle, but the LTM8062 charger does not

requireamanualreset.Onceabad-batteryfaultisdetected,

until the overtemperature condition is relieved.

8062f

14

LTM8062

APPLICATIONS INFORMATION

ADJ

BAT

GND

(OPTIONAL)

V

RUN

INREG

C

BAT

V

INA

C

GND

IN

V

IN

8062 F07

THERMAL VIAS

Figure 7. Suggested Layout and Via Placement

PCB Layout

printed circuit board. Pay attention to the location and

density of the thermal vias in Figure 5. The LTM8062

can benefit from the heat-sinking afforded by vias that

connecttointernalGNDplanesattheselocations,dueto

theirproximitytointernalpowerhandlingcomponents.

The optimum number of thermal vias depends upon

the printed circuit board design. For example, a board

might use very small via holes. It should employ more

thermal vias than a board that uses larger holes.

Most of the headaches associated with PCB layout have

been alleviated or even eliminated by the high level of

LTM8062 integration. The LTM8062 is nevertheless

a switching power supply, and care must be taken to

minimize EMI and ensure proper operation. Even with the

high level of integration, you may fail to achieve specified

operation with a haphazard or poor layout. See Figure 7

for a suggested layout. Ensure that the grounding and

heat sinking are acceptable.

Hot-Plugging Safely

1. Place the C capacitor as close as possible to the V

IN

The small size, robustness and low impedance of ceramic

capacitors make them an attractive option for the input

bypass capacitor of LTM8062. However, these capacitors

can cause problems if the LTM8062 is plugged into a

live input supply (see Application Note 88 for a complete

discussion). The low loss ceramic capacitor combined

with stray inductance in series with the power source

forms an underdamped tank circuit, and the voltage at the

and GND connection of the LTM8062.

2. If used, place the C

capacitor as close as possible

BAT

to the BAT and GND connection of the LTM8062.

3. PlacetheC andC (ifused)capacitorssuchthattheir

IN

BAT

ground current flows directly adjacent or underneath

the LTM8062.

4. Connect all of the GND connections to as large a copper

pour or plane area as possible on the top layer. Avoid

breaking the ground connection between the external

components and the LTM8062.

V

pin of the LTM8062 can ring to more than twice the

IN

nominal input voltage, possibly exceeding the LTM8062’s

rating and damage the part. If the input supply is poorly

controlled or the user will be plugging the LTM8062 into

anenergizedsupply,theinputnetworkshouldbedesigned

to prevent this overshoot. This can be accomplished by

5. Forgoodheatsinking,useviastoconnecttheGNDcop-

per area to the board’s internal ground planes. Liberally

distributetheseGNDviastoprovidebothagoodground

connectionandthermalpathtotheinternalplanesofthe

installing a small resistor in series with V , but the most

IN

popular method of controlling input voltage overshoot is

8062f

15

LTM8062

APPLICATIONS INFORMATION

to add an electrolytic bulk capacitor to the V net. This

of the package, but there is always heat flow out into

the ambient environment. As a result, this thermal re-

sistance value may be useful for comparing packages

but the test conditions don’t generally match the user’s

application.

IN

capacitor’s relatively high equivalent series resistance

damps the circuit and eliminates the voltage overshoot.

The extra capacitor improves low frequency ripple filter-

ing and can slightly improve the efficiency of the circuit,

though it is physically large.

3. θ

is determined with nearly all of the component

JCtop

power dissipation flowing through the top of the pack-

age.AstheelectricalconnectionsofthetypicalμModule

are on the bottom of the package, it is rare for an ap-

plication to operate such that most of the heat flows

from the junction to the top of the part. As in the case

Thermal Considerations

The thermal performance of the LTM8062 is given in the

TypicalPerformanceCharacteristicssection.Thesecurves

were generated by the LTM8062 mounted to a 58cm

4-layer FR4 printed circuit board. Boards of other sizes

and layer count can exhibit different thermal behavior, so

it is incumbent upon the user to verify proper operation

over the intended system’s line, load and environmental

operating conditions.

2

of θ

, this value may be useful for comparing

JCbottom

packages but the test conditions don’t generally match

the user’s application.

4. θ is the junction-to-board thermal resistance where

JB

almost all of the heat flows through the bottom of the

μModule and into the board, and is really the sum of the

Forincreasedaccuracyandfidelitytotheactualapplication,

many designers use FEA to predict thermal performance.

To that end, the Pin Configuration section of the data sheet

typically gives four thermal coefficients:

θ

andthethermalresistanceofthebottomofthe

JCbottom

part through the solder joints and through a portion of

the board. The board temperature is measured a speci-

fied distance from the package, using a two sided, two

layer board. This board is described in JESD 51-9.

1. θ : Thermal resistance from junction to ambient.

JA

2. θ

: Thermal resistance from junction to the bot-

JCbottom

The most appropriate way to use the coefficients is when

running a detailed thermal analysis, such as FEA, which

considers all of the thermal resistances simultaneously.

None of them can be individually used to accurately pre-

dict the thermal performance of the product, so it would

be inappropriate to attempt to use any one coefficient to

correlate to the junction temperature versus load graphs

given in the LTM8033 data sheet.

tom of the product case.

3. θ : Thermal resistance from junction to top of the

JCtop

product case.

4. θ : Thermal resistance from junction to the printed

JB

circuit board.

While the meaning of each of these coefficients may seem

to be intuitive, JEDEC has defined each to avoid confusion

and inconsistency. These definitions are given in JESD

51-12, and are quoted or paraphrased below:

A graphical representation of these thermal resistances

is given in Figure 8.

The blue resistances are contained within the μModule,

and the green are outside.

1. θ is the natural convection junction-to-ambient air

JA

thermal resistance measured in a one cubic foot sealed

enclosure.Thisenvironmentissometimesreferredtoas

“still air” although natural convection causes the air to

move.Thisvalueisdeterminedwiththepartmountedto

a JESD 51-9 defined test board, which does not reflect

an actual application or viable operating condition.

The die temperature of the LTM8062 must be lower than

the maximum rating of 125°C, so care should be taken in

the layout of the circuit to ensure good heat sinking of the

LTM8062. The bulk of the heat flow out of the LTM8062

is through the bottom of the module and the LGA pads

into the printed circuit board. Consequently a poor printed

circuit board design can cause excessive heating, result-

ing in impaired performance or reliability. Please refer to

the PCB Layout section for printed circuit board design

2. θ

is the junction-to-board thermal resistance

JCbottom

with all of the component power dissipation flowing

through the bottom of the package. In the typical

μModule, the bulk of the heat flows out the bottom

suggestions.

8062f

16

LTM8062

APPLICATIONS INFORMATION

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

JUNCTION-TO-CASE (TOP)

RESISTANCE

CASE (TOP)-TO-AMBIENT

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION

AMBIENT

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

80421 F08

μMODULE DEVICE

Figure 8. Thermal Resistances Among μModule Device

Printed Circuit Board and Ambient Environment

TYPICAL APPLICATIONS

Basic 2A, 2-Cell LiFePO₄Battery Charger with C/10 Termination

LTM8062

V

DC

IN

V

BAT

BIAS

INA

9.5V TO 32V

(OPTIONAL

ELECTROLYTIC

CAPACITOR)

IN

+

2-CELL

LiFePO

(2× 3.6V)

BATTERY

CHRG

FAULT

ADJ

INREG

549k

459k

4

RUN

TMR

NTC

4.7μF

GND

8062 TA02

2A Solar Panel Power Manager with 8.4V Lithium Ion Battery Pack and 16V Peak Power Tracking

V

IN

LTM8062

SOLAR

V

BAT

BIAS

INA

POWER UNIT

IN

CHRG

FAULT

ADJ

INREG

2-CELL

499k

100k

642k

412k

Li-ION

RUN

TMR

NTC

+

(OPTIONAL

ELECTROLYTIC

CAPACITOR)

(2× 4.2V)

BATTERY

NTC

10k

B = 3380

4.7μF

GND

8062 TA03

8062f

17

LTM8062

PACKAGE DESCRIPTION

Z

/ / b b b

Z

3 . 8 1 0

2 . 5 4 0

1 . 2 7 0

0 . 0 0 0

1 . 2 7 0

2 . 5 4 0

3 . 8 1 0

1 . 5 8 7 5

0 . 9 5 2 5

3 . 4 9 2 5

4 . 1 2 7 5

8062f

18

LTM8062

PACKAGE DESCRIPTION

Table 3. Pin Assignment Table

(Arranged by Pin Number)

A1

A2

A3

A4

A5

A6

A7

NAME

GND

BAT

B1

B2

B3

B4

B5

B6

B7

NAME

GND

BAT

C1

C2

C3

C4

C5

C6

C7

NAME

GND

BAT

D1

D2

D3

D4

D5

D6

D7

NAME

GND

BAT

E1

E2

E3

E4

E5

E6

E7

NAME

GND

BAT

F1

F2

F3

F4

F5

F6

F7

NAME

GND

BAT

G1

G2

G3

G4

G5

G6

G7

NAME

GND

BIAS

H1

H2

H3

H4

H5

H6

H7

NAME

GND

NTC

J1

J2

J3

J4

J5

J6

J7

NAME

GND

TMR

FAULT

K1

K2

K3

K4

K5

K6

K7

NAME

L1

L2

L3

L4

L5

L6

L7

NAME

V

IN

V

INA

RUN

V

INREG

ADJ

CHRG

GND

PACKAGE PHOTO

8062f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTM8062

TYPICAL APPLICATION

2A Solar Panel Power Manager for Charging 2-Cell 8.4V Lithium-Ion Battery, Featuring Three Hour

Charge Time and 16V Peak Power Tracking. Battery Powers Two μModule Regulators

V

IN

LTM8062

V

SOLAR

V

BAT

BIAS

LTM8023

LTM8021

OUT

INA

POWER UNIT

IN

CHRG

FAULT

ADJ

INREG

499k

100k

642k

412k

2-CELL

Li-Ion

(2s 4.2V)

BATTERY

RUN

TMR

NTC

4.7μF

10k

B = 3380

0.68μF

GND

8062 TA04

RELATED PARTS

PART NUMBER

DESCRIPTION

10A DC/DC μModule Regulator

COMMENTS

LTM4600

Basic 10A DC/DC μModule, 15mm × 15mm × 2.8mm LGA

–55°C to 125°C Operation, 15mm × 15mm × 2.8mm LGA

LTM4600HVMPV Military Plastic 10A DC/DC μModule Regulator

LTM4601/

LTM4601A

12A DC/DC μModule Regulator with PLL, Output

Tracking/Margining and Remote Sensing

Synchronizable, PolyPhase Operation, LTM4601-1 Version has no Remote

Sensing

LTM4602

LTM4603

6A DC/DC μModule Regulator

Pin Compatible with the LTM4600

6A DC/DC μModule Regulator with PLL and Output Synchronizable, PolyPhase Operation, LTM4603-1 Version has no Remote

Tracking/Margining and Remote Sensing

Sensing, Pin Compatible with the LTM4601

LTM4604A

LTM4608A

LTM8020

4A Low V DC/DC μModule Regulator

2.375V ≤ V ≤ 5V, 0.8V ≤ V

≤ 5V, 9mm × 15mm × 2.3mm LGA

IN

OUT

8A Low V DC/DC μModule Regulator

2.375V ≤ V ≤ 5V, 0.8V ≤ V

≤ 5V, 9mm × 15mm × 2.8mm LGA

IN

200mA, 36V DC/DC μModule Regulator

1A, 36V DC/DC μModule Regulator

2A, 36V DC/DC μModule Regulator

EN55022 Class B Compliant, Fixed 450kHz Frequency, 1.25V ≤ V

6.25mm × 6.25mm × 2.32mm LGA

≤ 5V,

OUT

LTM8022

LTM8023

Adjustable Frequency, 0.8V ≤ V

Pin Compatible to the LTM8023

≤ 5V, 9mm × 11.25mm × 2.82mm LGA,

OUT

Adjustable Frequency, 0.8V ≤ V

Pin Compatible to the LTM8022

≤ 5V, 9mm × 11.25mm × 2.82mm LGA,

OUT

LTM8025

LTM8021

3A, 36V DC/DC μModule Regulator

0.8V ≤ V ≤ 24V, 9mm × 15mm × 4.32mm LGA

OUT

500mA, 36V DC/DC μModule Regulator

EN55022 Class B Compliant, Fixed 1.1MHz Frequency, 0.8V ≤ V

6.25mm × 11.25mm × 2.82mm LGA

≤ 5V,

OUT

8062f

LT 0810 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTM8062EVPBF
厂家：	Linear
描述：	32VIN, 2A μModule Power Tracking Battery Charger 32VIN ，2A的μModule功率跟踪电池充电器电池
文件：	总20页 (文件大小：582K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM8062EVPBF [Linear]

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