LTP5902IPC-WHMA#PBF [Linear]
LTP5902-WHM - SmartMesh WirelessHART Mote Module with Antenna Connector; Package: PCA; Pins: 66; Temperature Range: -40°C to 85°C;
| 型号： | LTP5902IPC-WHMA#PBF |
| 厂家： | 
Linear |
| 描述： | LTP5902-WHM - SmartMesh WirelessHART Mote Module with Antenna Connector; Package: PCA; Pins: 66; Temperature Range: -40°C to 85°C |
| 文件： | 总29页 (文件大小：832K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A d v a n c e d I n f o r m a t i o n
S m a r t M e s h® W i r e l e s s H A R T T M
LTP5901/LTP5902-WHM
2.4 GHz 802.15.4 EternaTM Mote Module
About SmartMesh WirelessHART
SmartMesh WirelessHART products are designed for the harshest industrial environments, where low power, reliability, resilience and
scalability are key. SmartMesh WirelessHART solutions are well-suited for applications requiring WirelessHART standards compliance, as
well as a wide range of applications from renewable energy generation, such as solar and wind power, to factory machine health
monitoring and data center HVAC energy management. Smartmesh WirelessHART complies with the WirelessHART (IEC 62591)
standard, offers the lowest power consumption in its class and is the most widely used WirelessHART product available. SmartMesh
WirelessHART systems are easy for industrial automation vendors to integrate and simple for end users to deploy.
Product Descriptions – LTP5901/LTP5902-WHM
The LTP5901/LTP5902-WHM mote module combines Dust Networks’ robust sensor networking solution with Dust’s breakthrough
EternaTM SoC technology in an easy-to-integrate 22-pin module, and may serve as a drop-in replacement for Dust Networks’ M2510 mote
module. As part of the SmartMesh WirelessHART system, the LTP5901/LTP5902-WHM enables customers to integrate a standards-based
wireless network into sensors and actuators to provide scalable bidirectional communications.
The LTP5901/LTP5902-WHM is designed for use in line-powered, battery-powered, or energy-scavenging sensor and actuator
applications that demand reliable performance and ultra-low power operation. With Dust Networks’ innovative IEEE 802.15.4-compliant
design and integrated power amplifier, the LTP5901/LTP5902-WHM enables a decade of battery life on two AA batteries, including
routing motes. All motes function as wireless routers, enabling a redundant, high performance, full-mesh topology.
The LTP5901/LTP5902-WHM Mote modules combine Dust Networks’ robust sensor networking solution with Dust’s breakthrough
EternaTM SoC Technology in an easy-to-integrate surface-mount printed circuit board (PCB). The LTP5901-WHM module includes an on-
board chip antenna, while the LTP5902-WHM module includes an MMCX antenna connector. Both PCB modules will come with modular
certifications for FCC, CE, and IC. To accelerate customer development time and reduce development costs, Dust Networks provides a
fully engineered RF solution, comprehensive APIs, and complete development documentation.
Key Product Features
Highly Scalable
Ultra-low Power Operation
•
•
Automatic network formation—new motes join
•
Industry-leading radio technology capable of line-powered,
automatically from anywhere in the network
All motes are wireless routers, providing a full-mesh
network that easily scales to tens of thousands of motes per
square kilometer
battery-powered, or energy-scavenging operation
Automatic power optimization of every device in network,
enabling a decade of network operation on two Lithium AA
batteries
•
•
Time-synchronized communication across 15 channels
virtually eliminates in-network collisions, allowing for
dense deployments in overlapping radio space
Easy to Integrate and Deploy
•
Fully engineered RF, with power amplifier (PA), balun, and
antenna matching circuitry
Superior Reliability
•
A comprehensive application programming interface (API)
provides a rich and flexible functionality to ease software
development and device integration
•
Intelligent Networking Platform enables greater than
99.99% network reliability even in the most challenging
monitoring and control environments
Secure Global Market Solution
•
Time-synchronized channel hopping seamlessly
compensates for in band blocking and multipath fading in
dynamic RF environments
•
Operates on 2.4 GHz global license-free band, providing
customers with a single product for world-wide use
RF Modular certifications (pending)-FCC, IC, and CE
AES-128 bit encryption
•
•
WirelessHART (IEC62591) compliance
•
Interoperable with WirelessHART devices
Linear Technology / Dust Networks
A d v a n c e d I n f o r m a t i o n
Table of Contents
1.0
1.1
1.2
General ..............................................................................................................4
Related Documentation ..................................................................................... 4
Conventions..................................................................................................... 4
1.2.1 Signal Naming.............................................................................................. 4
1.2.2 Number Format ............................................................................................ 4
2.0
2.1
Introduction.......................................................................................................5
Power Supply................................................................................................... 5
2.1.1 Supply Monitoring and Reset .......................................................................... 6
2.2 Precision Timing............................................................................................... 6
2.2.1 Time Synchronization .................................................................................... 6
2.3
Time References............................................................................................... 6
2.3.1 Relaxation Oscillator...................................................................................... 6
2.3.2 32.768 kHz Crystal ....................................................................................... 6
2.3.3 20 MHz Crystal............................................................................................. 6
2.4
2.5
Radio.............................................................................................................. 6
UARTs............................................................................................................. 7
2.5.2 API UART Protocol......................................................................................... 7
2.5.3 CLI UART..................................................................................................... 8
2.6
2.7
2.8
Autonomous MAC ............................................................................................. 8
Security .......................................................................................................... 8
Temperature Sensor ......................................................................................... 8
2.8.1 Radio Inhibit ................................................................................................ 8
2.8.2 Sleep .......................................................................................................... 9
2.10 Flash Programming........................................................................................... 9
3.0
4.0
4.1
9
Operation...........................................................................................................9
Start Up.......................................................................................................... 9
4.1.1 Fuse Table..................................................................................................10
4.2
4.3
Serial Flash Emulation......................................................................................10
Operation.......................................................................................................10
4.3.1 Active State ................................................................................................10
4.3.2 Doze State..................................................................................................10
4.4
5.0
5.2
5.3
Duty Cycling and Autonomous Peripherals...........................................................11
Pinout ..............................................................................................................12
Eterna Mote Modules........................................................................................12
Power Supply..................................................................................................15
5.3.1 Antenna .....................................................................................................15
5.4
5.5
Analog ...........................................................................................................15
JTAG..............................................................................................................15
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A d v a n c e d I n f o r m a t i o n
6.0
7.0
8.0
Absolute Maximum Ratings..............................................................................16
Recommended Operating Conditions................................................................17
Electrical Characteristics..................................................................................17
8.1
Radio Specifications.........................................................................................17
DC Characteristics ...........................................................................................17
Radio Receive Characteristics ............................................................................18
Radio Transmitter Characteristics.......................................................................19
Digital I/O Characteristics.................................................................................19
Temperature Sensor Characteristics ...................................................................20
ADC Characteristics .........................................................................................20
System Characteristics.....................................................................................20
UART AC Characteristics...................................................................................21
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10 TIMEn AC Characteristics..................................................................................22
8.11 SLEEPn AC Characteristics ................................................................................22
8.12 RADIO_INHIBIT AC Characteristics.....................................................................22
8.13 FLASH AC Characteristics..................................................................................23
8.14 Flash Programming AC Characteristics................................................................23
9.0
Typical Performance Characteristics ................................................................24
10.0 Mechanical Details ...........................................................................................25
10.2 Mote Module...................................................................................................25
10.3 Soldering Information ......................................................................................27
11.0 Regulatory and Standards Compliance.............................................................27
11.1 Compliance to Restriction of Hazardous Substances (RoHS)...................................27
12.0 References .......................................................................................................27
13.0 Order Information............................................................................................27
Eterna Datasheet
Linear Technology / Dust Networks
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A d v a n c e d I n f o r m a t i o n
1.0 General
1.1
Related Documentation
• 040-0102 Eterna Integration Guide
• 040-0109 Design Specific Configuration Guide
• 040-0110 Eterna Serial Programmer Guide
1.2
Conventions
1.2.1
Signal Naming
The naming convention for Eterna signals is UPPER_CASE_SEPARATED_BY_UNDERSCORE. Active-low signals, such
as RESETn, add a trailing lower case n. An exception to the naming convention is UART transmit and receive signals which
are named consistent with industry practice as RX and TX, omitting the lower case n, despite being active low signals. The
terms assertion and active refers to a signal in a logically true state: logic ‘1’ for active high signals and logic ‘0’ for active
low signals. The terms negated and inactive refer to a signal being in its logically false state: logic ‘0’ for active high signals
and logic ‘1’ for active low signals.
1.2.2
Number Format
The 0x prefix indicates a hexadecimal number follows.
The 0b prefix indicates a binary number follows.
The lack of a prefix indicates a decimal number follows.
4
Linear Technology / Dust Networks
Eterna Datasheet
A d v a n c e d I n f o r m a t i o n
2.0 Introduction
Eterna is the world’s most energy-efficient IEEE 802.15.4 compliant platform enabling battery and energy harvested
endpoint, routing and network management solutions. With a powerful 32-bit ARM® Cortex™-M3, best in class radio, flash,
RAM and purpose-built peripherals, Eterna provides a flexible, scalable and robust networking solution for applications
demanding both minimal energy consumption and data reliability in even the most challenging RF environments.
Shown in Figure 1, Eterna integrates purpose-built peripherals that excel in both low operating-energy consumption and the
ability to rapidly and precisely cycle between operating and low-power states. Items in the shaded region correspond to the
analog/RF components.
32 kHz
Timers
Sched.
32 kHz, 20 MHz
Voltage Reference
Core Regulator
Primary
DC/DC
Converter
SRAM
72 KB
Clock Regulator
Analog Regulator
Flash
512 KB
PMU /
Clock
Control
Relaxation
Oscillator
PA
DC/DC
Converter
Flash
Controller
PoR
802.15.4
Mod
AES
LPF
DAC
PA
Code
802.15.4
Framing
DMA
PLL
Auto
MAC
Cortex-M3
System
802.15.4
Demod
ADC
Limiter
AGC
LNA
BPF
PPF
RSSI
IPCS
SPI
Slave
CLI
UART
(2 pin)
API
UART
(6-pin)
ADC
Ctrl.
10-bit
ADC
Bat.
Load
VGA
S
PTAT
4-bit
DAC
Figure 1 Eterna Block Diagram
2.1
Power Supply
Eterna is powered from a single pin, VSUPPLY, which powers the I/O cells and is also used to generate internal supplies.
Eterna’s two on-chip DC/DC converters minimize Eterna’s energy consumption while the device is awake. To prevent power
from being wasted the DC/DC converter is disabled when the device is in low-power state. Eterna’s rejection of supply noise
is substantial owing to the two integrated DC/DC converters and three integrated low-dropout regulators. Eterna’s operating
supply range is high enough to support direct connection to Li-SClO2 sources and wide enough to support battery operation
over a broad temperature range.
Eterna Datasheet
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A d v a n c e d I n f o r m a t i o n
2.1.1
Supply Monitoring and Reset
Eterna integrates an Power on Reset (PoR) circuit and as the RESETn input pin is nominally configured with an internal pull-
up resistor, thus no connection is required. For a graceful shutdown, the software and networking layers be cleanly halted
prior to assertion of the RESETn pin. Eterna includes a soft brown-out monitor that fully protects the Flash from corruption
in the event that power is removed while writing to flash. Integrated flash supervisory functionality in conjunction with ***
(do we do a JFS?) yields a robust non-volatile file system.
2.2
Precision Timing
Eterna, differs from competing 802.15.4 product offerings by providing low-power dedicated timing hardware and timing
algorithms that provide timing precision two to three orders of magnitude better than any other available low-power solution.
Improved timing accuracy allows motes to minimize the amount of radio listening time required to ensure packet reception
thereby lowering even further the power consumed by an Eterna network. Eterna’s patented timing hardware and timing
algorithms provide superior performance over rapid temperature changes, further differentiating Eterna’s reliability when
compared with other wireless products. In addition, precise timing enables networks to reduce spectral dead time, increasing
total network throughput.
2.2.1
Time Synchronization
In addition to coordinating timeslots across the network, which is transparent to the user, Eterna’s unparalleled timing
management is used to support two mechanisms to share network time. Having an accurate, shared, network-wide time base
enables events to be accurately time stamped or tasks to be performed in a synchronized fashion across a network. Eterna
will send a time packet through its serial interface when one of the following occurs:
•
•
Eterna receives an HDLC request to read time
The TIMEn signal is asserted
The use of TIMEn has the advantage of being more accurate. The value of the timestamp is captured in hardware relative to
the rising edge of TIMEn. If the HDLC request is used, due to packet processing the value of the timestamp may be captured
several milliseconds after receipt of the packet. See Section 8.10 for the time functions definition and specifications.
2.3
Time References
Eterna includes three clock sources: a low power oscillator designed for a 32.768 kHz crystal, the radio reference oscillator
designed for a 20 MHz crystal, and an internal relaxation oscillator.
2.3.1
Relaxation Oscillator
The relaxation oscillator is the primary clock source for Eterna, providing the clock for the CPU, memory subsystems, and all
peripherals. The internal relaxation oscillator typically starts up in a few μs, providing an expedient, low-energy method for
duty cycling between active and low power states. Quick start-up from the doze state, defined in section 4.0, allows Eterna to
wake up and receive data over the UART and SPI interfaces by simply by detecting activity the appropriate signals.
2.3.2
32.768 kHz Crystal
Once Eterna is powered up and the 32.768 kHz crystal source has begun oscillating, the 32.768 kHz crystal remains
operational while in the Active state, and is used as the timing basis when in Doze state. See Section 4.0 for a description of
Eterna’s operational states.
2.3.3
20 MHz Crystal
The 20 MHz crystal source provides a frequency reference for the radio, and is automatically enabled and disabled by Eterna
as needed.
2.4
Radio
Eterna is the lowest-power commercially available 2.4 GHz IEEE 802.15.4e radio by a substantial margin. (Please refer to
section 8.2 for power consumption numbers.). Eterna’s integrated power amplifier is calibrated and temperature-compensated
to consistently provide power at a limit suitable for worldwide radio certifications. Additionally, Eterna uniquely includes a
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A d v a n c e d I n f o r m a t i o n
hardware-based autonomous MAC that handles precise sequencing of peripherals, including the transmitter, the receiver, and
AES peripherals. The hardware-based autonomous MAC minimizes CPU activity, thereby further decreasing power
consumption.
2.5
UARTs
The principal network interface is through the application programming interface (API) UART. A command-line interface
(CLI) is also provided for support of test and debug functions. Both UARTs sense activity continuously, consuming virtually
no power until data is transferred over the port and then automatically returning to their lowest power state after the
conclusion of a transfer.
2.5.2
API UART Protocol
Eterna’s API UART operates in Mode 4, incorporating optional flow control, at 115200 baud. Packets are HDLC encoded
with one stop bit and no parity bits. The flow control signals for Eterna’s API receive path are shown in Figure 5. If the flow
control signals are used (recommended) transfers are initiated from a companion processor by asserting UART_RX_RTSn.
Eterna responds by asserting UART_RX_CTSn. If flow control is used, after detecting the assertion of UART_RX_CTSn the
companion processor may send the entire packet. Following the transmission of the final byte in the packet the companion
processor negates UART_RX_RTSn and waits until the negation of UART_RX_CTSn before asserting UART_RX_RTSn
again. Flow control automatically ensures compliance with inter-packet delay requirements, so explicit delay-checking is not
required.
If flow control is not desired or needed it may be disabled by tying UART_RX_RTSn high. When flow control is not used
the companion processor may send the entire packet; in this case the companion processor must comply with the minimum
inter-packet delay as defined in section 8.9.
Figure 5 UART Mode 4 Receive Flow Control
UART Mode 4 also incorporates level-sensitive flow control for Eterna UART transmissions on the UART TX pin. Packets
are HDLC encoded with one stop bit and no parity bits. The flow control signals for TX are shown in Figure 6. A transfer
request is signaled by Eterna device asserting UART_TX_RTSn. The UART_TX_CTSn signal may be actively driven by the
companion processor when it is ready to receive a packet or it may be tied low if the companion processor will always be
ready to receive a packet. After detecting a logic ‘0’ on UART_TX_CTSn Eterna sends the entire packet. Following the
transmission of the final byte in the packet Eterna negates UART_TX_RTSn and waits for a minimum period (what is the
period called?) defined in section 8.9 before asserting UART_TX_RTSn again (if a packet needs to be transmitted)
Eterna Datasheet
Linear Technology / Dust Networks
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A d v a n c e d I n f o r m a t i o n
Figure 6 UART Mode 4 Transmit Flow Control
For details on the timing of the UART protocol, see section 8.9 (UART AC Characteristics).
2.5.3
CLI UART
The Command Line Interface (CLI) UART port is a two wire protocol (TX and RX) that operates at a fixed 9600 baud rate
with one-stop bit and no parity. The CLI UART interface is intended to support command-line instructions and response
activity.
2.6
Autonomous MAC
Eterna was designed as a system solution with the objective of providing a reliable, ultra-low power, and secure network. A
reliable network capable of dynamically optimizing operation over changing environments requires solutions that are far too
complex to completely support through hardware acceleration alone. As described in Section 2.2, proper time management is
essential for optimizing a solution that is both low power and reliable. To address this solution Eterna includes the
Autonomous MAC, which includes hardware support for controlling all of the time-critical radio operations. The
Autonomous MAC provides two benefits: first, preventing variable software latency from affecting network timing and
second, greatly reducing system power consumption by allowing the CPU to remain inactive during the majority of the radio
activity. The Autonomous MAC, unique to Eterna, provides software-independent timing control of the radio and radio-
related functions, resulting in superior reliability and exceptionally low power.
2.7
Security
Network security is an often overlooked component of a complete network solution. Proper implementation of security
protocols is significant in terms of both engineering effort and market value in an OEM product. Eterna system solutions
provide a FIPS-197 validated encryption scheme, and goes further, providing a complete set of mechanisms to protect
network security. Eterna includes hardware support for electronically locking devices, thereby preventing access to Eterna’s
flash and RAM memory. This lock-out feature provides a means to securely unlock a device should support of a product
require access. For details see 040-0109 Design Specific Configuration Guide.
2.8
Temperature Sensor
Eterna includes a calibrated temperature sensor on chip. The temperature readings are available locally through Eterna’s
serial API, in addition to being available via the network manager. The performance characteristics of the temperature sensor
can be found in Section 8.6.
2.8.1
Radio Inhibit
The RADIO_INHIBIT digital interrupt enables an external controller to temporarily disable the radio software drivers (for
example, to take a sensor reading that is susceptible to radio interference). When RADIO_INHIBIT is asserted the software
radio drivers will disallow radio operations including clear channel assessment, packet transmits, or packet receipts. If a radio
event is in progress radio inhibit will take effect after the present operation completes. For details on the timing associated
with RADIO_INHIBIT, see Section 8.12.
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Eterna Datasheet
A d v a n c e d I n f o r m a t i o n
2.8.2
Sleep
The SLEEPn digital interrupt enables an external controller to temporarily disable Eterna’s duty cycling between active and
Doze states (see Section 4.0 for state definitions). Forcing Eterna to the Doze state should only be done when absolutely
necessary, such as when taking a very sensitive sensor reading, as forcing a device into a Doze state will on the average
increase the energy consumption of other devices in the network. When SLEEPn is asserted the software will go into a Doze
state until the SLEEPn signal is negated. For details on the timing associated with SLEEPn, see Section 8.11.
2.10
Flash Programming
Eterna’s software images are loaded via the IPCS, in-circuit programming control system, SPI interface. Sequencing of
RESETn and FLASH_P_ENn, as described in Section 4.0, places Eterna in a state emulating a serial flash to support in-
circuit programming. Hardware and software for supporting development and production programming of devices is
described in 040-0110 Eterna Serial Programmer Guide. The serial protocol, SPI, and timing parameters are described in
Section 8.13.
4.0 Operation
In order to provide capabilities and flexibility in addition to ultra low power, Eterna operates in various states, as shown in
Figure 8 and described in this section.
Power-On
Reset
VSUPPLY > PoR
RESETn low and
FLASH_P_ENn low
Load Fuse
Settings
Serial Flash
Emulation
RESETn low and
FLASH_P_ENn high
Set RESETn high and
FLASH_P_EN high
for 125 µs, then
set RESETn low
Reset
De-assert RESETn
Boot
Start Up
Assert RESETn
Deep Sleep
Assert RESETn
Assert RESETn
CPU and peripherals
inactive
Doze
Active
HW or PMU Event
lowPowerSleep
Command
Operation
Figure 8 State Diagram – Operating Modes
Inactive
4.1
Start Up
Start Up occurs as a result of either tripping of the power-on-reset circuit or the assertion of RESETn. After the completion
of power-on-reset (see Section 2.1.1) or the falling edge of an internally synchronized RESETn, Eterna loads its Fuse Table
(see section 4.1.1), including setting I/O direction. In this state, Eterna checks the state of the FLASH_P_ENn and RESETn
Eterna Datasheet
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A d v a n c e d I n f o r m a t i o n
and enters the serial flash emulation mode, if both signals are asserted. If the FLASH_P_ENn pin is not asserted but RESETn
is not asserted, Eterna automatically reduces its energy consumption to a minimum until RESETn is released. Once RESETn is de-
asserted, Eterna goes through a boot sequence, and then enters the Active state.
4.1.1
Fuse Table
Eterna’s Fuse Table is a 2 KB page in flash that contains two data structures, one for hardware configuration immediately
following Power on Reset or the assertion of RESETn and one for configuration of design specific parameters. Hardware
support for configuration includes configuration of I/O, preventing I/O leakage from negatively affecting current
consumption during power on, which can be a significant issue for current limited supplies. Examples of design-specific
parameters include setting of UART modes, clock sources and trim values. Fuse Tables are created via the Fuse Table
application software described in 040-0109 Design Specific Configuration Guide. Fuse Tables are loaded into flash using the
same software and in-circuit programmer used to load Eterna’s networking software image – see the 040-0110 Eterna Serial
Programmer Guide for details.
4.2
Serial Flash Emulation
When both RESETn and FLASH_P_ENn are asserted, Eterna disables normal operation and enters a mode to emulate the
operation of a serial flash. In this mode, its flash can be programmed with software updates. For details, see Section 2.10.
4.3
Operation
Once Eterna has completed startup, Eterna transitions to the Operational group of states (active / CPU active, active / CPU
inactive, and Doze). There, Eterna cycles between the various states, automatically selecting the lowest power state possible
while fulfilling the demands of network operation.
4.3.1
Active State
In Active state, the Eterna’s relaxation oscillator is running and peripherals are enabled as needed. The ARM Cortex-M3
cycles as needed between CPU-active and CPU-inactive (referred to in the ARM Cortex-M3 literature as “Sleep Now” or
“Sleep on Exit” modes). Eterna’s extensive use of DMA and intelligent peripherals that can independently move Eterna
between the Active and Doze states minimizes the time the CPU is active, significantly reducing Eterna’s energy
consumption.
4.3.2
Doze State
The Doze state consumes orders of magnitude less current than the Active state (see Table 6) and is entered when all of the
peripherals, save the low power portion of the timer module, and the CPU are inactive. In the Doze state Eterna’s full state is
retained and Eterna is configured to detect, wake, and rapidly respond to activity on I/Os (such as UART signals and the
TIMEn pin). The Doze state also uses the 32.768-kHz oscillator and 32 kHz based timers are active.
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Eterna Datasheet
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4.4
Duty Cycling and Autonomous Peripherals
Eterna’s ability to quickly and efficiently transition between Doze and Active states, in conjunction with the ability of
peripherals to operate autonomously for most operations (shown in Figure 9), enables the system solution to significantly
reduce power consumption. For example the system can automatically go from Doze to Active and determine if RF energy is
present. The CPU is then only woken if a packet is detected, otherwise Eterna returns to Doze mode.
Figure 9 Low Energy Duty Cycling
Eterna Datasheet
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A d v a n c e d I n f o r m a t i o n
5.0 Pinout
5.2
Eterna Mote Modules
The Eterna mote modules are shown in Figure 11 and Figure 12. Pins are described in Table 2, where they are grouped by
function. In some cases, a pin may have multiple possible functions.
Note: All unused input pins not configured with a pull resistor (see Pull column in pin out table) must be driven to an
inactive state to avoid excess leakage and undesired operation. Leakage due to floating inputs can be substantially greater
than Eterna’s average power consumption.
Antenna
Connector
GND
RESERVED
NC
1
2
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
GND
NC
3
RADIO_INHIBIT
TIMEn
LNA_EN
RADIO_TX
RADIO_TXn
AI_2
4
5
UART_TX
UART_TX_CTSn
UART_TX_RTSn
UART_RX
UART_RX_CTSn
UART_RX_RTSn
GND
6
7
AI_1
8
AI_3
9
AI_0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
RESERVED
NC
VSUPPLY
RESERVED
NC
NC
RESETn
TDI
NC
FLASH_P_ENn
SPIS_SSn
SPIS_SCK
GPIO26 / SPIS_MOSI
SPIS_MISO
PWM0
TDO
TMS
TCK
GND
DP4
RESERVED
RESERVED
RESERVED
DP3
DP1
SPIM_SS_0n
SPIM_SS_1n
GND
DP2 / GPIO21
SLEEPn
DP0
SPIM_SCK
SPIM_MOSI
IPCS_SSn / GPIO3
SPIM_MISO
GND
NC
GND
Figure 11 LTP5902-WHM – Mote Module with MMCX Antenna Connector
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Figure 12 LTP5901-WHM – Mote Module with Chip Antenna
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Linear Technology / Dust Networks
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A d v a n c e d I n f o r m a t i o n
Table 2
Eterna Mote Module Pinout Assignments
Mechanical
NA
No
1
MECH
Contacts for mechanical support of MMCX connector
Power Supply
GND
Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Type
1
I/O
Pull
Description
-
-
Ground
11
20
30
34
37
42
56
66
55
No
4
GND
-
-
Ground
GND
-
-
Ground
GND
-
-
Ground
GND
-
-
Ground
GND
-
-
Ground
GND
-
-
Ground
GND
-
-
Ground
GND
-
-
-
Ground
VSUPPLY
Radio
-
Module power supply input
Description
I/O
O
Pull
LNA_EN
GPIO17
RADIO_TX
GPIO18
RADIO_TXn
GPIO19
RADIO_INHIBIT
GPIO15
Analog
AI_0
-
External LNA enable
General purpose digital I/O
Radio TX active (external PA enable/switch control)
General purpose digital I/O
Radio TX active (external PA enable/switch control), active low
General purpose digital I/O
Radio Inhibit
1
I/O
O
-
5
1
-
1
I/O
O
-
6
1
-
1
I/O
I
-
64
1*
-
I/O
I/O
I
-
General purpose digital I/O
Description
No
10
8
Type
Analog
Analog
Analog
Analog
Type
1
Pull
-
Analog input 0
AI_1
I
-
Analog input 1
9
AI_3
I
-
Analog input 3
7
AI_2
I
-
Analog input 2
No
15
No
16
17
18
19
No
31
32
No
57
58
59
60
61
62
General
RESETn
I/O
I
Pull
Description
UP
Reset, Input, active low
JTAG
TDI
Type
I/O
Pull
Description
JTAG test data in
1
1
1
1
I
O
I
UP
TDO
JTAG test data out
-
TMS
JTAG test mode select
JTAG test clock
UP
TCK
I
DOWN
CLI
Type
I/O
Pull
Description
CLI UART 0 transmit
UARTC0_TX
UARTC0_RX
2
1
O
I
-
CLI UART 0 receive
UP
UART
Type
1*
1
I/O
Pull
Description
UART receive (RTS) request to send, active low
UART receive (CTS) clear to send, active low
UART receive
UART_RX_RTSn
UART_RX_CTSn
UART_RX
I
O
I
-
-
-
-
-
-
1*
1
UART_TX_RTSn
UART_TX_CTSn
UART_TX
O
I
UART transmit (RTS) request to send, active low
UART transmit (CTS) clear to send, active low
UART transmit
1*
2
O
14
Linear Technology / Dust Networks
Eterna Datasheet
A d v a n c e d I n f o r m a t i o n
No
IPCS SPI /
FLASH
Type
I/O
Pull
Description
Programming
33
35
36
39
IPCS_MISO
GPIO6
2
1
1
1
O
I/O
I
-
SPI flash emulation (MISO) master in slave out port
General purpose digital I/O
-
IPCS_MOSI
GPIO5
-
SPI flash emulation (MOSI) master out slave in port
General purpose digital I/O
I/O
I
-
IPCS_SCK
GPIO4
-
-
SPI flash emulation (SCK) serial clock port
General purpose digital I/O
I/O
I
IPCS_SSn
GPIO3
-
SPI flash emulation slave select, active low
General purpose digital I/O
I/O
I
-
51
FLASH_P_ENn
UP
Flash program enable, active low
Note that this functionality is available only when RESETn is asserted
No
Special
Type
I/O
Pull
Description
Purpose Digital
27
63
SLEEPn
TIMEn
1*
1*
I
I
-
-
Deep Sleep, active low
Time capture request, active low
* Input signals that must be driven or pulled to a valid state to avoid leakage.
5.3
Power Supply
Eterna is powered from a single pin, VSUPPLY, and generates all required supplies internally. With two integrated DC/DC
converters and four voltage regulators, the sensitivity to noise on VSUPPLY is minimal. However, during typical operation
Eterna will vary its load on the power supply from the μA range to 10’s of mA over a few μs. During such transients, the
power supply must meet the specifications for supply noise tolerance. Eterna is designed to operate with specific decoupling
capacitance on VCORE, VDDA, VOSC, VDDPA, and VPRIME, as well as the internal converter capacitors C1 through C4.
Failure to use correctly sized ceramic capacitors can result in supply instability and performance degradation.
5.3.1
Antenna
Eterna allows direct connection to a single-ended 50-Ohm antenna; an internal TX/RX switch simplifies external circuitry
requirements. Because both the transmit and the receive paths are single-ended, a balun (with its associated cost and
efficiency loss) are not required. Eterna provides options to set typical output power to 0 dBm or to +8 dBm using the on-chip
PA. For further details on radio transmit and receive, see section 2.4.
5.4
Analog
Eterna has four analog inputs. Its 10-bit ADC includes a 4-bit DAC for adjusting offset and a 3-bit VGA, as shown in Figure
13. The software application layer controls ADC operation and may be configured to automatically sample any combination
of the internal temperature sensor, or analog input signals.
Figure 13 Analog to Digital Chain
5.5
JTAG
Eterna includes an IEEE 1149.1-compliant JTAG port for boundary scan.
Eterna Datasheet
Linear Technology / Dust Networks
15
A d v a n c e d I n f o r m a t i o n
6.0 Absolute Maximum Ratings
The absolute maximum ratings shown in Table 3 should not be violated under any circumstances. Permanent damage to the
device may be caused by exceeding one or more of these parameters. Unless otherwise noted, all voltages in Table 3 are
relative to GND.
Table 3
Absolute Maximum Ratings
Parameter
Min
–0.3
–0.3
Typ
Max
Units
Comments
Supply voltage (VSUPPLY to GND)
Voltage on any digital I/O pin
3.76
V
V
VSUPPLY
+ 0.3
up to 3.76
Input RF level
+10
dBm
°C
Input power at antenna connector
Storage temperature range
–55
+105
Extended storage at high
temperature is discouraged, as this
negatively affects the data
retention of Eterna’s calibration
data.
Lead temperature
VSWR of antenna
ESD protection
+245
3:1
°C
For 10 seconds
Antenna pad
All other pads
±8000
±1000
±100
V
V
V
HBM
HBM
CDM
Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent
permanent damage.
16
Linear Technology / Dust Networks
Eterna Datasheet
A d v a n c e d I n f o r m a t i o n
7.0
Table 4
Recommended Operating Conditions
Recommended Operation Conditions
Parameter
Conditions
Min
Typ
Max
3.76
250
Units
V
VSUPPLY range
Including noise and load regulation
2.1
3.6
Voltage supply noise
Requires recommended RLC filter,
50 Hz to 2 MHz
mVp-p
Operating temperature range
Operating relative humidity
Power on Reset threshold
Temperature ramp
–40
10
+85
90
°C
% RH
V
Non-condensing
1.5
-8
+8
°C/min
8.0
Electrical Characteristics
8.1
Radio Specifications
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 5
Detailed Radio Specifications
Parameter
Conditions
Min
Typ
Max
Units
Frequency Band
As specified by [ 1 ]
2.4000
2.4835
GHz
Number of channels
15
5
Channel separation
As specified by [ 1 ]
At –20 dBc
MHz
MHz
MHz
Occupied channel bandwidth
Channel Center Frequency
2.7
Where k = 11 to 25.‡
2405 +
5 * (k-11)
Modulation
IEEE 802.15.4 DSSS
As specified by [ 1 ]
Raw data rate
250
kbps
Range*
25 °C, 50% RH, +2 dBi
omni-directional antenna
Indoor†
100
300
1200
m
m
m
Outdoor†
Free space
*
Actual RF range performance is subject to a number of installation-specific variables including, but not restricted to
ambient temperature, relative humidity, presence of active interference sources, line-of-sight obstacles, and near-
presence of objects (for example, trees, walls, signage, and so on) that may induce multipath fading. As a result, actual
performance varies.
†
1 meter above ground.
‡ Channel 26 as specified by [ 1 ] is not used..
8.2
DC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 6
DC Specifications
Parameter
Conditions
Min
Typ
1.2
0.8
1.2
Max
Units
µA
Reset
After power-on reset
Deep Sleep
Doze
µA
RAM on; ARM Cortex-M3, flash, radio,
and peripherals off, all data and state
retained, 32.768 kHz reference active
µA
Serial Flash Emulation
Peak Operating current
20
mA
mA
System operating at 14.7 MHz
Radio Tx
Flash Write
at +8 dBm output power
30
Eterna Datasheet
Linear Technology / Dust Networks
17
A d v a n c e d I n f o r m a t i o n
Parameter
Conditions
Min
Typ
Max
Units
at 0 dBm output power
26
mA
Active*
ARM Cortex-M3, RAM, and flash on;
radio and peripherals off
CLK = 7.37 MHz, Vcore = 1.8 V
Single bank write
2.4
3
mA
mA
mA
Flash write
Flash erase
Radio Tx†
Single bank page or mass erase
2.5
Mesh Network - CLK = 7.3728 MHz,
AES active
0 dBm output power
+8 dBm output power
5.4
9.7
mA
mA
Radio Rx†
Mesh Network - CLK = 7.3728 MHz,
AES active
4.5
mA
Note: See section 3.0 for detailed operational definitions of states.
* CLK = Clock frequency of CPU and peripherals.
†
Current with autonomous MAC handling packet transmission and reception; CPU idle.
8.3
Radio Receive Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 7
Radio Receive Characteristics
Parameter
Conditions
Min
Typ
–93
–95
0
Max
Units
dBm
dBm
dBm
dBc
Receiver sensitivity
PER = 1%, as specified by [ 1 ]
PER = 50%
Receiver sensitivity
Saturation (maximum input level)
Adjacent channel rejection (high
side)
Desired signal at -82 dBm, adjacent
modulated channel at 5 MHz, PER =
1%, as specified by [ 1 ]
22
Adjacent channel rejection (low
side)
Desired signal at -82 dBm, adjacent
modulated channel at -5 MHz, PER
= 1%, as specified by [ 1 ]
19
40
36
42
–6
dBc
dBc
dBc
dBc
dBc
Alternate channel rejection (high
side)
Desired signal at -82 dBm, adjacent
modulated channel at 10 MHz, PER
= 1%, as specified by [ 1 ]
Alternate channel rejection (low
side)
Desired signal at -82 dBm, adjacent
modulated channel at -10 MHz, PER
= 1%, as specified by [ 1 ]
Second alternate channel
rejection
Desired signal at -82 dBm, adjacent
modulated channel at +/-10 MHz,
PER = 1%, as specified by [ 1 ]
Co-channel rejection
Desired signal at -82 dBm.
Undesired signal is 802.15.4
modulated at same frequency. PER
= 1%, as specified by [ 1 ]
LO feed through
<–55
dBm
ppm
ppm
dBm
dB
Frequency error tolerance
Symbol rate error tolerance
RSSI input range
[ 1 ] requires ±40
±50
±50
–10 to –90
RSSI accuracy
±6
1
RSSI resolution
dB
18
Linear Technology / Dust Networks
Eterna Datasheet
A d v a n c e d I n f o r m a t i o n
8.4
Radio Transmitter Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 8
Radio Transmitter Characteristics
Parameter
Conditions
Min
Typ
Max
Units
Output power
Calibrated settings
Delivered to a 50 Ω load,
over temperature and voltage
ranges
0
+8
dBm
dBm
Spurious emissions
Conducted measurement with a
50 Ω single-ended load, +8 dBm
output power. All measurements
made with Max Hold. RF
implementation per Eterna reference
design.
30 MHz to 1000 MHz
1 GHz to 12.75 GHz
Upper Band Edge (Peak)
Upper Band Edge (Average)
Lower Band Edge
RBW = 120 kHz, VBW = 100 Hz
RBW = 1 MHz, VBW = 3 MHz
RBW = 1 MHz, VBW = 3 MHz
RBW = 1 MHz, VBW = 10 Hz
RBW = 100 kHz, VBW = 100 kHz
<–70
–45
-37
-49
-45
dBm
dBm
dBm
dBm
dBc
Harmonic emissions
Conducted measurement delivered
to a 50 Ω load, Resolution
Bandwidth = 1 MHz, Video
Bandwidth = 1 MHz, RF
implementation per Eterna reference
design
dBm
2nd Harmonic
3rd Harmonic
–50
–45
8.5
Digital I/O Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 9
Digital I/O Type 1
Parameter
Conditions
Min
Typ
Max
Units
VIL (low-level input voltage)
VIH (high-level input voltage)
–0.3
0.6
V
V
VSUPPLY
- 0.3†
VSUPPLY
+ 0.3†
VOL (low-level output voltage)
VOH (high-level output voltage)
IOL(max) = 1.2 mA
0.4
V
V
IOH(max) = −1.8 mA
VSUPPLY
- 0.3†
VSUPPLY
+ 0.3†
Input leakage current
pull-up / pull-down pins disabled.
50
nA
†
Min and Min and Max IO input levels must respect the Minimum and Maximum voltages for VSUPPLY.
Table 10 Digital I/O Type 2
Parameter
Conditions
Min
Typ
Max
Units
VIL (low-level input voltage)
VIH (high-level input voltage)
–0.3
0.6
V
V
VSUPPLY
- 0.3†
VSUPPLY
+ 0.3†
VOL (low-level output voltage)
Low Drive
I
I
I
OL(max) = 2.2 mA
OH(max) = −3.2 mA
O(max) = 4.5 mA
0.4
V
V
V
V
VOH (high-level output voltage)
Low Drive
VSUPPLY
- 0.3†
VSUPPLY
+ 0.3†
VOL (low-level output voltage)
High Drive
0.4
VOH (high-level output voltage)
IOH(max) = −6.3 mA
VSUPPLY
VSUPPLY
Eterna Datasheet
Linear Technology / Dust Networks
19
A d v a n c e d I n f o r m a t i o n
High Drive
- 0.3†
+ 0.3†
Max
Max
Input leakage current
50
nA
†
Min and Min and Max IO input levels must respect the Minimum and Maximum voltages for VSUPPLY.
8.6
Temperature Sensor Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 11 Temperature Sensor Characteristics
Parameter
Conditions
Min
Typ
±0.25
±0.033
Units
°C
Offset
Temperature offset error at 25 ºC
Slope error from -40 to +85 ºC
Slope error
°C/°C
8.7
ADC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 12 ADC Characteristics
Parameter
Conditions
Min
Typ
Units
Variable gain amplifier
Gain
1
8
1
Gain error
%
Digital to analog converter (DAC)
Offset output
1.8/16
1.8
7.2
V
mV
Differential non-linearity (DNL)
Analog to digital converter (ADC)
Full-scale, signal
1.80
1.8
V
Resolution
Offset
Differential non-linearity (DNL)
Integral non-linearity (INL)
Settling time
mV
LSB
LSB
LSB
µs
Midscale
±4
1
1
10
20
50
10-kOhm source impedance
Conversion time
Current consumption
µs
µA
Analog Inputs*
Load
17
1
35
2
pF
kOhm
Input resistance
* The analog inputs to the ADC can be model as a series resistor to a load capacitor. At a minimum the entire circuit,
including the source impedance for the signal driving the analog input should be designed to settle to within ¼ LSB within
the sampling window to match the performance of the ADC.
8.8
System Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 13 System Characteristics
Parameter
Doze to Active state delay
Doze to Radio TX or RX
Conditions
Min
Typ
5
Max
Units
µs
1.2
4
ms
QCCA charge to sample RF channel Start from Doze state
Radio baud rate
µC
250
kbps
µs
RESETn pulse width
125
20
Linear Technology / Dust Networks
Eterna Datasheet
A d v a n c e d I n f o r m a t i o n
8.9
UART AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 14 UART Timing Values
Parameter
Conditions
Min
–2
–1
0
Typ
Max
+2
Unit
%
tRX_BAUD
tTX_BAUD
Deviation from baud rate
Deviation from baud rate
+1
%
tRX_RTS_R to RX_CTS
Assertion of UART_RX_RTSn to
assertion of UART_RX_CTSn, or
negation of UART_RX_RTSn to
negation of UART_RX_CTSn
22
ms
tCTS_R to RX
Assertion of UART_RX_CTSn to start
of byte
0
0
0
20
22
22
ms
ms
ms
tEOP to RX_RTS
tTX_RTS_T to TX_CTS
End of packet (end of the last stop bit)
to negation of UART_RX_RTSn
Assertion of UART_TX_RTSn to
assertion of UART_TX_CTSn, or
negation of UART_TX_RTSn to
negation of UART_TX_CTSn
tTX_CTS_T to TX
tEOP to TX_RTS
Assertion of UART_TX_CTSn to start
of byte
0
0
2
1
bit
period
End of packet (end of the last stop bit)
to negation of UART_TX_RTSn
bit
period
tRX_INTERBYTE
tTX to TX_CTS
Receive Inter-byte delay
100
ms
ms
Start of byte to negation of
UART_TX_CTSn
0
tINTERPACKET
Transmit and Receive Inter-packet
delay (Mode 4 only)
100
ms
Figure 16 UART Timing
Eterna Datasheet
Linear Technology / Dust Networks
21
A d v a n c e d I n f o r m a t i o n
8.10
TIMEn AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified. Note that the time
pin must remain negated until the time packet has been received.
Table 15 Timestamp Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
µs
tstrobe
125
tresponse
Resolution
From rising edge of TIMEn
100
ms
µs
See the serial API definition for
getParameter<time>
+/- 1
Network-wide time accuracy
Stable temperature environment
+/- 50
µs
Figure 17 Timestamp Timing Diagram
8.11
SLEEPn AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified. Note that the time
pin must remain negated until the time packet has been received.
Table 16 SLEEPn Characteristics
Parameter
Conditions
Min
Typ
Max
20
Unit
ms
s
tdoze
From falling edge of SLEEPn
Maximum strobe width
Tsleep_strobe
2
Figure 18 SLEEPn Timing Diagram
8.12
RADIO_INHIBIT AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified. Note that the time
pin must remain negated until the time packet has been received.
Table 17 RADIO_INHIBIT Characteristics
Parameter
Conditions
Min
Typ
Max
20
Unit
ms
s
tradio_off
Tradio_inhibit_strobe
From rising edge of RADIO_INHIBIT
Maximum strobe width
2
22
Linear Technology / Dust Networks
Eterna Datasheet
A d v a n c e d I n f o r m a t i o n
Figure 19 RADIO_INHIBIT Timing Diagram
8.13
FLASH AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C, unless otherwise specified.
Table 18 FLASH AC Timing Values
Parameter
Conditions
Min
Typ
Max
21
Unit
µs
t32-BIT_WORD
tPAGE_ERASE
tMASS_ERASE
Writing a 32-bit word
Page Erase
21
ms
ms
Bank Erase
21
8.14
Flash Programming AC Characteristics
The following characteristics are measured with VSUPPLY = 3.6 V at 25 °C with 10 pF load capacitance, unless otherwise
specified.
Table 19 SPI Slave AC Timing Values
Parameter
Conditions
Min
Typ
Max
Unit
tSSS
tSSH
IPCS_SSn setup to leading edge of
IPCS_SCK
15
ns
IPCS_SSn hold from trailing edge of
IPCS_SCK
15
ns
tCK
IPCS_SCK period
50
15
5
ns
ns
ns
ns
ns
tDIS
tDIH
tDOV
tOFF
IPCS_MOSI data setup
IPCS_MOSI data hold
IPCS_MISO data valid
IPCS_MISO data tri-state
3
15
15
0
Figure 20 Flash Programming Slave Timing
Eterna Datasheet
Linear Technology / Dust Networks
23
A d v a n c e d I n f o r m a t i o n
9.0
Typical Performance Characteristics
Network motes typically route through at least two parents traffic destined for the manager. The bandwidth and keep-alive
overhead required to support network motes will be shared across all of the mote's parents. The supply current plots include a
parameter called traffic-weighted descendants. In these graphs the term traffic-weighted descendants refers to an amount of
activity equivalent to the number of descendants were all of the network traffic and keep-alives directed to the mote in
question. Generally the number of descendants of a parent is more (typically 2x or more) than the number of traffic-weighted
descendants. For example, with reference to Figure 25 mote P1 has 0.75 traffic-weighted descendants. To obtain this value
notice that mote D1 routes half its packets through mote P1 adding 0.5 to the traffic-weighted descendant value; the other
half of D1's traffic is routed through its other parent, P2. Mote D2 routes half its packets through mote D1 (the other half
going through parent P3), which we know routes half its packets to mote P1, adding another 0.25 to the traffic-weighted
descendant value for a total traffic-weighted descendant value of 0.75.
Figure 25 Network Graph Depicting Traffic Weighted Descendant Value Calculation
The following plots correspond to networks with a P2 bandwidth profile, an assumed path stability of 80%, an 80 byte packet
and unless otherwise specified operation at 25 degrees C.
24
Linear Technology / Dust Networks
Eterna Datasheet
A d v a n c e d I n f o r m a t i o n
10.0
Mechanical Details
10.2
Mote Module
The Eterna mote modules comes in 66-lead, 1 mm lead pitch castellated PCB, as illustrated in Figure 27 and in Figure 28.
Figure 27 Mechanical Drawing – LTP5901
Eterna Datasheet
Linear Technology / Dust Networks
25
A d v a n c e d I n f o r m a t i o n
Figure 28 Mechanical Drawing – LTP5902
26
Linear Technology / Dust Networks
Eterna Datasheet
A d v a n c e d I n f o r m a t i o n
10.3
Soldering Information
Eterna is suitable for both eutectic PbSn and RoHS-6 reflow. The maximum reflow soldering temperature is 260 ºC.
11.0
Regulatory and Standards Compliance
LTP5901 is compliant with EU, FCC and IC radio frequency regulations. For specific information on regulations, test
procedures, and labeling requirements, see the “LTP5901 Regulatory User Guide”.
LTP5902 is compliant with EU, FCC and IC radio frequency regulations. For specific information on regulations, test
procedures, and labeling requirements, see the “LTP5902 Regulatory User Guide”.
11.1
Compliance to Restriction of Hazardous Substances (RoHS)
Restriction of Hazardous Substances (RoHS) is a directive that places maximum concentration limits on the use of cadmium
(Cd), lead (Pb), hexavalent chromium (Cr+6), mercury (Hg), Polybrominated Biphenyl (PBB), and Polybrominated Diphenyl
Ethers (PBDE). Dust Networks is committed to meeting the requirements of the European Community directive 2002/95/EC.
This product has been specifically designed to utilize RoHS-compliant materials and to eliminate or reduce the use of
restricted materials to comply with 2002/95/EC.
The RoHS-compliant design features include:
•
•
•
•
•
•
•
RoHS-compliant solder for solder joints
RoHS-compliant base metal alloys
RoHS-compliant precious metal plating
RoHS-compliant cable assemblies and connector choices
Lead-free QFN package
Halogen-free mold compound
RoHS-compliant and 245 °C re-flow compatible
Note: Customers may elect to use certain types of lead-free solder alloys in accordance with the European Community
directive 2002/95/EC. Depending on the type of solder paste chosen, a corresponding process change to optimize reflow
temperatures may be required.
12.0
References
[ 1 ]
IEEE Std. 802.15.4-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications
for Low-Rate Wireless Personal Area Networks (LR-WPANs)
http://standards.ieee.org/getieee802/download/802.15.4-2006.pdf
13.0 Order Information
LEAD FREE FINISH**
PART
PACKAGE
TEMPERATURE
RANGE
MARKING* DESCRIPTION
LTP5901IPC-WHMA???#PBF
LTP5902IPC-WHMA???#PBF
LTP5901
LTP5902
66-Lead (42mm x
-40 °C to 85 °C
24mm) PCB
66-Lead (37.465mm x
24mm) PCB
-40 °C to 85 °C
** See http://www.linear.com/ or contact your sales representative to determine the three digit software version field, ???.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
Eterna Datasheet
Linear Technology / Dust Networks
27
A d v a n c e d I n f o r m a t i o n
Trademarks
SmartMesh Industrial and Eterna are trademarks of Dust Networks, Inc. The Dust Networks logo, Dust, Dust Networks, and SmartMesh are registered
trademarks of Dust Networks, Inc. The Linear logo is a registered trademark of Linear Technology Corporation. All third-party brand and product names
are the trademarks of their respective owners and are used solely for informational purposes.
ARM and Cortex are trademarks or registered trademarks of ARM Limited in the EU and other countries.
Copyright
This documentation is protected by United States and international copyright and other intellectual and industrial property laws. It is solely owned by
Dust Networks, Inc. and its licensors and is distributed under a restrictive license. This product, or any portion thereof, may not be used, copied, modified,
reverse assembled, reverse compiled, reverse engineered, distributed, or redistributed in any form by any means without the prior written authorization of
Dust Networks, Inc.
RESTRICTED RIGHTS: Use, duplication, or disclosure by the U.S. Government is subject to restrictions of FAR 52.227-14(g) (2)(6/87) and FAR
52.227-19(6/87), or DFAR 252.227-7015 (b)(6/95) and DFAR 227.7202-3(a), and any and all similar and successor legislation and regulation.
Disclaimer
This documentation is provided “as is” without warranty of any kind, either expressed or implied, including but not limited to, the implied warranties of
merchantability or fitness for a particular purpose.
This documentation might include technical inaccuracies or other errors. Corrections and improvements might be incorporated in new versions of the
documentation.
Dust Networks does not assume any liability arising out of the application or use of any products or services and specifically disclaims any and all
liability, including without limitation consequential or incidental damages.
Dust Networks products are not designed for use in life support appliances, devices, or other systems where malfunction can reasonably be expected to
result in significant personal injury to the user, or as a critical component in any life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Dust Networks customers using or selling these
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indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Dust Networks was
negligent regarding the design or manufacture of its products.
Dust Networks reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products or services at any
time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should
verify that such information is current and complete. All products are sold subject to Dust Network's terms and conditions of sale supplied at the time of
order acknowledgment or sale.
Dust Networks does not warrant or represent that any license, either express or implied, is granted under any Dust Networks patent right, copyright, mask
work right, or other Dust Networks intellectual property right relating to any combination, machine, or process in which Dust Networks products or
services are used. Information published by Dust Networks regarding third-party products or services does not constitute a license from Dust Networks to
use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or
other intellectual property of the third party, or a license from Dust Networks under the patents or other intellectual property of Dust Networks.
Dust Networks, Inc is a wholly owned subsidiary of Linear Technology Corporation.
© Dust Networks, Inc. 2012. All Rights Reserved.
28
Linear Technology / Dust Networks
Eterna Datasheet
A d v a n c e d I n f o r m a t i o n
Last Revised:
March 15, 2013
Document Status
Product Status
Definition
Advanced Information
Planned or under development This datasheet contains the design specifications for product
development. Dust Networks reserves the right to change
specifications in any manner without notice.
Preliminary
Engineering samples and
pre-production prototypes
This datasheet contains preliminary data; supplementary data will
be published at a later time. Dust Networks reserves the right to
make changes at any time without notice in order to improve
design and supply the best possible product. The product is not
fully qualified at this point.
No Identification Noted Full production
This datasheet contains the final specifications. Dust Networks
reserves the right to make changes at any time without notice in
order to improve design and supply the best possible product.
Obsolete
Not in production
This datasheet contains specifications for a product that has been
discontinued by Dust Networks. The datasheet is printed for
reference information only.
Eterna Datasheet
Linear Technology / Dust Networks
29
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