DS1230W-100+ [MAXIM]
3.3V 256k Nonvolatile SRAM;
| 型号： | DS1230W-100+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.3V 256k Nonvolatile SRAM 静态存储器 |
| 文件： | 总10页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5636; Rev 11/10
DS1230W
3.3V 256k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
. 10 years minimum data retention in the
absence of external power
VCC
A14
A12
A7
1
28
27
WE
A13
A8
2
3
4
26
25
. Data is automatically protected during power
loss
. Replaces 32k x 8 volatile static RAM,
EEPROM or Flash memory
. Unlimited write cycles
. Low-power CMOS
A6
A9
A11
OE
A10
CE
DQ7
DQ6
A5
A4
5
6
24
23
A3
A2
7
8
22
21
A1
9
20
19
A0
10
. Read and write access times of 100ns
. Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
. Optional industrial temperature range of
-40°C to +85°C, designated IND
. JEDEC standard 28-pin DIP package
. PowerCap Module (PCM) package
DQ0
11
12
18
17
DQ5
DQ4
DQ3
DQ1
DQ2
GND
13
14
16
15
28-Pin Encapsulated Package
740-Mil Extended
34
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
NC
NC
NC
33
32
31
30
2
-
-
Directly surface-mountable module
Replaceable snap-on PowerCap provides
lithium backup battery
3
4
5
6
7
8
9
NC
VCC
29
28
27
26
25
24
23
22
21
20
19
18
WE
OE
CE
-
-
Standardized pinout for all nonvolatile
SRAM products
Detachment feature on PowerCap allows
easy removal using a regular screwdriver
DQ7
DQ6
DQ5
DQ4
DQ3
10
11
12
13
14
15
16
17
VBAT
GND
DQ2
DQ1
DQ0
GND
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
PIN DESCRIPTION
A0 - A14
DQ0 - DQ7
CE
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+3.3V)
- Ground
WE
OE
VCC
GND
NC
- No Connect
1 of 10
DS1230W
DESCRIPTION
The DS1230W 3.3V 256k Nonvolatile SRAM is a 262,144-bit, fully static, nonvolatile SRAM organized
as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs,
the lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1230W devices can be used in place of existing 32k x 8 static
RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the
pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230W
devices in the PowerCap Module package are directly surface mountable and are normally paired with a
DS9034PC PowerCap to form a complete Nonvolatile SRAM Module. There is no limit on the number of
write cycles that can be executed and no additional support circuitry is required for microprocessor
interfacing.
READ MODE
The DS1230W executes a read cycle whenever
(Write Enable) is inactive (high) and
(Chip
CE
WE
Enable) and
(Output Enable) are active (low). The unique address specified by the 15 address inputs
OE
(A0 – A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing
that
and
(Output Enable) access times are also satisfied. If
and
access times are not
CE
CE
OE
OE
satisfied, then data access must be measured from the later-occurring signal (
or
) and the limiting
OE
CE
parameter is either tCO for
or tOE for
rather than address access.
OE
CE
WRITE MODE
The DS1230W executes a write cycle whenever the
and
signals are active (low) after address
CE
WE
inputs are stable. The later-occurring falling edge of
or
will determine the start of the write cycle.
WE
CE
The write cycle is terminated by the earlier rising edge of
or
. All address inputs must be kept
WE
CE
valid throughout the write cycle.
must return to the high state for a minimum recovery time (tWR)
WE
before another cycle can be initiated. The
control signal should be kept inactive (high) during write
OE
cycles to avoid bus contention. However, if the output drivers are enabled (
will disable the outputs in tODW from its falling edge.
and
active) then
OE WE
CE
DATA RETENTION MODE
The DS1230W provides full functional capability for VCC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As VCC
falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal
RAM operation can resume after VCC exceeds 3.0 volts.
FRESHNESS SEAL
Each DS1230W device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than 3.0 volts, the lithium energy source
is enabled for battery back-up operation.
2 of 10
DS1230W
PACKAGES
The DS1230W is available in two packages: 28-pin DIP and 34-pin PowerCap Module (PCM). The 28-
pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard, 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1230W to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1230W module base is reflow soldered, a DS9034PC PowerCap is snapped on top
of the base to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1230W module bases and DS9034PC PowerCaps are ordered separately and shipped in
separate containers. See the DS9034PC data sheet for further information.
3 of 10
DS1230W
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Commercial:
-0.3V to +4.6V
0°C to +70°C
Industrial:
-40°C to +85°C
Storage Temperature Range
EDIP
PowerCap
Lead Temperature (soldering, 10s)
Note: EDIP is wave or hand soldered only.
Soldering Temperature (reflow, PowerCap)
-40°C to +85°C
-55°C to +125°C
+260°C
+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA: See Note 10)
PARAMETER
Power Supply Voltage
Logic 1
SYMBOL MIN
TYP
MAX
3.6
UNITS NOTES
VCC
VIH
VIL
3.0
2.2
0.0
3.3
V
V
V
VCC
0.4
Logic 0
DC ELECTRICAL CHARACTERISTICS
(TA: See Note 10) (VCC = 3.3V ±0.3V)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Input Leakage Current
IIL
IIO
-1.0
-1.0
-1.0
2.0
+1.0
µA
µA
mA
mA
µA
µA
mA
V
+1.0
I/O Leakage Current
≥ VIH ≤ VCC
CE
Output Current @ 2.2V
Output Current @ 0.4V
IOH
IOL
ICCS1
ICCS2
ICCO1
VTP
50
30
250
150
50
Standby Current
Standby Current
=2.2V
CE
CE
=V -0.2V
CC
Operating Current
Write Protection Voltage
2.8
2.9
3.0
4 of 10
DS1230W
(TA = +25°C)
UNITS NOTES
pF
CAPACITANCE
PARAMETER
SYMBOL MIN
TYP
MAX
10
Input Capacitance
CIN
5
5
Input/Output Capacitance
CI/O
10
pF
AC ELECTRICAL CHARACTERISTICS
(TA: See Note 10) (VCC = 3.3V ±0.3V)
DS1230W-100
PARAMETER
SYMBOL
UNITS NOTES
MIN
MAX
Read Cycle Time
tRC
tACC
tOE
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Access Time
100
50
OE to Output Valid
CE to Output Valid
tCO
100
OE or CE to Output Active
Output High-Z from Deselection
Output Hold from Address Change
Write Cycle Time
tCOE
tOD
tOH
tWC
tWP
tAW
5
5
5
35
5
100
75
0
Write Pulse Width
3
Address Setup Time
tWR1
tWR2
5
20
ns
ns
12
13
Write Recovery Time
tODW
tOEW
tDS
35
ns
ns
ns
5
5
4
Output High-Z from
Output Active from
Data Setup Time
WE
WE
5
40
tDH1
tDH2
0
20
ns
ns
12
13
Data Hold Time
5 of 10
DS1230W
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
6 of 10
DS1230W
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
POWER-DOWN/POWER-UP CONDITION
7 of 10
DS1230W
POWER-DOWN/POWER-UP TIMING
(TA: See Note 10)
PARAMETER
SYMBOL MIN
tPD
tF
TYP
MAX
UNITS NOTES
1.5
11
µs
µs
µs
ms
ms
VCC Fail Detect to
and
Inactive
WE
CE
VCC slew from VTP to 0V
VCC slew from 0V to VTP
150
150
tR
tPU
tREC
2
VCC Valid to
and
Inactive
WE
CE
VCC Valid to End of Write Protection
125
(TA = +25°C)
UNITS NOTES
PARAMETER
SYMBOL MIN
tDR 10
TYP
MAX
Expected Data Retention Time
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
is high for a Read Cycle.
WE
2.
= VIH or VIL. If
= VIH during write cycle, the output buffers remain in a high-impedance state.
OE
OE
3. tWP is specified as the logical AND of
and
. t is measured from the latter of
or
CE WE
CE
WE
WP
going low to the earlier of
or
going high.
WE
CE
4. tDH, tDS are measured from the earlier of
or
going high.
WE
CE
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the low transition occurs simultaneously with or latter than the
low transition, the output
high transition, the output
CE
WE
WE
buffers remain in a high-impedance state during this period.
7. If the high transition occurs prior to or simultaneously with the
CE
buffers remain in high-impedance state during this period.
8. If is low or the low transition occurs prior to or simultaneously with the low transition,
CE
WE
WE
the output buffers remain in a high-impedance state during this period.
9. Each DS1230W has a built-in switch that disconnects the lithium source until VCC is first applied by
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
time power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
12. tWR1 and tDH1 are measured from
going high.
WE
13. tWR2 and tDH2 are measured from
going high.
CE
14. DS1230 modules are recognized by Underwriters Laboratories (UL) under file E99151.
8 of 10
DS1230W
DC TEST CONDITIONS
Outputs Open
Cycle = 200ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate
Input Pulse Levels: 0 to 2.7V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
SUPPLY
TOLERANCE
3.3V ± 0.3V
3.3V ± 0.3V
3.3V ± 0.3V
3.3V ± 0.3V
SPEED GRADE
PART
TEMP RANGE
PIN-PACKAGE
(ns)
100
100
100
100
DS1230W-100+
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
28 740 EDIP
34 PowerCap*
28 740 EDIP
34 PowerCap*
DS1230WP-100+
DS1230W-100IND+
DS1230WP-100IND+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PC+ or DS9034PCI+ (PowerCap) required. Must be ordered separately.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0245
LAND PATTERN NO.
—
28 EDIP
MDT28+3
—
34 PCAP
PC2+4
21-0246
9 of 10
DS1230W
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Added the Ordering Information table; removed the DIP module
package drawing and dimension table
121907
8
Updated the storage information, soldering temperature, and lead
temperature information in the Absolute Maximum Ratings section;
removed the -150 MIN/MAX information from the AC Electrical
Characteristics table; updated the Ordering Information table
(removed -150 parts and leaded -100 parts); removed the PowerCap
module drawings and updated the Package Information table
11/10
1, 4, 5, 9
10 of 10
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明