DS1245AB-70 [MAXIM]
1024k Nonvolatile SRAM; 1024K非易失SRAM型号: | DS1245AB-70 |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | 1024k Nonvolatile SRAM |
文件: | 总10页 (文件大小:229K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
19-5638; Rev 11/10
DS1245Y/AB
1024k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
. 10 years minimum data retention in the
absence of external power
NC
A16
A14
A12
A7
1
32
31
VCC
A15
NC
WE
A13
A8
2
3
4
30
29
. Data is automatically protected during power
loss
. Replaces 128k x 8 volatile static RAM,
EEPROM or Flash memory
. Unlimited write cycles
. Low-power CMOS
5
6
28
27
A6
A5
A4
A9
7
8
26
25
A11
OE
A10
CE
A3
9
24
23
A2
10
A1
. Read and write access times of 70 ns
. Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
. Full ±10% VCC operating range (DS1245Y)
. Optional ±5% VCC operating range
(DS1245AB)
. Optional industrial temperature range of
-40°C to +85°C, designated IND
. JEDEC standard 32-pin DIP package
. PowerCap Module (PCM) package
11
12
22
21
DQ7
DQ6
DQ5
DQ4
DQ3
A0
DQ0
DQ1
DQ2
GND
13
14
15
16
20
19
18
17
32-Pin Encapsulated Package
740-mil Extended
34
NC
NC
A14
1
2
3
NC
33
32
31
30
A15
A16
NC
4
5
6
A13
A12
A11
A10
A9
-
-
Directly surface-mountable module
Replaceable snap-on PowerCap provides
lithium backup battery
VCC
29
28
27
26
25
24
23
22
21
20
19
18
WE
7
OE
8
CE
9
A8
DQ7
10
11
12
13
14
15
16
17
A7
A6
A5
A4
A3
A2
A1
A0
-
-
Standardized pinout for all nonvolatile
SRAM products
Detachment feature on PowerCap allows
easy removal using a regular screwdriver
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
GND VBAT
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
PIN DESCRIPTION
A0 - A16
DQ0 - DQ7
CE
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+5V)
- Ground
WE
OE
VCC
GND
NC
- No Connect
1 of 10
DS1245Y/AB
DESCRIPTION
The DS1245 1024k Nonvolatile SRAMs are1,048,576-bit, fully static, nonvolatile SRAMs organized as
131,072 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1245 devices can be used in place of existing 128k x
8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1245 devices in the
PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1245 executes a read cycle whenever
(Write Enable) is inactive (high) and
(Chip Enable)
CE
WE
and
(Output Enable) are active (low). The unique address specified by the 17 address inputs (A0 -
OE
A16) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the eight
data output drivers within tACC (Access Time) after the last address input signal is stable, providing that
and
(Output Enable) access times are also satisfied. If
and
access times are not satisfied,
CE
CE
OE
OE
then data access must be measured from the later occurring signal (
or
) and the limiting parameter
OE
CE
is either tCO for
or tOE for
rather than address access.
OE
CE
WRITE MODE
The DS1245 executes a write cycle whenever the
inputs are stable. The later occurring falling edge of
and
signals are active (low) after address
CE
will determine the start of the write cycle.
WE
CE
or
WE
The write cycle is terminated by the earlier rising edge of
valid throughout the write cycle.
or
. All address inputs must be kept
WE
CE
must return to the high state for a minimum recovery time (tWR
)
WE
before another cycle can be initiated. The
control signal should be kept inactive (high) during write
OE
cycles to avoid bus contention. However, if the output drivers are enabled (
will disable the outputs in tODW from its falling edge.
and
active) then
OE WE
CE
DATA RETENTION MODE
The DS1245AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1245Y provides full functional capability for VCC greater than 4.5 volts and write-
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write-protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1245AB and 4.5 volts for the
DS1245Y.
FRESHNESS SEAL
Each DS1245 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When VCC is first applied at a level greater than 4.25 volts, the lithium energy source
is enabled for battery back-up operation.
2 of 10
DS1245Y/AB
PACKAGES
The DS1245 devices are available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM).
The 32-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a
single package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates
SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the
DS9034PC PowerCap. The PowerCap Module package design allows a DS1245 PCM device to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1245 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the
PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1245 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped
in separate containers. See the DS9034PC data sheet for further information.
3 of 10
DS1245Y/AB
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground
Operating Temperature Range
Commercial:
-0.3V to +6.0V
0°C to +70°C
Industrial:
-40°C to +85°C
Storage Temperature Range
EDIP
PowerCap
Lead Temperature (soldering, 10s)
Soldering Temperature (reflow, PowerCap)
Note: EDIP is wave or hand soldered only.
-40°C to +85°C
-55°C to +125°C
+260°C
+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
5.0
MAX
5.25
5.5
UNITS NOTES
DS1245AB Power Supply Voltage
DS1245Y Power Supply Voltage
Logic 1
VCC
VCC
VIH
VIL
4.75
4.5
2.2
0.0
V
V
V
V
5.0
VCC
0.8
Logic 0
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±5% for DS1245AB)
(TA: See Note 10) (VCC = 5V ±10% for DS1245Y)
PARAMETER
SYMBOL MIN
TYP
MAX
+1.0
UNITS NOTES
Input Leakage Current
IIL
IIO
-1.0
-1.0
-1.0
2.0
µA
µA
mA
mA
µA
µA
mA
V
+1.0
I/O Leakage Current
≥ VIH ≤ VCC
CE
Output Current @ 2.4V
Output Current @ 0.4V
IOH
IOL
ICCS1
ICCS2
ICCO1
VTP
VTP
200
50
600
150
85
Standby Current
Standby Current
=2.2V
CE
CE
=V -0.5V
CC
Operating Current
Write Protection Voltage (DS1245AB)
Write Protection Voltage (DS1245Y)
4.50
4.25
4.62
4.37
4.75
4.5
V
CAPACITANCE
PARAMETER
(TA = +25°C)
UNITS NOTES
SYMBOL MIN
TYP
MAX
10
Input Capacitance
CIN
5
5
pF
pF
Input/Output Capacitance
CI/O
10
4 of 10
DS1245Y/AB
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±5% for DS1245AB)
(TA: See Note 10) (VCC = 5V ±10% for DS1245Y)
DS1245AB-70
DS1245Y-70
PARAMETER
SYMBOL
UNITS
NOTES
MIN
MAX
Read Cycle Time
Access Time
tRC
tACC
tOE
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
35
70
to Output Valid
to Output Valid
OE
CE
OE
tCO
tCOE
tOD
tOH
tWC
tWP
tAW
5
5
5
or
to Output Active
CE
Output High Z from Deselection
Output Hold from Address Change
Write Cycle Time
25
5
70
55
0
Write Pulse Width
3
Address Setup Time
tWR1
tWR2
ns
ns
12
13
5
Write Recovery Time
15
tODW
tOEW
tDS
25
ns
ns
ns
5
5
4
Output High Z from
Output Active from
Data Setup Time
WE
WE
5
30
0
tDH1
tDH2
ns
ns
12
13
Data Hold Time
10
5 of 10
DS1245Y/AB
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8, and 12
6 of 10
DS1245Y/AB
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8, and 13
POWER-DOWN/POWER-UP CONDITION
7 of 10
DS1245Y/AB
POWER-DOWN/POWER-UP TIMING
(TA: See Note 10)
PARAMETER
SYMBOL MIN
tPD
tF
TYP
MAX
UNITS NOTES
1.5
11
µs
µs
µs
ms
ms
VCC Fail Detect to
and
Inactive
WE
CE
VCC slew from VTP to 0V
VCC slew from 0V to VTP
150
150
tR
tPU
tREC
2
VCC Valid to
and
Inactive
WE
CE
VCC Valid to End of Write Protection
125
(TA = +25°C)
UNITS NOTES
PARAMETER
SYMBOL MIN
tDR 10
TYP
MAX
Expected Data Retention Time
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
is high for a Read Cycle.
WE
2.
= VIH or VIL. If
= VIH during write cycle, the output buffers remain in a high impedance state.
OE
OE
3. tWP is specified as the logical AND of
and
. t is measured from the latter of
or
CE WE
CE
WE
WP
going low to the earlier of
or
going high.
WE
CE
4. tDH, tDS are measured from the earlier of
or
going high.
WE
CE
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the low transition occurs simultaneously with or latter than the
low transition, the output
high transition, the output
CE
WE
WE
buffers remain in a high impedance state during this period.
7. If the high transition occurs prior to or simultaneously with the
CE
buffers remain in high impedance state during this period.
8. If is low or the low transition occurs prior to or simultaneously with the low transition,
CE
WE
WE
the output buffers remain in a high impedance state during this period.
9. Each DS1245 has a built-in switch that disconnects the lithium source until the user first applies VCC.
The expected tDR is defined as accumulative time in the absence of VCC starting from the time power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
10. Each DS1245 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time
power is first applied by the user.
11. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
12. In a power-down condition the voltage on any pin may not exceed the voltage on VCC.
8 of 10
DS1245Y/AB
13. tWR1 and tDH1 are measured from
14. tWR2 and tDH2 are measured from
going high.
going high.
WE
CE
15. DS1245 modules are recognized by Underwriters Laboratories (UL) under file E99151.
DC TEST CONDITIONS
Outputs Open
Cycle = 200 ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
ORDERING INFORMATION
SUPPLY
TOLERANCE
5V ± 5%
SPEED GRADE
PART
TEMP RANGE
PIN-PACKAGE
(ns)
70
70
70
70
70
70
70
70
DS1245AB-70+
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
32 740 EDIP
34 PowerCap*
32 740 EDIP
34 PowerCap*
32 740 EDIP
34 PowerCap*
32 740 EDIP
34 PowerCap*
DS1245ABP-70+
DS1245AB-70IND+
DS1245ABP-70IND+
DS1245Y-70+
5V ± 5%
5V ± 5%
5V ± 5%
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
DS1245YP-70+
DS1245Y-70IND+
DS1245YP-70IND+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PC+ or DS9034PCI+ (PowerCap) required. Must be ordered separately.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0245
LAND PATTERN NO.
—
32 EDIP
MDT32+6
—
34 PCAP
PC2+3
21-0246
9 of 10
DS1245Y/AB
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Added Package Information table; removed the DIP module package
drawing and dimension table
121907
10, 11, 12
Updated the storage information, soldering temperature, and lead
temperature information in the Absolute Maximum Ratings section;
removed the -85, -100, and -120 MIN/MAX information from the AC
Electrical Characteristics table; updated the Ordering Information
table (removed -85, -100, and -120 parts and leaded -70 parts);
removed the PowerCap module drawings and updated the Package
Information table
11/10
1, 4, 5, 9
10 of 10
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