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DS1258W-150 [MAXIM]

3.3V 128k x 16 Nonvolatile SRAM;
DS1258W-150
型号： DS1258W-150
厂家： MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述：

3.3V 128k x 16 Nonvolatile SRAM

静态存储器 内存集成电路
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DS1258W  
3.3V 128k x 16 Nonvolatile  
SRAM  
www.maxim-ic.com  
FEATURES  
PIN ASSIGNMENT  
Cꢀ10-Year Minimum Data Retention in the  
Absence of External Power  
CEU  
1
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
VCC  
WE  
2
3
4
5
6
7
8
9
10  
11  
CEL  
DQ15  
DQ14  
DQ13  
DQ12  
DQ11  
DQ10  
DQ9  
A16  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
CꢀData is Automatically Protected During a  
Power Loss  
CꢀSeparate Upper Byte and Lower Byte Chip  
Select Inputs  
CꢀUnlimited Write Cycles  
CꢀLow-Power CMOS  
DQ8  
GND  
GND  
CꢀRead and Write Access Times as Fast as  
100ns  
12  
13  
14  
15  
16  
17  
18  
19  
20  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
DQ2  
DQ1  
DQ0  
OE  
CꢀLithium Energy Source is Electrically  
Disconnected to Retain Freshness Until  
Power is Applied for the First Time  
CꢀOptional Industrial Temperature Range of  
-40LC to +85LC, Designated IND  
40-Pin Encapsulated Package  
740mil Extended  
PIN DESCRIPTION  
A0 - A16  
DQ0 - DQ15  
CEU  
CEL  
WE  
- Address Inputs  
- Data In/Data Out  
- Chip Enable Upper Byte  
- Chip Enable Lower Byte  
- Write Enable  
OE  
- Output Enable  
VCC  
- Power (+3.3V)  
- Ground  
GND  
DESCRIPTION  
The DS1258W 3.3V 128k x 16 Nonvolatile SRAM is a 2,097,152-bit, fully static, nonvolatile (NV)  
SRAM, organized as 131,072 words by 16 bits. Each NV SRAM has a self-contained lithium energy  
source and control circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such  
a condition occurs, the lithium energy source is automatically switched on and write protection is  
unconditionally enabled to prevent data corruption. DIP-package DS1258W devices can be used in place  
of solutions which build nonvolatile 128k x 16 memory by utilizing a variety of discrete components.  
There is no limit on the number of write cycles that can be executed and no additional support circuitry is  
required for microprocessor interfacing.  
1 of 9  
083006  
DS1258W  
READ MODE  
The DS1258W executes a read cycle whenever WE (Write Enable) is inactive (high) and either/both of  
CEU or CEL (Chip Enables) are active (low) and OE (Output Enable)is active (low). The unique address  
specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is accessed. The  
status of CEU and CEL determines whether all or part of the addressed word is accessed. If CEU is active  
with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is inactive with  
CEL active, then only the lower byte of the addressed word is accessed. If both the CEU and CEL inputs  
are active (low), then the entire 16-bit word is accessed. Valid data will be available to the 16 data output  
drivers within tACC (Access Time) after the last address input signal is stable, providing that CEU , CEL  
and OE access times are also satisfied. If CEU , CEL , and OE access times are not satisfied, then data  
access must be measured from the later-occurring signal, and the limiting parameter is either tCO for CEU ,  
CEL , or tOE for OE rather than address access.  
WRITE MODE  
The DS1258W executes a write cycle whenever WE and either/both of CEU or CEL are active (low)  
after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines  
which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or  
part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of  
the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the  
addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word  
is accessed. The write cycle is terminated by the earlier rising edge of CEU and/or CEL , or WE . All  
address inputs must be kept valid throughout the write cycle. WE must return to the high state for a  
minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept  
inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled  
(CEU and/or CEL , and OE active) then WE will disable the outputs in tODW from its falling edge.  
READ/WRITE FUNCTION Table 1  
VCC  
CYCLE  
OE  
H
L
L
L
X
X
X
X
WE  
H
H
H
H
L
CEL  
X
L
L
H
L
CEU  
X
L
H
L
CURRENT  
DQ0-DQ7  
High-Z  
Output  
Output  
High-Z  
Input  
Input  
High-Z  
High-Z  
DQ8-DQ15 PERFORMED  
ICCO  
High-Z  
Output  
High-Z  
Output  
Input  
High-Z  
Input  
High-Z  
Output Disabled  
ICCO  
Read Cycle  
L
ICCO  
ICCS  
Write Cycle  
L
L
X
L
H
H
H
L
H
Output Disabled  
DATA RETENTION MODE  
The DS1258W provides full functional capability for VCC greater than 3.0V, and write-protects by 2.8V.  
Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static  
RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write-  
protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls  
below approximately 2.5V, a power-switching circuit connects the lithium energy source to RAM to  
retain data. During power-up, when VCC rises above approximately 2.5V, the power switching circuit  
2 of 9  
DS1258W  
connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can  
resume after VCC exceeds 3.0V.  
FRESHNESS SEAL  
Each DS1258W device is shipped from Dallas Semiconductor with its lithium energy source  
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than 3.0V,  
the lithium energy source is enabled for battery backup operation.  
3 of 9  
DS1258W  
ABSOLUTE MAXIMUM RATINGS*  
Voltage on Any Pin Relative to Ground  
Operating Temperature Range  
Storage Temperature Range  
-0.3V to +4.6V  
0°C to 70°C, -40LC to +85LC for Industrial Parts  
-40°C to +70°C, -40LC to +85LC for Industrial Parts  
+260°C for 10 seconds  
Soldering Temperature  
Caution: Do Not Reflow  
(Wave or Hand Solder Only)  
* This is a stress rating only and functional operation of the device at these or any other conditions above  
those indicated in the operation sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods of time may affect reliability.  
RECOMMENDED DC OPERATING CONDITIONS  
(tA: See Note 10)  
PARAMETER  
Power Supply Voltage  
SYMBOL MIN  
TYP  
3.3  
MAX  
3.6  
VCC  
0.4  
UNITS NOTES  
VCC  
VIH  
VIL  
3.0  
2.2  
0.0  
V
V
V
Logic 1  
Logic 0  
DC ELECTRICAL CHARACTERISTICS  
(tA: See Note 10) (VCC = 3.3V Mꢀ0.3V)  
PARAMETER  
Input Leakage Current  
SYMBOL MIN  
TYP  
MAX  
+2.0  
UNITS NOTES  
IIL  
-2.0  
-1.0  
-1.0  
2.0  
ꢀA  
ꢀA  
mA  
mA  
ꢀA  
ꢀA  
mA  
V
IIO  
IOH  
+1.0  
I/O Leakage Current CE O VIH ? VCC  
Output Current @ 2.2V  
Output Current @ 0.4V  
IOL  
ICCS1  
ICCS2  
ICCO1  
VTP  
100  
60  
450  
250  
100  
3.0  
Standby Current CEU , CEL =2.2V  
Standby Current CEU , CEL =VCC-0.2V  
Operating Current  
Write Protection Voltage  
2.8  
2.9  
CAPACITANCE  
PARAMETER  
Input Capacitance  
(tA = +25LC)  
SYMBOL MIN  
TYP  
20  
5
MAX  
25  
10  
UNITS NOTES  
CIN  
CI/O  
pF  
pF  
Input/Output Capacitance  
4 of 9  
DS1258W  
DC ELECTRICAL CHARACTERISTICS  
(tA: See Note 10) (VCC = 3.3V Mꢀ0.3V)  
DS1258W-100 DS1258W-150  
MIN  
PARAMETER  
SYMBOL  
UNITS NOTES  
MAX MIN MAX  
Read Cycle Time  
Access Time  
OE to Output Valid  
CE to Output Valid  
OE or CE to Output Valid  
Output High-Z from Deselection  
tRC  
tACC  
tOE  
tCO  
tCOE  
100  
150  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
100  
50  
100  
150  
70  
150  
5
5
5
5
5
5
tOD  
tOH  
35  
35  
35  
35  
Output Hold from Address  
Change  
Write Cycle Time  
Write Pulse Width  
Address Setup Time  
Write Recovery Time  
tWC  
tWP  
tAW  
100  
75  
0
150  
100  
0
ns  
ns  
ns  
3
tWR1  
5
5
ns  
12  
13  
5
5
4
tWR2  
20  
20  
ns  
tODW  
tOEW  
tDS  
ns  
ns  
ns  
Output High Z from WE  
Output Active from WE  
Data Setup Time  
5
40  
5
60  
Data Hold Time  
tDH1  
0
0
ns  
12  
tDH2  
20  
20  
ns  
13  
READ CYCLE  
SEE NOTE 1  
5 of 9  
DS1258W  
WRITE CYCLE 1  
SEE NOTE 2, 3, 4, 6, 7, 8 AND 12  
WRITE CYCLE 2  
6 of 9  
DS1258W  
POWER-DOWN/POWER-UP CONDITION  
POWER-DOWN/POWER-UP TIMING  
(tA: See Note 10)  
PARAMETER  
VCC Fail Detect to CE and WE Inactive  
VCC slew from VTP to 0V  
SYMBOL MIN  
TYP  
TYP  
MAX  
1.5  
UNITS NOTES  
tPD  
tF  
11  
ꢀs  
ꢀs  
150  
150  
VCC slew from 0V to VTP  
tR  
ꢀs  
ms  
ms  
tPU  
tREC  
2
125  
VCC Valid to CE and WE Inactive  
VCC Valid to End of Write Protection  
(tA = +25LC)  
PARAMETER  
Expected Data Retention Time  
SYMBOL MIN  
tDR 10  
MAX  
UNITS NOTES  
years  
9
WARNING:  
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery  
backup mode.  
7 of 9  
DS1258W  
NOTES:  
1) WE is high for a Read Cycle.  
2) OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.  
3) tWP is specified as the logical AND of CEU or CEL and WE . tWP is measured from the latter of CEU ,  
CEL or WE going low to the earlier of CEU , CEL or WE going high.  
4) tDS is measured from the earlier of CEU or CEL or WE going high.  
5) These parameters are sampled with a 5pF load and are not 100% tested.  
6) If the CEU or CEL low transition occurs simultaneously with or later than the WE low transition in  
the output buffers remain in a high impedance state during this period.  
7) If the CEU or CEL high transition occurs prior to or simultaneously with the WE high transition, the  
output buffers remain in high impedance state during this period.  
8) If WE is low or the WE low transition occurs prior to or simultaneously with the CEU or CEL low  
transition, the output buffers remain in a high impedance state during this period.  
9) Each DS1258W has a built-in switch that disconnects the lithium source until VCC is first applied by  
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the  
time power is first applied by the user.  
10) All AC and DC electrical characteristics are valid over the full operating temperature range. For  
commercial products, this range is 0 to +70LC. For industrial products, this range is -40LC to +85LC.  
11) In a power-down condition the voltage on any pin may not exceed the voltage on VCC.  
12) tWR1, tDH1 are measured from WE going high.  
13) tWR2, tDH2 are measured from CEU OR CEL going high.  
14) DS1258W DIP modules are recognized by Underwriters Laboratory (U.L.®) under file E99151.  
DC TEST CONDITIONS  
Outputs Open  
AC TEST CONDITIONS  
Output Load: 100pF + 1TTL Gate  
Input Pulse Levels:  
Cycle = 200ns  
All voltages are referenced to ground  
0.0V to 2.7V  
Timing Measurement Reference Levels  
Input: 1.5V  
Output: 1.5V  
Input pulse Rise and Fall Times: 5ns  
ORDERING INFORMATION  
Supply  
Part Number  
DS1258W-100  
Temperature Range  
Pin/Package  
Speed Grade  
Tolerance  
0°C to +70°C  
0°C to +70°C  
-40°C to +85°C  
-40°C to +85°C  
0°C to +70°C  
0°C to +70°C  
40 / 740 EMOD  
40 / 740 EMOD  
40 / 740 EMOD  
40 / 740 EMOD  
40 / 740 EMOD  
40 / 740 EMOD  
100ns  
100ns  
100ns  
100ns  
150ns  
150ns  
3.3V M 0.3V  
3.3V M 0.3V  
3.3V M 0.3V  
3.3V M 0.3V  
3.3V M 0.3V  
3.3V M 0.3V  
DS1258W-100#  
DS1258W-100IND  
DS1258W-100IND#  
DS1258W-150  
DS1258W-150#  
# Denotes RoHS-compliant product.  
* DS9034PC or DS9034PCI (PowerCap) required. Must be ordered separately.  
8 of 9  
DS1258W NONVOLATILE SRAM 40-PIN, 740-MIL EXTENDED MODULEDS1258W  
PKG  
DIM  
40-PIN  
MIN  
MAX  
A IN.  
MM  
2.080  
52.83  
2.100  
53.34  
B IN.  
MM  
0.715  
18.16  
0.740  
18.80  
C IN.  
MM  
0.345  
8.76  
0.365  
9.27  
D IN.  
MM  
0.085  
2.16  
0.115  
2.92  
E IN.  
MM  
0.015  
0.38  
0.030  
0.76  
F IN.  
MM  
0.120  
3.05  
0.160  
4.06  
G IN.  
MM  
0.090  
2.29  
0.110  
2.79  
H IN.  
MM  
0.590  
14.99  
0.630  
16.00  
J IN.  
MM  
0.008  
0.20  
0.012  
0.30  
K IN.  
MM  
0.015  
0.43  
0.025  
0.58  
9 of 9  

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