DS1258Y-70IND [MAXIM]

128k x 16 Nonvolatile SRAM;


型号：	DS1258Y-70IND
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	128k x 16 Nonvolatile SRAM 静态存储器内存集成电路
文件：	总8页 (文件大小：207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS1258Y/AB

128k x 16 Nonvolatile SRAM

www.maxim-ic.com

FEATURES

PIN ASSIGNMENT

Cꢀ10-Year Minimum Data Retention in the

Absence of External Power

CEU

CEL

V_CC

A16

A15

A14

A13

A12

A11

A10

CꢀData is Automatically Protected During a

Power Loss

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

CꢀSeparate Upper Byte and Lower Byte Chip-

Select Inputs

CꢀUnlimited Write Cycles

CꢀLow-Power CMOS

DQ8

GND

CꢀRead and Write Access Times as Fast as 70ns

CꢀLithium Energy Source is Electrically

Disconnected to Retain Freshness Until

Power is Applied for the First Time

CꢀFull M10% Operating Range (DS1258Y)

CꢀOptional M5% Operating Range (DS1258AB)

CꢀOptional Industrial Temperature Range of

-40LC to +85LC, Designated IND

GND

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

40-Pin Encapsulated Package

740mil Extended

PIN DESCRIPTION

A0 to A16

DQ0 to DQ15

CEU

CEL

- Address Inputs

- Data In/Data Out

- Chip Enable Upper Byte

- Chip Enable Lower Byte

- Write Enable

- Output Enable

V_CC

- Power (+5V)

GND

- Ground

DESCRIPTION

The DS1258 128k x 16 nonvolatile (NV) SRAMs are 2,097,152-bit fully static, NV SRAMs, organized as

131,072 words by 16 bits. Each NV SRAM has a self-contained lithium energy source and control

circuitry that constantly monitors V_CCfor an out-of-tolerance condition. When such a condition occurs,

the lithium energy source is automatically switched on and write protection is unconditionally enabled to

prevent data corruption. DIP-package DS1258 devices can be used in place of solutions that build NV

128k x 16 memory by utilizing a variety of discrete components. There is no limit on the number of write

cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.

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083006

DS1258Y/AB

READ MODE

The DS1258 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and either/both

of CEU or CEL (Chip Enables) are active (low) and OE (Output Enable) is active (low). The unique

address specified by the 17 address inputs (A0-A16) defines which of the 131,072 words of data is

accessed. The status of CEU and CEL determines whether all or part of the addressed word is accessed. If

CEU is active with CEL inactive, then only the upper byte of the addressed word is accessed. If CEU is

inactive with CEL active, then only the lower byte of the addressed word is accessed. If both the CEU

and CEL inputs are active (low), then the entire 16-bit word is accessed. Valid data will be available to

the 16 data output drivers within t_ACC(Access Time) after the last address input signal is stable, providing

that CEU , CEL and OE access times are also satisfied. If CEU , CEL , and OE access times are not

satisfied, then data access must be measured from the later occurring signal, and the limiting parameter is

either t_COfor CEU , CEL , or t_OEfor OE rather than address access.

WRITE MODE

The DS1258 devices execute a write cycle whenever WE and either/both of CEU or CEL are active (low)

after address inputs are stable. The unique address specified by the 17 address inputs (A0-A16) defines

which of the 131,072 words of data is accessed. The status of CEU and CEL determines whether all or

part of the addressed word is accessed. If CEU is active with CEL inactive, then only the upper byte of

the addressed word is accessed. If CEU is inactive with CEL active, then only the lower byte of the

addressed word is accessed. If both the CEU and CEL inputs are active (low), then the entire 16-bit word

is accessed. The write cycle is terminated by the earlier rising edge of CEU and/or CEL , or WE . All

address inputs must be kept valid throughout the write cycle. WE must return to the high state for a

minimum recovery time (t_WR) before another cycle can be initiated. The OE control signal should be kept

inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled

(CEU and/or CEL , and OE active) then WE will disable the outputs in t_ODWfrom its falling edge.

READ/WRITE FUNCTION Table 1

V_CC

CYCLE

CEL

CEU

CURRENT

DQ0-DQ7

High-Z

Output

High-Z

Input

High-Z

DQ8-DQ15 PERFORMED

I_CCO

High-Z

Output

High-Z

Output

Input

High-Z

Input

High-Z

Output Disabled

I_CCO

Read Cycle

I_CCO

I_CCS

Write Cycle

Output Disabled

DATA RETENTION MODE

The DS1258AB provides full functional capability for V_CCgreater than 4.75V, and write protects by

4.5V. The DS1258Y provides full functional capability for V_CCgreater than 4.5V and write protects by

4.25V. Data is maintained in the absence of V_CCwithout any additional support circuitry. The NV static

RAMs constantly monitor V_CC. Should the supply voltage decay, the NV SRAMs automatically write

protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As V_CCfalls

below approximately 3.0V, a power switching circuit connects the lithium energy source to RAM to

2 of 8

DS1258Y/AB

retain data. During power-up, when V_CCrises above approximately 3.0V, the power switching circuit

connects external V_CCto RAM and disconnects the lithium energy source. Normal RAM operation can

resume after V_CCexceeds 4.75V for the DS1258AB and 4.5V for the DS1258Y.

FRESHNESS SEAL

The DS1258 devices are shipped from Dallas Semiconductor with the lithium energy sources

disconnected, guaranteeing full energy capacity. When V_CCis first applied at a level greater than V_TP, the

lithium energy source is enabled for battery backup operation.

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground

Operating Temperature Range

Storage Temperature Range

Soldering Temperature

-0.3V to +6.0V

0°C to +70°C, -40LC to +85LC for Industrial Parts

-40°C to +70°C, -40LC to +85LC for Industrial Parts

+260°C for 10 seconds

Caution: Do Not Reflow

(Wave or Hand Solder Only)

* This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

(t_A: See Note 10)

PARAMETER

DS1258AB Power Supply Voltage

DS1258Y Power Supply Voltage

Logic 1

SYMBOL MIN

TYP

5.0

MAX

5.25

5.5

V_CC

+0.8

UNITS NOTES

V_CC

V_IH

V_IL

4.75

4.5

2.2

0.0

Logic 0

DC ELECTRICAL

CHARACTERISTICS

PARAMETER

(V_CC= 5V Mꢀ5% for DS1258AB)

(t_A: See Note 10) (V_CC= 5V Mꢀ10% for DS1258Y)

SYMBOL MIN

TYP

MAX

UNITS NOTES

Input Leakage Current

I_IL

-2.0

+2.0

ꢀA

I/O Leakage Current CEU = CEL O V_IH

? V_CC

I_IO

-1.0

+1.0

ꢀA

Output Current @ 2.4V

Output Current @ 0.4V

I_OH

I_OL

I_CCS1

I_CCS2

I_CCO1

V_TP

-1.0

2.0

0.7

150

1.5

300

170

4.75

4.5

Standby Current CEU , CEL =2.2V

Standby Current CEU , CEL =V_CC- 0.5V

Operating Current

Write Protection Voltage (DS1258AB)

Write Protection Voltage (DS1258Y)

ꢀA

4.50

4.25

4.62

4.37

V_TP

3 of 8

DS1258Y/AB

(t_A= +25LC)

UNITS NOTES

CAPACITANCE

PARAMETER

SYMBOL MIN

TYP

MAX

Input Capacitance

C_IN

Input/Output Capacitance

C_I/O

AC ELECTRICAL

(V_CC= 5V Mꢀ5% for DS1258AB)

CHARACTERISTICS

(t_A: See Note 10) (V_CC= 5V Mꢀ10% for DS1258Y)

DS1258AB-70 DS1258AB-100

DS1258Y-70

DS1258Y-100

PARAMETER

Read Cycle Time

Access Time

SYMBOL

t_RC

UNITS NOTES

MIN MAX MIN MAX

100

t_ACC

t_OE

t_CO

t_COE

t_OD

t_OH

t_WC

t_WP

t_AW

100

OE to Output Valid

CEU or CEL to Output Valid

OE or CEU or CEL to Output Valid

Output High Z from Deselection

Output Hold from Address Change

Write Cycle Time

Write Pulse Width

Address Setup Time

Write Recovery Time

100

t_WR1

t_WR2

t_ODW

t_OEW

t_DS

Output High Z from WE

Output Active from WE

Data Setup Time

Data Hold Time

t_DH1

t_DH2

READ CYCLE

SEE NOTE 1

4 of 8

DS1258Y/AB

WRITE CYCLE 1

SEE NOTE 2, 3, 4, 6, 7, 8 AND 12

WRITE CYCLE 2

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DS1258Y/AB

POWER-DOWN/POWER-UP CONDITION

POWER-DOWN/POWER-UP TIMING

(t_A: See Note 10)

PARAMETER

CEU , CEL at V_IHbefore Power-Down

V_CCslew from V_TPto 0V

SYMBOL MIN

TYP

MAX

UNITS NOTES

t_PD

t_F

ꢀs

300

V_CCslew from 0V to V_TP

t_R

t_REC

125

CEU , CEL at V_IHafter Power-Up

(t_A=+25LC)

PARAMETER

Expected Data Retention Time

SYMBOL MIN

t_DR10

MAX

UNITS NOTES

years

WARNING:

Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery

backup mode.

NOTES:

1) WE is high for a Read Cycle.

2) OE = V_IHor V_IL. If OE = V_IHduring write cycle, the output buffers remain in a high impedance state.

3) t_WPis specified as the logical AND of CEU or CEL and WE . t_WPis measured from the latter of CEU ,

CEL or WE going low to the earlier of CEU , CEL or WE going high.

4) t_DSis measured from the earlier of CEU or CEL or WE going high.

5) These parameters are sampled with a 5pF load and are not 100% tested.

6) If the CEU or CEL low transition occurs simultaneously with or later than the WE low transition in

the output buffers remain in a high impedance state during this period.

7) If the CEU or CEL high transition occurs prior to or simultaneously with the WE high transition, the

output buffers remain in high impedance state during this period.

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DS1258Y/AB

8) If WE is low or the WE low transition occurs prior to or simultaneously with the CEU or CEL low

transition, the output buffers remain in a high impedance state during this period.

9) Each DS1258 has a built-in switch that disconnects the lithium source until the user first applies V_CC.

The expected t_DRis defined as accumulative time in the absence of V_CCstarting from the time power

is first applied by the user. This parameter is assured by component selection, process control, and

design. It is not measured directly during production testing.

10) All AC and DC electrical characteristics are valid over the full operating temperature range. For

commercial products, this range is 0LC to +70LC. For industrial products, this range is -40LC to

+85LC.

11) In a power-down condition the voltage on any pin may not exceed the voltage on V_CC.

12) t_WR1, t_DH1are measured from WE going high.

13) t_WR2, t_DH2are measured from CEU OR CEL going high.

14) DS1258 DIP modules are recognized by Underwriters Laboratory (U.L.^®) under file E99151.

DC TEST CONDITIONS

Outputs Open

AC TEST CONDITIONS

Output Load: 100 pF + 1TTL Gate

Input Pulse Levels:

Cycle = 200ns

All voltages are referenced to ground

0.0V to 3.0V

Timing Measurement Reference Levels

Input: 1.5V

Output: 1.5V

Input pulse Rise and Fall Times: 5ns

ORDERING INFORMATION

Supply

Tolerance

5V M 5%

5V M 10%

Part Number

DS1258AB-70

Temperature Range

Pin/Package

Speed Grade

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

40 / 740 EMOD

70ns

100ns

70ns

100ns

DS1258AB-70#

DS1258AB-70IND

DS1258AB-70IND#

DS1258AB-100

DS1258AB-100#

DS1258Y-70

DS1258Y-70#

DS1258Y-70IND

DS1258Y-70IND#

DS1258Y-100

DS1258Y-100#

# Denotes RoHS-compliant product.

* DS9034PC or DS9034PCI (PowerCap) required. Must be ordered separately.

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DS1258Y/AB

DS1258Y/AB NONVOLATILE SRAM 40-PIN, 740-MIL EXTENDED MODULE

PKG

DIM

40-PIN

MIN

MAX

A IN.

2.080

52.83

2.100

53.34

B IN.

0.715

18.16

0.740

18.80

C IN.

0.345

8.76

0.365

9.27

D IN.

0.085

2.16

0.115

2.92

E IN.

0.015

0.38

0.030

0.76

F IN.

0.120

3.05

0.160

4.06

G IN.

0.090

2.29

0.110

2.79

H IN.

0.590

14.99

0.630

16.00

J IN.

0.008

0.20

0.012

0.30

K IN.

0.015

0.43

0.025

0.58

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DS1258Y-70IND [MAXIM]

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