DS1312 [MAXIM]

Nonvolatile Controller with Lithium Battery Monitor;


型号：	DS1312
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Nonvolatile Controller with Lithium Battery Monitor 电池光电二极管
文件：	总12页 (文件大小：507K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

19-6306; Rev 6/12

DS1312

Nonvolatile Controller with Lithium Battery Monitor

FEATURES

PIN ASSIGNMENT

. Converts CMOS SRAM into nonvolatile

memory

V_CCO

V_BAT

TOL

GND

V_CCI

V_CCO

V_BAT

TOL

GND

V_CCI

. Unconditionally write-protects SRAM when

V_CCis out of tolerance

CEO

CEI

CEO

CEI

. Automatically switches to battery backup

supply when V_CCpower failure occurs

. Monitors voltage of a lithium cell and

provides advanced warning of impending

battery failure

DS1312 8-Pin DIP

(300 mils)

DS1312S-2 8-Pin SOIC

(150 mils)

V_CCO

V_CCI

RST

V_CCI

RST

. Signals low-battery condition on active low

Battery Warning output signal

V_BAT

CEO

. Optional 5% or 10% power-fail detection

. Space-saving 8-pin DIP and SOIC packages

. Optional 16-pin SOIC and 20-pin TSSOP

versions reset processor when power failure

occurs and hold processor in reset during

system power-up

TOL

CEO

GND

CEI

DS1312S 16-Pin SOIC

(300 mils)

GND

CEI

DS1312E 20-Pin TSSOP

. Industrial temperature range of -40°C to

+85°C

PIN DESCRIPTION

V_CCI

V_CCO

V_BAT

- +5V Power Supply Input

- SRAM Power Supply Output

- Backup Battery Input

CEI

- Chip Enable Input

CEO

- Chip Enable Output

- V_CCTolerance Select

TOL

- Battery Warning Output

(Open Drain)

RST

GND

- Reset Output (Open Drain)

- Ground

- No Connection

DESCRIPTION

The DS1312 Nonvolatile Controller with Battery Monitor is a CMOS circuit which solves the application

problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-

of-tolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write

protection and the battery is switched on to supply the RAM with uninterrupted power. Special circuitry

uses a low-leakage CMOS process which affords precise voltage detection at extremely low battery

consumption.

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DS1312

In addition to battery-backup support, the DS1312 performs the important function of monitoring the

remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life.

Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority

of its life, accurate battery monitoring requires loaded-battery voltage measurement. The DS1312

performs such measurement by periodically comparing the voltage of the battery as it supports an internal

resistive load with a carefully selected reference voltage. If the battery voltage falls below the reference

voltage under such conditions, the battery will soon reach end-of-life. As a result, the Battery Warning

pin is activated to signal the need for battery replacement.

MEMORY BACKUP

The DS1312 performs all the circuit functions required to provide battery-backup for an SRAM. First, the

device provides a switch to direct power from the battery or the system power supply (V_CCI). Whenever

V_CCIis less than the switch point V_SWand V_CCIis less than the battery voltage V_BAT, the battery is

switched in to provide backup power to the SRAM. This switch has voltage drop of less than 0.2 volts.

Second, the DS1312 handles power failure detection and SRAM write-protection. V_CCIis constantly

monitored, and when the supply goes out of tolerance, a precision comparator detects power failure and

inhibits chip enable output (CEO ) in order to write-protect the SRAM. This is accomplished by holding

CEO to within 0.2 volts of V_CCOwhen V_CCIis out of tolerance. If CEI is (active) low at the time that

power failure is detected, the CEO signal is kept low until CEI is brought high again. Once CEI is

brought high, CEO is taken high and held high until after V_CCIhas returned to its nominal voltage level. If

CEI is not brought high by 1.5 µs after power failure is detected, CEO is forced high at that time. This

specific scheme for delaying write protection for up to 1.5 µs guarantees that any memory access in

progress when power failure occurs will complete properly. Power failure detection occurs in the range

of 4.75 to 4.5 volts (5% tolerance) when the TOL pin is wired to GND or in the range of 4.5 to 4.25 volts

(10% tolerance) when TOL is connected to V_CCO

BATTERY VOLTAGE MONITORING

The DS1312 automatically performs periodic battery voltage monitoring at a factory-programmed time

interval of 24 hours. Such monitoring begins within t_RECafter V_CCIrises above V_CCTP, and is suspended

when power failure occurs.

After each 24-hour period (t_BTCN) has elapsed, the DS1312 connects V_BATto an internal 1.2 MΩ test

resistor (R_INT) for one second (t_BTPW). During this one second, if V_BATfalls below the factory-

programmed battery voltage trip point (V_BTP), the battery warning output BW is asserted. While BW is

active battery testing will be performed with period t_BTCWto detect battery removal and replacement.

Once asserted, BW remains active until the battery is physically removed and replaced by a fresh cell.

The battery is still retested after each V_CCpower-up, however, even if BW was active on power-down. If

the battery is found to be higher than V_BTPduring such testing, BW is deasserted and regular 24-hour

testing resumes. BW has an open-drain output driver.

Battery replacement following BW activation is normally done with V_CCInominal so that SRAM data is

not lost. During battery replacement, the minimum time duration between old battery detachment and

new battery attachment (t_BDBA) must be met or BW will not deactivate following attachment of the new

2 of 12

DS1312

battery. Should BW not deactivate for this reason, the new battery can be detached for t_BDBAand then re-

attached to clear BW .

NOTE: The DS1312 cannot constantly monitor an attached battery because such monitoring would

drastically reduce the life of the battery. As a result, the DS1312 only tests the battery for one second out

of every 24 hours and does not monitor the battery in any way between tests. If a good battery (one that

has not been previously flagged with BW ) is removed between battery tests, the DS1312 may not

immediately sense the removal and may not activate BW until the next scheduled battery test. If a battery

is then reattached to the DS1312, the battery may not be tested until the next scheduled test.

NOTE: Battery monitoring is only a useful technique when testing can be done regularly over the entire

life of a lithium battery. Because the DS1312 only performs battery monitoring when V_CCis nominal,

systems which are powered-down for excessively long periods can completely drain their lithium cells

without receiving any advanced warning. To prevent such an occurrence, systems using the DS1312

battery monitoring feature should be powered–up periodically (at least once every few months) in order

to perform battery testing. Furthermore, anytime BW is activated on the first battery test after a power-up,

data integrity should be checked via checksum or other technique.

POWER MONITORING

DS1312S and DS1312E varieties have an additional reset pin. These varieties detect out-of-tolerance

power supply conditions and warn a processor-based system of impending power failure. When V_CCIfalls

below the trip point level defined by the TOL pin (V_CCTP), the V_CCIcomparator activates the reset signal

RST . Reset occurs in the range of 4.75 to 4.5 volts (5% tolerance) when the TOL pin is connected to

GND or in the range of 4.5 to 4.25 volts (10% tolerance) when TOL is connected to V_CCO

RST also serves as a power-on reset during power-up. After V_CCIexceeds V_CCTP, RST will be held active

for 200 ms nominal (t_RPU). This reset period is sufficiently long to prevent system operation during

power-on transients and to allow t_RECto expire. RST has an open-drain output driver.

FRESHNESS SEAL MODE

When the battery is first attached to the DS1312 without V_CCpower applied, the device does not

immediately provide battery-backup power on V_CCO. Only after V_CCIexceeds V_CCTPwill the DS1312

leave Freshness Seal Mode. This mode allows a battery to be attached during manufacturing but not used

until after the system has been activated for the first time. As a result, no battery energy is drained during

storage and shipping.

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DS1312

FUNCTIONAL BLOCK DIAGRAM Figure 1

4 of 12

DS1312

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground

Operating Temperature Range

Storage Temperature Range

Soldering Temperature (reflow, SO or TSSOP)

Lead Temperature (soldering, 10s)

-0.5V to +6.0V

-40°C to +85°C

-55°C to +125°C

+260°C

+300°C

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the

operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of

time may affect reliability.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

PDIP

Junction-to-Ambient Thermal Resistance (θ_JA).…………………...………………………....110°C/W

Junction-to-Case Thermal Resistance (θ_JC)……………………………………………………40°C/W

8 SO

Junction-to-Ambient Thermal Resistance (θ_JA).……………………………………………...132°C/W

Junction-to-Case Thermal Resistance (θ_JC)……………………………………………………38°C/W

16 SO

Junction-to-Ambient Thermal Resistance (θ_JA).…………………...………………………......71°C/W

Junction-to-Case Thermal Resistance (θ_JC)……………………………………………………23°C/W

TSSOP

Junction-to-Ambient Thermal Resistance (θ_JA).……………………………………………..73.8°C/W

Junction-to-Case Thermal Resistance (θ_JC)……………………………………………………20°C/W

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board for the SMT packages. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-

tutorial.

Note 1:

RECOMMENDED OPERATING CONDITIONS

(-40°C to +85°C)

PARAMETER

SYMBOL

V_CCI

MIN

4.75

4.5

2.0

TYP

5.0

MAX

5.5

6.0

V_CCI+0.3

+0.8

UNITS NOTES

Supply Voltage TOL=GND

Supply Voltage TOL=VCCO

Battery Supply Voltage

Logic 1 Input

2, 13

V_CCI

V_BAT

V_IH

Logic 0 Input

V_IL

-0.3

DC ELECTRICAL CHARACTERISTICS

(-40°C to +85°C; V_CCI>V_CCTP)

PARAMETER

SYMBOL

I_CC1

MIN

TYP

200

MAX

400

100

UNITS NOTES

Operating Current (TTL inputs)

Operating Current (CMOS inputs)

RAM Supply Current

µA

3, 6

I_CC2

I_CCO1

140

(V_CCO≥ V_CCI-0.2V)

RAM Supply Current

I_CCO1

200

(V_CCO≥ V_CCI-0.3V)

V_CCTrip Point (TOL=GND)

V_CCTrip Point (TOL=V_CCO

V_BATTrip Point

V_CCTP

V_BTP

4.50

4.25

2.5

4.62

4.37

2.6

4.75

4.50

2.7

)

5 of 12

DS1312

8, 11

V_CC/V_BATSwitch Point

Output Current @ 2.4V

Output Current @ 0.4V

Input Leakage

Output Leakage

Battery Monitoring Test Load

V_SW

I_OH

I_OL

I_IL

I_LO

2.6

-1

2.7

1.2

2.8

µA

MΩ

-1.0

0.8

+1.0

1.5

R_INT

DC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; V_CCI< V_BAT; V_CCI< V_SW)

PARAMETER

Battery Current

Battery Backup Current

Supply Voltage

SYMBOL

I_BAT

MIN

TYP

MAX

100

500

UNITS NOTES

µA

I_CCO2

V_CCO

V_OHL

V_BAT-0.2

2, 9

CEO Output

CAPACITANCE

(T_A= +25°C)

UNITS NOTES

PARAMETER

SYMBOL

MIN

TYP

MAX

C_IN

Input Capacitance (CEI , TOL)

Output Capacitance

C_OUT

(CEO , BW , RST

)

AC ELECTRICAL CHARACTERISTICS

PARAMETER

(-40°C to +85°C; V_CCI> V_CCTP)

SYMBOL

TYP

MAX

UNITS NOTES

t_PD

µs

CEI to CEO Propagation Delay

t_CE

1.5

CE Pulse Width

V_CCValid to End of

Write Protection

t_REC

125

t_PU

350

V_CCValid to CEI Inactive

V_CCValid to RST Inactive

V_CCValid to BW Valid

t_RPU

t_BPU

150

200

AC ELECTRICAL CHARACTERISTICS

(-40°C to +85°C; V_CCI< V_CCTP)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

V_CCSlew Rate

t_F

t_RPD

150

µs

V_CCFail Detect to RST Active

V_CCSlew Rate

t_R

150

µs

AC ELECTRICAL CHARACTERISTICS

(-40°C to +85°C; V_CCI> V_CCTP)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

t_BW

Battery Test to BW Active

Battery Test Cycle-Normal

Battery Test Cycle-Warning

Battery Test Pulse Width

t_BTCN

t_BTCW

t_BTPW

t_BDBA

t_BABW

Battery Detach to Battery Attach

Battery Attach to BW Inactive

6 of 12

DS1312

TIMING DIAGRAM: POWER-UP

NOTE:

If V_BAT< V_SW, V_CCOwill begin to slew with V_CCIwhen V_CCI= V_BAT

7 of 12

DS1312

TIMING DIAGRAM: POWER-DOWN

NOTE:

If V_BAT< V_SW, V_CCOwill slew down with V_CCIuntil V_CCI= V_BAT

8 of 12

DS1312

TIMING DIAGRAM: BATTERY WARNING DETECTION

NOTE:

t_BWis measured from the expiration of the internal timer to the activation of the battery warning output

TIMING DIAGRAM: BATTERY REPLACEMENT

9 of 12

DS1312

NOTES:

2. All voltages referenced to ground.

3. Measured with outputs open circuited.

4. I_CCO1is the maximum average load which the DS1312 can supply to attached memories at V_CCO

V_CCI-0.2V.

5. I_CCO1is the maximum average load which the DS1312 can supply to attached memories at V_CCO

V_CCI-0.3V.

6. All inputs within 0.3V of ground or V_CCI

7. I_CCO2is the maximum average load current which the DS1312 can supply to the memories in the

battery backup mode.

8. Measured with a load as shown in Figure 2.

9. Chip Enable Output CEO can only sustain leakage current in the battery backup mode.

10. CEO will be held high for a time equal to t_RECafter V_CCIcrosses V_CCTPon power-up.

11. BW and RST are open-drain outputs and, as such, cannot source current. External pull-up resistors

should be connected to these pins for proper operation. Both BW and RST can sink 10 mA.

12. t_CEmaximum must be met to ensure data integrity on power-down.

13. In battery-backup mode, inputs must never be below ground or above V_CCO

14. The DS1312 is recognized by Underwriters Laboratories (UL) under file E99151.

DC TEST CONDITIONS

Outputs Open

All voltages are referenced to ground

AC TEST CONDITIONS

Output Load: See below

Input Pulse Levels: 0 - 3.0V

Timing Measurement Reference Levels

Input: 1.5V

Output: 1.5V

Input pulse Rise and Fall Times: 5 ns

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DS1312

OUTPUT LOAD Figure 2

ORDERING INFORMATION

TEMP

RANGE

PART

PIN-PACKAGE

DS1312+

-40°C to +85°C 8 PDIP

-40°C to +85°C 8 SO

-40°C to +85°C 16 SO

DS1312S-2+

DS1312S+

DS1312E+

-40°C to +85°C 20 TSSOP

+Denotes a lead(Pb)-free/RoHS-compliant package.

PACKAGE INFORMATION

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the

drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE

8 PDIP

PACKAGE CODE

P8+2

OUTLINE NO.

21-0043

LAND PATTERN NO.



8 SO

16 SO

20 TSSOP

S8+4

W16+1

U20+1

21-0041

21-0042

21-0066

90-0096

90-0107

90-0116

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DS1312

DATA SHEET REVISION SUMMARY

The following represent the key differences between 12/16/96 and 06/12/97 version of the DS1312 data

sheet. Please review this summary carefully.

1. Changed V_BATmax to 6V

2. Changed t_BABWfrom 75 to 1s max

3. Changed block diagram to show UL compliance

The following represent the key differences between 06/12/97 and 08/29/97 version of the DS1312 data

sheet. Please review this summary carefully.

1. Changed AC test conditions

The following represent the key differences between 08/29/97 and 12/16/97 version of the DS1312 data

sheet. Please review this summary carefully.

1. Specified Input Capacitance as being only for CEI , TOL and output capacitance as being only for

CEO BW and RST . This is not a change but rather a clarification.

2. Add note 13 describing UL recognition.

The following represent the key differences between 08/29/97 and 6/12 version of the DS1312 data sheet.

Please review this summary carefully.

1. Update soldering, ordering, package info, and notes.

12 of 12

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim

reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000

Maxim is a registered trademark of Maxim Integrated Products, Inc.

DS1312 [MAXIM]

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