DS1314S-2/T&R/C04 [MAXIM]
Power Management Circuit, CMOS, PDSO8;
| 型号： | DS1314S-2/T&R/C04 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Management Circuit, CMOS, PDSO8 光电二极管 |
| 文件： | 总11页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1314
3V Nonvolatile Controller with
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
CꢀConverts CMOS SRAM into nonvolatile
memory
VCCO
VBAT
TOL
GND
1
2
3
4
8
7
6
5
VCCI
BW
CEO
CEI
VCCO
VBAT
TOL
GND
1
2
3
4
8
7
6
5
VCCI
BW
CEO
CEI
CꢀUnconditionally write-protects SRAM when
VCC is out of tolerance
CꢀAutomatically switches to battery backup
supply when VCC power failure occurs
CꢀMonitors voltage of a lithium cell and
provides advanced warning of impending
battery failure
DS1314 8-Pin DIP
(300-mil)
DS1314S-2 8-Pin SOIC
(150-mil)
NC
VCCO
NC
VBAT
NC
NC
TOL
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
NC
NC
VCCO
NC
VBAT
NC
TOL
NC
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
VCCI
RST
NC
NC
BW
NC
CEO
NC
CEI
VCCI
RST
NC
BW
CEO
NC
CꢀSignals low-battery condition on active low
Battery Warning output signal
16
CꢀAutomatic VCC power-fail detection for 3.0V
or 3.3V power supplies
15
14
13
12
11
CꢀSpace-saving 8-pin DIP and SOIC packages
CꢀOptional 16-pin SOIC and 20-pin TSSOP
versions reset processor when power failure
occurs and hold processor in reset during
system power-up
CEI
NC
GND
DS1314S 16-Pin SOIC
(300-mil)
DS1314E 20-Pin TSSOP
PIN DESCRIPTION
CꢀIndustrial temperature range of -40°C to
+85°C
VCCI
VCCO
VBAT
- Power Supply Input
- SRAM Power Supply Output
- Backup Battery Input
CEI
- Chip Enable Input
CEO
TOL
- Chip Enable Output
- VCC Tolerance Select
BW
- Battery Warning Output
(Open Drain)
RST
GND
NC
- Reset Output (Open Drain)
- Ground
- No Connection
DESCRIPTION
The DS1314 Nonvolatile Controller with Battery Monitor is a CMOS circuit which solves the application
problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-
of-tolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write
protection and the battery is switched on to supply the RAM with uninterrupted power. Special circuitry
uses a low-leakage CMOS process which affords precise voltage detection at extremely low battery
consumption.
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070505
DS1314
In addition to battery-backup support, the DS1314 performs the important function of monitoring the
remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life.
Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority
of its life, accurate battery monitoring requires loaded-battery voltage measurement. The DS1314
performs such measurement by periodically comparing the voltage of the battery as it supports an internal
resistive load with a carefully selected reference voltage. If the battery voltage falls below the reference
voltage under such conditions, the battery will soon reach end-of-life. As a result, the Battery Warning
pin is activated to signal the need for battery replacement.
MEMORY BACKUP
The DS1314 performs all the circuit functions required to provide battery-backup for an SRAM. First, the
device provides a switch to direct power from the battery or the system power supply (VCCI). Whenever
VCCI is less than the switch point VSW and VCCI is less than the battery voltage VBAT, the battery is
switched in to provide backup power to the SRAM. This switch has voltage drop of less than 0.2 volts.
Second, the DS1314 handles power failure detection and SRAM write protection. VCCI is constantly
monitored, and when the supply goes out of tolerance, a precision comparator detects power failure and
inhibits chip enable output (CEO ) in order to write-protect the SRAM. This is accomplished by holding
CEO to within 0.2 volts of VCCO when VCCI is out of tolerance. If CEI is (active) low at the time that
power failure is detected, the CEO signal is kept low until CEI is brought high again. Once CEI is
brought high, CEO is taken high and held high until after VCCI has returned to its nominal voltage level. If
CEI is not brought high by 1.5 ꢀs after power failure is detected, CEO is forced high at that time. This
specific scheme for delaying write protection for up to 1.5 ꢀs guarantees that any memory access in
progress when power failure occurs will complete properly. Power failure detection occurs at 3.0V
nominal (3.3V supply) when the TOL pin is wired to GND or at 2.7V nominal (3.0V supply) when TOL
is connected to VCCO
.
BATTERY VOLTAGE MONITORING
The DS1314 automatically performs periodic battery voltage monitoring at a factory-programmed time
interval of 24 hours. Such monitoring begins within tREC after VCCI rises above VCCTP, and is suspended
when power failure occurs.
After each 24-hour period (tBTCN) has elapsed, the DS1314 connects VBAT to an internal 1.2 Mꢁꢂtest
resistor (RINT) for one second (tBTPW). During this one second, if VBAT falls below the factory-
programmed battery voltage trip point (VBTP), the battery warning output BW is asserted. While BW is
active battery testing will be performed with period tBTCW to detect battery removal and replacement.
Once asserted, BW remains active until the battery is physically removed and replaced by a fresh cell.
The battery is still re-tested after each VCC power-up, however, even if BW was active on power-down. If
the battery is found to be higher than VBTP during such testing, BW is deasserted and regular 24-hour
testing resumes. BW has an open-drain output driver.
Battery replacement following BW activation is normally done with VCCI nominal so that SRAM data is
not lost. During battery replacement, the minimum time duration between old battery detachment and
new battery attachment (tBDBA) must be met or BW will not deactivate following attachment of the new
battery. Should BW not deactivate for this reason, the new battery can be detached for tBDBA and then re-
attached to clear BW .
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DS1314
NOTE: The DS1314 cannot constantly monitor an attached battery because such monitoring would
drastically reduce the life of the battery. As a result, the DS1314 only tests the battery for one second out
of every 24 hours and does not monitor the battery in any way between tests. If a good battery (one that
has not been previously flagged with BW ) is removed between battery tests, the DS1314 may not
immediately sense the removal and may not activate BW until the next scheduled battery test. If a battery
is then reattached to the DS1314, the battery may not be tested until the next scheduled test.
NOTE: Battery monitoring is only a useful technique when testing can be done regularly over the entire
life of a lithium battery. Because the DS1314 only performs battery monitoring when VCC is nominal,
systems which are powered-down for excessively long periods can completely drain their lithium cells
without receiving any advanced warning. To prevent such an occurrence, systems using the DS1314
battery monitoring feature should be powered-up periodically (at least once every few months) in order to
perform battery testing. Furthermore, anytime BW is activated on the first battery test after a power-up,
data integrity should be checked via checksum or other technique.
POWER MONITORING
DS1314S and DS1314E varieties have an additional reset pin. These varieties detect out-of-tolerance
power supply conditions and warn a processor-based system of impending power failure. When VCCI falls
below the trip point level defined by the TOL pin (VCCTP), the VCCI comparator activates the reset signal
RST . Reset occurs at 3.0V nominal (3.3V supply) when the TOL pin is connected to GND or at 2.7V
nominal (3.0V supply) when TOL is connected to VCCO
.
RST also serves as a power-on reset during power-up. After VCCI exceeds VCCTP, RST will be held active
for 200 ms nominal (tRPU). This reset period is sufficiently long to prevent system operation during
power-on transients and to allow tREC to expire. RST has an open-drain output driver.
FRESHNESS SEAL MODE
When the battery is first attached to the DS1314 without VCC power applied, the device does not
immediately provide battery-backup power on VCCO. Only after VCCI exceeds VCCTP and later falls below
both VSW and VBAT will the DS1314 leave Freshness Seal Mode and provide battery-backup power. This
mode allows a battery to be attached during manufacturing but not used until after the system has been
activated for the first time. As a result, no battery energy is drained during storage and shipping.
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DS1314
FUNCTIONAL BLOCK DIAGRAM Figure 1
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DS1314
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-0.5V to +7.0V
-40LC to +85LC
Storage Temperature
-55LC to +125LC
260LC for 10 seconds
Soldering Temperature
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(-40°C to +85°C)
PARAMETER
SYMBOL
VCCI
MIN
3.0
TYP
3.3
MAX
3.6
UNITS NOTES
Supply Voltage TOL=GND
Supply Voltage TOL=VCCO
Battery Supply Voltage
Logic 1 Input
V
V
V
V
V
1
1
VCCI
2.7
3.0
3.3
VBAT
VIH
2.0
6.0
VCCI+0.3
+0.8
1
2.0
-0.3
1, 12
1, 12
Logic 0 Input
VIL
DC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C; VCCI = OVCCTP
)
PARAMETER
SYMBOL
ICC1
MIN
TYP
50
MAX
200
100
80
UNITS NOTES
Operating Current (TTL inputs)
Operating Current (CMOS inputs)
RAM Supply Current
µA
µA
mA
2
2, 5
3
ICC2
30
ICCO1
(VCCO O VCCI -0.2V)
RAM Supply Current
ICCO1
140
mA
4
(VCCO O VCCI -0.3V)
VCC Trip Point (TOL=GND)
VCCTP
VCCTP
VBTP
VSW
2.8
2.5
2.5
2.6
2.9
2.6
2.6
2.7
3.0
2.7
2.7
2.8
V
V
V
V
1
1
1
1
VCC Trip Point (TOL=VCCO
)
VBAT Trip Point
VCC/VBAT Switch Point
(TOL=GND)
VCC/VBAT Switch Point
VSW
2.4
-1
2.5
2.6
V
1
(TOL= VCCO
)
Output Current @ 2.2V
Output Current @ 0.4V
Input Leakage
IOH
IOL
IIL
mA
mA
µA
7, 10
7, 10
4
-1.0
-1.0
0.8
+1.0
+1.0
1.5
Output Leakage
ILO
µA
Battery Monitoring Test Load
RINT
1.2
MΩ
DC ELECTRICAL CHARACTERISTICS (-40°C to +85°C; VCCI < VBAT; VCCI < VSW)
PARAMETER
SYMBOL
IBAT
MIN
TYP
MAX
100
500
UNITS NOTES
Battery Current
nA
µA
V
2
6
Battery-Backup Current
Supply Voltage
CEO Output
ICCO2
VBAT-0.2
VBAT-0.2
VCCO
VOHL
1
V
1, 8
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DS1314
CAPACITANCE
(tA =25°C)
UNITS NOTES
pF
PARAMETER
SYMBOL
MIN
MIN
TYP
MAX
CIN
7
Input Capacitance (CEI , TOL)
Output Capacitance
COUT
7
pF
(CEO , BW , RST )
AC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C; VCCI O VCCTP)
PARAMETER
SYMBOL
TYP
MAX
UNITS NOTES
tPD
12
20
ns
µs
ms
CEI to CEO Propagation Delay
tCE
tREC
1.5
125
11
9
CE Pulse Width
VCC Valid to End of
12
Write Protection
tPU
tRPU
tBPU
2
350
1
ms
ms
s
VCC Valid to CEI Inactive
VCC Valid to RST Inactive
VCC Valid to BW Valid
150
200
10
10
AC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C; VCCI < VCCTP)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
VCC Slew Rate
VCC Fail Detect to RST Active
tF
tRPD
150
µs
µs
5
15
10
VCC Slew Rate
tR
150
µs
AC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C; VCCI O VCCTP)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
tBW
1
s
10
Battery Test to BW Active
Battery Test Cycle-Normal
Battery Test Cycle-Warning
Battery Test Pulse Width
tBTCN
tBTCW
tBTPW
tBDBA
tBABW
24
5
hr
s
1
1
s
Battery Detach to Battery Attach
7
s
s
10
Battery Attach to BW Inactive
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DS1314
TIMING DIAGRAM: POWER-UP
NOTE:
If VBAT < VSW, VCCO will begin to slew with VCCI when VCCI = VBAT
.
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DS1314
TIMING DIAGRAM: POWER-DOWN
NOTE:
If VBAT < VSW, VCCO will slew down with VCCI until VCCI = VBAT
.
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DS1314
TIMING DIAGRAM: BATTERY WARNING DETECTION
NOTE:
tBW is measured from the expiration of the internal timer to the activation of the battery warning output
BW .
TIMING DIAGRAM: BATTERY REPLACEMENT
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DS1314
NOTES:
1. All voltages referenced to ground.
2. Measured with outputs open circuited.
3. ICCO1 is the maximum average load which the DS1314 can supply to attached memories at VCCO
CCI -0.2V.
O
O
V
4. ICCO1 is the maximum average load which the DS1314 can supply to attached memories at VCCO
VCCI -0.3V.
5. All inputs within 0.3V of ground or VCCI.
6. ICCO2 is the maximum average load current which the DS1314 can supply to the memories in the
battery-backup mode.
7. Measured with a load as shown in Figure 2.
8. Chip Enable Output CEO can only sustain leakage current in the battery-backup mode.
9. CEO will be held high for a time equal to tREC after VCCI crosses VCCTP on power-up.
10. BW and RST are open drain outputs and as such cannot source current. External pull-up resistors
should be connected to these pins for proper operation. Both BW and RST can sink 10 mA.
11. tCE maximum must be met to ensure data integrity on power-down.
12. In battery-backup mode, inputs must never be below ground or above VCCO
.
DC TEST CONDITIONS
Outputs Open
AC TEST CONDITIONS
Output Load: See below
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
All voltages are referenced to ground
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
OUTPUT LOAD Figure 2
* INCLUDING SCOPE AND JIG CAPACITANCE
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DS1314
DATA SHEET REVISION SUMMARY
The following represent the key differences between 12/16/96 and 06/12/97 version of the DS1314 data
sheet. Please review this summary carefully.
1.
2.
3.
4.
Changed VBAT max to 6V.
Changed VCCTP values to 2.8 - 3.0V (TOL = GND) and 2.5 - 2.7V (TOL = VCC).
Changed tBABW from 7s to 1s max.
Changed block diagram to show U L compliance.
The following represent the key differences between 06/12/97 and 08/29/97 version of the DS1314 data
sheet. Please review this summary carefully.
1.
2.
Changed AC test conditions.
Changed tPD to 20 max & 12 typ.
The following represent the key differences between 08/29/97 and 12/16/97 version of the DS1314 data
sheet. Please review this summary carefully.
1.
2.
3.
Changed VCCI mins from 3.05V to 3.0V (TOL=GND) and from 275V to 2.7V (TOL=VCCD) (this
should have been done on 06/12/97 revision but was overlooked).
Specified Input Capacitance as being only for CEI , TOL and Output Capacitance as being only for
CEO , BW and RST . This is not a change but rather clarification.
Removed “preliminary” from title bar.
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