DS1682S+T&R [MAXIM]
Time Recorder, Non-Volatile, 0 Timer(s), CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8;
| 型号： | DS1682S+T&R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Time Recorder, Non-Volatile, 0 Timer(s), CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8 时钟 光电二极管 外围集成电路 |
| 文件： | 总14页 (文件大小：692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1682
Total-Elapsed-Time Recorder
with Alarm
General Description
Benefits and Features
● Records the Total Time That the Event Input Has
Been Active and the Number of Events That Have
Occurred
The DS1682 is an integrated elapsed-time recorder con-
taining a factory-calibrated, temperature-compensated
RC time base that eliminates the need for an external
crystal. Using EEPROM technology to maintain data in
the absence of power, the DS1682 requires no backup
power source. The DS1682 detects and records the num-
ber of events on the EVENT pin and the total cumulative
event time since the DS1682 was last reset to 0. The
ALARM pin alerts the user when the total time accu-
mulated equals the user-programmed alarm value. The
polarity of the open-drain ALARM pin can be programmed
to either drive low or to become high impedance upon an
alarm condition. The DS1682 is ideal for applications that
monitor the total amount of time that a device has been
in operation and/or the number of uses since inception of
service, repair, or the last calibration.
● 32-Bit, Nonvolatile, Elapsed Time Counter (ETC)
Monitors Event Duration with Quarter-Second
Resolution and Provides 34 Years of Total Time
Accumulation
● Programmable Elapsed Time ALARM Output
● Nonvolatile, 17-Bit Event Counter Records the Total
Number of Times an Event has Occurred
● Calibrated, Temperature-Compensated RC Time
Base Accurate to 2% Typical
● 10 Bytes of EEPROM User Memory
● Write Disable Function to Prevent the Memory from
Being Changed or Erased
Applications
● 2-Wire Serial Communication
●
High-Temp, Rugged, Industrial Applications Where
Vibration or Shock Could Damage a Quartz Crystal
Any System Where Time-of-Use is Important
(Warranty Tracking)
● Wide 2.5V to 5.5V Power-Supply Range
● Useful in Time-of-Use Warranty, Calibration, Repair,
●
and Maintenance Applications
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/DS1682.related.
Ordering Information appears at end of data sheet.
SCL
SDA
SERIAL INTERFACE
USER, CONTROL, AND
CONFIGURATION
REGISTERS
DS1682
ELAPSED TIME
COUNTER (ETC)
OSCILLATOR
AND DIVIDER
EEPROM ARRAY
ALARM REGS
AND
COMPARE LOGIC
V
CC
CONTROL
LOGIC AND
EVENT
GLITCH
FILTER
ALARM
EVENT
EVENT COUNTER
Figure 1. Block Diagram
19-6835; Rev 1; 11/13
DS1682
Total-Elapsed-Time Recorder
with Alarm
Absolute Maximum Ratings
Voltage Range on Any Pin Relative to Ground ......-0.3V to +6V
Operating Temperature Range........................... -40°C to +85°C
Storage Temperature Range............................ -55°C to +125°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Recommended DC Operating Conditions
(T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.5
TYP
MAX
5.5
UNITS
Power-Supply Voltage
V
V
CC
0.3 x
0.5 x
0.7 x
V
CC
Input Trip Point
V
V
ETP
V
V
CC
CC
1% of
Event Trip-Point Hysteresis
V
%
HYS
V
CC
DC Electrical Characteristics
(V
= 2.5V to 5.5V, T = -40°C to +85°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
+1
UNITS
Input Leakage
I
V
V
-1
µA
V
LI
0.8
ALARM Output (I = 10mA)
OL
OL
OL
SDA Output (I = 4mA)
OL
0.8
V
Active Supply Current
(Event Active)
I
(Note 1)
120
300
µA
CCA
V
V
= 5.5V
6
2
15
4
Standby Current
(Event Active) (Note 1)
CC
I
µA
µA
CCS
= 3.0V
CC
EEPROM Write Current
I
(Note 1)
150
300
EE
Event Timing
(V
= 2.5V to 5.5V, T = -40°C to +85°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
35
MAX
70
UNITS
ms
Time Event Minimum
Time Event Start
t
(Note 1)
(Note 1)
(Note 1)
G
t
112
125
250
137
262.5
34
ms
ES
Time Event Increment
Time Event Max
t
237.5
ms
EI
t
Years
EM
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DS1682
Total-Elapsed-Time Recorder
with Alarm
AC Electrical Characteristics
(V
= 2.5V to 5.5V, T = -40°C to +85°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
50k
UNITS
writes
ms
EEPROM Endurance
EEPROM Write Time
EEPROM Transfer to RAM
E
(Note 2)
E
t
(Notes 1, 3, 4)
(Notes 1, 5)
150
1
300
EW
t
ms
ER
ALARM Output Active-Low Pulse
Width
t
(Note 1)
(Note 1)
(Note 1)
62.5
437.5
500
ms
ms
ms
SL
ALARM Output Active-High Pulse
Width
t
SH
ALARM Input Pulled Low
and Released Pulse Width
t
SPL
SCL
Fast mode
400
100
SCL Clock Frequency
f
kHz
µs
µs
µs
µs
µs
µs
ns
Standard mode
Fast mode
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.0
0
Bus Free Time Between a
STOP and START Condition
t
BUF
Standard mode
Fast mode
Hold Time (Repeated)
START Condition (Note 6)
t
HD:STA
Standard mode
Fast mode
Low Period of SCL
High Period of SCL
t
LOW
Standard mode
Fast mode
t
HIGH
Standard mode
Fast mode
Setup Time for a Repeated
START
t
SU:STA
HD:DAT
Standard mode
Fast mode
Data Hold Time (Notes 7, 8)
Data Setup Time (Note 9)
t
Standard mode
Fast mode
0
100
250
20 +
t
SU:DAT
Standard mode
Fast mode
300
1000
300
0.1C
Rise Time of SDA and SCL
Signals (Note 10)
B
t
ns
R
20 +
0.1C
Standard mode
Fast mode
B
20 +
0.1C
Fall Time of SDA and SCL
Signals (Note 10)
B
t
ns
µs
F
20 +
0.1C
Standard mode
300
B
Fast mode
Standard mode
(Note 1)
0.6
Setup Time for STOP
Input Capacitance
t
SU:STO
4.0
C
10
pF
pF
I/O
Capacitive Load for Each
Bus Line
C
(Note 10)
400
B
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DS1682
Total-Elapsed-Time Recorder
with Alarm
Timing Diagram
SDA
t
BUF
t
F
t
SP
t
HD:STA
t
LOW
SCL
t
HIGH
t
SU:STA
t
t
R
HD:STA
t
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IL(MAX)
IH(MIN)
Note 1: Typical values are at T = +25°C, V
= 4.0V.
A
CC
Note 2: The elapsed time and event counters are backed by three EEPROM arrays, which are used sequentially, allowing up to 3 x
E . The configuration register, alarm trip-point register, and user memory use a single array, limiting them to one E .
E
E
Note 3: A decoupling capacitor to supply high instantaneous currents during EEPROM writes is recommended. A typical value is
0.01μF. V must be maintained above V minimum, including transients, during EEPROM writes.
CC
CC
Note 4: VCC must be at or above 2.5V for t
after the end of an event to ensure data transfer to the EEPROM.
EW
Note 5: Reading data while the contents of EEPROM are transferred to RAM results in incorrect reads.
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
to bridge the undefined region of the falling edge of SCL.
of the SCL signal)
IH(MIN)
Note 8: The maximum t
has only to be met if the device does not stretch the low period (t
) of the SCL signal.
HD:DAT
LOW
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement t
≥ 250ns must be met. This is
SU:DAT
automatically the case if the device does not stretch the t
. If such a device does stretch t
, it must output the next
LOW
LOW
data bit to the SDA line t
+ t
= 1000 + 250 = 1250ns before the SCL line is released.
R(MAX)
SU:DAT
Note 10: C —Total capacitance of one bus line in pF.
B
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DS1682
Total-Elapsed-Time Recorder
with Alarm
Pin Configuration
TOP VIEW
+
EVENT
N.C.
1
2
3
4
8
7
6
5
V
CC
DS1682
N.C.
SDA
SCL
ALARM
GND
SO
(150 mils)
Pin Description
PIN
NAME
FUNCTION
Event Input. The EVENT pin is the input the DS1682 monitors to determine when an event occurs. When
the pin is pulled high, the contents of the EEPROM are transferred to the ETC and the oscillator starts.
The ETC begins to count in quarter-second increments. When the EVENT pin falls to logic 0, the event
counter increments, and the event counter, ETC, and user-memory data are stored in the EEPROM array.
1
EVENT
When the EVENT pin changes states, the 2-wire bus is unavailable for communications for t
(falling)
EW
and t
(rising). The EVENT input is also deglitched (t ) to prevent short noise spikes from triggering an
G
ER
event.
2, 7
3
N.C.
No Connection. These pins are not connected internally.
Active-Low Alarm Output. The DS1682 monitors the values in the ETC for the programmed value in
the alarm register. When the ETC matches the alarm value, the alarm flag (AF) is set. Once set, the
alarm flag cannot be reset. See the operating descriptions for the AOS and AP bits for details about the
operation of the ALARM pin.
ALARM
4
5
GND
SCL
Ground
2-Wire Serial-Clock Input. The SCL pin is the serial-clock input for the 2-wire synchronous
communications channel. The SCL pin is an input that requires an external pullup resistor.
2-Wire Input/Output. The SDA pin is the data input/output signal for the 2-wire synchronous
communications channel. The SDA pin is an open-drain I/O, which requires an external pullup resistor.
6
8
SDA
V
+2.5V to +5.5V Input Supply
CC
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DS1682
Total-Elapsed-Time Recorder
with Alarm
Figure 3 shows the DS1682 in a total time-of-use applica-
tion where power may be removed at the same time as
Operation
The block diagram in Figure 1 shows the relationship
between the major functional blocks, the serial interface,
and the EEPROM memory section of the DS1682. Upon
power-up, the DS1682 transfers the contents of the
EEPROM into the counters and memory registers where
the data can be read and written through the serial inter-
face. The content of the counters and memory registers
are written into the EEPROM memory when the EVENT
pin transitions from a logic-high to a logic-low.
the end of the event. The V
slew rate at power-down is
CC
fast with respect to t . A capacitor maintains V
on the
EW
CC
DS1682 above 2.5V until the EEPROM write completes. A
Schottky diode blocks current from the capacitor to other
devices connected to V
.
CC
V
CC
The DS1682 uses a calibrated, temperature-compensat-
ed RC time base to increment an ETC while an event
is active. When the event becomes active, the contents
of the nonvolatile EEPROM are transferred to the ETC
and event counter and the oscillator starts. As the event
continues, the ETC is incremented in quarter-second
increments. When the event becomes inactive, the event
counter is incremented and the contents of the ETC and
event counter are written to the nonvolatile EEPROM.
V
EVENT
CC
0.01µF
30µF typ
DS1682
LED
ALARM
GND
SCL
SDA
Figure 3. Total Time-of-Use Application with Fast V
Slew Rate
CC
The V
holding capacitor value of 30μF is calculated
using the maximum EEPROM write current and EEPROM
write time. This assumes that the V slew rate allows
CC
The ALARM output can be used to indicate when the ETC
has matched the value in the alarm register.
CC
The DS1682 can be configured to prevent clearing the
alarm and the elapsed time and event counters.The user
memory can be separately write protected.
time from EVENT trip point to V
at 2.5V on the DS1682
CC
is at least t
.
EW
Figure 4 shows the DS1682 in a total time-of-use applica-
tion with power that can be removed at the sametime as
the end of the event. In this application, the V
User-modified data is not stored in EEPROM until an
event becomes inactive.
slew rate
CC
at power-down is slow with respect to t . The external
EW
Figure 2 shows the DS1682 measuring total run time and
operating from a battery with the alarm tied to an LED and
a pushbutton switch to trigger the alarm output.
reset IC (DS1816) ends the event as V
begins to drop.
CC
V
must remain above 2.5V until the end of t
.
CC
EW
V
CC
TRIGGER SWITCH
0.01µF
LED
V
EVENT
DS1682
CC
R
PU
R
PU
LED
V
CC
V
ALARM
DS1682
CC
0.01µF
ALARM
SCL
SDA
DS1816
EVENT
SCL
SDA
R
= t /C
R BUS
PU
GND
PUSHBUTTON
SWITCH
GND
Figure 4. Total Time-of-Use Application with Slow V
Slew Rate
CC
Figure 2. Total Run Time
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DS1682
Total-Elapsed-Time Recorder
with Alarm
Table 1. Memory Map
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
Configuration
Register
00h
0
AF
WDF
WMDF
AOS
RE
AP
ECMSB
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Low Byte
Low-Middle Byte
High-Middle Byte
High Byte
Alarm Register
Low Byte
Low-Middle Byte
High-Middle Byte
High Byte
Elapsed Time
Counter (ETC)
Low Byte
High Byte
Event Counter
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Byte 10
User Memory
Not Used (reads 00h)
Not Used
Reset Command
Write Disable
Reset Command
Write Disable
Write Memory Disable
Memory Disable
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DS1682
Total-Elapsed-Time Recorder
with Alarm
Event Logging
Device Setup
When the DS1682 is powered up, the event time and
count values recorded in the EEPROM are transferred to
the ETC and event counter, and the device waits for an
event. When an event triggers the input by transitioning
the EVENT pin from a low to a high level, the following
occurs:
Once installed in a system, the DS1682 can be pro-
grammed to record events as required by the application,
and can be tested by generating events and monitoring
the results. Afterwards, it can be “locked” to prevent
alteration of the event and alarm registers and the alarm
condition.
1) The RC oscillator starts.
The following is a typical sequence:
2) The alarm, ETC, and event counter are transferred
from EEPROM to RAM.
1) Write the configuration register, alarm registers, and
user memory to the desired values.
3) Note: Reading the RAM during the transfer results in
invalid data.
2) Write-protect the alarm, ETC, and event counter regis-
ters with the write disable command if needed.
4) After t , the ETC increments. An event greater than
3) Write-protect the user memory with the write-memory-
disable command, if needed.
ES
t
but less than t increments the event counter, but
G
ES
not the ETC (zero-length event).
4) Issue a reset (described in the Reset Command section).
5) The ETC increments every t . The ETC holds time in
EI
The alarm, ETC and event counter registers, and user
memory, once locked, cannot be changed.
quarter-second resolution.
6) When the EVENT pin goes low, the event counter
increments, the oscillator stops, and the ETC and
event counter are transferred to EEPROM. The 2-wire
Upon reset, the ETC and event counter registers are
cleared. The device clears the RE bit, and the configu-
ration register becomes read-only. Additional resets are
ignored.
bus is not available for t
.
EW
The ETC stops counting and does not roll over once
FFFFFFFFh, or approximately 34 years, is reached. See
Figure 5 for timing.
t
G
EVENT INPUT
t
EI
INTERNAL EVENT
CLOCK
t
ES
Figure 5. Event Input Timing
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DS1682
Total-Elapsed-Time Recorder
with Alarm
User-modified data in any of the registers is stored in
EEPROM only if the data was written while an event was
active and is stored when the event ends.
Alarm
The alarm register is a 32-bit register that holds time in
quarter-second resolution. When a nonzero number is
programmed into the alarm register, the ALARM func-
tion is enabled and the DS1682 monitors the values in
the ETC for the programmed value in the alarm register.
When the ETC matches the alarm value, the alarm flag
is set.
Event Counter Register
This 17-bit event counter register set provides the total
number of data samples logged during the life of the prod-
uct up to 131,072 separate events. The event counter
consists of 2 bytes of memory in the memory map plus
the event counter MSB bit (ECMSB) in the configuration
register. Once the event counter reaches 1FFFFh, event
counting stops.
EEPROM Array
When power is applied, the contents of the EEPROM are
transferred to the configuration register, alarm register,
ETC, event counter, and user memory. When the event
Reset Command
pin goes low, V
must remain above V
minimum for
CC
CC
If RE is set to a 1, a reset occurs when a reset command
is sent through the 2-wire bus. A reset command is issued
by writing 55h twice into memory location 1Dh. The writes
t
to ensure the EEPROM is properly written.
EW
The EEPROM array for the ETC and the event counter is
made up of three banks. Each bank can be written a maxi-
mum of 50k times. The device switches between banks
based upon the value in the event counter. Resetting the
event counter before the counter reaches 50,000 causes
additional writes to the first bank, which can allow writes
in excess of 50k. If the event counter is set to greater
than 50k or 100k prior to reset, the device stays on the
selected bank. This could result in writes in excess of 50k
to one bank.
need not be consecutive. Cycling power on V
prior to
CC
the second write terminates the reset sequence.
Upon reset, the ETC and event counter registers are
cleared. The AF, RE, and ECMSB bits are cleared by the
device, and the configuration register becomes read-only.
The data are written to the EEPROM, and additional
resets are ignored.
When a reset command is issued, no additional command
should be issued during the EEPROM write time (t ).
EW
The configuration and alarm registers and the user mem-
ory are held in one bank of EEPROM. Writes at the end
of an event only occur if the data has changed in one or
more of those registers.
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DS1682
Total-Elapsed-Time Recorder
with Alarm
Configuration Register
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
AF
WDF
WMDF
AOS
RE
AP
ECMSB
Note: The configuration register is not stored in EEPROM until an event becomes inactive. RE does not need to be stored in
EEPROM to reset the device.
Bit 6: Alarm Flag (AF). The alarm flag is set to a 1 when
the ETC value matches the alarm register. Once the AF
bit is set to a 1, it cannot be set to a 0. This bit is read-only.
another device to indicate that an alarm has occurred. AP
has no affect on the output when AOS is 0.
If AOS is a 1 and AF is true, the ALARM output is constant
when the alarm is active. AP determines the polarity of
the output.
Bit 5: Write Disable Flag (WDF). When the write disable
command is written to AAh twice at memory location 1Eh,
the WDF is set to a 1 and cannot be cleared or reset.
When WDF is set to a 1, the alarm, ETC, and event coun-
ter registers are read-only. This bit is read-only. The writes
Bit 2: Reset Enable (RE). The reset enable bit allows the
device to be reset by enabling the reset command. The
sections of the DS1682 that are reset are then dependent
on the value in the WDF. With the WDF set to 0 and the
reset enable bit set to a 1, the reset command clears
the ETC, EEPROM, and event counter. When the reset
enable bit is set to a 0, the reset command is disabled.
need not be consecutive. Cycling power on V
prior to
CC
the second write terminates the reset sequence.
Bit 4: Write-Memory-Disable Flag (WMDF). When the
write-memory-disable command is written to F0h twice
at memory location 1Fh, the WMDF is set to a 1 and
cannot be reset or cleared. Once the WMDF is set to a
1, the 10-byte user memory becomes read-only. This bit
is read-only. The writes need not be consecutive. Cycling
Bit 1: Alarm Polarity (AP). When the alarm polarity bit
in the configuration register is set to 0, the ALARM output
is high impedance during the period that the value in the
ETC is less than the alarm register value. When the ETC
matches the alarm value, the ALARM pin is driven low.
If the AP bit is set to a 1, the ALARM output is driven
low during the period that the ETC is less than the alarm
value.
power on V
prior to the second write terminates the
CC
reset sequence.
Bit 3: Alarm Output Select (AOS). If AOS is 0 and AF is
true, the DS1682 activates the ALARM output during an
event when AF becomes true. The DS1682 also activates
the ALARM output by pulling the pin low four times at
power-up, at the start and end of an event, or when the
ALARM pin is pulled low and released. This output mode
can be used to flash an LED or to communicate with
When the ETC matches the alarm value, the ALARM pin
becomes high impedance. The AP bit has no affect if AOS
is set to a 0.
Bit 0: Event Counter MSB (ECMSB). This bit is read-
only.
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DS1682
Total-Elapsed-Time Recorder
with Alarm
defines a START condition.
User Memory
There are 10 bytes of user-programmable, EEPROM
memory. Once the write-memory disable flag is set to
1, the memory becomes read-only. User memory is not
stored in EEPROM until an event becomes inactive.
Stop Data Transfer: A change in the state of the data
line, from low to high, while the clock line is high, defines
the STOP condition.
Data Valid: The state of the data line represents valid
data when, after a START condition, the data line is stable
for the duration of the high period of the clock signal. The
data on the line must be changed during the low period of
the clock signal. There is one clock pulse per bit of data.
2-Wire Serial Data Bus
The DS1682 supports a bidirectional, 2-wire bus and
data-transmission protocol. A device that sends data onto
the bus is defined as a transmitter and a device receiving
data, a receiver. The device that controls the message is
called a master, and the devices controlled by the master
are slaves. A master device that generates the serial clock
(SCL), controls the bus access, and generates the START
and STOP conditions must control the bus. The DS1682
operates as a slave on the 2-wire bus. Connections to
the bus are made through the open-drain I/O lines SDA
and SCL.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between START and STOP condi-
tions are not limited, and are determined by the master
device. The information is transferred byte-wise and each
receiver acknowledges with a ninth bit. Within the bus
specifications a standard mode (100kHz clock rate) and a
fast mode (400kHz clock rate) are defined.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an acknowledge after it receives
each byte. The master device must generate an extra
clock pulse, which is associated with this acknowledge bit.
The following bus protocol has been defined (Figure 6):
● Data transfer can be initiated only when the bus is
not busy.
● During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that
the SDA line is stable low during the high period of the
acknowledge-related clock pulse. Of course, setup and
hold times must be considered. A master must signal an
end-of-data to the slave by not generating an acknowl-
edge bit on the last byte that has been clocked out of the
slave. In this case, the slave must leave the data line high
to enable the master to generate the STOP condition.
Accordingly, the following bus conditions have been
defined:
Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data
line, from high to low, while the clock is high,
SDA
MSB
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3-8
8
9
ACK
ACK
START
CONDITION
STOP CONDITION
OR
REPEATED IF MORE BYTES
ARE TRANSFERRED
REPEATED
START CONDITION
Figure 6. Timing Diagram: Data Transfer on 2-Wire Serial Bus
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DS1682
Total-Elapsed-Time Recorder
with Alarm
Depending upon the state of the R/W bit, two types of
condition. The address byte contains the 7-bit DS1682
address, which is 1101011 (D6h), followed by the direction
bit (R/W). The second byte from the master is the register
address. This sets the register pointer. The master then
transmits each byte of data, with the DS1682 acknowledg-
ing each byte received. The register pointer increments
after each byte is written. The master generates a STOP
condition to terminate the data write (Figure 7).
data transfer are possible:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received
byte.
Data transfer from a slave transmitter to a master
receiver. The master transmits the first byte (the slave
address). The slave then returns an acknowledge bit. Next
follows a number of data bytes transmitted by the slave to
the master. The master returns an acknowledge bit after
all received bytes other than the last byte. A “not acknowl-
edge” is returned at the end of the last received byte.
Slave Transmitter Mode (Read Mode): The first byte
is received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the DS1682 while the serial clock is input on SCL.
The slave address byte is the first byte received after the
master generates a START condition. The address byte
contains the 7-bit DS1682 address, followed by the direc-
tion bit (R/W). After receiving a valid slave address byte
and direction bit, the DS1682 generates an acknowledge
on the SDA line. The DS1682 begins to transmit data on
each SCL pulse starting with the register address pointed
to by the register pointer. As the master reads each byte,
it must generate an acknowledge. The register pointer
increments after each byte is read. The DS1682 must
receive a “not acknowledge” on the last byte to end a
read (Figure 8).
The master device generates all of the serial clock pulses
and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START condi-
tion. Since a repeated START condition is also the begin-
ning of the next serial transfer, the bus is not released.
Slave Receiver Mode (Write Mode): Serial data and
clock are received through SDA and SCL. After each byte
is received, the receiver transmits an acknowledge bit.
START and STOP conditions are recognized as the begin-
ning and end of a serial transfer. The slave address byte is
the first byte received after the master generates a START
SLAVE
ADDRESS
REGISTER
ADDRESS
R/W
0
DATA (n)
DATA (n + 1)
XXXXXXXX
DATA (n + x)
XXXXXXXX
S
1101011
A
XXXXXXXX
A
XXXXXXXX
A
A
P
S – START
DATA TRANSFERRED
A – ACKNOWLEDGE
P – STOP
(X + 1 BYTES + ACKNOWLEDGE)
R/W – READ/WRITE OR DIRECTION BIT
Figure 7. Data Write—Slave Receiver Mode
SLAVE
ADDRESS
R/W
1
DATA (n)
XXXXXXXX
DATA (n + 1)
XXXXXXXX
DATA (n + 2)
XXXXXXXX
DATA (n + x)
XXXXXXXX
S
1101011
A
A
A
A
/A
S – START
DATA TRANSFERRED
A – ACKNOWLEDGE
P – STOP
(X + 1 BYTES + ACKNOWLEDGE)
/A – NOT ACKNOWLEDGE
R/W – READ/WRITE OR DIRECTION BIT
Figure 8. Data Read—Slave Transmitter Mode
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DS1682
Total-Elapsed-Time Recorder
with Alarm
Ordering Information
Chip Information
PROCESS: CMOS
PART
DS1682S+
DS1682S+T&R
PIN-PACKAGE
TOP MARK
DS1682
8 SO
8 SO
DS1682
Package Information
Note: All devices are specified over the -40°C to +85°C operating
range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 SO
S8+5
21-0041
90-0096
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DS1682
Total-Elapsed-Time Recorder
with Alarm
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
Added the lead and soldering temperature information to the Absolute Maximum
Ratings section; updated the Ordering Information and Package Information tables
1
11/13
2, 14
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2013 Maxim Integrated Products, Inc.
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