DS1876_V01_技术文档

DS1876

SFP Controller with Dual LDD Interface

General Description

Features

S Meets All SFF-8472 Transmitter Control and

The DS1876 controls and monitors all functions for

dual transmitter modules. The memory map is based

on SFF-8472. The DS1876 supports APC and modula-

tion control and eye safety functionality for two laser

drivers. It continually monitors for high output current,

high bias current, and low and high transmit power to

ensure that laser shutdown for eye safety requirements

are met without adding external components. Six ADC

Monitoring Requirements

S Six Analog Monitor Channels: Temperature, V

PMON1, BMON1, PMON2, BMON2

PMON_ and BMON_ Support Internal and

External Calibration

,

CC

Scalable Dynamic Range

Internal Direct-to-Digital Temperature Sensor

Alarm and Warning Flags for All Monitored

Channels

channels monitor V , temperature, and four external

monitor inputs that can be used to meet all monitoring

requirements.

CC

S Six Quick Trips for Fast Monitoring of Critical

Functions for Laser Safety

Applications

S Four 10-Bit Delta-Sigma Outputs

Each Controlled by 72-Entry Temperature

Lookup Table (LUT)

Dual Tx Video SFP Modules

S Digital I/O Pins: Six Inputs, Five Outputs

Ordering Information

S Comprehensive Fault Measurement System with

PART

DS1876T+

TEMP RANGE

-40NC to +95NC

PIN-PACKAGE

28 TQFN-EP*

Maskable Laser Shutdown Capability

S Flexible, Two-Level Password Scheme Provides

DS1876T+T&R

Three Levels of Security

+Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

*EP = Exposed pad.

S 256 Additional Bytes Located at A0h Slave

Address

S Transmitter 1 is Accessed at A2h Slave Address

S Transmitter 2 is Accessed at B2h Slave Address

S I²C-Compatible Interface

S +2.85V to +3.9V Operating Voltage Range

S -40NC to +95NC Operating Temperature Range

S 28-Pin TQFN (5mm x 5mm x 0.8mm) Package

For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

19-5153; Rev 0; 2/10

DS1876

SFP Controller with Dual LDD Interface

TABLE OF CONTENTS

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

MOD_, APC_ Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Analog Quick-Trip Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Analog Voltage Monitoring Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Digital Thermometer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Quick-Trip Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2

I C AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Nonvolatile Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Typical Operating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DACs During Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DACs as a Function of Transmit Disable (TXD1, TXD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Quick-Trip Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Monitors and Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Six Quick-Trip Monitors and Alarms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Six ADC Monitors and Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Low-Voltage Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Delta-Sigma Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

IN1, RSEL, OUT1, RSELOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

TXF1, TXF2, TXFOUT, TXD1, TXD2, TXDOUT1, TXDOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Transmit Fault (TXFOUT) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2

I C Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2

I C Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2

I C Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

TABLE OF CONTENTS (continued)

Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Shadowed EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Memory Map Access Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Memory Addresses A0h, A2h, and B2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Lower Memory Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 01h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 02h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 04h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 05h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 06h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Auxiliary Memory A0h Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Lower Memory Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 02h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 04h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 06h Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Auxiliary Memory A0h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Power-Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

SDA and SCL Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Maxim Integrated

3

DS1876

SFP Controller with Dual LDD Interface

LIST OF FIGURES

Figure 1. Power-Up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. TXD1, TXD2 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3. Quick-Trip Sample Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4. ADC Round-Robin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. Low-Voltage Hysteresis Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Recommended RC Filter for DAC Outputs in Voltage Mode and Current Sink Mode . . . . . . . . . . . . . . . . . 16

Figure 7. 3-Bit (8-Position) Delta-Sigma Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. DAC OFFSET LUTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9. Logic Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. Logic Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11a. TXFOUT Nonlatched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11b. TXFOUT Latched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2

Figure 12. I C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2

Figure 13. Example I C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14. Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

LIST OF TABLES

Table 1. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 2. ADC Default Monitor Full-Scale Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

ABSOLUTE MAXIMUM RATINGS

Voltage Range on PMON_, BMON_, RSEL,

IN1, TXF_, and TXD_ Pins

Continuous Power Dissipation

28-Pin TQFN (derate 34.5mW/°C) above +70°C....2758.6mW

Operating Temperature Range.......................... -40NC to +95NC

Programming Temperature Range ....................... 0NC to +95NC

Storage Temperature Range............................ -55NC to +125NC

Soldering Temperature .........................Refer to the IPC/JEDEC

J-STD-020 Specification.

Relative to Ground...............................-0.5V to (V

+ 0.5V)*

CC

Voltage Range on V , SDA, SCL,

CC

OUT1, RSELOUT, and TXFOUT Pins

Relative to Ground...............................................-0.5V to +6V

*Subject to not exceeding +6V.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

(T = -40NC to +95NC, unless otherwise noted.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

+2.85

0.7 x

TYP

MAX

UNITS

Main Supply Voltage

V

CC

(Note 1)

+3.9

V

High-Level Input Voltage

(SDA, SCL)

V

CC

0.3

+

V

IH:1

V

CC

Low-Level Input Voltage

(SDA, SCL)

0.3 x

V

IL:1

-0.3

2.0

V

CC

High-Level Input Voltage

(TXD_, TXF_, RSEL, IN1)

V

CC

0.3

+

V

IH:2

Low-Level Input Voltage

(TXD_, TXF_, RSEL, IN1)

V

IL:2

-0.3

+0.8

DC ELECTRICAL CHARACTERISTICS

(V

CC

= +2.85V to +3.9V, T = -40NC to +95NC, unless otherwise noted.)

A

PARAMETER

Supply Current

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

I

(Notes 1, 2)

2.5

10

mA

CC

Output Leakage (SDA, OUT1,

RSELOUT, TXFOUT)

I

1

FA

V

LO

Low-Level Output Voltage

(SDA, OUT1, RSELOUT,

TXDOUT_, MOD_, APC_,

TXFOUT)

I

= 4mA

= 6mA

0.4

0.6

OL

V

OL

High-Level Output Voltage

(MOD_, APC_, TXDOUT_)

V

CC

0.4

-

V

OH

I

= 4mA

V

OH

TXDOUT_ Before EEPROM

Recall

10

100

1

nA

FA

MOD_, APC_ Before Recall

Figure 1

Input Leakage Current

(SCL, TXD_, RSEL, IN1, TXF_)

I

LI

Digital Power-On Reset

Analog Power-On Reset

POD

POA

1.0

2.0

2.2

V

2.75

Maxim Integrated

5

DS1876

SFP Controller with Dual LDD Interface

MOD_, APC_ ELECTRICAL CHARACTERISTICS

(V

CC

= +2.85V to +3.9V, T = -40NC to +95NC, unless otherwise noted.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Main Oscillator Frequency

f

5

MHz

OSC

Delta-Sigma Input-Clock

Frequency

f

/2

OSC

MHz

DS

Reference Voltage Input (REFIN)

Output Range

V

Minimum 0.1FF to GND

2

0

V

REFIN

CC

V

REFIN

See the Delta-Sigma Outputs section for

details

Output Resolution

Output Impedance

10

Bits

R

DS

35

100

I

ANALOG QUICK-TRIP CHARACTERISTICS

(V

CC

= +2.85V to +3.9V, T = -40NC to +95NC, unless otherwise noted.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TXP HI, TXP LO Full-Scale

Voltage

2.507

V

HBIAS Full-Scale Voltage

PMON_ Input Resistance

Resolution

1.25

50

8

35

65

kW

Bits

%FS

LSB

%FS

mV

Error

T

A

= +25°C

±2

Integral Nonlinearity

Differential Nonlinearity

Temperature Drift

Offset

-1

+1

-2.5

-5

+2.5

+10

ANALOG VOLTAGE MONITORING CHARACTERISTICS

(V

CC

= +2.85V to +3.9V, T = -40NC to +95NC, unless otherwise noted.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

ADC Resolution

13

Bits

Input/Supply Accuracy

ACC

At factory setting

0.25

64

0

0.5

78

5

%FS

ms

LSB

V

(BMON_, PMON_, V

)

CC

Update Rate for Temperature,

t

RR

BMON_, PMON_, V

CC

Input/Supply Offset

V

(Note 3)

OS

(BMON_, PMON_, V

)

CC

BMON_, PMON_

2.5

Factory Setting (Note 4)

V

CC

6.5536

6

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

DIGITAL THERMOMETER CHARACTERISTICS

(V

CC

= +2.85V to +3.9V, T = -40NC to +95NC, unless otherwise noted.)

A

PARAMETER

Thermometer Error

SYMBOL

CONDITIONS

-40NC to +95NC

MIN

TYP

MAX

UNITS

T

ERR

-3

+3

NC

AC ELECTRICAL CHARACTERISTICS

(V

CC

= +2.85V to +3.9V, T = -40NC to +95NC, unless otherwise noted.)

A

PARAMETER

TXD_ Enable

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

t

5

Fs

OFF

From TXD_

Recovery from TXD_ Disable

(Figure 2)

t

1

ms

ON

t

131

161

INITR1

INITR2

FAULT

Fault Reset Time (to TXFOUT = 0)

Fault Assert Time (to TXFOUT = 1)

ms

On power-up or TXD_, when VCC LO

alarm is detected (Note 5)

After HTXP_, LTXP_, HBATH_

1.6

10.5

Fs

QUICK-TRIP TIMING CHARACTERISTICS

(V

CC

= +2.85V to +3.9V, T = -40NC to +95NC, unless otherwise noted.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Output-Enable Time Following POA

t

20

ms

INIT

Sample Time per Quick-Trip

Comparison

t

1.6

Fs

REP

2

I C AC ELECTRICAL CHARACTERISTICS

2

(V

CC

= +2.85V to +3.9V, T = -40NC to +95NC, timing referenced to V

and V

, unless otherwise noted. See the I C

A

IL(MAX)

IH(MIN)

Communication section.)

PARAMETER

SCL Clock Frequency

Clock Pulse-Width Low

Clock Pulse-Width High

SYMBOL

CONDITIONS

MIN

0

TYP

MAX

UNITS

kHz

Fs

f

(Note 6)

400

SCL

t

1.3

0.6

LOW

t

Fs

HIGH

Bus Free Time Between STOP and

START Condition

t

1.3

Fs

BUF

START Hold Time

START Setup Time

Data Out Hold Time

Data In Setup Time

t

0.6

0

Fs

ns

HD:STA

t

SU:STA

t

0.9

HD:DAT

t

100

SU:DAT

Rise Time of Both SDA and SCL

Signals

20 +

t

(Note 7)

300

ns

R

0.1C

B

Fall Time of Both SDA and SCL

Signals

20 +

t

F

0.1C

B

STOP Setup Time

t

0.6

Fs

pF

ms

SU:STO

Capacitive Load for Each Bus Line

EEPROM Write Time

C

400

20

B

t

(Note 8)

WR

Maxim Integrated

7

DS1876

SFP Controller with Dual LDD Interface

NONVOLATILE MEMORY CHARACTERISTICS

(V

CC

= +2.85V to +3.9V, unless otherwise noted.)

PARAMETER

EEPROM Write Cycles

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

At +25NC

At +85NC

200,000

50,000

Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.

Note 2: Inputs are at supply rail. Outputs are not loaded.

Note 3: This parameter is guaranteed by design.

Note 4: Full scale is user programmable.

Note 5: A temperature conversion is completed and MOD1 DAC, MOD2 DAC, APC1 DAC, and APC2 DAC values are recalled

from the LUT and V

has been measured to be above VCC LO alarm, if the VCC LO alarm is enabled.

CC

2

Note 6: I C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I C stan-

dard mode.

Note 7: C —Total capacitance of one bus line in pF.

B

Note 8: EEPROM write begins after a STOP condition occurs.

8

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Typical Operating Characteristics

(V

CC

= 3.3V, T = +25°C, unless otherwise noted.)

A

SUPPLY CURRENT vs. TEMPERATURE

SUPPLY CURRENT vs. SUPPLY VOLTAGE

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

DAC POSITIONS = 1FFh

SDA = SCL = V

DACs AT 1FFh

CC

SDA = SCL = V

CC

+95°C

V

= 3.9V

CC

V

= 3.3V

CC

+25°C

-40°C

V

= 2.85V

-15

CC

-40

10

35

60

85

2.850

3.150

3.450

(V)

3.750

TEMPERATURE (°C)

V

CC

APC1/2 AND MOD1/2 DAC DNL

APC1/2 AND MOD1/2 DAC INL

1.0

0.8

3

2

0.6

0.4

1

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

-1

-2

-3

0

500

1000

0

500

1000

DAC POSITION (DEC)

PMON1/2 AND BMON1/2 DNL

PMON1/2 AND BMON1/2 INL

1.0

0.8

1.0

0.8

USING FACTORY-PROGRAMMED FULL-SCALE

VALUE OF 2.5V

USING FACTORY-PROGRAMMED FULL-SCALE

VALUE OF 2.5V

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

0.5

1.0

1.5

2.0

2.5

0

0.5

1.0

1.5

2.0

2.5

PMON1/2 AND BMON1/2 INPUT VOLTAGE (V)

Maxim Integrated

9

DS1876

SFP Controller with Dual LDD Interface

Pin Configuration

TOP VIEW

21 20 19 18 17 16 15

14

13

REFIN 22

TXD2 23

BMON1

PMON1

12 BMON2

24

25

26

27

28

APC2

APC1

DS1876

PMON2

TXDOUT1

RSEL

11

10

9

V

CC

TXF2

OUT1

*EP

+

8

GND

1

2

3

4

5

6

7

THIN QFN

(5mm × 5mm × 0.8mm)

*EXPOSED PAD.

Pin Description

1

NAME

FUNCTION

NAME

BMON1

N.C.

FUNCTION

RSELOUT Rate-Select Output

2

External Monitor Input BMON1

and HBATH1 Quick Trip

14

2

SCL

SDA

I C Serial-Clock Input

2

3

I C Serial-Data Input/Output

15

16, 26

17

No Connection

V

CC

Power-Supply Input

Transmit Fault Output, Open

Drain

4

5

TXFOUT

TXF1

TXDOUT2 Transmit Disable Output 2

Transmit Fault Input 1

19

MOD2

MOD1

MOD2 DAC, Delta-Sigma Output

MOD1 DAC, Delta-Sigma Output

20

Digital Input. General-purpose

input, AS1 in SFF-8079, or RS1

in SFF-8431.

6

IN1

Reference Input for DAC1 and

DAC2

22

REFIN

7

TXD1

GND

RSEL

Transmit Disable Input 1

Ground Connection

Rate-Select Input

23

24

25

27

TXD2

APC2

APC1

TXF2

Transmit Disable Input 2

8, 18, 21

APC2 DAC, Delta-Sigma Output

APC1 DAC, Delta-Sigma Output

Transmit Fault Input 2

9

10

TXDOUT1 Transmit Disable Output 1

External Monitor Input PMON2

PMON2

Digital Output. General-purpose

output, AS1 output in SFF-8079,

or RS1 output in SFF-8431.

11

12

13

and HTXP2/LTXP2 Quick Trip

28

—

OUT1

EP

External Monitor Input BMON2

BMON2

and HBATH2 Quick Trip

Exposed Pad (Connect to GND)

External Monitor Input PMON1

PMON1

and HTXP1/LTXP1 Quick Trip

10

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Block Diagram

REFIN

V

CC

MOD2 DAC

10 BITS

V

CC

MOD2

APC2

MOD1

APC1

MAIN MEMORY

EEPROM/SRAM

2

SDA

SCL

I C

INTERFACE

A/D CONFIGURATION/RESULTS,

SYSTEM STATUS/CONTROL BITS,

ALARMS/WARNINGS,

APC2 DAC

10 BITS

EEPROM

256 BYTES

AT A0h

LOOKUP TABLES,

USER MEMORY

MOD1 DAC

10 BITS

V

CC

APC1 DAC

10 BITS

13-BIT

ADC

BMON1

PMON1

BMON2

PMON2

8-BIT

QTs

TXFOUT

POWER-ON

ANALOG

INTERRUPT

TEMPERATURE

SENSOR

V

CC

TXD1

TXD2

TXF1

TXF2

TXDOUT1

LOGIC

CONTROL

V

CC

TXDOUT2

RSELOUT

RSEL

IN1

LOGIC

CONTROL

OUT1

GND

DS1876

Maxim Integrated

11

DS1876

SFP Controller with Dual LDD Interface

Typical Operating Circuit

TOSA2

LDD2

BMON

APCIN

FAULT

APCSET

MODSET

DISABLE

TOSA1

LDD1

BMON

APCIN

FAULT

APCSET

MODSET

DISABLE

RC FILTERS

(FIGURE 6)

MOD1

DAC

DS1876

APC1

DAC

TXF1

TXF2

TXFOUT

TXDOUT1

TXDOUT2

TXD1

EEPROM

MOD2

DAC

TX_FAULT

APC2

DAC

TX_DISABLE1

TX_DISABLE2

TXD2

BMON1

PMON1

BMON2

PMON2

QUICK

TRIP

SDA

SCL

MODE_DEF2 (SDA)

MODE_DEF1 (SCL)

2

I C

R

B1

P1

B1

P2

ADC

set in EEPROM. After a temperature conversion is com-

pleted and if the VCC LO alarm is enabled, an additional

Detailed Description

The DS1876 integrates the control and monitoring func-

tionality required in a dual transmitter system. Key com-

ponents of the DS1876 are shown in the Block Diagram

and described in subsequent sections.

V

CC

conversion above the customer-defined VCC LO

alarm level is required before the DACs are updated with

the value determined by the temperature conversion and

the DAC LUT.

DACs During Power-Up

If a fault is detected, and TXD1 and TXD2 are toggled

to re-enable the outputs, the DS1876 powers up fol-

lowing a similar sequence to an initial power-up. The

On power-up, the DS1876 sets the DACs to high imped-

ance. After time t

, the DACs are set to an initial condition

INIT

12

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

only difference is that the DS1876 already has deter-

Table 1. Acronyms

ACRONYM

mined the present temperature, so the t

time is not

INIT

DESCRIPTION

required for the DS1876 to recall the APC and MOD

set points from EEPROM. See Figure 1.

ADC

AGC

APC

APD

ATB

DAC

LOS

LUT

NV

Analog-to-Digital Converter

Automatic Gain Control

Automatic Power Control

Avalanche Photodiode

Alarm Trap Bytes

DACs as a Function of Transmit Disable

(TXD1, TXD2)

If TXD1 or TXD2 are asserted (logic 1) during normal

operation, the associated outputs are disabled within

Digital-to-Analog Converter

Loss of Signal

t

. When TXD1 or TXD2 are deasserted (logic 0), the

OFF

DS1876 sets the DACs with the value associated with

the present temperature. When asserted, soft TXD1 or

soft TXD2 (TXDC) (Lower Memory, Register 6Eh) would

allow a software control identical to the TXD1 or TXD2 pin

(Figure 2). The POLARITY register (Table 02h, Register

C6h) determines if the off-state value of the DACs is

Lookup Table

Nonvolatile

QT

Quick Trip

TE

Tracking Error

TIA

Transimpedance Amplifier

Receiver Optical Subassembly

Shadowed EEPROM

Small Form Factor

V

or 0V.

REFIN

ROSA

SEE

SFF

Quick-Trip Timing

As shown in Figure 3, the DS1876’s input compara-

tor is shared among the six quick-trip alarms (TXP1

HI, TXP1 LO, TXP2 HI, TXP2 LO, BIAS1 HI, and BIAS2

HI). The comparator polls the alarms in a multiplexed

sequence. The updates are used to compare the HTXP1,

LTXP1, HTXP2, and LTXP2 (monitor diode voltages) and

the HBATH1 and HBATH2 (BMON1, BMON2) signals

against the internal APC and BIAS reference, respec-

tively. Depending on the results of the comparison, the

Document Defining Register Map of SFPs

and SFFs

SFF-8472

SFP

SFP+

TOSA

TXP

Small Form Factor Pluggable

Enhanced SFP

Transmit Optical Subassembly

Transmit Power

V

POA

V

CC

t

500µs

INIT

DAC

SETTINGS

HIGH IMPEDANCE

OFF STATE

LUT VALUE

Figure 1. Power-Up Timing

TXD_

DAC

t

ON

OFF

LUT VALUE

OFF STATE

LUT VALUE

SETTINGS

Figure 2. TXD1, TXD2 Timing

Maxim Integrated

13

DS1876

SFP Controller with Dual LDD Interface

QT CYCLE

LTXP2

SAMPLE

HBIAS1

SAMPLE

HBIAS2

SAMPLE

HTXP1

SAMPLE

HTXP2

SAMPLE

LTXP1

SAMPLE

LTXP2

SAMPLE

HBIAS1

SAMPLE

QUICK-TRIP SAMPLE TIMES

t

REP

Figure 3. Quick-Trip Sample Timing

Table 2. ADC Default Monitor Full-Scale Ranges

SIGNAL (UNITS)

Temperature (NC)

(V)

+FS SIGNAL

127.996

6.5528

+FS HEX

-FS SIGNAL

-FS HEX

8000

7FFF

FFF8

-128

V

CC

0

0000

PMON1, PMON2 and BMON1, BMON2 (V)

2.4997

0000

corresponding alarms and warnings (TXP HI1, TXP LO1,

TXP HI2, TXP LO2, BIAS HI1, and BIAS HI2) are asserted

or deasserted.

The high and low transmit power quick-trip registers

(HTXP1, HTXP2, LTXP1, and LTXP2) set the thresholds

used to compare against the PMON1 and PMON2 volt-

ages to determine if the transmit power is within speci-

fication. The HBATH1 and HBATH2 QTs compare the

BMON1 and BMON2 inputs (generally from the laser

driver’s bias monitor output) against their threshold set-

tings to determine if the present bias current is above

specification. The bias and power QTs are routed to

FETG through interrupt masks to allow combinations

of these alarms to be used to trigger FETG. The bias

and power QTs are directly connected to TXFOUT (see

Figure 9). The user can program up to eight different

temperature-indexed threshold levels for HBATH1 and

HBATH2 (Table 06h, Registers E0h-E7h).

After resetting, the device completes one QT cycle

before making comparisons. The TXP LO quick-trip

alarm updates its alarm bit, but does not create FETG

until after TXD

. TXP HI and BIAS HI can also be con-

EXT

figured to wait for TXD

; however, this can be disabled

EXT

using QTHEXT_ (Table 02h, Register 88h).

Monitors and Fault Detection

Monitors

Monitoring functions on the DS1876 include six quick-

trip comparators and six ADC channels. This monitoring

combined with the alarm enables (Table 01h/05h) deter-

mines when/if the DS1876 turns off DACs and triggers

the TXFOUT and TXDOUT1, TXDOUT2 outputs. All the

monitoring levels and interrupt masks are user program-

mable.

Six ADC Monitors and Alarms

The ADC monitors six channels that measure tem-

perature (internal temp sensor), V , PMON1, PMON2,

CC

BMON1, and BMON2 using an analog multiplexer to

measure them round-robin with a single ADC (see the

ADC Timing section). The channels have a customer-

programmable full-scale range, and all channels have a

customer-programmable offset value that is factory pro-

grammed to a default value (see Table 2). Additionally,

PMON1, PMON2 and BMON1, BMON2 can right-shift

results by up to 7 bits before the results are compared

Six Quick-Trip Monitors and Alarms

Six quick-trip monitors are provided to detect potential

laser safety issues and LOS status. These monitor the

following:

1) High Bias Current 1 (HBATH1), causing QT BIAS1 HI

2) Low Transmit Power 1 (LTXP1), causing QT TXP1 LO

3) High Transmit Power 1 (HTXP1), causing QT TXP1 HI

4) High Bias Current 2 (HBATH2), causing QT BIAS2 HI

5) Low Transmit Power 2 (LTXP2), causing QT TXP2 LO

6) High Transmit Power 2 (HTXP2), causing QT TXP2 HI

2

to alarm thresholds or read over the I C bus. This allows

customers with specified ADC ranges to calibrate the

n

ADC full scale to a factor of 1/2 of their specified range

to measure small signals. The DS1876 can then right-

shift the results by n bits to maintain the bit weight of their

specification.

14

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

The ADC results (after right-shifting, if used) are com-

shifts. Up to seven right-shift operations are allowed and

are executed as a part of every conversion before the

results are compared to the high and low alarm levels, or

loaded into their corresponding measurement registers

(Lower Memory, Registers 64h–6Bh). This is true during

the setup of internal calibration as well as during subse-

quent data conversions.

pared to the alarm and warning thresholds after each

conversion, and the corresponding alarms are set that

can be used to trigger the TXFOUT output. These ADC

thresholds are user programmable, as are the masking

registers that can be used to prevent the alarms from trig-

gering the TXFOUT output.

ADC Timing

There are six analog channels that are digitized in a

round-robin fashion in the order as shown in Figure 4.

Low-Voltage Operation

The DS1876 contains two power-on reset (POR) levels.

The lower level is a digital POR (POD) and the higher

level is an analog POR (POA). At startup, before the sup-

ply voltage rises above POA, the outputs are disabled,

all SRAM locations are set to their defaults, shadowed

EEPROM (SEE) locations are zero, and all analog cir-

The total time required to convert all six channels is t

RR

(see the Analog Voltage Monitoring Characteristics table

for details).

Right-Shifting ADC Result

If the weighting of the ADC digital reading must conform

to a predetermined full-scale (PFS) value defined by

a standard’s specification (e.g., SFF-8472), then right-

shifting can be used to adjust the PFS analog measure-

ment range while maintaining the weighting of the ADC

results. The DS1876’s range is wide enough to cover all

requirements; when the maximum input value is P 1/2

the FS value, right-shifting can be used to obtain greater

accuracy. For instance, the maximum voltage might be

1/8 the specified PFS value, so only 1/8 of the converter’s

range is effective over this range. An alternative is to cali-

brate the ADC’s full-scale range to 1/8 the readable PFS

value and use a right-shift value of 3. With this implemen-

tation, the resolution of the measurement is increased by

a factor of 8, and because the result is digitally divided

by 8 by right-shifting, the bit weight of the measurement

still meets the standard’s specification (i.e., SFF-8472).

cuitry is disabled. When V

reaches POA, the SEE is

CC

recalled, and the analog circuitry is enabled. While V

CC

remains above POA, the device is in its normal operating

state, and it responds based on its nonvolatile configu-

ration. If during operation V

falls below POA, but is

CC

still above POD, the SRAM retains the SEE settings from

the first SEE recall, but the device analog is shut down

and the outputs disabled. If the supply voltage recovers

back above POA, the device immediately resumes nor-

mal operation. If the supply voltage falls below POD, the

device SRAM is placed in its default state and another

SEE recall is required to reload the nonvolatile settings.

The EEPROM recall occurs the next time V

exceeds POA. Figure 5 shows the sequence of events

as the voltage varies.

2

Any time V

is above POD, the I C interface can be

CC

used to determine if V

is below the POA level. This

CC

is accomplished by checking the RDYB bit in the status

byte (Lower Memory, Register 6Eh). RDYB is set when

The right-shift operation on the ADC result is carried

out based on the contents of right-shift control registers

(Table 02h, Registers 8Eh-8Fh) in EEPROM. Four analog

channels—PMON1, PMON2, BMON1, and BMON2—

each have 3 bits allocated to set the number of right-

V

is below POA; when V

rises above POA, RDYB

CC

is timed (within 500Fs) to go to 0, at which point the part

is fully functional.

ONE ROUND-ROBIN ADC CYCLE

TEMP

V

BMON1

BMON2

PMON1

PMON2

TEMP

CC

t

RR

NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND V ONLY UNTIL V IS ABOVE THE VCC LO

CC

ALARM THRESHOLD. THIS ALSO OCCURS IF THERE ARE BOTH A TXD1 EVENT AND A TXD2 EVENT UNDER THE SAME CONDITIONS AS PREVIOUSLY MENTIONED.

Figure 4. ADC Round-Robin Timing

Maxim Integrated

15

DS1876

SFP Controller with Dual LDD Interface

SEE RECALL

V

POA

V

CC

V

POD

PRECHARGED

TO 0

PRECHARGED

TO 0

SEE

RECALLED VALUE

PRECHARGED TO 0

RECALLED VALUE

Figure 5. Low-Voltage Hysteresis Example

A delta-sigma DAC has a digital output using pulse-

density modulation. It provides much lower output ripple

than a standard digital PWM output given the same clock

3.24kΩ

DAC

VOLTAGE OUTPUT

0.01µF

rate and filter components. Before t

, the DAC outputs

INIT

0.01µF

are high impedance. The external RC filter components

are chosen based on ripple requirements, output load,

delta-sigma frequency, and desired response time.

Figure 6 shows a recommended filter.

DS1876

1kΩ

CURRENT SINK

For illustrative purposes, a 3-bit example is provided in

Figure 7.

0.1µF

2kΩ

In LUT mode the DACs are each controlled by an LUT

with high-temperature resolution and an OFFSET LUT

with lower temperature resolution. The high-resolution

LUTs each have 2NC resolutions. The OFFSET LUTs

are located in the upper eight registers (F8h-FFh) of

the table containing each high-resolution LUT. The DAC

values are determined as follows:

Figure 6. Recommended RC Filter for DAC Outputs in Voltage

Mode and Current Sink Mode

For all device addresses sourced from EEPROM (Table

02h, Register 8Bh), the default device addresses are

DAC value = LUT + 4 x (OFFSET LUT)

An example calculation for MOD1 DAC is as follows:

Assumptions:

A2h and B2h until V

exceeds POA allowing the device

CC

address to be recalled from the EEPROM.

1) Temperature is +43NC

Delta-Sigma Outputs

2) Table 04h (MOD1 OFFSET LUT), Register FCh = 2Ah

3) Table 04h (MOD1 LUT), Register AAh = 7Bh

Four delta-sigma outputs are provided: MOD1, MOD2,

APC1, and APC2. With the addition of an external RC

filter, these outputs provide 10-bit resolution analog

outputs with the full-scale range set by the input REFIN.

Each output is either manually controlled or controlled

using a temperature-indexed LUT.

Because the temperature is +43NC, the MOD1 LUT index

is AAh and the MOD1 OFFSET LUT index is FCh.

MOD1 DAC = 7Bh + 4 x 2Ah = 123h = 291

16

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

O

1

2

3

4

5

6

7

Figure 7. 3-Bit (8-Position) Delta-Sigma Example

DAC OFFSET LUTs (04h/06h)[A2h/B2h]

EIGHT REGISTERS PER DAC

DAC OFFSET LUTs (04h/06h)[A2h/B2h]

EIGHT REGISTERS PER DAC

EACH OFFSET REGISTER CAN BE INDEPENDENTLY

SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS

EXAMPLE ILLUSTRATES POSITIVE TEMPCO.

EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN

0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE

AND NEGATVE TEMPCO.

FFh

1023

767

511

255

0

1023

767

511

255

0

DAC

LUT

BITS

7:0

FEh

DAC

LUT

BITS

7:0

FDh

FCh

FEh

DAC

LUT

BITS

7:0

FFh

FBh

DAC

LUT

BITS

7:0

DAC

LUT

BITS

7:0

FCh

LUT

BITS

7:0

DAC

LUT

BITS

7:0

FAh

DAC

LUT

BITS

7:0

DAC

LUT

BITS

7:0

FBh

DAC

LUT

BITS

7:0

F9h

FAh

DAC

LUT

BITS

7:0

DAC

LUT

BITS

7:0

F9h

F8h

DAC

LUT

BITS

7:0

DAC

LUT

BITS

7:0

DAC

LUT

BITS

7:0

DAC

LUT

BITS

7:0

-40°C -8°C +8°C +24°C +40°C +56°C +70°C +88°C +104°C

Figure 8. DAC OFFSET LUTs

When temperature controlled, the DACs are updated

after each temperature conversion.

REFIN and its decoupling must be able to support the

edge rate requirements of the delta-sigma outputs. In

a typical application, a 0.1FF capacitor should be con-

nected between REFIN and ground.

The reference input, REFIN, is the supply voltage for the

output buffer of all four DACs. The voltage connected to

Maxim Integrated

17

DS1876

SFP Controller with Dual LDD Interface

V

CC

SET BIAS_ DAC AND

MOD_ DAC TO HIGH

IMPEDANCE

TXDS_

R

PU

TXD_

TXDIO_

TXDFG_

TXD_

TXDC_

R

S

C

D

Q

TXDOUT_

FETG_

TXP_ HI FLAG

TXP HI ENABLE

HBAL_ FLAG

TXDFLT_

HBAL ENABLE

TXFOUTS_

TXFINT

QTHEXT_

TXFOUTS1

TXFOUTS2

TXP_ LO FLAG

TXP LO ENABLE

TXFOUT

INVTXF_

TXF_

FAULT RESET TIMER

(130ms)

TXD (t

EXT INITR1

)

OUT

IN

TXFS_

POWER-ON

RESET

NOTE:

IN

_ CAN BE EITHER 1 OR 2 CORRESPONDING TO TRANSMITTERS 1 OR 2.

REFERS TO A PIN.

OUT

Figure 9. Logic Diagram 1

Register 89h). The open-drain RSELOUT output is

software controlled and/or inverted through the STATUS

register and CNFGA register (Table 02h, Register 88h).

External pullup resistors must be provided on OUT1 and

RSELOUT to realize high logic levels.

IN1S

OUT1

INVOUT1

IN1C

IN1

INVRSOUT

TXF1, TXF2, TXFOUT, TXD1, TXD2,

TXDOUT1, TXDOUT2

RSELOUT

RSELS

TXDOUT1 and TXDOUT2 are generated from a com-

bination of TXF1, TXF2, TXD1, TXD2, and the internal

signals FETG1 and FETG2 (Table 02h, Register 8Ah). A

software control identical to TXD1 and TXD2 is also avail-

able (TXDC1 and TXDC2, Lower Memory, Register 6Eh).

RSELC

RSEL

= PINS

Figure 10. Logic Diagram 2

A TXD1 or TXD2 pulse is internally extended (TXD

)

EXT

Digital I/O Pins

Six digital input pins and five digital output pins are pro-

vided for monitoring and control.

by time t

to inhibit the latching of low alarms and

INITR1

warnings related to the APC loop to allow for the loop to

stabilize. The nonlatching alarms and warnings are TXP

LO, BMON1 LO, BMON2 LO, PMON1 LO, and PMON2

LO. In addition, TXP LO is disabled from creating FETG.

See the Transmit Fault (TXFOUT) Output section for a

detailed explanation of TXFOUT. As shown in Figure 9,

the same signals and faults can also be used to gener-

ate the internal signal FETG. FETG is used to send a fast

“turn-off” command to the laser driver. The intended use

is a direct connection to the laser driver’s TXD1, TXD2

IN1, RSEL, OUT1, RSELOUT

Digital input pins IN1 and RSEL primarily serve to meet

the rate-select requirements of SFP and SFP+. They

can also serve as general-purpose inputs. OUT1 and

RSELOUT are driven by a combination of the IN1, RSEL,

and logic dictated by control registers in the EEPROM

(see Figure 10). The levels of IN1 and RSEL can be

read from the STATUS register (Lower Memory, Register

6Eh). The open-drain output OUT1 can be controlled

and/or inverted using the CNFGB register (Table 02h,

input if this is desired. When V

TXDOUT2 are high impedance.

< POA, TXDOUT1 and

CC

18

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

DETECTION OF TXFOUT FAULT

TXFOUT

Figure 11a. TXFOUT Nonlatched Operation

DETECTION OF TXFOUT FAULT

TXD_ OR TXFOUT RESET

TXFOUT

Figure 11b. TXFOUT Latched Operation

Transmit Fault (TXFOUT) Output

START Condition: A START condition is generated

by the master to initiate a new data transfer with a

slave. Transitioning SDA from high to low while SCL

remains high generates a START condition. See

Figure 12 for applicable timing.

TXFOUT can be triggered by all alarms, warnings, QTs,

TXD1, TXD2, TXF1, and TXF2 (see Figure 9). The six

ADC alarms and warnings are controlled by enable bits

(Table 01h/05h, Registers F8h and FCh). See Figures

11a and 11b for nonlatched and latched operation for

TXFOUT. The CNFGB register (Table 02h, Register 89h)

controls the latching of the alarms.

STOP Condition: A STOP condition is generated

by the master to end a data transfer with a slave.

Transitioning SDA from low to high while SCL remains

high generates a STOP condition. See Figure 12 for

applicable timing.

Die Identification

The DS1876 has an ID hardcoded in its memory. Two

registers (Table 02h, Registers 86h-87h) are assigned

for this feature. Register 86h reads 76h to identify the

part as the DS1876; Register 87h reads the present

device version.

Repeated START Condition: The master can use

a repeated START condition at the end of one data

transfer to indicate that it will immediately initiate a

new data transfer following the current one. Repeated

STARTs are commonly used during read operations

to identify a specific memory address to begin a data

transfer. A repeated START condition is issued identi-

cally to a normal START condition. See Figure 12 for

applicable timing.

2

I C Communication

2

I C Definitions

The following terminology is commonly used to describe

2

I C data transfers.

Bit Write: Transitions of SDA must occur during the

low state of SCL. The data on SDA must remain valid

and unchanged during the entire high pulse of SCL

plus the setup and hold time requirements (Figure 12).

Data is shifted into the device during the rising edge

of the SCL.

Master Device: The master device controls the slave

devices on the bus. The master device generates SCL

clock pulses and START and STOP conditions.

Slave Devices: Slave devices send and receive data

at the master’s request.

Bus Idle or Not Busy: Time between STOP and

START conditions when both SDA and SCL are inac-

tive and in their logic-high states.

Bit Read: At the end of a write operation, the master

must release the SDA bus line for the proper amount

of setup time (Figure 12) before the next rising edge

Maxim Integrated

19

DS1876

SFP Controller with Dual LDD Interface

of SCL during a bit read. The device shifts out each

bit of data on SDA at the falling edge of the previous

SCL pulse and the data bit is valid at the rising edge

of the current SCL pulse. Remember that the master

generates all SCL clock pulses, including when it is

reading bits from the slave.

bit read definition, and the master transmits an ACK

using the bit write definition to receive additional data

bytes. The master must NACK the last byte read to

terminate communication so the slave returns control

of SDA to the master.

2

Slave Address Byte: Each slave on the I C bus

Acknowledgement (ACK and NACK): An acknowl-

edgement (ACK) or not-acknowledge (NACK) is

always the 9th bit transmitted during a byte transfer.

The device receiving data (the master during a read

or the slave during a write operation) performs an ACK

by transmitting a zero during the 9th bit. A device per-

forms a NACK by transmitting a one during the 9th bit.

Timing (Figure 12) for the ACK and NACK is identical

to all other bit writes. An ACK is the acknowledgment

that the device is properly receiving data. A NACK is

used to terminate a read sequence or as an indication

that the device is not receiving data.

responds to a slave address byte sent immediately

following a START condition. The slave address byte

contains the slave address in the most significant 7bits

and the R/W bit in the least significant bit.

The DS1876 responds to three slave addresses. The

2

auxiliary memory always responds to a fixed I C slave

address, A0h. (If the main device’s slave address

is programmed to be A0h, access to the auxiliary

memory is disabled.) The Lower Memory and Tables

2

00h–06h respond to I C slave addresses whose lower

3 bits are configurable (A0h–AEh, B0h-BEh) using the

DEVICE ADDRESS byte (Table 02h, Register 8Bh). The

user also must set the ASEL bit (Table 02h, Register

88h) for this address to be active. By writing the cor-

rect slave address with R/W = 0, the master indicates

it writes data to the slave. If R/W = 1, the master reads

data from the slave. If an incorrect slave address is

written, the DS1876 assumes the master is communi-

Byte Write: A byte write consists of 8 bits of informa-

tion transferred from the master to the slave (most

significant bit first) plus a 1-bit acknowledgement from

the slave to the master. The 8 bits transmitted by the

master are done according to the bit write definition

and the acknowledgement is read using the bit read

definition.

2

cating with another I C device and ignores the com-

munications until the next START condition is sent.

Byte Read: A byte read is an 8-bit information transfer

from the slave to the master plus a 1-bit ACK or NACK

from the master to the slave. The 8 bits of information

that are transferred (most significant bit first) from the

slave to the master are read by the master using the

2

Memory Address: During an I C write operation

to the DS1876, the master must transmit a memory

address to identify the memory location where the

slave is to store the data. The memory address is

SDA

t

BUF

t

F

t

SP

t

HD:STA

t

LOW

SCL

t

HIGH

t

SU:STA

t

R

HD:STA

t

SU:STO

t

SU:DAT

HD:DAT

STOP

START

REPEATED

START

NOTE: TIMING IS REFERENCED TO V

AND V .

IH(MIN)

IL(MAX)

2

Figure 12. I C Timing

20

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

always the second byte transmitted during a write

operation following the slave address byte.

For example: A 3-byte write starts at address 06h and

writes three data bytes (11h, 22h, and 33h) to three

“consecutive” addresses. The result is that addresses

06h and 07h would contain 11h and 22h, respec-

tively, and the third data byte, 33h, would be written

to address 00h.

2

I C Protocol

2

See Figure 13 for an example of I C timing.

Writing a Single Byte to a Slave: The master must

generate a START condition, write the slave address

byte (R/W = 0), write the memory address, write

the byte of data, and generate a STOP condition.

Remember that the master must read the slave’s

acknowledgement during all byte write operations.

To prevent address wrapping from occurring, the

master must send a STOP condition at the end of

the page, then wait for the bus-free or EEPROM write

time to elapse. Then the master can generate a new

START condition and write the slave address byte

(R/W = 0) and the first memory address of the next

memory row before continuing to write data.

Writing Multiple Bytes to a Slave: To write multiple

bytes to a slave, the master generates a START condi-

tion, writes the slave address byte (R/W = 0), writes

the memory address, writes up to 8 data bytes, and

generates a STOP condition. The DS1876 writes 1 to

8 bytes (one page or row) with a single write trans-

action. This is internally controlled by an address

counter that allows data to be written to consecutive

addresses without transmitting a memory address

before each data byte is sent. The address counter

limits the write to one 8-byte page (one row of the

memory map). Attempts to write to additional pages

of memory without sending a STOP condition between

pages result in the address counter wrapping around

to the beginning of the present row.

Acknowledge Polling: Any time a EEPROM page is

written, the DS1876 requires the EEPROM write time

(t ) after the STOP condition to write the contents of

WR

the page to EEPROM. During the EEPROM write time,

the DS1876 does not acknowledge its slave address

because it is busy. It is possible to take advantage

of that phenomenon by repeatedly addressing the

DS1876, which allows the next page to be written

as soon as the DS1876 is ready to receive the data.

The alternative to acknowledge polling is to wait for

maximum period of t

to elapse before attempting

WR

to write again to the DS1876.

2

TYPICAL I C WRITE TRANSACTION

MSB

X

LSB

R/W

MSB

LSB

MSB

LSB

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

START

X

0

1

b7 b6 b5 b4 b3 b2 b1 b0

STOP

SLAVE

ADDRESS*

READ/

WRITE

REGISTER ADDRESS

DATA

*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h/B2h FOR THE MAIN MEMORY.

IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Bh FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED

ADDRESS FOR THE MAIN MEMORY IS A0h.

2

EXAMPLE I C TRANSACTIONS WITH A2h AS THE SLAVE ADDRESS

A2h

BAh

00h

A) SINGLE-BYTE WRITE

-WRITE 00h TO REGISTER BAh

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

START 1 0 1 0 0 0 1 0

1 0 1 1 1 0 1 0

0 0 0 0 0 0 0 0

STOP

A2h

BAh

A3h

1 0 1 0 0 0 1 1

DATA

B) SINGLE-BYTE READ

-READ REGISTER BAh

SLAVE

ACK

SLAVE

ACK

REPEATED

START

SLAVE

ACK

MASTER

NACK

START 1 0 1 0 0 0 1 0

1 0 1 1 1 0 1 0

DATA IN BAh

STOP

A2h

C8h

01h

75h

0 1 1 1 0 1 0 1

C) TWO-BYTE WRITE

-WRITE 01h AND 75h TO

REGISTERS C8h AND C9h

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

SLAVE

ACK

START 1 0 1 0 0 0 1 0

1 1 0 0 1 0 0 0

0 0 0 0 0 0 0 1

STOP

A2h

C8h

A3h

1 0 1 0 0 0 1 1

DATA

DATA IN C8h

DATA

DATA IN C9h

D) TWO-BYTE READ

-READ C8h AND C9h

SLAVE

ACK

SLAVE

ACK

REPEATED

START

SLAVE

ACK

MASTER

ACK

MASTER

NACK

START 1 0 1 0 0 0 1 0

1 1 0 0 1 0 0 0

STOP

2

Figure 13. Example I C Timing

Maxim Integrated

21

DS1876

SFP Controller with Dual LDD Interface

EEPROM Write Cycles: When EEPROM writes occur,

the DS1876 writes the whole EEPROM memory page,

even if only a single byte on the page was modified.

Writes that do not modify all 8 bytes on the page are

allowed and do not corrupt the remaining bytes of

memory on the same page. Because the whole page

is written, bytes on the page that were not modi-

fied during the transaction are still subject to a write

cycle. This can result in a whole page being worn

out over time by writing a single byte repeatedly.

Writing a page 1 byte at a time wears the EEPROM

out 8x faster than writing the entire page at once. The

DS1876’s EEPROM write cycles are specified in the

Nonvolatile Memory Characteristics table. The speci-

fication shown is at the worst-case temperature. It can

handle approximately 10x that many writes at room

temperature. Writing to SRAM-shadowed EEPROM

memory with SEEB = 1 does not count as a EEPROM

write cycle when evaluating the EEPROM’s estimated

lifetime.

Table 01h, A2h primarily contains user EEPROM (with

PW1 level access) as well as alarm and warning enable

bytes.

Table 02h, A2h/B2h is a multifunction space that con-

tains configuration registers, scaling and offset values,

passwords, and interrupt registers as well as other mis-

cellaneous control bytes. All functions and status can be

written and read from either A2h or B2h addresses.

Table 04h, A2h contains a temperature-indexed LUT for

control of the MOD1 voltage. The MOD1 LUT can be pro-

grammed in 2NC increments over the -40NC to +102NC

range. This also contains a temperature-indexed LUT for

the MOD1 offsets.

Table 05h, A2h is empty by default. It can be config-

ured to contain the alarm and warning enable bytes

from Table 01h, Registers F8h–FFh with the MASK bit

enabled (Table 02h, Register 88h). In this case Table

01h is empty.

Table 06h, A2h contains a temperature-indexed LUT for

control of the APC1 voltage. The APC1 LUT can be pro-

grammed in 2NC increments over the -40NC to +102NC

range. This also contains a temperature-indexed LUT for

the APC1 offsets.

Reading a Single Byte from a Slave: Unlike the

write operation that uses the memory address byte

to define where the data is to be written, the read

operation occurs at the present value of the memory

address counter. To read a single byte from the slave,

the master generates a START condition, writes the

slave address byte with R/W = 1, reads the data byte

with a NACK to indicate the end of the transfer, and

generates a STOP condition.

The main device located at B2h is used for transmitter 2

control, calibration, alarms, warnings, and monitoring.

Lower Memory, B2h is addressed from 00h–7Fh and

contains alarm and warning thresholds, flags, masks,

several control registers, PWE, and the table-select byte.

Manipulating the Address Counter for Reads: A

dummy write cycle can be used to force the address

pointer to a particular value. To do this, the mas-

ter generates a START condition, writes the slave

address byte (R/W = 0), writes the memory address

where it desires to read, generates a repeated START

condition, writes the slave address byte (R/W = 1),

reads data with ACK or NACK as applicable, and

generates a STOP condition.

Table 01h, B2h contains alarm and warning enable

bytes.

Table 04h, B2h contains a temperature-indexed LUT for

control of the MOD2 voltage. The MOD2 LUT can be pro-

grammed in 2NC increments over the -40NC to +102NC

range. This also contains a temperature-indexed LUT for

the MOD2 offsets.

Table 05h, B2h is empty by default. It can be config-

ured to contain the alarm and warning enable bytes

from Table 01h, Registers F8h–FFh with the MASK bit

enabled (Table 02h, Register 88h). In this case Table

01h is empty.

Memory Organization

The DS1876 features nine separate memory tables

that are internally organized into 8-byte rows. The main

device located at A2h is used for overall device con-

figuration and transmitter 1 control, calibration, alarms,

warnings, and monitoring.

Table 06h, B2h contains a temperature-indexed LUT for

control of the APC2 voltage. The APC2 LUT can be pro-

grammed in 2NC increments over the -40NC to +102NC

range. This also contains a temperature-indexed LUT for

the APC2 offsets.

Lower Memory, A2h is addressed from 00h–7Fh and

contains alarm and warning thresholds, flags, masks,

several control registers, password entry area (PWE),

and the table-select byte.

22

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

2

I C ADDRESS A0h

00h

I C ADDRESS A2h/B2h

00h

LOWER

MEMORY

2

NOTE 1: IF ASEL = 0, THEN THE MAIN DEVICE I C SLAVE ADDRESS IS A2h/B2h.

IF ASEL = 1, THEN THE MAIN DEVICE I C SLAVE ADDRESS IS DETERMINED BY THE VALUE IN

TABLE 02h, REGISTER 8Bh.

NOTE 2: TABLE 00h DOES NOT EXIST.

NOTE 3: ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING THE

MASK BIT IN TABLE 02h, REGISTER 88h.

PASSWORD ENTRY

(PWE) (4 BYTES)

TABLE-SELECT

BYTE

7Fh

EEPROM

(256 BYTES)

80h

TABLE 04h

TABLE 06h

TABLE 02h

ALARM-ENABLE ROW

CAN BE CONFIGURED

TO EXIST AT TABLE 01h

OR TABLE 05h USING

MASK BIT IN TABLE 02h,

REGISTER 88h.

TABLE 01h

(A2h ONLY)

MOD1 (A2h)

MOD2 (B2h)

LOOKUP TABLE

(72 BYTES)

APC1 (A2h)

APC2 (B2h)

LOOKUP TABLE

(72 BYTES)

NONLOOKUP

TABLE CONTROL

AND

CONFIGURATION

REGISTERS

EEPROM

(120 BYTES)

C7h

F7h

FFh

(B2h ONLY CONTAINS

TRANSMITTER 2-

RELATED REGISTERS)

E0h

F8h

(APC1/2, HBATH1/2,

TXP HI 1/2, TXP LO 1/2)

TABLE 05h

ALARM-

ENABLE ROW

(8 BYTES)

MOD1/2

OFFSET LUT

ALARM-ENABLE ROW

OFFSET LUT

(8 BYTES)

FFh

Figure 14. Memory Map

Auxiliary Memory (Device A0h) contains 256 bytes

of EE memory accessible from address 00h–FFh. It is

selected with the device address of A0h.

SEEB, is not set and these locations act as ordinary

EEPROM. By setting SEEB, these locations function

like SRAM cells, which allow an infinite number of write

cycles without concern of wearing out the EEPROM.

This also eliminates the requirement for the EEPROM

See the Register Descriptions section for a more com-

plete detail of each byte’s function, as well as for read/

write permissions for each byte.

write time, t . Because changes made with SEEB

WR

enabled do not affect the EEPROM, these changes are

not retained through power cycles. The power-on value

is the last value written with SEEB disabled. This func-

tion can be used to limit the number of EEPROM writes

during calibration or to change the monitor thresholds

periodically during normal operation helping to reduce

the number of times EEPROM is written. Figure 14 shows

the memory map and indicates which locations are

shadowed EEPROM.

Shadowed EEPROM

Many nonvolatile memory locations (listed within the

Register Descriptions section) are actually shadowed

EEPROM and are controlled by the SEEB bit in Table

02h, Register 80h.

The DS1876 incorporates shadowed EEPROM memory

locations for key memory addresses that can be writ-

ten many times. By default the shadowed EEPROM bit,

Maxim Integrated

23

DS1876

SFP Controller with Dual LDD Interface

Memory Map Access Codes

Register Descriptions

The following section provides the DS1876 register defi-

nitions. Each register or row of registers has an access

descriptor that determines the password level required

to read or write the memory. Level 2 password is

intended for the module manufacture access only. Level

1 password allows another level of protection for items

the end consumer wishes to protect. Many registers are

always readable, but require password access to write.

There are a few registers that cannot be read without

password access. The following access codes describe

each mode used by the DS1876 with factory settings for

the PW_ENA and PW_ENB (Table 02h, Registers C0h–

C1h) registers.

The register maps show each byte/word (2 bytes) in

terms of its row in the memory. The first byte in the row

is located in memory at the row address (hexadecimal)

in the leftmost column. Each subsequent byte on the row

is one/two memory locations beyond the previous byte/

word’s address. A total of 8 bytes are present on each

row. For more information about each of these bytes, see

the corresponding register description.

ACCESS CODE

READ ACCESS

WRITE ACCESS

At least 1 byte/bit in the row/byte is different than the rest of the row/byte, so look at each byte/bit

separately for permissions.

<0/_>

<1/_>

<2/_>

Read all

Write PW2

Write not applicable

Write all, but the DS1876 hardware also writes to

these bytes/bits

<3/_>

Read all

<4/_>

<5/_>

<6/_>

<7/_>

<8/_>

<9/_>

<10/_>

<11/_>

Read PW2

Read all

Write PW2 + mode_bit

Write all

Read not applicable

Read PW1

Write all

Write PW1

Read PW2

Write PW2

Read not applicable

Read PW2

Write PW2

Write not applicable

Write PW1

Read all

using A2h. Transmitter 2 is accessed using B2h. Many

of the registers in A2h and B2h are shared registers.

These registers can be read and written from both A2h

and B2h.

Memory Addresses A0h, A2h, and B2h

2

There are three separate I C addresses in the DS1876:

A0h, A2h, and B2h. A2h and B2h are used to configure

and monitor two transmitters. Transmitter 1 is accessed

MEMORY CODE

A2h AND B2h REGISTERS

A common memory location is used for A2h and B2h device addresses. Reading or writing to these

locations is identical, regardless of using A2h or B2h addresses.

Different memory locations are used for A2h and B2h device addresses.

Mixture of common and different memory locations for A2h and B2h device addresses. See the individual

bytes within the row for clarification. If “M” is used on an individual byte, see the expanded bit descriptions

to determine which bits are common vs. different.

24

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Lower Memory Register Map

LOWER MEMORY

WORD 0

WORD 1

BYTE 2/A BYTE 3/B

TEMP ALARM LO

ALARM LO

WORD 2

BYTE 4/C BYTE 5/D

TEMP WARN HI

WARN HI

WORD 3

ROW

(HEX)

ROW NAME

BYTE 0/8

TEMP ALARM HI

ALARM HI

BYTE 1/9

BYTE 6/E

TEMP WARN LO

WARN LO

BYTE 7/F

<1/C>

00

08

THRESHOLD

0

<1/C >

<1/D>

THRESHOLD

V

CC

1

2

3

CC

10

THRESHOLD

BMON ALARM HI

BMON ALARM LO

BMON WARN HI

BMON WARN LO

18

PMON ALARM HI

PMON ALARM LO

PMON WARN HI

PMON WARN LO

<1/C >

20–40

48–50

58

EEPROM

EE

<1/D >

<1/C >

EE

TEMP VALUE

RESERVED

ALARM

EE

VALUE

EE

BMON VALUE

RESERVED

WARN RESERVED

3

EE

<2/M>

<0/M>

<5/D>

<0/M>

<C>

<D>

60

ADC VALUES

V

PMON VALUE

<3/D>

0

1

CC

RESERVED

<0/M>

68

STATUS

RESERVED

PWE LSW

UPDATE

70

ALARM/WARN

TABLE SELECT

ALARM

RESERVED

3

2

1

<6/C>

<5/D>

78

RESERVED

PWE MSW

TBL SEL

<C> or <_/C> = Common, <D> or <_/D> = Different, <M> or <_/M> = Mixture of common and different.

Table 01h Register Map

TABLE 01h

WORD 1

WORD 0

WORD 2

WORD 3

ROW

(HEX)

ROW NAME

BYTE 0/8

BYTE 1/9

EE

BYTE 2/A

BYTE 3/B

BYTE 4/C

BYTE 5/D

EE

BYTE 6/E

EE

BYTE 7/F

EE

<1/C>

80–F7

F8

EEPROM

EE

<7/M>

<M>

<D>

<M>

ALARM ENABLE

ALARM EN

RESERVED

ALARM EN

RESERVED

WARN EN

3

RESERVED

3

1

<C> or <_/C> = Common, <D> or <_/D> = Different, <M> or <_/M> = Mixture of common and different.

Note: The ALARM ENABLE bytes (Registers F8h–FFh) can be configured to exist in Table 05h instead of here at Table 01h with

the MASK bit (Table 02h, Register 88h). If the row is configured to exist in Table 05h, these location are empty in Table 01h.

The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).

These registers also allow for custom permissions.

ACCESS

CODE

<0/_>

<1/_>

<2/_>

<3/_>

<4/_>

<5/_>

<6/_>

<7/_>

<8/_>

<9/_>

<10/_> <11/_>

Read

Access

All

PW2

All

N/A

PW1

PW2

N/A

PW2

N/A

All

See each

bit/byte

separately

All and

DS1876

Hardware

PW2 +

mode

bit

Write

Access

PW2

N/A

All

PW1

PW2

PW1

Maxim Integrated

25

DS1876

SFP Controller with Dual LDD Interface

Table 02h Register Map

TABLE 02h (PW2)

WORD 1

WORD 0

WORD 2

BYTE 4/C

RESERVED

RANGING

WORD 3

ROW

(HEX)

ROW NAME

BYTE 0/8

BYTE 1/9

BYTE 2/A

BYTE 3/B

RESERVED

BYTE 5/D

BYTE 6/E

BYTE 7/F

<0/C>

<8/C>

<4/C>

<10>

80

88

CONFIG

MODE

TINDEX

CNFGB

RESERVED

BMON2 SCALE

RESERVED

CNFGC

RESERVED

DEVICE ID

DEVICE VER

0

1

<8/C>

CNFGA

DEVICE ADDRESS

SCALE

CC

RANGING

RSHIFT

1

2

1

2

90

SCALE

V

RESERVED

BMON1 SCALE

RESERVED

0

98

PMON2 SCALE

OFFSET

PMON1 SCALE

RESERVED

1

A0

OFFSET

INTERNAL TEMP OFFSET*

BMON2 OFFSET

PW1 MSW

V

CC

0

1

A8

PMON2 OFFSET

PW1 LSW

BMON1 OFFSET

PW2 MSW

PMON1 OFFSET

PW2 LSW

<9/C>

<8/C>

<4/C>

B0

PWD VALUE

THRESHOLD

PWD ENABLE

DAC VALUES

EMPTY

B8

RESERVED

PW_ENA

HBIAS2 DAC

PW_ENB

HTXP2 DAC

LTXP2 DAC

RESERVED

HBIAS1 DAC

RESERVED

HTXP1 DAC

POLARITY

LTXP1 DAC

TBLSELPON

C0

RESERVED

C8

MOD2 DAC

APC2 DAC

MOD1 DAC

APC1 DAC

D0–FF

EMPTY

<C> or <_/C> = Common, <D> or <_/D> = Different, <M> or <_/M> = Mixture of common and different.

*The final result must be XORed with BB40h before writing to this register.

Table 04h Register Map

TABLE 04h (MODULATION LUT)

WORD 1

WORD 0

WORD 2

WORD 3

ROW

(HEX)

ROW NAME

BYTE 0/8

MOD

BYTE 1/9

MOD

BYTE 2/A

MOD

BYTE 3/B

MOD

BYTE 4/C

MOD

BYTE 5/D

MOD

BYTE 6/E

MOD

BYTE 7/F

MOD

<8/D>

LUT4

80–C7

C8–F7

EMPTY

MOD OFFSET

LUT

MOD OFFSET

LUT

MOD OFFSET

LUT

MOD OFFSET

LUT

MOD OFFSET

LUT

MOD OFFSET

LUT

MOD OFFSET

LUT

MOD OFFSET

LUT

<8/D>

F8

MOD OFFSET

<C> or <_/C> = Common, <D> or <_/D> = Different, <M> or <_/M> = Mixture of common and different.

The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).

These registers also allow for custom permissions.

ACCESS

CODE

<0/_>

<1/_>

<2/_>

<3/_>

<4/_>

<5/_>

<6/_>

<7/_>

<8/_>

<9/_>

<10/_> <11/_>

Read

Access

All

PW2

All

N/A

PW1

PW2

N/A

PW2

N/A

All

See each

bit/byte

separately

All and

DS1876

Hardware

PW2 +

mode

bit

Write

Access

PW2

N/A

All

PW1

PW2

PW1

26

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 05h Register Map

TABLE 05h

WORD 0

WORD 1

WORD 2

WORD 3

ROW

(HEX)

ROW NAME

BYTE 0/8

BYTE 1/9

EMPTY

BYTE 2/A

BYTE 3/B

EMPTY

BYTE 4/C

BYTE 5/D

EMPTY

BYTE 6/E

BYTE 7/F

EMPTY

80–F7

F8

EMPTY

<7/M>

<M>

<D>

<M>

ALARM ENABLE

ALARM EN

RESERVED

ALARM EN

RESERVED

WARN EN

3

RESERVED

3

1

<C> or <_/C> = Common, <D> or <_/D> = Different, <M> or <_/M> = Mixture of common and different.

Note: Table 05h is empty by default. It can be configured to contain the alarm and warning enable bytes from Table 01h,

Registers F8h–FFh with the MASK bit enabled (Table 02h, Register 88h). In this case Table 01h is empty.

Table 06h Register Map

TABLE 06h (APC LUT)

WORD 1

WORD 0

WORD 2

WORD 3

ROW

(HEX)

ROW NAME

BYTE 0/8

APC LUT

EMPTY

BYTE 1/9

APC LUT

EMPTY

BYTE 2/A

BYTE 3/B

APC LUT

EMPTY

BYTE 4/C

APC LUT

EMPTY

BYTE 5/D

APC LUT

EMPTY

BYTE 6/E

APC LUT

EMPTY

BYTE 7/F

APC LUT

EMPTY

<8/D>

LUT6

80–C7

C8–DF

E0

APC LUT

EMPTY

<8/D>

HBATH

HBATH LUT

HTXP LUT

LTXP LUT

HBATH LUT

HTXP LUT

LTXP LUT

HBATH LUT

HTXP LUT

LTXP LUT

HBATH LUT

HTXP LUT

LTXP LUT

HBATH LUT

HTXP LUT

LTXP LUT

HBATH LUT

HTXP LUT

LTXP LUT

HBATH LUT

HTXP LUT

LTXP LUT

HBATH LUT

HTXP LUT

LTXP LUT

<8/D>

HTXP

E8

<8/D>

LTXP

F0

APC OFFSET

LUT

APC OFFSET

LUT

APC OFFSET

LUT

APC OFFSET

LUT

APC OFFSET

LUT

APC OFFSET

LUT

APC OFFSET

LUT

APC OFFSET

LUT

<8/D>

F8

APC OFFSET

<C> or <_/C> = Common, <D> or <_/D> = Different, <M> or <_/M> = Mixture of common and different.

Auxiliary Memory A0h Register Map

AUXILIARY MEMORY (A0h)

WORD 1

WORD 0

WORD 2

BYTE 4/C

WORD 3

ROW

(HEX)

ROW NAME

BYTE 0/8

BYTE 1/9

BYTE 2/A

BYTE 3/B

BYTE 5/D

BYTE 6/E

BYTE 7/F

<5>

00–7F

80–FF

AUX EE

EE

<5>

AUX EE

<C> or <_/C> = Common, <D> or <_/D> = Different, <M> or <_/M> = Mixture of common and different.

The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).

These registers also allow for custom permissions.

ACCESS

CODE

<0/_>

<1/_>

<2/_>

<3/_>

<4/_>

<5/_>

<6/_>

<7/_>

<8/_>

<9/_>

<10/_> <11/_>

Read

Access

All

PW2

All

N/A

PW1

PW2

N/A

PW2

N/A

All

See each

bit/byte

separately

All and

DS1876

Hardware

PW2 +

mode

bit

Write

Access

PW2

N/A

All

PW1

PW2

PW1

Maxim Integrated

27

DS1876

SFP Controller with Dual LDD Interface

Lower Memory Register Descriptions

Lower Memory, Register 00h–01h: TEMP ALARM HI

Lower Memory, Register 04h–05h: TEMP WARN HI

FACTORY DEFAULT

READ ACCESS

7FFFh

All

WRITE ACCESS

PW2 or (PW1 and WLOWER)

Common A2h and B2h memory location

Nonvolatile (SEE)

A2h AND B2h MEMORY

MEMORY TYPE

6

5

4

3

2

1

0

00h, 04h

01h, 05h

S

2

-1

-2

-3

-4

-5

-6

-7

-8

2

BIT 7

BIT 0

Temperature measurement updates above this two’s complement threshold set its corresponding alarm or

warning bit. Temperature measurement updates equal to or below this threshold clear its alarm or warning bit.

Lower Memory, Register 02h–03h: TEMP ALARM LO

Lower Memory, Register 06h–07h: TEMP WARN LO

FACTORY DEFAULT

READ ACCESS

8000h

All

WRITE ACCESS

PW2 or (PW1 and WLOWER)

Common A2h and B2h memory location

Nonvolatile (SEE)

A2h AND B2h MEMORY

MEMORY TYPE

6

5

4

3

2

1

0

02h, 06h

03h, 07h

S

2

-1

-2

-3

-4

-5

-6

-7

-8

2

BIT 7

BIT 0

Temperature measurement updates below this two’s complement threshold set its corresponding alarm or

warning bit. Temperature measurement updates equal to or above this threshold clear its alarm or warning bit.

28

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 08h–09h: V

ALARM HI

WARN HI

CC

Lower Memory, Register 0Ch–0Dh: V

CC

FACTORY DEFAULT

READ ACCESS

FFFFh

All

WRITE ACCESS

PW2 or (PW1 and WLOWER)

Common A2h and B2h memory location

Nonvolatile (SEE)

A2h AND B2h MEMORY

MEMORY TYPE

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

08h, 0Ch

09h, 0Dh

2

BIT 7

BIT 0

Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit.

Voltage measurements equal to or below this threshold clear its alarm or warning bit.

Lower Memory, Register 0Ah–0Bh: V

ALARM LO

WARN LO

CC

Lower Memory, Register 0Eh–0Fh: V

CC

FACTORY DEFAULT

READ ACCESS

0000h

All

WRITE ACCESS

PW2 or (PW1 and WLOWER)

Common A2h and B2h memory location

Nonvolatile (SEE)

A2h AND B2h MEMORY

MEMORY TYPE

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

0Ah, 0Eh

0Bh, 0Fh

2

BIT 7

BIT 0

Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage

measurements equal to or above this threshold clear its alarm or warning bit.

Maxim Integrated

29

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 10h–11h: BMON ALARM HI

Lower Memory, Register 14h–15h: BMON WARN HI

Lower Memory, Register 18h–19h: PMON ALARM HI

Lower Memory, Register 1Ch–1Dh: PMON WARN HI

FACTORY DEFAULT

READ ACCESS

FFFFh

All

WRITE ACCESS

PW2 or (PW1 and WLOWER)

Different A2h and B2h memory locations

Nonvolatile (SEE)

A2h AND B2h MEMORY

MEMORY TYPE

10h, 14h,

18h, 1Ch

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

2

11h, 15h,

19h, 1Dh

2

BIT 7

BIT 0

Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit.

Voltage measurements equal to or below this threshold clear its alarm or warning bit.

Lower Memory, Register 12h–13h: BMON ALARM LO

Lower Memory, Register 16h–17h: BMON WARN LO

Lower Memory, Register 1Ah–1Bh: PMON ALARM LO

Lower Memory, Register 1Eh–1Fh: PMON WARN LO

FACTORY DEFAULT

READ ACCESS

0000h

All

WRITE ACCESS

PW2 or (PW1 and WLOWER)

Different A2h and B2h memory locations

Nonvolatile (SEE)

A2h AND B2h MEMORY

MEMORY TYPE

12h, 16h,

1Ah, 1Eh

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

2

13h, 17h,

1Bh, 1Fh

2

BIT 7

BIT 0

Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage

measurements equal to or above this threshold clear its alarm or warning bit.

30

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 20h–47h: EE

FACTORY DEFAULT

READ ACCESS

00h

All

WRITE ACCESS

PW2 or (PW1 and WLOWER)

Common A2h and B2h memory location

Nonvolatile (EE)

A2h AND B2h MEMORY

MEMORY TYPE

20h–47h

EE

BIT 7

BIT 0

PW2 level access-controlled EEPROM.

Lower Memory, Register 48h–57h: EE

FACTORY DEFAULT

READ ACCESS

00h

All

PW2 or (PW1 and WLOWER)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

Different A2h and B2h memory locations

Nonvolatile (EE)

48h–57h

EE

BIT 7

BIT 0

PW2 level access-controlled EEPROM.

Lower Memory, Register 58h–5Fh: EE

FACTORY DEFAULT

READ ACCESS

00h

All

PW2 or (PW1 and WLOWER)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

Common A2h and B2h memory location

Nonvolatile (EE)

58h–5Fh

EE

BIT 7

BIT 0

PW2 level access-controlled EEPROM.

Maxim Integrated

31

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 60h–61h: TEMP VALUE

FACTORY DEFAULT

READ ACCESS

0000h

All

WRITE ACCESS

N/A

A2h AND B2h MEMORY

MEMORY TYPE

Common A2h and B2h memory location

Volatile

6

5

4

3

2

1

0

60h

61h

S

2

-1

-2

-3

-4

-5

-6

-7

-8

2

BIT 7

BIT 0

Signed two’s complement direct-to-temperature measurement.

Lower Memory, Register 62h–63h: V

VALUE

CC

POWER-ON VALUE

READ ACCESS

0000h

All

WRITE ACCESS

N/A

A2h AND B2h MEMORY

MEMORY TYPE

Common A2h and B2h memory location

Volatile

15

7

14

6

13

5

12

4

11

3

10

9

8

62h

63h

2

1

0

2

BIT 7

BIT 0

Left-justified unsigned voltage measurement.

32

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 64h–65h: BMON VALUE

Lower Memory, Register 66h–67h: PMON VALUE

POWER-ON VALUE

READ ACCESS

0000h

All

WRITE ACCESS

N/A

A2h AND B2h MEMORY

MEMORY TYPE

Different A2h and B2h memory locations

Volatile

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

64h, 66h

65h, 67h

2

BIT 7

BIT 0

Left-justified unsigned voltage measurement.

Lower Memory, Register 68h–6Dh: RESERVED

POWER-ON VALUE

READ ACCESS

N/A

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

68h, 6Dh

0

BIT 7

BIT 0

These registers are reserved. The value when read is 00h.

Maxim Integrated

33

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 6Eh: STATUS

POWER-ON VALUE

READ ACCESS

X0XX 0XXXb

All

WRITE ACCESS

See below

A2h AND B2h MEMORY Mixture of common memory locations and different memory locations (see below)

MEMORY TYPE

Volatile

Write Access

6Eh

N/A

All

N/A

<C>

All

N/A

<D>

<C>

<D>

<C>

TXDS

BIT 7

TXDC

IN1S

RSELS

RSELC

TXFS

RAM

RDYB

BIT 0

TXDS1 [A2h]: TXD1 status bit. Reflects the logic state of the TXD1 pin (read-only).

0 = TXD1 pin is logic-low.

1 = TXD1 pin is logic-high.

TXDS2 [B2h]: TXD2 status bit. Reflects the logic state of the TXD2 pin (read-only).

0 = TXD2 pin is logic-low.

BIT 7

1 = TXD2 pin is logic-high.

TXDC1 [A2h]: TXD1 software control bit. This bit allows for software control that is identical to the

TXD1 pin. See the DACs as a Function of Transmit Disable (TXD1, TXD2) section for further infor-

mation. Its value is wire-ORed with the logic value of the TXD1 pin (writable by all users).

0 = (default)

1 = Forces the device into a TXD1 state regardless of the value of the TXD1 pin.

TXDC2 [B2h]: TXD2 software control bit. This bit allows for software control that is identical to the

TXD2 pin. See the DACs as a Function of Transmit Disable (TXD1, TXD2) section for further infor-

mation. Its value is wire-ORed with the logic value of the TXD2 pin (writable by all users).

0 = (default)

BIT 6

1 = Forces the device into a TXD2 state regardless of the value of the TXD2 pin.

IN1S [A2h or B2h]: IN1 status bit. Reflects the logic state of the IN1 pin (read-only).

0 = IN1 pin is logic-low.

1 = IN1 pin is logic-high.

BIT 5

BIT 4

RSELS [A2h or B2h]: RSEL status bit. Reflects the logic state of the RSEL pin (read-only).

0 = RSEL pin is logic-low.

1 = RSEL pin is logic-high.

RSELC [A2h or B2h]: RSEL software control bit. This bit allows for software control that is iden-

tical to the RSEL pin. Its value is wire-ORed with the logic value of the RSEL pin to create the

RSELOUT pin’s logic value (writable by all users).

BIT 3

BIT 2

0 = (default)

1 = Forces the device into a RSEL state regardless of the value of the RSEL pin.

TXFS1 [A2h]: Reflects state of the TXF1 pin (read-only).

0 = TXF1 pin is low.

1 = TXF1 pin is high.

TXFS2 [B2h]: Reflects the state of the TXF2 pin (read-only).

0 = TXF2 pin is low.

1 = TXF2 pin is high.

RAM1 [A2h]: Volatile memory location.

RAM2 [B2h]: Volatile memory location.

BIT 1

BIT 0

RDYB [A2h or B2h]: Ready bar.

0 = V

1 = V

is above POA.

CC

2

is below POA and/or too low to communicate over the I C bus.

34

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 6Fh: UPDATE

POWER-ON VALUE

READ ACCESS

00h

All

WRITE ACCESS

All and DS1876 hardware

A2h AND B2h MEMORY Different A2h and B2h memory locations

MEMORY TYPE

Volatile

TEMP

RDY

BMON

RDY

PMON

RDY

6Fh

VCC RDY

RESERVED

BIT 0

BIT 7

TEMP RDY, VCC RDY, BMON RDY, PMON RDY: Update of completed conversions. At power-on,

these bits are cleared and are set as each conversion is completed. These bits can be cleared so

that a completion of a new conversion is verified.

BITS 7:4

BITS 3:0

RESERVED

Maxim Integrated

35

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 70h: ALARM

3

POWER-ON VALUE

READ ACCESS

10h

All

WRITE ACCESS

N/A

A2h AND B2h MEMORY

MEMORY TYPE

Different A2h and B2h memory locations

Volatile

70h

TEMP HI

BIT 7

TEMP LO

VCC HI

VCC LO

BMON HI

BMON LO

PMON HI

PMON LO

BIT 0

TEMP HI: High alarm status for temperature measurement.

0 = (default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 7

BIT 6

BIT 5

TEMP LO: Low alarm status for temperature measurement.

0 = (default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

VCC HI: High alarm status for V

measurement.

CC

0 = (default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

VCC LO: Low alarm status for V

measurement. This bit is set when the V

supply is below

CC

the POA trip point value. It clears itself when a V

above the low threshold.

measurement is completed and the value is

CC

BIT 4

0 = Last measurement was equal to or above threshold setting.

1 = (default) Last measurement was below threshold setting.

BMON HI: High alarm status for BMON measurement.

0 = (default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 3

BIT 2

BIT 1

BIT 0

BMON LO: Low alarm status for BMON measurement.

0 = (default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

PMON HI: High alarm status for PMON measurement.

0 = (default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

PMON LO: Low alarm status for PMON measurement.

0 = (default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

36

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 71h: ALARM

2

POWER-ON VALUE

READ ACCESS

00h

All

WRITE ACCESS

N/A

A2h AND B2h MEMORY

MEMORY TYPE

Mixed A2h and B2h memory locations

Volatile

71h RESERVED

RESERVED

^<C>TXFOUTS

^<D>FETG

^<D>TXFINT

BIT 0

BIT 7

BITS 7:3

BIT 2

TXFOUTS: TXFOUT status. Indicates the state the open-drain output is attempting to achieve.

0 = TXFOUT is pulling low.

1 = TXFOUT is high impedance.

FETG: Status of internal signal FETG. The FETG signal is part of the internal shutdown logic.

BIT 1

BIT 0

0 = (default) FETG is low.

1 = FETG is high.

TXFINT: TXF interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with

their corresponding enable bits, plus the wire-ORed logic of HBAL, TXP HI, and TXP LO. The enable

bits are found in Table 01h/05h, Registers F8h–FFh.

Lower Memory, Register 72h: ALARM

1

POWER-ON VALUE

READ ACCESS

00h

All

WRITE ACCESS

N/A

A2h AND B2h MEMORY

MEMORY TYPE

Different A2h and B2h memory locations

Volatile

72h RESERVED

BIT 7

RESERVED

HBAL

RESERVED

TXP HI

TXP LO

BIT 0

BITS 7:4, 2 RESERVED

HBAL: High bias alarm status; fast comparison. A TXD event clears this alarm.

0 = (default) Last comparison was below threshold setting.

1 = Last comparison was above threshold setting.

BIT 3

BIT 1

BIT 0

TXP HI: High alarm status TXP; fast comparison. A TXD event clears this alarm.

0 = (default) Last comparison was below threshold setting.

1 = Last comparison was above threshold setting.

TXP LO: Low alarm status TXP; fast comparison. A TXD event clears this alarm.

0 = (default) Last comparison was above threshold setting.

1 = Last comparison was below threshold setting.

Maxim Integrated

37

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 73h: RESERVED

POWER-ON VALUE

READ ACCESS

N/A

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

This register is reserved.

Lower Memory, Register 74h: WARN

3

POWER-ON VALUE

READ ACCESS

10h

All

WRITE ACCESS

N/A

A2h AND B2h MEMORY

MEMORY TYPE

Different A2h and B2h memory locations

Volatile

74h

TEMP HI

BIT 7

TEMP LO

VCC HI

VCC LO

BMON HI

BMON LO

PMON HI

PMON LO

BIT 0

TEMP HI: High warning status for temperature measurement.

0 = (default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 7

BIT 6

BIT 5

TEMP LO: Low warning status for temperature measurement.

0 = (default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

VCC HI: High warning status for V

measurement.

CC

0 = (default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

VCC LO: Low warning status for V

measurement. This bit is set when the V

supply is below

CC

the POA trip-point value. It clears itself when a V

above the low threshold.

measurement is completed and the value is

CC

BIT 4

0 = Last measurement was equal to or above threshold setting.

1 = (default) Last measurement was below threshold setting.

BMON HI: High warning status for BMON measurement.

0 = (default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 3

BIT 2

BIT 1

BIT 0

BMON LO: Low warning status for BMON measurement.

0 = (default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

PMON HI: High warning status for PMON measurement.

0 = (default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

PMON LO: Low warning status for PMON measurement.

0 = (default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

38

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Registers 75h–7Ah: RESERVED MEMORY

POWER-ON VALUE

READ ACCESS

N/A

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

These registers are reserved. The value when read is 00h.

Lower Memory, Registers 7Bh–7Eh: PASSWORD ENTRY (PWE)

POWER-ON VALUE

READ ACCESS

FFFF FFFFh

N/A

WRITE ACCESS

All

A2h AND B2h MEMORY

MEMORY TYPE

Common A2h and B2h memory location

Volatile

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

7Bh

7Ch

7Dh

7Eh

2

1

0

2

BIT 7

BIT 0

There are two passwords for the DS1876. Each password is 4 bytes long. The lower level password (PW1) has

all the access of a normal user plus those made available with PW1. The higher level password (PW2) has all the

access of PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside PW2

memory. At power-up, all PWE bits are set to 1. All reads at this location are 0.

Maxim Integrated

39

DS1876

SFP Controller with Dual LDD Interface

Lower Memory, Register 7Fh: TABLE SELECT (TBL SEL)

POWER-ON VALUE

READ ACCESS

TBLSELPON (Table 02h, Register C7h)

All

WRITE ACCESS

All

A2h AND B2h MEMORY

MEMORY TYPE

Different A2h and B2h memory locations

Volatile

7

6

5

4

3

2

1

0

7Fh

2

BIT 7

BIT 0

The upper memory tables of the DS1876 are accessible by writing the desired table value in this register. The

power-on value of this register is defined by the value written to TBLSELPON (Table 02h, Register C7h).

Table 01h Register Descriptions

Table 01h, Register 80h–F7h: EEPROM

POWER-ON VALUE

READ ACCESS

00h

PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A)

PW2 or (PW1 and RWTBL1A)

Common A2h and B2h memory location

Nonvolatile (EE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

80h–F7h

EE

BIT 7

BIT 0

EEPROM for PW1 and/or PW2 level access.

40

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 01h, Register F8h: ALARM EN

3

POWER-ON VALUE

READ ACCESS

00h

PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)

PW2 or (PW1 and RWTBL1C)

WRITE ACCESS

Mixture of common memory locations and different memory locations (see the

descriptions below)

A2h AND B2h MEMORY

MEMORY TYPE

Nonvolatile (SEE)

<C>

<D>

F8h

TEMP HI

BIT 7

TEMP LO

VCC HI

VCC LO

BMON HI

BMON LO

PMON HI

PMON LO

BIT 0

Layout is identical to ALARM in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory,

3

Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h.

TEMP HI [A2h or B2h]:

BIT 7

BIT 6

BIT 5

BIT 4

0 = Disables interrupt from TEMP HI alarm.

1 = Enables interrupt from TEMP HI alarm.

TEMP LO [A2h or B2h]:

0 = Disables interrupt from TEMP LO alarm.

1 = Enables interrupt from TEMP LO alarm.

VCC HI [A2h or B2h]:

0 = Disables interrupt from VCC HI alarm.

1 = Enables interrupt from VCC HI alarm.

VCC LO [A2h or B2h]:

0 = Disables interrupt from VCC LO alarm.

1 = Enables interrupt from VCC LO alarm.

BMON1 HI [A2h]:

0 = Disables interrupt from BMON1 HI alarm.

1 = Enables interrupt from BMON1 HI alarm.

BMON2 HI [B2h]:

0 = Disables interrupt from BMON2 HI alarm.

1 = Enables interrupt from BMON2 HI alarm.

BIT 3

BIT 2

BIT 1

BIT 0

BMON1 LO [A2h]:

0 = Disables interrupt from BMON1 LO alarm.

1 = Enables interrupt from BMON1 LO alarm.

BMON2 LO [B2h]:

0 = Disables interrupt from BMON2 LO alarm.

1 = Enables interrupt from BMON2 LO alarm.

PMON1 HI [A2h]:

0 = Disables interrupt from PMON1 HI alarm.

1 = Enables interrupt from PMON1 HI alarm.

PMON2 HI [B2h]:

0 = Disables interrupt from PMON2 HI alarm.

1 = Enables interrupt from PMON2 HI alarm.

PMON1 LO [A2h]:

0 = Disables interrupt from PMON1 LO alarm.

1 = Enables interrupt from PMON1 LO alarm.

PMON2 LO [B2h]:

0 = Disables interrupt from PMON2 LO alarm.

1 = Enables interrupt from PMON2 LO alarm.

Maxim Integrated

41

DS1876

SFP Controller with Dual LDD Interface

Table 01h, Register F9h: RESERVED

POWER-ON VALUE

READ ACCESS

N/A

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

This register is reserved.

Table 01h, Register FAh: ALARM EN

1

POWER-ON VALUE

READ ACCESS

00h

PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)

PW2 or (PW1 and RWTBL1C)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

Different A2h and B2h memory locations

Nonvolatile (SEE)

FAh

RESERVED

BIT 7

RESERVED

HBAL

RESERVED

TXP HI

TXP LO

BIT 0

Layout is identical to ALARM in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see

1

Figure 9). The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h.

BITS 7:4, 2

BIT 3

RESERVED

HBAL: Enables alarm to create internal signal FETG.

0 = Disables interrupt from HBAL alarm.

1 = Enables interrupt from HBAL alarm.

TXP HI: Enables alarm to create internal signal FETG.

0 = Disables interrupt from TXP HI alarm.

1 = Enables interrupt from TXP HI alarm.

BIT 1

BIT 0

TXP LO: Enables alarm to create internal signal FETG.

0 = Disables interrupt from TXP LO alarm.

1 = Enables interrupt from TXP LO alarm.

Table 01h, Register FBh: RESERVED

POWER-ON VALUE

READ ACCESS

N/A

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

This register is reserved.

42

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 01h, Register FCh: WARN EN

3

POWER-ON VALUE

READ ACCESS

00h

PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)

PW2 or (PW1 and RWTBL1C)

WRITE ACCESS

Mixture of common memory locations and different memory locations (see the bit

descriptions)

A2h AND B2h MEMORY

MEMORY TYPE

Nonvolatile (SEE)

<C>

<D>

FCh

TEMP HI

BIT 7

TEMP LO

VCC HI

VCC LO

BMON HI

BMON LO

PMON HI

PMON LO

BIT 0

Layout is identical to WARN in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory,

3

Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h.

TEMP HI [A2h or B2h]:

BIT 7

BIT 6

BIT 5

BIT 4

0 = Disables interrupt from TEMP HI warning.

1 = Enables interrupt from TEMP HI warning.

TEMP LO [A2h or B2h]:

0 = Disables interrupt from TEMP LO warning.

1 = Enables interrupt from TEMP LO warning.

VCC HI [A2h or B2h]:

0 = Disables interrupt from VCC HI warning.

1 = Enables interrupt from VCC HI warning.

VCC LO [A2h or B2h]:

0 = Disables interrupt from VCC LO warning.

1 = Enables interrupt from VCC LO warning.

BMON1 HI [A2h]:

0 = Disables interrupt from BMON1 HI warning.

1 = Enables interrupt from BMON1 HI warning.

BMON1 HI [B2h]:

0 = Disables interrupt from BMON2 HI warning.

1 = Enables interrupt from BMON2 HI warning.

BIT 3

BIT 2

BIT 1

BIT 0

BMON1 LO [A2h]:

0 = Disables interrupt from BMON1 LO warning.

1 = Enables interrupt from BMON1 LO warning.

BMON2 LO [B2h]:

0 = Disables interrupt from BMON2 LO warning.

1 = Enables interrupt from BMON2 LO warning.

PMON1 HI [A2h]:

0 = Disables interrupt from PMON1 HI warning.

1 = Enables interrupt from PMON1 HI warning.

PMON2 HI [B2h]:

0 = Disables interrupt from PMON2 HI warning.

1 = Enables interrupt from PMON2 HI warning.

PMON1 LO [A2h]:

0 = Disables interrupt from PMON1 LO warning.

1 = Enables interrupt from PMON1 LO warning.

PMON2 LO [B2h]:

0 = Disables interrupt from PMON2 LO warning.

1 = Enables interrupt from PMON2 LO warning.

Maxim Integrated

43

DS1876

SFP Controller with Dual LDD Interface

Table 01h, Register FDh–FFh: RESERVED

POWER-ON VALUE

READ ACCESS

N/A

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

These registers are reserved.

Table 02h Register Descriptions

Table 02h, Register 80h: MODE

POWER-ON VALUE

READ ACCESS

7Fh

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

Common A2h and B2h memory location

Volatile

80h

SEEB

BIT 7

MOD2EN

QT2EN

APC2EN

AEN

MOD1EN

QT1EN

APC1EN

BIT 0

SEEB:

0 = (default) Enables EEPROM writes to SEE bytes.

BIT 7

BIT 6

1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the

part is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write

the SEE locations again for data to be written to the EEPROM.

MOD2EN:

0 = MOD2 DAC is writable by the user and the LUT recalls are disabled. This allows the user to

interactively test their modules by writing the values for MOD2. The output is updated with the new

2

value at the end of the write cycle. The I C STOP condition is the end of the write cycle.

1 = (default) Enables automatic control of the LUT for MOD2 DAC.

QT2EN:

0 = QTs (HBIAS, TXP HI, TXP LO) for transmitter 2 are writable by the user and the LUT recalls are

disabled. This allows the user to interactively test their modules by writing to the QT thresholds.

The thresholds are updated with the new values at the end of the write cycle. The I C STOP

condition is the end of the write cycle.

1 = (default) Enables automatic control of the LUT QTs for transmitter 2.

BIT 5

BIT 4

BIT 3

2

APC2EN:

0 = APC2 DAC is writable by the user and the LUT recalls are disabled. This allows the user to

interactively test their modules by writing the values for APC2. The output is updated with the new

2

value at the end of the write cycle. The I C STOP condition is the end of the write cycle.

1 = (default) Enables automatic control of the LUT for APC2 DAC.

AEN:

0 = The temperature-calculated index value TINDEX is writable by the user and the updates

of calculated indexes are disabled. This allows the user to interactively test their modules by

controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC

registers after the next completion of a temperature conversion.

1 = (default) The temperature-calculated index value TINDEX is used to control the LUTs.

44

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register 80h: MODE (continued)

MOD1EN:

0 = MOD1 DAC is writable by the user and the LUT recalls are disabled. This allows the user to

interactively test their modules by writing the values for MOD1. The output is updated with the new

value at the end of the write cycle. The I C STOP condition is the end of the write cycle.

BIT 2

BIT 1

BIT 0

2

1 = (default) Enables automatic control of the LUT for MOD1 DAC.

QT1EN:

0 = QTs (HBIAS, TXP HI, TXP LO) for transmitter 1 are writable by the user and the LUT recalls are

disabled. This allows the user to interactively test their modules by writing to the QT thresholds.

2

The thresholds are updated with the new values at the end of the write cycle. The I C STOP

condition is the end of the write cycle.

1 = (default) Enables automatic control of the LUT QTs for transmitter 1.

APC1EN:

0 = APC1 DAC is writable by the user and the LUT recalls are disabled. This allows the user to

interactively test their modules by writing the values for APC1. The output is updated with the new

2

value at the end of the write cycle. The I C STOP condition is the end of the write cycle.

1 = (default) Enables automatic control of the LUT for APC1 DAC.

Table 02h, Register 81h: TEMPERATURE INDEX (TINDEX)

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

(PW2 and AEN = 0) or (PW1 and RWTBL2 and AEN = 0)

Common A2h and B2h memory location

Volatile

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

81h

2

BIT 7

BIT 0

Holds the calculated index based on the temperature measurement. This index is used for the address during lookup

of Tables 04h and 06h. Temperature measurements below -40NC or above +102NC are clamped to 80h and C7h,

respectively. The calculation of TINDEX is as follows:

Temp_Value + 40°C

TINDEX =

+ 80h

2°C

For the temperature-indexed LUTs (2NC), the index used during the lookup function for each table is as follows:

Table 04h (MOD)

Table 06h (APC)

1

TINDEX

6

5

4

3

2

1

0

5

4

3

2

1

0

For the 8-position LUT tables, the following table shows the lookup function:

TINDEX

BYTE

1000_0xxx 1001_0xxx 1001_1xxx 1010_0xxx 1010_1xxx 1011_0xxx 1011_1xxx 11xx_xxxx

F8

F9

FA

FB

FC

FD

FE

FF

TEMP (NC)

< -8

-8 to +8

+8 to +24 +24 to +40 +40 to +56 +56 to +72 +72 to +88

R 88

Maxim Integrated

45

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register 82h–85h: RESERVED

FACTORY DEFAULT

READ ACCESS

N/A

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

These registers are reserved.

Table 02h, Register 86h: DEVICE ID

FACTORY DEFAULT

READ ACCESS

76h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

WRITE ACCESS

MEMORY TYPE

N/A

ROM

86h

0

1

0

1

0

BIT 7

BIT 0

Hardwired connections to show the device ID.

Table 02h, Register 87h: DEVICE VER

FACTORY DEFAULT

READ ACCESS

DEVICE VERSION

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

WRITE ACCESS

MEMORY TYPE

N/A

ROM

87h

DEVICE VERSION

BIT 7

BIT 0

Hardwired connections to show the device version.

46

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register 88h: CNFGA

FACTORY DEFAULT

READ ACCESS

C0h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

WRITE ACCESS

A2h AND B2h MEMORY Common A2h and B2h memory location

MEMORY TYPE

Nonvolatile (SEE)

88h

QTHEXT2

BIT 7

QTHEXT1

RESERVED

ASEL

MASK

INVRSOUT

INVTXFOUT2

INVTXFOUT1

BIT 0

QTHEXT2: QT high extension for transmitter 2.

0 = Disabled. TXP HI and HBIAS QT alarms of transmitter 2 immediately create FETG.

1 = (default) Enabled. TXP HI and HBIAS QT alarms of transmitter 2 do not create FETG until the

timeout of the TXD time interval.

BIT 7

EXT

QTHEXT1: QT high extension for transmitter 1.

0 = Disabled. TXP HI and HBIAS QT alarms of transmitter 1 immediately create FETG.

1 = (default) Enabled. TXP HI and HBIAS QT alarms of transmitter 1 do not create FETG until the

BIT 6

BIT 5

BIT 4

timeout of the TXD

time interval.

EXT

RESERVED

ASEL: Address select.

0 = (default) Device address is A2h for transmitter 1 and B2h for transmitter 2.

1 = The DEVICE ADDRESS register (Table 02h, Register 8Bh) is used to determine the main device

address.

MASK:

0 = (default) Alarm-enable row exists at Table 01h, Registers F8h–FFh. Table 05h, Registers F8h–

BIT 3

FFh are empty.

1 = Alarm-enable row exists at Table 05h, Registers F8h–FFh. Table 01h, Registers F8h–FFh are

empty.

INVRSOUT: Allow for inversion of the RSELOUT pin (see Figure 10).

0 = (default) RSELOUT is not inverted.

1 = RSELOUT is inverted.

BIT 2

BIT 1

BIT 0

INVTXFOUT2: Allow for inversion of signal driven by the TXF2 input pin.

0 = (default) TXF2 signal is not inverted.

1 = TXF2 signal is inverted.

INVTXFOUT1: Allow for inversion of signal driven by the TXF1 input pin.

0 = (default) TXF1 signal is not inverted.

1 = TXF1 signal is inverted.

Maxim Integrated

47

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register 89h: CNFGB

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

WRITE ACCESS

A2h AND B2h MEMORY Common A2h and B2h memory location

MEMORY TYPE Nonvolatile (SEE)

89h

IN1C

BIT 7

INVOUT1

ALATCH2

QTLATCH2

WLATCH2

ALATCH1

QTLATCH1

WLATCH1

BIT 0

IN1C: IN1 software control bit (see Figure 10).

0 = IN1 pin’s logic controls OUT1 pin.

1 = OUT1 is active (bit 6 defines the polarity).

BIT 7

BIT 6

INVOUT1: Inverts the active state for OUT1 (see Figure 10).

0 = Noninverted.

1 = Inverted.

ALATCH2: ADC alarm’s comparison latch for transmitter 2. Latches alarms in Lower Memory,

Registers 70h–71h.

0 = ADC alarm and flags reflect the status of the last comparison.

1 = ADC alarm flags remain set.

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

QTLATCH2: QT’s comparison latch for transmitter 2. Latches QT alarms in Lower Memory,

Registers 72h–73h and 76h.

0 = QT alarm and warning flags reflect the status of the last comparison.

1 = QT alarm and warning flags remain set.

WLATCH2: ADC warning’s comparison latch for transmitter 2. Latches warnings in Lower Memory,

Registers 74h–75h.

0 = ADC warning flags reflect the status of the last comparison.

1 = ADC warning flags remain set.

ALATCH1: ADC alarm’s comparison latch for transmitter 1. Latches alarms in Lower Memory,

Registers 70h–71h.

0 = ADC alarm and flags reflect the status of the last comparison.

1 = ADC alarm flags remain set.

QTLATCH1: QT’s comparison latch for transmitter 1. Latches QT alarms in Lower Memory,

Registers 72h–73h and 76h.

0 = QT alarm and warning flags reflect the status of the last comparison.

1 = QT alarm and warning flags remain set.

WLATCH1: ADC warning’s comparison latch for transmitter 1. Latches warnings in Lower Memory,

Registers 74h–75h.

0 = ADC warning flags reflect the status of the last comparison.

1 = ADC warning flags remain set.

48

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register 8Ah: CNFGC

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

8Ah

TXDFG2

BIT 7

TXDFLT2

TXDIO2

TXDFG1

TXDFLT1

TXDIO1

RESERVED

BIT 0

TXDFG2: See Figure 9.

0 = FETG2, an internal signal, has no effect on TXDOUT2.

1 = FETG2 is enabled and ORed with other possible signals to create TXDOUT2.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

TXDFLT2: See Figure 9.

0 = TXF2 pin has no effect on TXDOUT2.

1 = TXF2 pin is enabled and ORed with other possible signals to create TXDOUT2.

TXDIO2: See Figure 9.

0 = (default) TXD2 input signal is enabled and ORed with other possible signals to create TXDOUT2.

1 = TXD2 input signal has no effect on TXDOUT2.

TXDFG1: See Figure 9.

0 = FETG1, an internal signal, has no effect on TXDOUT1.

1 = FETG1 is enabled and ORed with other possible signals to create TXDOUT1.

TXDFLT1: See Figure 9.

0 = TXF1 pin has no effect on TXDOUT1.

1 = TXF1 pin is enabled and ORed with other possible signals to create TXDOUT1.

TXDIO1: See Figure 9.

BIT 2

0 = (default) TXD1 input signal is enabled and ORed with other possible signals to create TXDOUT1.

1 = TXD1 input signal has no effect on TXDOUT1.

BITS 1:0

RESERVED

Table 02h, Register 8Bh: DEVICE ADDRESS

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

3

2

1

8Bh

SEE

2

SEE

BIT 7

BIT 0

2

This value becomes the I C slave address for the main memory when the ASEL bit (Table 02h, Register 88h)

is set. If A0h is programmed to this register, the auxiliary memory is disabled. For example, writing xxxx_010x

makes the main device addresses A4h and B4h.

Maxim Integrated

49

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register 8Ch: RANGING

2

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

8Ch

RESERVED

BIT 7

HBIAS2

RESERVED

TXP2

0

2

1

0

2

1

BIT 0

The upper nibble of this byte controls the full-scale range of the QT monitoring for BMON2. The lower nibble of

this byte controls the full-scale range for the QT monitoring for PMON2.

BITS 7, 3

RESERVED (default = 0)

HBIAS2 : HBIAS2 full-scale ranging: 3-bit value to select the full-scale comparison voltage for

[2:0]

BMON2. Default is 000b and creates a full scale of 1.25V.

HBIAS2

% OF 1.25V

100.00

80.03

FS VOLTAGE (V)

1.250

[2:0]

000b

001b

010b

011b

100b

101b

110b

111b

1.000

BITS 6:4

66.71

0.834

50.07

0.626

40.08

0.501

33.41

0.418

28.65

0.358

25.08

0.314

TXP2

: TXP2 full-scale ranging: 3-bit value to select the full-scale comparison voltage for

[2:0]

PMON2. Default is 000b and creates a full scale of 2.5V.

TXP2

% OF 2.5V

100.00

80.03

FS VOLTAGE (V)

2.507

[2:0]

000b

001b

010b

011b

100b

101b

110b

111b

2.006

BITS 2:0

66.71

1.672

50.07

1.255

40.08

1.005

33.41

0.838

28.65

0.718

25.08

0.629

50

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register 8Dh: RANGING

1

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

8Dh

RESERVED

BIT 7

HBIAS1

RESERVED

TXP1

0

2

1

0

2

1

BIT 0

The upper nibble of this byte controls the full-scale range of the QT monitoring for BMON1. The lower nibble of

this byte controls the full-scale range for the QT monitoring for PMON1.

BITS 7, 3

RESERVED (default = 0)

HBIAS1 : HBIAS1 full-scale ranging: 3-bit value to select the full-scale comparison voltage for

[2:0]

BMON1. Default is 000b and creates a full scale of 1.25V.

HBIAS1

% OF 1.25V

100.00

80.03

FS VOLTAGE (V)

1.250

[2:0]

000b

001b

010b

011b

100b

101b

110b

111b

1.000

BITS 6:4

66.71

0.834

50.07

0.626

40.08

0.501

33.41

0.418

28.65

0.358

25.08

0.314

TXP1

: TXP1 full-scale ranging: 3-bit value to select the full-scale comparison voltage for

[2:0]

PMON1. Default is 000b and creates a full scale of 2.5V.

TXP1

% OF 2.5V

100.00

80.03

FS VOLTAGE (V)

2.507

[2:0]

000b

001b

010b

011b

100b

101b

110b

111b

2.006

BITS 2:0

66.71

1.672

50.07

1.255

40.08

1.005

33.41

0.838

28.65

0.718

25.08

0.629

Maxim Integrated

51

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register 8Eh: RIGHT-SHIFT (RSHIFT )

2

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

Common A2h and B2h memory location

Nonvolatile (SEE)

8Eh

RESERVED

BIT 7

BMON2

RESERVED

PMON2

BIT 0

2

1

0

2

1

0

Allows for right-shifting the final answer of BMON2 and PMON2 voltage measurements. This allows for scaling the

measurement to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the

correct LSB.

Table 02h, Register 8Fh: RIGHT-SHIFT (RSHIFT )

1

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

Common A2h and B2h memory location

Nonvolatile (SEE)

8Fh

RESERVED

BIT 7

BMON1

RESERVED

PMON1

2

1

0

2

1

0

BIT 0

Allows for right-shifting the final answer of BMON1 and PMON1 voltage measurements. This allows for scaling the

measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to

the correct LSB.

Table 02h, Register 90h–91h: RESERVED

FACTORY DEFAULT

READ ACCESS

N/A

WRITE ACCESS

N/A

A2h AND B2h MEMORY

MEMORY TYPE

These registers are reserved.

52

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register 92h–93h: V

SCALE

CC

Table 02h, Register 94h–97h: RESERVED

Table 02h, RegisteR 98h–99h: BMON2 SCALE

Table 02h, Register 9Ah–9Bh: PMON2 SCALE

Table 02h, Register 9Ch–9Dh: BMON1 SCALE

Table 02h, Register 9Eh–9Fh: PMON1 SCALE

FACTORY CALIBRATED

READ ACCESS

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

WRITE ACCESS

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

A2h AND B2h MEMORY

MEMORY TYPE

92h, 94h,

96h, 98h,

9Ah, 9Ch,

9Eh

15

14

13

12

11

10

2

9

1

8

0

2

93h, 95h,

97h, 99h,

9Bh, 9Dh,

9Fh

7

6

5

4

3

2

BIT 7

BIT 0

Controls the scaling or gain of the full-scale voltage measurements. The factory-calibrated value produces an FS

voltage of 6.5536V for V and 2.5V for BMON2, PMON2, BMON1, and PMON1.

CC

Table 02h, Register A0h–A1h: INTERNAL TEMP OFFSET

FACTORY CALIBRATED

READ ACCESS

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

WRITE ACCESS

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

A2h AND B2h MEMORY

MEMORY TYPE

8

7

6

5

4

3

2

A0h

A1h

S

2

1

0

-1

-2

-3

-4

-5

-6

2

BIT 7

BIT 0

Allows for offset control of temperature measurement if desired. The final result must be XORed with BB40h

before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius.

Maxim Integrated

53

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register A2h–A3h: V

OFFSET

CC

Table 02h, Register A4h–A7h: RESERVED

Table 02h, Register A8h–A9h: BMON2 OFFSET

Table 02h, Register AAh–ABh: PMON2 OFFSET

Table 02h, Register ACh–ADh: BMON1 OFFSET

Table 02h, Register AEh–AFh: PMON1 OFFSET

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

A2h, A4h,

A6h, A8h,

AAh, ACh,

AEh

15

14

13

12

4

11

3

10

2

S

2

A3h, A5h,

A7h, A9h,

ABh, ADh,

AFh

9

2

8

7

6

5

2

BIT 7

Allows for offset control of these voltage measurements if desired. This number is two’s complement.

BIT 0

Table 02h, Register B0h–B3h: PW1

FACTORY DEFAULT

READ ACCESS

FFFF FFFFh

N/A

WRITE ACCESS

MEMORY TYPE

PW2 or (PW1 and WPW1)

Nonvolatile (SEE)

31

23

15

7

30

22

14

6

29

21

13

5

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

2

B0h

B1h

B2h

B3h

2

16

2

8

2

1

0

2

BIT 7

BIT 0

The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the

PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-on without writing

the password entry. All reads of this register are 00h.

54

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register B4h–B7h: PW2

FACTORY DEFAULT

READ ACCESS

FFFF FFFFh

N/A

WRITE ACCESS

MEMORY TYPE

PW2

Nonvolatile (SEE)

31

23

15

7

30

29

2

28

20

12

4

27

19

11

3

26

18

10

2

25

17

9

24

16

8

B4h

B5h

B6h

B7h

2

22

14

6

21

2

13

2

5

1

0

2

BIT 7

BIT 0

The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the

PWE value is set to all ones. Thus, writing these bytes to all ones grants PW2 access on power-on without writing

the password entry. All reads of this register are 00h.

Table 02h, Register B8h: RESERVED

FACTORY DEFAULT

READ ACCESS

N/A

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

This register is reserved.

Table 02h, Register B9h: HBIAS2 DAC

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

(PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0)

Common A2h and B2h memory location

Volatile

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

B9h

2

BIT 7

BIT 0

The digital value used for the HBIAS2 reference and recalled from Table 06h (Registers E0h–E7h) (transmitter 2) at

the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.

Comparisons greater than V

compared against V

create an HBAL alarm.

HBIAS2

BMON2

Full Scale

256

V

=

×HBIAS2 DAC

HBIAS2

Maxim Integrated

55

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register BAh: HTXP2 DAC

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

(PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0)

Common A2h and B2h memory location

Volatile

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

BAh

2

BIT 7

BIT 0

The digital value used for the HTXP2 reference and recalled from Table 06h (Registers E8h–EFh) (transmitter 2) at

the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.

Comparisons greater than V

compared against V

create a TXP HI alarm.

HTXP2

PMON2

Full Scale

256

V

=

×HTXP2 DAC

HTXP2

Table 02h, Register BBh: LTXP2 DAC

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

(PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0)

Common A2h and B2h memory location

Volatile

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

BBh

2

BIT 7

BIT 0

The digital value used for the LTXP2 reference and recalled from Table 06h (Registers F0h–F7h) (transmitter 2) at

the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.

Comparisons less than V

compared against V

create a TXP LO alarm.

LTXP2

PMON2

Full Scale

256

V

=

×LTXP2 DAC

LTXP2

Table 02h, Register BCh: RESERVED

FACTORY DEFAULT

READ ACCESS

N/A

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

This register is reserved.

56

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register BDh: HBIAS1 DAC

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

(PW2 and QT1EN = 0) or (PW1 and RWTBL2 and QT1EN = 0)

Common A2h and B2h memory location

Volatile

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

BDh

2

BIT 7

BIT 0

The digital value used for the HBIAS1 reference and recalled from Table 06h (Registers E0h–E7h) (transmitter 1) at

the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.

Comparisons greater than V

compared against V

create an HBAL alarm.

HBIAS1

BMON1

Full Scale

256

V

=

×HBIAS1DAC

HBIAS1

Table 02h, Register BEh: HTXP1 DAC

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

(PW2 and QT1EN = 0) or (PW1 and RWTBL2 and QT1EN = 0)

Common A2h and B2h memory location

Volatile

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

BEh

2

BIT 7

BIT 0

The digital value used for the HTXP1 reference and recalled from Table 06h (Registers E8h–EFh) (transmitter 1) at

the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.

Comparisons great than V

compared against V

create a TXP HI alarm.

HTXP1

PMON1

Full Scale

256

V

=

×HTXP1DAC

HTXP1

Table 02h, Register BFh: LTXP1 DAC

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

(PW2 and QT1EN = 0) or (PW1 and RWTBL2 and QT1EN = 0)

Common A2h and B2h memory location

Volatile

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

BFh

2

BIT 7

BIT 0

The digital value used for the LTXP1 reference and recalled from Table 06h (Registers F0h–F7h) (transmitter 1) at

the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion.

Comparisons less than V

compared against V

create a TXP LO alarm.

LTXP1

PMON1

Full Scale

256

V

=

×LTXP1DAC

LTXP1

Maxim Integrated

57

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register C0h: PW_ENA

FACTORY DEFAULT

READ ACCESS

10h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

C0h

RESERVED

BIT 7

RWTBL1C

RWTBL2

RWTBL1A

RWTBL1B

WLOWER

WAUXA

WAUXB

BIT 0

BIT 7

BIT 6

RESERVED

RWTBL1C: Table 01h or 05h bytes F8–FFh. Table address is dependent on MASK bit (Table 02h,

Register 88h).

0 = (default) Read and write access for PW2 only.

1 = Read and write access for both PW1 and PW2.

RWTBL2: Table 02h. Writing a nonvolatile value to this bit requires PW2 access.

0 = (default) Read and write access for PW2 only.

1 = Read and write access for both PW1 and PW2.

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

RWTBL1A: Table 01h, Registers 80h–BFh.

0 = Read and write access for PW2 only.

1 = (default) Read and write access for both PW1 and PW2.

RWTBL1B: Table 01h, Registers C0h–F7h.

0 = (default) Read and write access for PW2 only.

1 = Read and write access for both PW1 and PW2.

WLOWER: Bytes 00h–5Fh in main memory. All users can read this area.

0 = (default) Write access for PW2 only.

1 = Write access for both PW1 and PW2.

WAUXA: Auxiliary memory, Registers 00h–7Fh. All users can read this area.

0 = (default) Write access for PW2 only.

1 = Write access for both PW1 and PW2.

WAUXB: Auxiliary memory, Registers 80h–FFh. All users can read this area.

0 = (default) Write access for PW2 only.

1 = Write access for both PW1 and PW2.

58

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register C1h: PW_ENB

FACTORY DEFAULT

READ ACCESS

03h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

C1h

RWTBL46

BIT 7

RTBL1C

RTBL2

RTBL1A

RTBL1B

WPW1

WAUXAU

WAUXBU

BIT 0

RWTBL46: Tables 04h and 06h.

BIT 7

BIT 6

0 = (default) Read and write access for PW2 only.

1 = Read and write access for PW1 and PW2.

RTBL1C: Table 01h or Table 05h, Registers F8h–FFh. Table address is dependent on MASK bit

(Table 02h, Register 88h).

0 = (default) Read and write access for PW2 only.

1 = Read access for PW1 and PW2.

RTBL2: Table 02h.

BIT 5

BIT 4

BIT 3

0 = (default) Read and write access for PW2 only.

1 = Read access for PW1 and PW2.

RTBL1A: Table 01h, Registers 80h–BFh.

0 = (default) Read and write access for PW2 only.

1 = Read access for PW1 and PW2.

RTBL1B: Table 01h, Registers C0h–F7h.

0 = (default) Read and write access for PW2 only.

1 = Read access for PW1 and PW2.

WPW1: Register PW1 (Table 02h, Registers B0h–B3h). For security purposes these registers are

not readable.

0 = (default) Write access for PW2 only.

1 = Write access for PW1 and PW2.

BIT 2

WAUXAU: Auxiliary memory, Registers 00h–7Fh. All users can read this area.

0 = Write access for PW2 only.

1 = (default) Write access for user, PW1, and PW2.

BIT 1

BIT 0

WAUXBU: Auxiliary memory, Registers 80h–FFh. All users can read this area.

0 = Write access for PW2 only.

1 = (default) Write access for user, PW1, and PW2.

Table 02h, Register C2h–C5h: RESERVED

FACTORY DEFAULT

READ ACCESS

N/A

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

These registers are reserved.

Maxim Integrated

59

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register C6h: POLARITY

FACTORY DEFAULT

READ ACCESS

0Fh

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

C6h

RESERVED

BIT 7

RESERVED

MOD2P

APC2P

MOD1P

APC1P

BIT 0

BITS 7:4

RESERVED

MOD2P: MOD2 DAC polarity. The MOD2 DAC (Table 02h, Registers C8h–C9h) range is

000h–3FFh. A setting of 000h creates a pulse-density of zero and 3FFh creates a pulse-density of

1023/1024. This polarity bit allows the user to use GND or V as the reference. The power-on

REFIN

of MOD2 DAC is 000h; thus an application that needs V

inverted polarity.

to be the off state should use the

REFIN

BIT 3

0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a

setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at V

.

REFIN

1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at V

a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND.

and

REFIN,

APC2P: APC2 DAC polarity. The APC2 DAC (Table 02h, Registers CAh–CBh) range is 000h–3FFh.

A setting of 000h creates a pulse-density of zero, and 3FFh creates a pulse-density of 1023/1024.

This polarity bit allows the user to use GND or V

as the reference. The power-on of APC DAC

REFIN

is 000h; thus an application that needs V

0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a

setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at V

to be the off state should use the inverted polarity.

REFIN

BIT 2

.

REFIN

1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at V

a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND.

and

REFIN,

MOD1P: MOD1 DAC polarity. The MOD1 DAC (Table 02h, Registers CCh–CDh) range is

000h–3FFh. A setting of 000h creates a pulse-density of zero and 3FFh creates a pulse-density of

1023/1024. This polarity bit allows the user to use GND or V as the reference. The power-on

REFIN

of MOD1 DAC is 000h; thus an application that needs V

inverted polarity.

to be the off state should use the

REFIN

BIT 1

0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a

setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at V

.

REFIN

1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at V

a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND.

and

REFIN,

APC1P: APC1 DAC polarity. The APC1 DAC (Table 02h, Registers CEh–CFh) range is 000h–3FFh.

A setting of 000h creates a pulse-density of zero, and 3FFh creates a pulse-density of 1023/1024.

This polarity bit allows the user to use GND or V

as the reference. The power-on of APC1

REFIN

DAC is 000h; thus an application that needs V

polarity.

to be the off state should use the inverted

REFIN

BIT 0

0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a

setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at V

.

REFIN

1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at V

a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND.

and

REFIN,

60

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register C7h: TBLSELPON

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

PW2 or (PW1 and RWTBL2)

Common A2h and B2h memory location

Nonvolatile (SEE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

C7h

2

BIT 7

BIT 0

Chooses the initial value for the TBL SEL byte (Lower Memory, Register 7Fh) at power-on.

Table 02h, Register C8h–C9h: MOD2 DAC

FACTORY DEFAULT

READ ACCESS

0000h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

WRITE ACCESS

(PW2 and MOD2EN = 0) or (PW1 and RWTBL2 and MOD2EN = 0)

Common A2h and B2h memory location

Volatile

A2h AND B2h MEMORY

MEMORY TYPE

9

8

C8h

C9h

0

2

7

6

5

4

3

2

1

0

2

BIT 7

BIT 0

The digital value used for MOD2 DAC. It is the result of LUT4 plus MOD2 OFFSET times 4 recalled from Table

04h (Registers F8h–FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of

the temperature conversion.

MOD2 DAC = LUT4 + MOD2 OFFSET x 4

V

REFIN

V

=

× MOD2 DAC

MOD2

1024

Maxim Integrated

61

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register CAh–CBh: APC2 DAC

FACTORY DEFAULT

READ ACCESS

0000h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

(PW2 and APC2EN = 0) or (PW1 and RWTBL2 and APC2EN = 0)

Common A2h and B2h memory location

Volatile

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

9

8

0

CAh

CBh

0

2

7

6

5

4

3

2

1

2

BIT 7

BIT 0

The digital value used for APC2 DAC. It is the result of LUT6 plus APC2 OFFSET times 4 recalled from Table

06h (Registers F8h–FFh) at the adjusted memory address found in TINDEX. This register is updated at the end

of the temperature conversion.

APC2 DAC = LUT6 + APC2 OFFSET x 4

V

REFIN

V

=

×APC2 DAC

APC2

1024

Table 02h, Register CCh–CDh: MOD1 DAC

FACTORY DEFAULT

READ ACCESS

0000h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

(PW2 and MOD1EN = 0) or (PW1 and RWTBL2 and MOD1EN = 0)

Common A2h and B2h memory location

Volatile

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

9

8

0

CCh

CDh

0

2

7

6

5

4

3

2

1

2

BIT 7

BIT 0

The digital value used for MOD1 DAC. It is the result of LUT4 plus MOD1 OFFSET times 4 recalled from Table

04h (Registers F8h–FFh) at the adjusted memory address found in TINDEX. This register is updated at the end

of the temperature conversion.

MOD1 DAC = LUT4 + MOD1 OFFSET x 4

V

REFIN

V

=

× MOD1 DAC

MOD1

1024

62

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 02h, Register CEh–CFh: APC1 DAC

FACTORY DEFAULT

READ ACCESS

0000h

PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)

(PW2 and APC1EN = 0) or (PW1 and RWTBL2 and APC1EN = 0)

Common A2h and B2h memory location

Volatile

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

9

8

0

CEh

CFh

0

2

7

6

5

4

3

2

1

2

BIT 7

BIT 0

The digital value used for APC1 DAC. It is the result of LUT6 plus APC1 OFFSET times 4 recalled from Table

06h (Registers F8h–FFh) at the adjusted memory address found in TINDEX. This register is updated at the end

of the temperature conversion.

APC1 DAC = LUT6 + APC1 OFFSET x 4

V

REFIN

V

=

×APC1 DAC

APC1

1024

Table 02h, Register D0h–FFh: EMPTY

FACTORY DEFAULT

READ ACCESS

00h

N/A

None

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

These registers do not exist.

Maxim Integrated

63

DS1876

SFP Controller with Dual LDD Interface

Table 04h Register Descriptions

Table 04h, Register 80h–C7h: MODULATION LUT (MOD)

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL46)

Different A2h and B2h memory locations

Nonvolatile (EE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

80h–C7h

2

BIT 7

BIT 0

Digital value for the MOD1 DAC (A2h address) and MOD2 DAC (B2h address) outputs. The MODULATION LUT

is a set of registers assigned to hold the temperature profile for the MOD1 and MOD2 DACs. The temperature

measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 2NC increments from -40NC to

+102NC, starting at 80h in Table 04h. Register 80h defines the -40NC to -38NC MOD output, Register 81h defines

-38NC to -36NC MOD output, and so on. Values recalled from this EEPROM memory table are written into the

MOD1 and MOD2 DACs (Table 02h, Registers C8h–C9h, CCh–CDh) locations that hold the values until the next

temperature conversion. The part can be placed into a manual mode (MOD1EN and MOD2EN bits, Table 02h,

Register 80h), where MOD1 and MOD2 DACs are directly controlled for calibration. If the temperature compen-

sation functionality is not required, program the entire Table 04h to the desired modulation setting.

Table 02h, Register C8h–F7h: EMPTY

FACTORY DEFAULT

READ ACCESS

00h

N/A

None

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

These registers do not exist.

64

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 04h, Register F8h–FFh: MOD OFFSET LUT

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL46)

Different A2h and B2h memory locations

Nonvolatile (EE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

9

8

7

6

5

4

3

2

F8h–FFh

2

BIT 7

BIT 0

The digital value for the temperature offset of the MOD1 and MOD2 DAC outputs.

F8h

F9h

FAh

FBh

FCh

FDh

FEh

FFh

Less than or equal to -8NC

Greater than -8NC up to +8NC

Greater than +8NC up to +24NC

Greater than +24NC up to +40NC

Greater than +40NC up to +56NC

Greater than +56NC up to +72NC

Greater than +72NC up to +88NC

Greater than +88NC

The MOD DAC is a 10-bit value. The MODULATION LUT is an 8-bit LUT. The MOD OFFSET LUT times 4 plus

the MODULATION LUT makes use of the entire 10-bit range.

Table 06h Register Descriptions

Table 06h, Register 80h–C7h: APC LUT

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL46)

Different A2h and B2h memory locations

Nonvolatile (EE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

80h–C7h

2

BIT 7

BIT 0

The digital value for the APC1 DAC (A2h address) and APC2 DAC (B2h address) outputs. The APC LUT is a

set of registers assigned to hold the temperature profile for the APC1 and APC2 DACs. The temperature mea-

surement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 2NC increments from -40NC to +102NC,

starting at 80h. Register 80h defines the -40NC to -38NC APC output, Register 81h defines -38NC to -36NC APC

output, and so on. Values recalled from this EEPROM memory table are written into the APC1 and APC2 DACs

(Table 02h, Registers CAh–CBh, CEh–CFh) locations that hold the values until the next temperature conver-

sion. The part can be placed into a manual mode (APC1EN and APC2EN bits, Table 02h, Register 80h), where

APC1 and APC2 DACs are directly controlled for calibration. If the temperature compensation functionality is not

required, program the entire Table 06h to the desired APC setting.

Maxim Integrated

65

DS1876

SFP Controller with Dual LDD Interface

Table 06h, Register C8h–DFh: EMPTY

FACTORY DEFAULT

READ ACCESS

00h

N/A

None

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

These registers do not exist.

Table 06h, Register E0h–E7h: HBATH LUT

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL46)

Different A2h and B2h memory locations

Nonvolatile (EE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

E0h–E7h

2

BIT 7

BIT 0

The high bias alarm threshold (HBATH) LUT is used to temperature compensate the bias QT threshold (HBIAS).

The table below shows the range of temperature for each byte’s location. The table shows a rising temperature;

for a falling temperature there is 1NC of hysteresis.

E0h

E1h

E2h

E3h

E4h

E5h

E6h

E7h

Less than or equal to -8NC

Greater than -8NC up to +8NC

Greater than +8NC up to +24NC

Greater than +24NC up to +40NC

Greater than +40NC up to +56NC

Greater than +56NC up to +72NC

Greater than +72NC up to +88NC

Greater than +88NC

66

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Table 06h, Register E8h–EFh: HTXP LUT

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL46)

Different A2h and B2h memory locations

Nonvolatile (EE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

E8h–EFh

2

BIT 7

BIT 0

The HTXP LUT is used to temperature compensate the transmit power-high QT threshold (TXP HI). The table

below shows the range of temperature for each byte’s location. The table shows a rising temperature; for a fall-

ing temperature there is 1NC of hysteresis.

E8h

E9h

EAh

EBh

ECh

EDh

EEh

EFh

Less than or equal to -8NC

Greater than -8NC up to +8NC

Greater than +8NC up to +24NC

Greater than +24NC up to +40NC

Greater than +40NC up to +56NC

Greater than +56NC up to +72NC

Greater than +72NC up to +88NC

Greater than +88NC

Table 06h, Register F0h–F7h: LTXP LUT

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL46)

Different A2h and B2h memory locations

Nonvolatile (EE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

7

6

5

4

3

2

1

0

F0h–F7h

2

BIT 7

BIT 0

The LTXP LUT is used to temperature compensate the transmit power-low QT threshold (TXP LO). The table

below shows the range of temperature for each byte’s location. The table shows a rising temperature; for a fall-

ing temperature there is 1NC of hysteresis.

F0h

F1h

F2h

F3h

F4h

F5h

F6h

F7h

Less than or equal to -8NC

Greater than -8NC up to +8NC

Greater than +8NC up to +24NC

Greater than +24NC up to +40NC

Greater than +40NC up to +56NC

Greater than +56NC up to +72NC

Greater than +72NC up to +88NC

Greater than +88NC

Maxim Integrated

67

DS1876

SFP Controller with Dual LDD Interface

Table 06h, Register F8h–FFh: APC OFFSET LUT

FACTORY DEFAULT

READ ACCESS

00h

PW2 or (PW1 and RWTBL46)

Different A2h and B2h memory locations

Nonvolatile (EE)

WRITE ACCESS

A2h AND B2h MEMORY

MEMORY TYPE

9

8

7

6

5

4

3

2

F8h–FFh

2

BIT 7

BIT 0

The digital value for the temperature offset of the APC1 and APC2 DAC outputs.

F8h

F9h

FAh

FBh

FCh

FDh

FEh

FFh

Less than or equal to -8NC

Greater than -8NC up to +8NC

Greater than +8NC up to +24NC

Greater than +24NC up to +40NC

Greater than +40NC up to +56NC

Greater than +56NC up to +72NC

Greater than +72NC up to +88NC

Greater than +88NC

The APC DAC is a 10-bit value. The APC LUT is an 8-bit LUT. The APC OFFSET LUT times 4 plus

the APC LUT makes use of the entire 10-bit range.

Auxiliary Memory A0h Register Descriptions

Auxiliary Memory A0h, Register 00h–7Fh: EEPROM

FACTORY DEFAULT

READ ACCESS

00h

All

WRITE ACCESS

MEMORY TYPE

PW2 or (PW1 and WAUXA) or (WAUXAU)

Nonvolatile (EE)

7

6

5

4

3

2

1

0

00h–7Fh

2

BIT 7

BIT 0

Accessible with the slave address A0h.

68

Maxim Integrated

DS1876

SFP Controller with Dual LDD Interface

Auxiliary Memory A0h, Register 80h–FFh: EEPROM

FACTORY DEFAULT

READ ACCESS

00h

All

WRITE ACCESS

MEMORY TYPE

PW2 or (PW1 and WAUXB) or (WAUXBU)

Nonvolatile (EE)

7

6

5

4

3

2

1

0

80h–FFh

2

BIT 7

BIT 0

Accessible with the slave address A0h.

Applications Information

Package Information

For the latest package outline information and land patterns, go

to www.maximintegrated.com/packages. Note that a “+”, “#”,

or “-” in the package code indicates RoHS status only. Package

drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

Power-Supply Decoupling

To achieve best results, it is recommended that the power

supply is decoupled with a 0.01FF or a 0.1FF capacitor.

Use high-quality, ceramic, surface-mount capacitors,

and mount the capacitors as close as possible to the

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

V

CC

and GND pins to minimize lead inductance.

28 TQFN-EP

T2855+6

21-0140

SDA and SCL Pullup Resistors

SDA is an open-collector output on the DS1876 that

requires a pullup resistor to realize high logic levels. A

master using either an open-collector output with a pul-

lup resistor or a push-pull output driver can be used for

SCL. Pullup resistor values should be chosen to ensure

2

that the rise and fall times listed in the I C AC Electrical

Characteristics table are within specification.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent

licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and

max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000

69

©

2010 Maxim Integrated Products, Inc.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.


型号：	DS1876_V01
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	SFP Controller with Dual LDD Interface
文件：	总69页 (文件大小：2165K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS1876_V01 [MAXIM]

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