DS2120B [MAXIM]

Ultra3 LVD SCSI Terminator;


型号：	DS2120B
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Ultra3 LVD SCSI Terminator 光电二极管接口集成电路
文件：	总10页 (文件大小：490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS2120

Ultra3 LVD SCSI Terminator

www.maxim-ic.com

FEATURES

PIN CONFIGURATION

ꢀ Fully Compliant with Ultra3, Ultra160,

Ultra320, and Ultra2 (LVD only) SCSI

ꢀ Provides Low-Voltage Differential (LVD)

Termination for Nine Signal Line Pairs

ꢀ Zero Temperature Coefficient Termination

Resistors

TPWR

VREF

R1P

R9N

R1N

R2P

R2N

R9P

R8N

HS GND

R3P

R8P

HS GND

R7N

ꢀ Autoselection of LVD Termination

ꢀ 5% Tolerance on LVD Termination

Resistance

R3N

R4P

R7P

R6N

R4N

R5P

R5N

ISO

R6P

ꢀ Low Power-Down Capacitance of 3pF

ꢀ Built-In Mode Change Filter/Delay

ꢀ On-Board Thermal Shutdown Circuitry

ꢀ SCSI Bus Hot Plug Compatible

DIFF_CAP

DIFFSENSE

MSTR/SLV

GND

TSSOP

VREF

TPWR

APPLICATIONS

Raid Systems

LVD

R1P

SCSI Host Bus Adapter Cards (HBA)

Servers

R9N

R1N

R9P

R2P

R8N

R2N

SCSI Cables

HS GND

R3P

R8P

Network Attached Storage (NAS)

Storage Area Networks (SANs)

HS GND

R7N

R3N

R4P

R7P

R4N

R5P

R5N

ISO

R6N

R6P

DIFF_CAP

DIFFSENSE

MSTR/SLV

GND

SSOP

ORDERING INFORMATION

VOLTAGE

PART

TEMP RANGE

PIN-PACKAGE

TOP MARK*

(V)

DS2120B

36 SSOP

DS2120

0°C to +70°C

DS2120B/T&R

DS2120E

36 SSOP/Tape and Reel

28 TSSOP

DS2120E+

28 TSSOP

28 TSSOP/Tape and Reel DS2120

DS2120E/T&R

DS2120E+T&R

+ Denotes lead-free/RoHS-compliant package.

* The top mark includes a "+" on lead-free packages.

1 of 10

REV: 010506

DS2120

GENERAL DESCRIPTION

The DS2120 Ultra3 LVD SCSI terminator is a low-voltage differential (LVD) terminator. If the device is

connected in an LVD-only bus, the DS2120 uses LVD termination. If any single-ended (SE) or high-

voltage differential (HVD) devices are connected to the bus, the DS2120 disconnects from the bus. This

is accomplished inside the part automatically by sensing the voltage on the SCSI bus DIFFSENS line.

For the LVD termination, the DS2120 integrates two current sources with nine precision resistor strings.

Three DS2120 terminators are needed for a wide SCSI bus.

REFERENCE DOCUMENTS

Small Computer Systems Interface (SCSI-3) SCSI Parallel Interface (SPI)

Project: 0855-M, 1995

Small Computer Systems Interface (SCSI-3) SCSI Parallel Interface 2 (SPI-2) Project: 1142-M, 1998

Small Computer Systems Interface (SCSI-3) SCSI Parallel Interface 3 (SPI-3) Project: 1302-D, 1999

Small Computer Systems Interface (SCSI-3) SCSI Parallel Interface 4 (SPI-4) Project: 1365-D, 200x

Available from:

American National Standards Institute (ANSI) Phone: 212-642-4900

Global Engineering Documents 15 Inverness Way East; Englewood, CO 80112 Phone: 800-854-7179

FUNCTIONAL DESCRIPTION

The DS2120 combines LVD termination with DIFFSENSE sourcing and detection.

LVD termination is provided by a laser-trimmed resistor biased with two current sources and a common-

mode voltage source, generated from a bandgap reference of 1.25V. The configuration is a y-type

terminator with a 105Ω differential and 150Ω common-mode resistance. A fail-safe bias of 112mV is

maintained when no drivers are connected to the SCSI bus. In non-LVD mode, the resistors are isolated

from the bus.

The DIFF_CAP pin of DS2120 monitors the DIFFSENS line to determine the proper operating mode of

the device. If the voltage on the DIFF_CAP is between 0.7V and 1.9V, the device enters LVD mode after

the mode-change delay. If the voltage at the DIFF_CAP later crosses one of the thresholds, the DS2120

again changes modes after the mode-change delay. The mode-change delay is the same when changing in

or out of LVD mode. A new mode change can start anytime after a previous mode change has been

detected. These modes are the following:

•

LVD Mode: LVD termination is provided by a precision laser-trimmed resistor string with two

current sources. This configuration yields a 105Ω differential and 150Ω common-mode

impedance. A fail-safe bias of 112mV is maintained when no drivers are connected to the SCSI

bus.

•

SE Isolation Mode: The DS2120 identifies that there is a SE (single-ended) device on the SCSI

bus and isolates the termination pins from the bus.

HVD Isolation Mode: The DS2120 identifies that there is an HVD device on the SCSI bus and

isolates the termination pins from the bus.

When ISO is pulled high, the termination pins are isolated from the SCSI bus and VREF remains active.

The mode-change delay/filter is still active and the LVD pin continues to indicate the correct bus mode.

2 of 10

DS2120

During thermal shutdown, the termination pins are isolated from the SCSI bus and VREF becomes high

impedance. The DIFFSENS driver is shut down during either of these two events. The DIFF_CAP

receiver is disabled and the LVD goes low, indicating a non-LVD condition.

To ensure proper operation, the TPWR pin should be connected to the SCSI bus TERMPWR line. As

with all analog circuitry, the TERMPWR and V_DDlines should be bypassed locally. A 2.2µF capacitor

and a 0.01µF high-frequency capacitor are recommended between TPWR and ground and placed as close

as possible to the DS2120. The DS2120 should be placed as close as possible to the SCSI connector to

minimize signal and power trace length, thereby lessening input capacitance and reflections that can

degrade the bus signals.

To maintain the specified regulation, a 4.7µF capacitor is required between the VREF pin and ground of

each DS2120. A high-frequency cap (0.1µF ceramic recommended) can also be placed on the VREF pin

in applications that use fast rise/fall-time drivers. A typical SCSI bus configuration is shown in Figure 2.

DIFFSENS Noise Filtering: The DS2120 incorporates a digital filter to remove high-frequency

transients on the DIFFSENS control line, thereby eliminating erroneous switching between modes. This

filter eliminates the need for the external capacitor and resistor, which previously performed this function.

The external filter can be used in addition to the digital filter if the DS2120 and DS2118M or DS2119M

are to be used interchangeably.

NOTES:

1) DIFFSENS: Refers to the SCSI bus signal.

2) DIFFSENSE: Refers to the Dallas Semiconductor pin name and internal circuitry relating to

differential sensing.

3 of 10

DS2120

Figure 1. Block Diagram

2.15V

LVD

Mode Change

Delay/Filter

DIFF CAP

1.30V

DIFFSENSE

0.6V

THERMAL

SHUTDOWN

ISO

CONTROL

LOGIC

MSTR/SLV

R1N

R1P

I_GEN

2.15V

REFERENCE

GENERATOR

1.30V

0.6V

R9N

R9P

1.25V

VREF

4 of 10

DS2120

Figure 2. SCSI Bus Configuration

5 of 10

DS2120

PIN DESCRIPTION

NAME

FUNCTION

TSSOP

SSOP

Regulator Output Voltage. 1.25V reference in LVD

VREF

mode; must be decoupled with a 4.7µF cap.

2–5, 7–12,

18–21,

4–7, 11–16,

22–25,

RxP, RxN

HS_GND

Signal Termination. Connect to SCSI bus signal lines.

23–26

29–32

Heat Sink Ground. Internally connected to the mounting

pad. Should be connected to ground.

6, 22

8–10, 26–28

Isolation. When pulled high, terminating resistors and

ISO

biasing current sources are isolated from the SCSI bus.

GND

Signal Ground

Master/Slave. Mode select for the noncontrolling

MSTR/SLV terminator. When pulled high (MSTR), the DIFFSENS

driver is enabled.

DIFFSENSE. Output to drive the SCSI bus DIFFSENS

DIFFSENSE

line.

DIFFSENSE Capacitor. Connect a 0.1µF capacitor for

DIFF_CAP

TPWR

DIFFSENSE filter. Input to detect the type of device

(differential or single-ended) on the SCSI bus.

Termination Power. Connect to the SCSI TERMPWR

line and decouple with 2.2µF capacitor.

27, 28

Low-Voltage Differential. Output of DIFFSENSE

—

LVD

receiver; output high indicates LVD bus operation.

2, 3, 33, 35

No Connection. Do not connect pins.

RECOMMENDED OPERATING CONDITIONS

PARAMETER

Termpower Voltage, LVD Mode

Logic 0

SYMBOL

V_TPWR(LVD)

V_IL

MIN

2.7

TYP

MAX UNITS NOTES

5.5

+0.8

V_TPWR

0.3

-0.3

Logic 1

V_IH

2.0

Operating Temperature

V_AMB

°C

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DS2120

LOW-VOLTAGE DIFFERENTIAL CHARACTERISTICS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Differential Mode

R_DM

100

110

Ω

Termination Resistance

Common Mode Termination

Resistance

R_CM

110

190

Ω

Differential Mode Bias

Common Mode Bias

Output Capacitance

Mode-Change Delay

V_DM

V_CM

C_OUT

M_CD

100

1.125

125

1.375

1, 12

0.66

1.25

DC CHARACTERISTICS

PARAMETER

SYMBOL

I_TPMR

I_IH

MIN

TYP

MAX

UNITS

NOTES

2, 3

Termpower Current

Input Leakage High

Input Leakage Low

Output Current High

Output Current Low

DIFF_CAP LVD

-1.0

µA

14, 15

4, 6

I_IL

1.0

-1.0

µA

I_OH

I_OL

4.0

0.7

5, 6

V_LVDOR

V_DSO

I_DSH

1.9

1.4

Operating Range

DIFFSENSE Driver

Output Voltage

1.2

7, 8

DIFFSENSE Driver

Source Current

µA

7, 9, 11

7, 10, 11

DIFFSENSE Driver

I_DSL

200

Sink Current

MSTR/SLV Input Leakage

ISO Input Leakage

I_MSTRSLV

I_ISO

-6.5

-125

+125

+6.5

µA

°C

Thermal Shutdown

150

7 of 10

DS2120

REGULATOR CHARACTERISTICS

PARAMETER

VREF Line Regulation

VREF Load Regulation

SYMBOL

LI_REG

MIN

TYP

1.0

1.3

MAX

2.0

3.5

UNITS

NOTES

LO_REG

VREF Current Limit

I_LIM

200

VREF Sink Current

I_SINK

200

NOTES:

1) Guaranteed by design.

2) All lines open.

3) ISO = 1

4) V_OUT= 2.4V

5) V_OUT= 0.4V

6) LVD pin only.

7) MSTR/SLV = 1

8) I_DS= 0 to 5mA

9) V_DSO= 0.0V

10) V_DSO= 2.75V

11) TPWR = 5.5V

12) M_CDis extended by the RC time constant formed by the resistor connected from DIFFSENSE to

DIFF_CAP and the capacitor connected from DIFF_CAP to ground.

13) MSTR/SLV and ISO pins.

14) Terminator pins only.

15) DIFFCAP pin only.

8 of 10

DS2120

PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package

outline information, go to www.maxim-ic.com/DallasPackInfo.)

9 of 10

DS2120

PACKAGE INFORMATION (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package

outline information, go to www.maxim-ic.com/DallasPackInfo.)

10 of 10

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

DS2120B [MAXIM]

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