DS2151QBX2_技术文档

DS2151Q

T1 Single-Chip Transceiver

www.maxim-ic.com

FEATURES

PIN CONFIGURATION

ꢀ Complete DS1/ISDN-PRI Transceiver

Functionality

FUNCTIONAL BLOCKS

ꢀ Line Interface Can Handle Both Long- and

Short-Haul Trunks

ꢀ 32-Bit or 128-Bit Jitter Attenuator

ꢀ Generates DSX-1 and CSU Line Build-Outs

ꢀ Frames to D4, ESF, and SLC-96^RFormats

ꢀ Dual On-Board Two-Frame Elastic Store Slip

Buffers that Connect to Backplanes Up to

8.192MHz

PARALLEL CONTROL

PORT

ꢀ 8-Bit Parallel Control Port That can be Used

on Either Multiplexed or Nonmultiplexed

Buses

ꢀ Extracts and Inserts Robbed-Bit Signaling

ꢀ Detects and Generates Yellow and Blue

Alarms

Dallas

ACTUAL SIZE OF 44-PIN PLCC

DS2151Q

T1SCT

ꢀ Programmable Output Clocks for Fractional

T1

ꢀ Fully Independent Transmit and Receive

Functionality

ALE(AS)

WR (R/W)

RLINK

RLCLK

DVSS

RCLK

RCHCLK

RSER

7

8

TSER

TCLK

39

38

ꢀ On-Board FDL Support Circuitry

ꢀ Generates and Detects CSU Loop Codes

ꢀ Contains ANSI One’s Density Monitor and

Enforcer

9

37

36

35

DVDD

TSYNC

TLINK

TLCLK

TCHBLK

TRING

TVDD

TVSS

DS2151Q

10

11

12

34

33

13

14

15

ꢀ Large Path and Line Error Counters Including

BPV, CV, CRC6, and Framing Bit Errors

ꢀ Pin Compatible with DS2153Q E1 Single-

Chip Transceiver

32

31

RSYNC

RLOS/LOTC

SYSCLK

16

17

30

29

TTIP

ꢀ 5V Supply; Low-Power CMOS

ORDERING INFORMATION

PLCC

TEMP

PIN-

PART

RANGE

PACKAGE

44 PLCC

DS2151Q

0°C to +70°C

-40°C to +85°C

DS2151Q+

DS2151QN

DS2151QN+

44 PLCC

+Denotes lead-free/RoHS-compliant package.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

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REV: 011706

DS2151Q

TABLE OF CONTENTS

1 DETAILED DESCRIPTION....................................................................................................4

1.1 INTRODUCTION................................................................................................................................4

2 PIN DESCRIPTION................................................................................................................6

2.1 DS2151Q REGISTER MAP...............................................................................................................8

3 PARALLEL PORT.................................................................................................................9

4 CONTROL REGISTERS......................................................................................................10

4.1 LOCAL LOOPBACK .........................................................................................................................15

4.2 REMOTE LOOPBACK ......................................................................................................................15

4.3 PAYLOAD LOOPBACK.....................................................................................................................15

4.4 FRAMER LOOPBACK ......................................................................................................................15

4.5 LOOP CODE GENERATION .............................................................................................................18

4.6 PULSE DENSITY ENFORCER...........................................................................................................18

4.7 POWER-UP SEQUENCE .................................................................................................................18

5 STATUS AND INFORMATION REGISTERS......................................................................19

5.1 LOOP UP/DOWN CODE DETECTION................................................................................................23

6 ERROR COUNT REGISTERS.............................................................................................27

6.1 LINE CODE VIOLATION COUNT REGISTER (LCVCR) .......................................................................27

6.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR)......................................................................28

6.3 MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR) ............................................................29

7 FDL/FS EXTRACTION AND INSERTION...........................................................................30

7.1 RECEIVE SECTION.........................................................................................................................30

7.2 TRANSMIT SECTION.......................................................................................................................31

8 SIGNALING OPERATION...................................................................................................32

9 TRANSMIT TRANSPARENCY AND IDLE REGISTERS ....................................................34

10 CLOCK BLOCKING REGISTERS....................................................................................36

11 ELASTIC STORES OPERATION.....................................................................................37

11.1

11.2

11.3

RECEIVE SIDE............................................................................................................................37

TRANSMIT SIDE..........................................................................................................................37

MINIMUM DELAY SYNCHRONOUS SYSCLK MODE.......................................................................37

12 RECEIVE MARK REGISTERS.........................................................................................38

13 LINE INTERFACE FUNCTIONS.......................................................................................39

13.1

13.2

13.3

RECEIVE CLOCK AND DATA RECOVERY.......................................................................................40

TRANSMIT WAVESHAPING AND LINE DRIVING ..............................................................................41

JITTER ATTENUATOR..................................................................................................................42

14 TIMING DIAGRAMS.........................................................................................................46

15 DC CHARACTERISTICS..................................................................................................52

16 AC CHARACTERISTICS..................................................................................................53

17 PACKAGE INFORMATION..............................................................................................60

17.1

44-PIN PLCC (56-G4003-001)..................................................................................................60

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DS2151Q

LIST OF FIGURES

Figure 1-1. DS2151Q Block Diagram.........................................................................................................5

Figure 13-1. External Analog Connections...............................................................................................43

Figure 13-2. Jitter Tolerance ....................................................................................................................43

Figure 13-3. Transmit Waveform Template..............................................................................................44

Figure 13-4. Jitter Attenuation ..................................................................................................................45

Figure 14-1. Receive Side D4 Timing.......................................................................................................46

Figure 14-2. Receive Side ESF Timing ....................................................................................................46

Figure 14-3. Receive Side Boundary Timing with Elastic Store(s) Disabled ............................................47

Figure 14-4. 1.544MHz Boundary Timing with Elastic Store(s) Enabled..................................................47

Figure 14-5. 2.048MHz Boundary Timing with Elastic Store(s) Enabled..................................................48

Figure 14-6. Transmit Side D4 Timing......................................................................................................48

Figure 14-7. Transmit Side ESF Timing ...................................................................................................49

Figure 14-8. Transmit Side Boundary Timing with Elastic Store(s) Disabled ...........................................50

Figure 14-9. Transmit Data Flow..............................................................................................................51

Figure 16-1. Intel Bus Read AC Timing....................................................................................................54

Figure 16-2. Intel Bus Write AC Timing....................................................................................................54

Figure 16-3. Motorola Bus AC Timing ......................................................................................................55

Figure 16-4. Receive Side AC Timing ......................................................................................................57

Figure 16-5. Transmit Side AC Timing .....................................................................................................59

LIST OF TABLES

Table 4-1. Output Pin Test Modes............................................................................................................13

Table 5-1. Receive T1 Level Indication ....................................................................................................21

Table 5-2. Alarm Set and Clear Criteria ...................................................................................................23

Table 6-1. Line Code Violation Counting Arrangements ..........................................................................27

Table 6-2. Path Code Violation Counting Arrangements..........................................................................28

Table 6-3. Multiframes Out of Sync Counting Arrangements ...................................................................29

Table 13-1. Source of RCLK Upon RCL...................................................................................................40

Table 13-2. LBO Select in LICR ...............................................................................................................41

Table 13-3. Transformer Specifications....................................................................................................41

Table 13-4. Crystal Selection Guidelines .................................................................................................42

Table 15-1. Recommended DC Characteristics.......................................................................................52

Table 15-2. Capacitance ..........................................................................................................................52

Table 15-3. DC Characteristics ................................................................................................................52

Table 16-1. AC Characteristics—Parallel Port .........................................................................................53

Table 16-2. AC Characteristics—Receive Side........................................................................................56

Table 16-3. AC Characteristics—Transmit Side.......................................................................................58

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DS2151Q

1 DETAILED DESCRIPTION

The DS2151Q T1 single-chip transceiver (SCT) contains all the necessary functions for connection to T1

lines whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry automatically

adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX-1 line

build-outs as well as CSU build-outs of -7.5dB, -15dB, and -22.5dB. The on-board jitter attenuator

(selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The

framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also

used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of 64

8-bit internal registers that the user can access to control the operation of the unit. Quick access via the

parallel control port allows a single micro to handle many T1 lines. The device fully meets all of the latest

T1 specifications including ANSI T1.403-199X, AT&T TR 62411 (12-90), and ITU G.703, G.704,

G.706, G.823, and I.431.

1.1 Introduction

The analog AMI waveform off of the T1 line is transformer coupled into the RRING and RTIP pins of

the DS2151Q. The device recovers clock and data from the analog signal and passes it through the jitter

attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing

pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency

differences between the recovered T1 data stream and an asynchronous backplane clock which is

provided at the SYSCLK input.

The transmit side of the DS2151Q is totally independent from the receive side in both the clock

requirements and characteristics. Data can be either provided directly to the transmit formatter or via an

elastic store. The transmit formatter will provide the necessary data overhead for T1 transmission. Once

the data stream has been prepared for transmission, it is sent via the jitter attenuation mux to the

waveshaping and line driver functions. The DS2151Q will drive the T1 line from the TTIP and TRING

pins via a coupling transformer.

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DS2151Q

Figure 1-1. DS2151Q Block Diagram

5 of 60

DS2151Q

2 PIN DESCRIPTION

NAME

TYPE

FUNCTION

1–4, AD4–AD7,

I/O

Address/Data Bus. An 8-bit multiplexed address/data bus.

41–44 AD0–AD3

5

6

RD(DS)

I

Active-Low Read Input (Data Strobe)

CS

Active-Low Chip Select. Must be low to read or write the port.

Address Latch Enable (Address Strobe). A positive going edge serves to

7

ALE(AS)

I

demultiplex the bus.

8

WR(R/W)

Active-Low Write Input (Read/Write)

Receive Link Data. Updated with either FDL data (ESF) or Fs bits (D4) or

Z bits (ZBTSI) one RCLK before the start of a frame. See Section 14 for

timing details.

9

RLINK

O

Receive Link Clock. 4kHz or 2kHz (ZBTSI) demand clock for the RLINK

output. See Section 14 for timing details.

10

RLCLK

O

11

12

DVSS

RCLK

—

O

Digital Signal Ground. 0.0V. Should be tied to local ground plane.

Receive Clock. Recovered 1.544MHz clock.

Receive Channel Clock. 192kHz clock that pulses high during the LSB of

each channel. Useful for parallel to serial conversion of channel data,

locating Robbed-Bit signaling bits, and for blocking clocks in DDS

applications. See Section 14 for timing details.

13

14

RCHCLK

RSER

O

Receive Serial Data. Received NRZ serial data, updated on rising edges of

RCLK or SYSCLK.

Receive Sync. An extracted pulse, one RCLK wide, is output at this pin,

which identifies either frame (RCR2.4 = 0) or multiframe boundaries

(RCR2.4 = 1). If set to output frame boundaries, then via RCR2.5, RSYNC

can also be set to output double-wide pulses on signaling frames. If the

elastic store is enabled via the CCR1.2, then this pin can be enabled to be

an input via RCR2.3 at which a frame boundary pulse is applied. See

Section 14 for timing details.

15

RSYNC

I/O

Receive Loss of Sync/Loss of Transmit Clock. A dual function output. If

CCR3.5 = 0, will toggle high when the synchronizer is searching for the T1

frame and multiframe; if CCR3.5 = 1, will toggle high if the TCLK pin has

not toggled for 5µs.

System Clock. 1.544MHz or 2.048MHz clock. Only used when the elastic

store functions are enabled via either CCR1.7 or CCR1.2. Should be tied

low in applications that do not use the elastic store. If tied high for more

than 100µs, will force all output pins (including the parallel port) to tri-

state.

RLOS/LOT

C

16

17

O

I

SYSCLK

Receive Channel Block. A user-programmable output that can be forced

high or low during any of the 24 T1 channels. Useful for blocking clocks to

a serial UART or LAPD controller in applications where not all T1

channels are used such as Fractional T1, 384kbps service, 768kbps, or

ISDN-PRI. Also useful for locating individual channels in drop-and-insert

applications. See Section 14 for timing details.

Alternate Clock Input. Upon a receive carrier loss, the clock applied at

this pin (normally 1.544MHz) will be routed to the RCLK pin. If no clock

is routed to this pin, then it should be tied to DVSS via a 1kΩ resistor.

18

19

RCHBLK

ACLKI

O

I

6 of 60

DS2151Q

NAME

TYPE

FUNCTION

Bus Type Select. Strap high to select Motorola bus timing; strap low to select

Intel bus timing. This pin controls the function of the RD(DS), ALE(AS), and

WR(R/W) pins. If BTS = 1, then these pins assume the function listed in

parentheses.

20

BTS

I

RTIP,

Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects

21, 22

—

RRING

to a 1:1 transformer (see Section 13 for details).

Receive Analog Positive Supply. 5.0V. Should be tied to DVDD and TVDD

23

24

RVDD

RVSS

—

pins.

Receive Signal Ground. 0V. Should be tied to local ground plane.

XTAL1,

Crystal Connections. A pullable 6.176MHz crystal must be applied to these

25, 26

—

XTAL2

pins. See Section 13 for crystal specifications.

Receive Alarm Interrupt 1. Flags host controller during alarm conditions

defined in Status Register 1. Active low, open drain output.

Receive Alarm Interrupt 2. Flags host controller during conditions defined

in Status Register 2. Active low, open drain output.

INT1

INT2

27

28

O

Transmit Tip. Analog line driver output; connects to a step-up transformer

(see Section 13 for details).

29

30

31

TTIP

TVSS

TVDD

—

Transmit Signal Ground. 0V. Should be tied to local ground plane.

Transmit Analog Positive Supply. 5.0V. Should be tied to DVDD and

RVDD pins.

Transmit Ring. Analog line driver outputs; connects to a step-up transformer

(see Section 13 for details).

32

TRING

—

Transmit Channel Block. A user-programmable output that can be forced

high or low during any of the 24 T1 channels. Useful for blocking clocks to a

serial UART or LAPD controller in applications where not all T1 channels are

used such as Fractional T1, 384kbps service, 768kbps, or ISDN-PRI. Also

useful for locating individual channels in drop-and-insert applications. See

Section 14 for timing details.

33

TCHBLK

O

Transmit Link Clock. 4kHz or 2kHz (ZBTSI) demand clock for the TLINK

input. See Section 14 for timing details.

34

35

TLCLK

TLINK

O

I

Transmit Link Data. If enabled via TCR1.2, this pin will be sampled during

the F-bit time on the falling edge of TCLK for data insertion into either the

FDL stream (ESF) or the Fs bit position (D4) or the Z-bit position (ZBTSI).

See Section 14 for timing details.

Transmit Sync. A pulse at this pin will establish either frame or multiframe

boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can be programmed

to output either a frame or multiframe pulse at this pin. If this pin is set to

output pulses at frame boundaries, it can also be set via TCR2.4 to output

double-wide pulses at signaling frames. See Section 14 for timing details.

Digital Positive Supply. 5.0V. Should be tied to RVDD and TVDD pins.

Transmit Clock. 1.544MHz primary clock.

36

TSYNC

I/O

37

38

DVDD

TCLK

—

I

Transmit Serial Data. Transmit NRZ serial data, sampled on the falling edge

of TCLK.

39

TSER

I

Transmit Channel Clock. 192kHz clock that pulses high during the LSB of

each channel. Useful for parallel to serial conversion of channel data, locating

robbed-bit signaling bits, and for blocking clocks in DDS applications. See

Section 14 for timing details.

40

TCHCLK

O

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DS2151Q

2.1 DS2151Q Register Map

ADDRESS R/W

REGISTER NAME

ADDRESS R/W

REGISTER NAME

20

21

R/W Status Register 1

R/W Status Register 2

30

31

R/W Common Control Register 3

R/W Receive Information Register 2

22

23

24

25

26

R/W Receive Information Register 1

32

33

34

35

36

R/W Transmit Channel Blocking Register 1

R/W Transmit Channel Blocking Register 2

R/W Transmit Channel Blocking Register 3

R/W Transmit Control Register 1

Line Code Violation Count

R

Register 1

Line Code Violation Count

R

Register 2

Path Code Violation Count

R

Register 1 (Note 1)

Path Code Violation Count

R

R/W Transmit Control Register 2

Register 2

Multiframe Out of Sync Count

27

28

29

R

37

38

39

R/W Common Control Register 1

R/W Common Control Register 2

R/W Transmit Transparency Register 1

Register 2

R

Receive FDL Register

R/W Receive FDL Match Register 1

R/W Receive FDL Match Register 2

R/W Receive Control Register 1

2A

2B

3A

3B

R/W Transmit Transparency Register 2

R/W Transmit Transparency Register 3

2C

2D

2E

2F

60

61

62

63

64

65

66

67

68

69

6A

6B

R/W Receive Control Register 2

R/W Receive Mark Register 1

R/W Receive Mark Register 2

R/W Receive Mark Register 3

3C

3D

3E

3F

70

71

72

73

74

75

76

77

78

79

7A

7B

R/W Transmit Idle Register 1

R/W Transmit Idle Register 2

R/W Transmit Idle Register 3

R/W Transmit Idle Definition Register

R/W Transmit Signaling Register 1

R/W Transmit Signaling Register 2

R/W Transmit Signaling Register 3

R/W Transmit Signaling Register 4

R/W Transmit Signaling Register 5

R/W Transmit Signaling Register 6

R/W Transmit Signaling Register 7

R/W Transmit Signaling Register 8

R/W Transmit Signaling Register 9

R/W Transmit Signaling Register 10

R/W Transmit Signaling Register 11

R/W Transmit Signaling Register 12

R

Receive Signaling Register 1

Receive Signaling Register 2

Receive Signaling Register 3

Receive Signaling Register 4

Receive Signaling Register 5

Receive Signaling Register 6

Receive Signaling Register 7

Receive Signaling Register 8

Receive Signaling Register 9

Receive Signaling Register 10

Receive Signaling Register 11

Receive Signaling Register 12

Receive Channel Blocking

Register 1

6C

R/W

7C

R/W Line Interface Control Register

Receive Channel Blocking

Register 2

6D

7D

R/W Test Register (Note 2)

Receive Channel Blocking

Register 3

6E

6F

7E

7F

R/W Transmit FDL Register

R/W Interrupt Mask Register 1

R/W Interrupt Mask Register 2

Note 1: Address 25 also contains Multiframe Out of Sync Count Register 1.

Note 2: The Test Register is used only by the factory; this register must be cleared (set to all 0s) on power-up initialization to insure proper

operation.

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DS2151Q

3 PARALLEL PORT

The DS2151Q is controlled via a multiplexed bidirectional address/data bus by an external

microcontroller or microprocessor. The DS2151Q can operate with either Intel or Motorola bus timing

configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will

be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in Section 14

for more details. The multiplexed bus on the DS2151Q saves pins because the address information and

data information share the same signal paths. The addresses are presented to the pins in the first portion of

the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses

must be valid prior to the falling edge of ALE (AS), at which time the DS2151Q latches the address from

the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS

or WR pulses. In a read cycle, the DS2151Q outputs a byte of data during the latter portion of the DS or

RD pulses. The read cycle is terminated and the bus returns to a high impedance state as RD transitions

high in Intel timing or as DS transitions low in Motorola timing. The DS2151Q can also be easily

connected to nonmultiplexed buses. Refer to the separate application note for a detailed discussion of this

topic.

9 of 60

DS2151Q

4 CONTROL REGISTERS

The operation of the DS2151Q is configured via a set of eight registers. Typically, the control registers

are only accessed when the system is first powered up. Once the DS2151Q has been initialized, the

control registers will only need to be accessed when there is a change in the system configuration. There

are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and

TCR2), a Line Interface Control Register (LICR), and three Common Control Registers (CCR1, CCR2,

and CCR3). Seven of the eight registers are described below. The LICR is described in Section 13.

RCR1: RECEIVE CONTROL REGISTER 1 (Address = 2B Hex)

(MSB)

(LSB)

LCVCRF

ARC

OOF1

OOF2

SYNCC

SYNCT

SYNCE RESYNC

SYMBOL

POSITION

NAME AND DESCRIPTION

LCVCRF

RCR1.7

Line Code Violation Count Register Function Select.

0 = do not count excessive 0s

1 = count excessive 0s

ARC

RCR1.6

RCR1.5

RCR1.4

RCR1.3

Auto Resync Criteria.

0 = Resync on OOF or RCL event

1 = Resync on OOF only

OOF1

Out Of Frame Select 1.

0 = 2/4 frame bits in error

1 = 2/5 frame bits in error

OOF2

Out Of Frame Select 2.

0 = follow RCR1.5

1 = 2/6 frame bits in error

SYNCC

Sync Criteria.

In D4 Framing Mode

0 = search for Ft pattern, then search for Fs pattern

1 = cross couple Ft and Fs pattern

In ESF Framing Mode

0 = search for FPS pattern only

1 = search for FPS and verify with CRC6

SYNCT

SYNCE

RCR1.2

RCR1.1

RCR1.0

Sync Time.

0 = qualify 10 bits

1 = qualify 24 bits

Sync Enable.

0 = auto resync enabled

1 = auto resync disabled

RESYNC

Resync. When toggled from low to high, a resynchronization

of the receive side framer is initiated. Must be cleared and set

again for a subsequent resync.

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DS2151Q

RCR2: RECEIVE CONTROL REGISTER 2 (Address = 2C Hex)

(MSB)

(LSB)

RCS

RZBTSI

RSDW

RSM

RSIO

RD4YM

FSBE

MOSCRF

SYMBOL

POSITION

NAME AND DESCRIPTION

Receive Code Select.

RCS

RCR2.7

RCR2.6

RCR2.5

0 = idle code (7F Hex)

1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)

RZBTSI

RSDW

Receive Side ZBTSI Enable.

0 = ZBTSI disabled

1 = ZBTSI enabled

RSYNC Double-Wide.

0 = do not pulse double-wide in signaling frames

1 = do pulse double-wide in signaling frames (Note: this bit

must be set to 0 when RCR2.4 = 1 or when RCR2.3 = 1.)

RSM

RSIO

RCR2.4

RCR2.3

RSYNC Mode Select.

0 = frame mode (see the timing in Section 14)

1 = multiframe mode (see the timing in Section 14)

RSYNC I/O Select.

0 = RSYNC is an output

1 = RSYNC is an input (only valid if elastic store enabled)

(Note: this bit must be set to 0 when CCR1.2 = 0.)

RD4YM

FSBE

RCR2.2

RCR2.1

Receive Side D4 Yellow Alarm Select.

0 = 0s in bit 2 of all channels

1 = a 1 in the S-bit position of frame 12

PCVCR Fs Bit Error Report Enable.

0 = do not report bit errors in Fs bit position; only Ft bit

position

1 = report bit errors in Fs bit position as well as Ft bit position

MOSCRF

RCR2.0

Multiframe Out of Sync Count Register Function Select.

0 = count errors in the framing bit position

1 = count the number of multiframes out of sync

11 of 60

DS2151Q

TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 35 Hex)

(MSB)

(LSB)

LOTCMC

TFPT

TCPT

RBSE

GB7S

TLINK

TBL

TYEL

SYMBOL

POSITION

NAME AND DESCRIPTION

LOTCMC

TCR1.7

Loss Of Transmit Clock Mux Control. Determines whether

the transmit side formatter should switch to the ever present

RCLK if the TCLK input should fail to transition (Figure 1-1).

0 = do not switch to RCLK if TCLK stops

1 = switch to RCLK if TCLK stops

TFPT

TCPT

RBSE

TCR1.6

TCR1.5

TCR1.4

Transmit Framing Pass Through. (See note below.)

0 = Ft or FPS bits sourced internally

1 = Ft or FPS bits sampled at TSER during F-bit time

Transmit CRC Pass Through. (See note below.)

0 = source CRC6 bits internally

1 = CRC6 bits sampled at TSER during F-bit time

Robbed-Bit Signaling Enable. (See note below.)

0 = no signaling is inserted in any channel

1 = signaling is inserted in all channels (the TTR registers can

be used to block insertion on a channel by channel basis)

GB7S

TCR1.3

Global Bit 7 Stuffing. (See note below.)

0 = allow the TTR registers to determine which channels

containing all 0s are to be Bit 7 stuffed

1 = force Bit 7 stuffing in all 0 byte channels regardless of how

the TTR registers are programmed

TLINK

TBL

TCR1.2

TCR1.1

TCR1.0

TLINK Select. (See note below.)

0 = source FDL or Fs bits from TFDL register

1 = source FDL or Fs bits from the TLINK pin

Transmit Blue Alarm. (See note below.)

0 = transmit data normally

1 = transmit an unframed all 1s code at TPOS and TNEG

TYEL

Transmit Yellow Alarm. (See note below.)

0 = do not transmit yellow alarm

1 = transmit yellow alarm

Note: For a detailed description of how the bits in TCR1 affect the transmit side formatter of the

DS2151Q, see Figure 14-9.

12 of 60

DS2151Q

TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 36 Hex)

(MSB)

(LSB)

TEST1

TEST0

TZBTSI

TSDW

TSM

TSIO

TD4YM

B7ZS

SYMBOL

POSITION

NAME AND DESCRIPTION

TEST1

TCR2.7

Test Mode Bit 1 for Output Pins. See Table 4-1.

Test Mode Bit 0 for Output Pins. See Table 4-1.

TEST0

TCR2.6

TCR2.5

TZBTSI

Transmit Side ZBTSI Enable.

0 = ZBTSI disabled

1 = ZBTSI enabled

TSDW

TCR2.4

TSYNC Double-Wide. (Note: This bit must be set to 0 when

TCR2.3 = 1 or when TCR2.2 = 0.)

0 = do not pulse double-wide in signaling frames

1 = do pulse double-wide in signaling frames

TSM

TSIO

TCR2.3

TCR2.2

TCR2.1

XTCR2.0

TSYNC Mode Select.

0 = frame mode (see the timing in Section 14)

1 = multiframe mode (see the timing in Section 14)

TSYNC I/O Select.

0 = TSYNC is an input

1 = TSYNC is an output

TD4YM

B7ZS

Transmit Side D4 Yellow Alarm Select.

0 = 0s in bit 2 of all channels

1 = 1 in the S-bit position of frame 12

Bit 7 Zero Suppression Enable.

0 = No stuffing occurs

1 = Bit 7 force to a 1 in channels with all 0s

Table 4-1. Output Pin Test Modes

TEST1

TEST0

EFFECT ON OUTPUT PINS

0

1

0

1

0

1

Operate normally

Force all output pins tri-state (including all I/O pins and parallel port pins)

Force all output pins low (including all I/O pins except parallel port pins)

Force all output pins high (including all I/O pins except parallel port pins)

13 of 60

DS2151Q

CCR1: COMMON CONTROL REGISTER 1 (Address = 37 Hex)

(MSB)

(LSB)

TESE

LLB

RSAO

RLB

SCLKM

RESE

PLB

FLB

SYMBOL

POSITION

NAME AND DESCRIPTION

Transmit Elastic Store Enable.

0 = elastic store is bypassed

1 = elastic store is enabled

TESE

CCR1.7

LLB

RSAO

RLB

CCR1.6

CCR1.5

CCR1.4

CCR1.3

CCR1.2

CCR1.1

CCR1.0

Local Loopback.

0 = loopback disabled

1 = loopback enabled

Receive Signaling All 1s.

0 = allow robbed signaling bits to appear at RSER

1 = force all robbed signaling bits at RSER to 1

Remote Loopback.

0 = loopback disabled

1 = loopback enabled

SCLKM

RESE

PLB

SYSCLK Mode Select.

0 = if SYSCLK is 1.544MHz

1 = if SYSCLK is 2.048MHz

Receive Elastic Store Enable.

0 = elastic store is bypassed

1 = elastic store is enabled

Payload Loopback.

0 = loopback disabled

1 = loopback enabled

FLB

Framer Loopback.

0 = loopback disabled

1 = loopback enabled

14 of 60

DS2151Q

4.1 Local Loopback

When CCR1.6 is set to a 1, the DS2151Q will be forced into Local Loopback (LLB). In this loopback,

data will continue to be transmitted as normal through the transmit side of the SCT. Data being received

at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass

through the jitter attenuator and the jitter attenuator should be programmed to be in the transmit path.

LLB is primarily used in debug and test applications. See Figure 1-1 for more details.

4.2 Remote Loopback

When CCR1.4 is set to a 1, the DS2151Q will be forced into Remote Loopback (RLB). In this loopback,

data recovered off the T1 line from the RTIP and RRING pins will be transmitted back onto the T1 line

(with any BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to

pass through the receive side of the DS2151Q as it would normally and the data at the TSER input will be

ignored. Data in this loopback will pass through the jitter attenuator. RLB is used to place the DS2151Q

into “line” loopback, which is a requirement of both ANSI T1.403 and AT&T TR62411. See Figure 1-1

for more details.

4.3 Payload Loopback

When CCR1.1 is set to a 1, the DS2151Q will be forced into Payload Loopback (PLB). Normally, this

loopback is only enabled when ESF framing is being performed. In a PLB situation, the DS2151Q will

loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit

section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not looped back, they are

reinserted by the DS2151Q. When PLB is enabled, the following will occur:

1) Data will be transmitted from the TTIP and TRING pins synchronous with RCLK instead of

TCLK.

2) All the receive side signals will continue to operate normally.

3) The TCHCLK and TCHBLK signals are forced low.

4) Data at the TSER pin is ignored.

5) The TLCLK signal will become synchronous with RCLK instead of TCLK.

4.4 Framer Loopback

When CCR1.0 is set to a 1, the DS2151Q will enter a Framer Loopback (FLB) mode. This loopback is

useful in testing and debugging applications. In FLB, the DS2151Q will loop data from the transmit side

back to the receive side. When FLB is enabled, the following will occur:

1) Unless the RLB is active, an unframed all 1s code will be transmitted at TTIP and TRING.

2) Data off the T1 line at RTIP and RRING will be ignored.

3) The RCLK output will be replaced with the TCLK input.

15 of 60

DS2151Q

CCR2: COMMON CONTROL REGISTER 2 (Address = 38 Hex)

(MSB)

(LSB)

TFM

TB8ZS

TSLC96

TFDL

RFM

RB8ZS

RSLC96

RFDL

SYMBOL

POSITION

NAME AND DESCRIPTION

Transmit Frame Mode Select.

0 = D4 framing mode

TFM

CCR2.7

CCR2.6

CCR2.5

CCR2.4

CCR2.3

CCR2.2

CCR2.1

CCR2.0

1 = ESF framing mode

TB8ZS

TSLC96

TFDL

Transmit B8ZS Enable.

0 = B8ZS disabled

1 = B8ZS enabled

Transmit SLC-96/Fs Bit Loading Enable.

0 = SLC-96/Fs bit Loading disabled

1 = SLC-96/Fs bit Loading enabled

Transmit FDL 0 Stuffer Enable.

0 = 0 stuffer disabled

1 = 0 stuffer enabled

RFM

Receive Frame Mode Select.

0 = D4 framing mode

1 = ESF framing mode

RB8ZS

RSLC96

RFDL

Receive B8ZS Enable.

0 = B8ZS disabled

1 = B8ZS enabled

Receive SLC-96 Enable.

0 = SLC-96 disabled

1 = SLC-96 enabled

Receive FDL 0 Destuffer Enable.

0 = 0 destuffer disabled

1 = 0 destuffer enabled

16 of 60

DS2151Q

CCR3: COMMON CONTROL REGISTER 3 (Address = 30 Hex)

(MSB)

(LSB)

ESMDM

ESR

P16F

RSMS

PDE

TLD

TLU

LIRST

SYMBOL

POSITION

NAME AND DESCRIPTION

ESMDM

ESR

CCR3.7

Elastic Store Minimum Delay Mode. See Section 11 for

details.

0=elastic stores operate at full two-frame depth

1=elastic stores operate at 32-bit depth

CCR3.6

Elastic Store Reset. Setting this bit from a 0 to a 1 will force

the elastic stores to a known depth. Should be toggled after

SYSCLK has been applied and is stable. Must be cleared and

set again for a subsequent reset.

P16F

CCR3.5

CCR3.4

Function of Pin 16.

0 = Receive Loss of Sync (RLOS).

1 = Loss of Transmit Clock (LOTC).

RSMS

RSYNC Multiframe Skip Control. Useful in framing format

conversions from D4 to ESF.

0 = RSYNC will output a pulse at every multiframe

1 = RSYNC will output a pulse at every other multiframe note:

for this bit to have any affect, the RSYNC must be set to output

multiframe pulses (RCR2.4 = 1 and RCR2.3 = 0) and the

receive elastic store must be bypassed. (CCR1.2 = 0).

PDE

TLD

CCR3.3

CCR3.2

CCR3.1

CCR3.0

Pulse Density Enforcer Enable.

0 = disable transmit pulse density enforcer

1 = enable transmit pulse density enforcer

Transmit Loop Down Code (001).

0 = transmit data normally

1 = replace normal transmitted data with Loop Down code

TLU

Transmit Loop Up Code (00001).

0 = transmit data normally

1 = replace normal transmitted data with Loop Up code

LIRST

Line Interface Reset. Setting this bit from a 0 to a one will

initiate an internal reset that affects the slicer, AGC, clock

recovery state machine and jitter attenuator. Normally this bit is

only toggled on power-up. Must be cleared and set again for a

subsequent reset.

17 of 60

DS2151Q

4.5 Loop Code Generation

When either the CCR3.1 or CCR3.2 bits are set to 1, the DS2151Q will replace the normal transmitted

payload with either the Loop Up or Loop Down code, respectively. The DS2151Q will overwrite the

repeating loop code pattern with the framing bits. The SCT will continue to transmit the loop codes as

long as either bit is set. It is an illegal state to have both CCR3.1 and CCR3.2 set to 1 at the same time.

4.6 Pulse Density Enforcer

The SCT always examines both the transmit and receive data streams for violations of the following rules

which are required by ANSI T1.403-199X:

– no more than 15 consecutive 0s

– at least N 1s in each and every time window of 8 x (N +1) bits where N = 1 through 23

Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits

respectively.

When the CCR3.3 is set to 1, the DS2151Q will force the transmitted stream to meet this requirement no

matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should be set to 0,

since B8ZS encoded data streams cannot violate the pulse density requirements.

4.7 Power-Up Sequence

On power-up, after the supplies are stable, the DS2151Q should be configured for operation by writing to

all of the internal registers (this includes setting the Test Register to 00Hex) since the contents of the

internal registers cannot be predicted on power-up. Next, the LIRST bit should be toggled from 0 to 1 to

reset the line interface (it will take the DS2151Q about 40ms to recover from the LIRST being toggled).

Finally, after the SYSCLK input is stable, the ESR bit should be toggled from a 0 to a 1 (this step can be

skipped if the elastic stores are disabled).

18 of 60

DS2151Q

5 STATUS AND INFORMATION REGISTERS

There is a set of four registers that contain information on the current real time status of the DS2151Q:

Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register 1 (RIR1), and Receive

Information Register 2 (RIR2). When a particular event has occurred (or is occurring), the appropriate bit

in one of these four registers will be set to a 1. All of the bits in these registers operate in a latched

fashion. This means that if an event occurs and a bit is set to a 1 in any of the registers, it will remain set

until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the

event has occurred again or if the alarm(s) is still present.

The user will always precede a read of these registers with a write. The byte written to the register will

inform the DS2151Q which bits the user wishes to read and have cleared. The user will write a byte to

one of these four registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit positions

he or she does not wish to obtain the latest information on. When a 1 is written to a bit location, the read

register will be updated with current value and the previous value will be cleared. When a 0 is written to a

bit position, the read register will not be updated and the previous value will be held. A write to the status

and information registers will be immediately followed by a read of the same register. The read result

should be logically ANDed with the mask byte that was just written and this value should be written back

into the same register to ensure that the bit does indeed clear. This second write is necessary because the

alarms and events in the status registers occur asynchronously in respect to their access via the parallel

port. The write-read-write scheme is unique to the four status registers and it allows an external

microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the

register. This operation is key in controlling the DS2151Q with higher-order software languages.

The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2

pins, respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked

from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2)

respectively.

19 of 60

DS2151Q

RIR1: RECEIVE INFORMATION REGISTER 1 (Address = 22 Hex)

(MSB)

(LSB)

COFA

8ZD

16ZD

RESF

RESE

SEFE

B8ZS

FBE

SYMBOL

POSITION

NAME AND DESCRIPTION

COFA

RIR1.7

Change of Frame Alignment. Set when the last resync

resulted in a change of frame or multiframe alignment.

8ZD

RIR1.6

RIR1.5

RIR1.4

RIR1.3

RIR1.2

RIR1.1

Eight 0 Detect. Set when a string of eight consecutive 0s have

been received at RPOS and RNEG.

16ZD

RESF

RESE

SEFE

B8ZS

Sixteen 0 Detect. Set when a string of 16 consecutive 0s have

been received at RPOS and RNEG.

Receive Elastic Store Full. Set when the receive elastic store

buffer fills and a frame is deleted.

Receive Elastic Store Empty. Set when the receive elastic

store buffer empties and a frame is repeated.

Severely Errored Framing Event. Set when 2 out of 6

framing bits (Ft or FPS) are received in error.

B8ZS Codeword Detect. Set when a B8ZS codeword is

detected at RPOS and RNEG independent of whether the B8ZS

mode is selected or not via CCR2.6.

FBE

RIR1.0

Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing

bit is received in error.

20 of 60

DS2151Q

RIR2: RECEIVE INFORMATION REGISTER 2 (Address = 31 Hex)

(MSB)

(LSB)

RL1

RL0

TESF

TESE

TSLIP

JALT

RPDV

TPDV

SYMBOL

POSITION

NAME AND DESCRIPTION

RL1

RIR2.7

Receive Level Bit 1. See Table 5-1.

RL0

RIR2.6

RIR2.5

Receive Level Bit 0. See Table 5-1.

TESF

Transmit Elastic Store Full. Set when the transmit elastic

store buffer fills and a frame is deleted.

TESE

TSLIP

JALT

RIR2.4

RIR2.3

RIR2.2

Transmit Elastic Store Empty. Set when the transmit elastic

store buffer empties and a frame is repeated.

Transmit Elastic Store Slip Occurrence. Set when the

transmit elastic store has either repeated or deleted a frame.

Jitter Attenuator Limit Trip. Set when the jitter attenuator

FIFO reaches to within 4 bits of its limit; useful for debugging

jitter attenuation operation.

RPDV

TPDV

RIR2.1

RIR2.0

Receive Pulse Density Violation. Set when the receive data

stream does not meet the ANSI T1.403 requirements for pulse

density.

Transmit Pulse Density Violation. Set when the transmit data

stream does not meet the ANSI T1.403 requirements for pulse

density.

Table 5-1. Receive T1 Level Indication

TYPICAL LEVEL

RL1

RL0

RECEIVED (dB)

+2 to -7.5

0

1

0

1

0

1

-7.5 to -15

-15 to -22.5

Less than -22.5

21 of 60

DS2151Q

SR1: STATUS REGISTER 1 (Address = 20 Hex)

(MSB)

(LSB)

LUP

LDN

LOTC

RSLIP

RBL

RYEL

RCL

RLOS

SYMBOL

POSITION

NAME AND DESCRIPTION

LUP

SR1.7

Loop Up Code Detected. Set when the repeating ...00001...

loop up code is being received.

LDN

SR1.6

SR1.5

Loop Down Code Detected. Set when the repeating ...001...

loop down code is being received.

LOTC

Loss of Transmit Clock. Set when the TCLK pin has not

transitioned for one channel time (or 5.2µs). Will force pin 16

high if enabled via CCR1.6. Based on RCLK.

RSLIP

RBL

SR1.4

SR1.3

SR1.2

SR1.1

SR1.0

Receive Elastic Store Slip Occurrence. Set when the receive

elastic store has either repeated or deleted a frame.

Receive Blue Alarm. Set when a blue alarm is received at

RTIP and RRING. See note below.

RYEL

RCL

Receive Yellow Alarm. Set when a yellow alarm is received at

RTIP and RRING.

Receive Carrier Loss. Set when 192 consecutive 0s have been

detected at RTIP and RRING.

RLOS

Receive Loss of Sync. Set when the device is not synchronized

to the receive T1 stream.

22 of 60

DS2151Q

Table 5-2. Alarm Set and Clear Criteria

ALARM

SET CRITERIA

CLEAR CRITERIA

Blue Alarm (AIS) (see note below) When over a 3ms window, five or When over a 3ms window, six or

less 0s are received

more 0s are received

When bit 2 of 256 consecutive

Yellow Alarm

When bit 2 of 256 consecutive

1. D4 bit 2 mode (RCR2.2=0)

channels is set to 0 for at least 254 channels is set to 0 for less than 254

occurrences

2. D4 12^thF-bit mode (RCR2.2=1;

this mode is also referred to as

the “Japanese Yellow Alarm”)

When the 12^thframing bit is set to When the 12^thframing bit is set to 0

1 for two consecutive occurrences for two consecutive occurrences

3. ESF Mode

When 16 consecutive patterns of

00FF hex appear in the FDL

When 14 or less patterns of 00FF

hex out of 16 possible appear in the

FDL

When 14 or more 1s out of 112

possible bit positions are received

starting with the first 1 received

Red Alarm (RCL) (this alarm is

When 192 consecutive 0s are

received

also referred to as Loss of Signal)

Note: The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all-ones signal. Blue alarm detectors should

be able to operate properly in the presence of a 10-3 error rate and they should not falsely trigger on a framed all-ones signal.

The blue alarm criteria in the DS2151Q has been set to achieve this performance. It is recommended that the RBL bit be

qualified with the RLOS status bit in detecting a blue alarm.

5.1 Loop Up/Down Code Detection

Bits SR1.7 and SR1.6 will indicate when either the standard Loop Up or Loop Down codes are being

received by the DS2151Q. When a Loop Up code has been received for 5 seconds, the CPE is expected to

loop the recovered data (without correcting BPVs) back to the source. The Loop Down code indicates

that the loopback should be discontinued. See the AT&T publication TR 62411 for more details. The

DS2151Q will detect the Loop Up/Down codes in both framed and unframed circumstances with bit error

rates as high as 10**-2. The loop code detector has a nominal integration period of 48ms. Hence, after

about 48ms of receiving either code, the proper status bit will be set to a 1. After this initial indication, it

is recommended that the software poll the DS2151Q every 100ms to 500ms until 5 seconds have elapsed

to insure that the code is continuously present. Once 5 seconds have passed, the DS2151Q should be

taken into or out of loopback via the Remote Loopback (RLB) bit in CCR1.

23 of 60

DS2151Q

SR2: STATUS REGISTER 2 (Address = 21 Hex)

(MSB)

(LSB)

RMF

TMF

SEC

RFDL

TFDL

RMTCH

RAF

-

SYMBOL

POSITION

NAME AND DESCRIPTION

RMF

SR2.7

Receive Multiframe. Set on receive multiframe boundaries.

Transmit Multiframe. Set on transmit multiframe boundaries.

TMF

SEC

SR2.6

SR2.5

One Second Timer. Set on increments of 1 second based on

RCLK; will be set in increments of 999ms, 999ms, and 1002ms

every 3 seconds.

RFDL

TFDL

RMTCH

RAF

SR2.4

SR2.3

SR2.2

SR2.1

SR2.0

Receive FDL Buffer Full. Set when the receive FDL buffer

(RFDL) fills to capacity (8 bits).

Transmit FDL Buffer Empty. Set when the transmit FDL

buffer (TFDL) empties.

Receive FDL Match Occurrence. Set when the RFDL

matches either RFDLM1 or RFDLM2.

Receive FDL Abort. Set when eight consecutive ones are

received in the FDL.

—

Not Assigned. Should be set to 0 when written.

24 of 60

DS2151Q

IMR1: INTERRUPT MASK REGISTER 1 (Address = 7F Hex)

(MSB)

(LSB)

LUP

LDN

LOTC

SLIP

RBL

RYEL

RCL

RLOS

SYMBOL

POSITION

NAME AND DESCRIPTION

Loop Up Code Detected.

0 = interrupt masked

LUP

IMR1.7

1 = interrupt enabled

LDN

LOTC

SLIP

IMR1.6

IMR1.5

IMR1.4

IMR1.3

IMR1.2

IMR1.1

IMR1.0

Loop Down Code Detected.

0 = interrupt masked

1 = interrupt enabled

Loss of Transmit Clock.

0 = interrupt masked

1 = interrupt enabled

Elastic Store Slip Occurrence.

0 = interrupt masked

1 = interrupt enabled

RBL

Receive Blue Alarm.

0 = interrupt masked

1 = interrupt enabled

RYEL

RCL

Receive Yellow Alarm.

0 = interrupt masked

1 = interrupt enabled

Receive Carrier Loss.

0 = interrupt masked

1 = interrupt enabled

RLOS

Receive Loss of Sync.

0 = interrupt masked

1 = interrupt enabled

25 of 60

DS2151Q

IMR2: INTERRUPT MASK REGISTER 2 (Address = 6F Hex)

(MSB)

(LSB)

RMF

TMF

SEC

RFDL

TFDL

RMTCH

RAF

—

SYMBOL

POSITION

NAME AND DESCRIPTION

Receive Multiframe.

0 = interrupt masked

RMF

IMR2.7

1 = interrupt enabled

TMF

IMR2.6

IMR2.5

IMR2.4

IMR2.3

IMR2.2

IMR2.1

IMR2.0

Transmit Multiframe.

0 = interrupt masked

1 = interrupt enabled

SEC

One-Second Timer.

0 = interrupt masked

1 = interrupt enabled

RFDL

TFDL

RMTCH

RAF

Receive FDL Buffer Full.

0 = interrupt masked

1 = interrupt enabled

Transmit FDL Buffer Empty.

0 = interrupt masked

1 = interrupt enabled

Receive FDL Match Occurrence.

0 = interrupt masked

1 = interrupt enabled

Receive FDL Abort.

0 = interrupt masked

1 = interrupt enabled

—

Not Assigned. Should be set to 0 when written to.

26 of 60

DS2151Q

6 ERROR COUNT REGISTERS

There are a set of three counters in the DS2151Q that record bipolar violations, excessive 0s, errors in the

CRC6 codewords, framing bit errors, and number of multiframes that the device is out of receive

synchronization. Each of these three counters are automatically updated on one second boundaries as

determined by the one second timer in Status Register 2 (SR2.5). Hence, these registers contain

performance data from the previous second. The user can use the interrupt from the 1-second timer to

determine when to read these registers. The user has a full second to read the counters before the data is

lost. All three counters will saturate at their respective maximum counts and they will not rollover (note:

only the Line Code Violation Count Register has the potential to overflow).

6.1 Line Code Violation Count Register (LCVCR)

Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least

significant word of a 16-bit counter that records code violations (CVs). CVs are defined as Bipolar

Violations (BPVs) or excessive 0s. See Table 6-1 for details of exactly what the LCVCRs count. If the

B8ZS mode is set for the receive side via CCR2.2, then B8ZS codewords are not counted. This counter is

always enabled; it is not disabled during receive loss of synchronization (RLOS = 1) conditions.

LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address = 23 Hex)

LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address = 24 Hex)

(MSB)

LCV15

LCV7

(LSB)

LCV14

LCV6

LCV13

LCV5

LCV12

LCV4

LCV11

LCV3

LCV10

LCV2

LCV9

LCV1

LCV8 LCVCR1

LCV0 LCVCR2

SYMBOL

POSITION

NAME AND DESCRIPTION

LCV15

LCVCR1.7

MSB of the 16-bit code violation count

LCV0

LCVCR2.0

LSB of the 16-bit code violation count

Table 6-1. Line Code Violation Counting Arrangements

COUNT

EXCESSIVE 0S?

(RCR1.7)

No

B8ZS

ENABLED?

(CCR2.2)

No

WHAT IS COUNTED

IN THE

LCVCRs

BPVs

Yes

No

BPVs + 16 consecutive 0s

BPVs (B8ZS codewords

not counted)

No

Yes

BPVs + 8 consecutive 0s

27 of 60

DS2151Q

6.2 Path Code Violation Count Register (PCVCR)

When the receive side of the DS2151Q is set to operate in the ESF framing mode (CCR2.3 = 1), PCVCR

will automatically be set as a 12-bit counter that will record errors in the CRC6 codewords. When set to

operate in the D4 framing mode (CCR2.3 = 0), PCVCR will automatically count errors in the Ft framing

bit position. Via the RCR2.1 bit, the DS2151Q can be programmed to also report errors in the Fs framing

bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS = 1) conditions.

See Table 6-2 for a detailed description of exactly what errors the PCVCR counts.

PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address = 25 Hex)

PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address = 26 Hex)

(MSB)

(LSB)

(Note 1)

CRC/FB11 CRC/FB10 CRC/FB9 CRC/FB8 PCVCR1

CRC/FB7 CRC/FB6 CRC/FB5 CRC/FB4 CRC/FB3

CRC/FB2

CRC/FB1 CRC/FB0 PCVCR2

SYMBOL POSITION NAME AND DESCRIPTION

CRC/FB11 PCVCR1.3 MSB of the 12-Bit CRC6 Error or Frame Bit Error

Count (Note 2)

CRC/FB0 PCVCR2.0 LSB of the 12-Bit CRC6 Error or Frame Bit Error Count

(Note 2)

Note 1: The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register.

Note 2: PCVCR counts either errors in CRC codewords (in the ESF framing mode; CCR2.3 = 1) or errors in the framing bit position (in the

D4 framing mode; CCR2.3 = 0).

Table 6-2. Path Code Violation Counting Arrangements

FRAMING MODE

COUNT FS ERRORS?

WHAT IS COUNTED

(CCR2.3)

D4

(RCR2.1)

No

IN THE PCVCRs

Errors in the Ft pattern

Errors in both the Ft and Fs patterns

Errors in the CRC6 codewords

D4

ESF

Yes

Don’t Care

28 of 60

DS2151Q

6.3 Multiframes Out of Sync Count Register (MOSCR)

Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of

sync (RCR2.0 = 1). This number is useful in ESF applications needing to measure the parameters Loss Of

Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the

MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS = 1)

conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft

framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the

MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS = 1)

conditions. See Table 6-3 for a detailed description of what the MOSCR is capable of counting.

MOSCR1: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1 (Address = 25

Hex)

MOSCR2: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2 (Address = 27

Hex)

(MSB)

(LSB)

MOS/FB11 MOS/FB10 MOS/FB9 MOS/FB8

(Note 1)

MOSCR1

MOSCR2

MOS/FB7

MOS/FB6

MOS/FB5 MOS/FB4 MOS/FB3 MOS/FB2 MOS/FB1 MOS/FB0

SYMBOL

POSITION

NAME AND DESCRIPTION

MOS/FB11

MOSCR1.7

MSB of the 12-Bit Multiframes Out of Sync or F-Bit

Error Count (Note 2)

MOS/FB0

MOSCR2.0

LSB of the 12-Bit Multiframes Out of Sync or F-Bit Error

Count (Note 2)

Note 1: The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register.

Note 2: MOSCR counts either errors in framing bit position (RCR2.0 = 0) or the number of multiframes out of sync (RCR2.0 = 1).

Table 6-3. Multiframes Out of Sync Counting Arrangements

FRAMING MODE COUNT MOS OR F-BIT

WHAT IS COUNTED

(CCR2.3)

D4

ERRORS? (RCR2.0)

IN THE MOSCRs

MOS

F-Bit

MOS

F-Bit

Number of multiframes out of sync

Errors in the Ft pattern

Number of multiframes out of sync

Errors in the FPS pattern

D4

ESF

29 of 60

DS2151Q

7 FDL/FS EXTRACTION AND INSERTION

The DS2151Q can extract/insert data from/into the Facility Data Link (FDL) in the ESF framing mode

and from/into Fs bit position in the D4 framing mode. Since SLC-96 utilizes the Fs bit position, this

capability can also be used in SLC-96 applications. The operation of the receive and transmit sections

will be discussed separately.

7.1 Receive Section

In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL

register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2ms (8 times 250µs). The

DS2151Q will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via

IMR2.4, the INT2 pin will toggle low indicating that the buffer has filled and needs to be read. The user

has 2ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed

into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT2 pin will be

toggled low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or

Fs pattern until an important event occurs.

The DS2151Q also contains a 0 destuffer that is controlled via the CCR2.0 bit. In both ANSI T1.403 and

TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states

that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or

closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2151Q will

automatically look for five 1s in a row, followed by a 0. If it finds such a pattern, it will automatically

remove the 0. If the 0 destuffer sees six or more 1s in a row followed by a 0, the 0 is not removed. The

CCR2.0 bit should always be set to a 1 when the DS2151Q is extracting the FDL. More on how to use the

DS2151Q in FDL and SLC-96 applications is covered in a separate application note. Also, contact the

factory for C code software that implements both ANSI T1.403 and AT&T TR54016.

RFDL: RECEIVE FDL REGISTER (Address = 28 Hex)

(MSB)

(LSB)

RFDL7

RFDL6

RFDL5

RFDL4

RFDL3

RFDL2

RFDL1

RFDL0

SYMBOL

POSITION

NAME AND DESCRIPTION

RFDL7

RFDL.7

MSB of the Received FDL Code

RFDL0

RFDL.0

LSB of the Received FDL Code

The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs

bits. The LSB is received first.

30 of 60

DS2151Q

RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex)

RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex)

(MSB)

(LSB)

RFDL7

RFDL6

RFDL5

RFDL4

RFDL3

RFDL2

RFDL1

RFDL0

SYMBOL

POSITION

NAME AND DESCRIPTION

RFDL7

RFDL.7

MSB of the FDL Match Code

RFDL0

RFDL.0

LSB of the FDL Match Code

When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers

(RFDLM1/RFDLM2), SR2.2 will be set to a 1 and the INT2 will go active if enabled via IMR2.2.

7.2 Transmit Section

The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or

the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value

is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing

T1 data stream. After the full 8 bits have been shifted out, the DS2151Q will signal the host

microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The

INT2 will also toggle low if enabled via IMR2.3. The user has 2ms to update the TFDL with a new value.

If the TFDL is not updated, the old value in the TFDL will be transmitted once again.

The DS2151Q also contains a 0 stuffer that is controlled via the CCR2.4 bit. In both ANSI T1.403 and

TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states

that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or

closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the DS2151Q will

automatically look for five 1s in a row. If it finds such a pattern, it will automatically insert a 0 after the

five 1s. The CCR2.4 bit should always be set to a 1 when the DS2151Q is inserting the FDL. More on

how to use the DS2151Q in FDL and SLC-96 applications is covered in a separate application note.

TFDL: TRANSMIT FDL REGISTER (Address = 7E Hex)

(MSB)

(LSB)

TFDL7

TFDL6

TFDL5

TFDL4

TFDL3

TFDL2

TFDL1

TFDL0

SYMBOL

POSITION

NAME AND DESCRIPTION

TFDL7

TFDL.7

MSB of the FDL code to be transmitted

TFDL0

TFDL.0

LSB of the FDL code to be transmitted

The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be

inserted on a byte basis into the outgoing T1 data stream in ESF mode. The LSB is transmitted first. In

D4 operation the TFDL can be the source of the Fs pattern. In this case a 1ch is written to the TFDL

register.

31 of 60

DS2151Q

8 SIGNALING OPERATION

The Robbed-Bit signaling bits embedded in the T1 stream can be extracted from the receive stream and

inserted into the transmit stream by the DS2151Q. There is a set of 12 registers for the receive side (RS1

to RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below.

The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to 0,

then the robbed signaling bits will appear at RSER in their proper position as they are received. If

CCR1.5 is set to a 1, then the robbed signaling bit positions will be forced to a 1 at RSER.

RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address = 60 to 6B Hex)

(MSB)

A(8)

(LSB)

A(1)

A(7)

A(15)

A(23)

B(7)

A(6)

A(14)

A(22)

B(6)

A(5)

A(13)

A(21)

B(5)

A(4)

A(12)

A(20)

B(4)

A(3)

A(11)

A(19)

B(3)

A(2)

A(10)

A(18)

B(2)

B(10)

B(18)

A/C(2)

A/C(10)

RS1 (60)

RS2 (61)

RS3 (62)

RS4 (63)

RS5 (64)

RS6 (65)

RS7 (66)

RS8 (67)

RS9 (68)

RS10 (69)

RS11 (6A)

A(16)

A(24)

B(8)

A(9)

A(17)

B(1)

B(16)

B(24)

A/C(8)

B(15)

B(23)

A/C(7)

B(14)

B(22)

A/C(6)

B(13)

B(21)

A/C(5)

B(12)

B(20)

A/C(4)

B(11)

B(19)

A/C(3)

B(9)

B(17)

A/C(1)

A/C(9)

A/C(16) A/C(15) A/C(14) A/C(13) A/C(12) A/C(11)

A/C(24) A/C(23) A/C(22) A/C(1) A/C(20) A/C(19)

A/C(18) A/C(17)

B/D(8)

B/D(7)

B/D(6)

B/D(5)

B/D(4)

B/D(3)

B/D(2)

B/D(10)

B/D(1)

B/D(9)

B/D(16) B/D(15) B/D(14) B/D(13) B/D(12) B/D(11)

B/D(24) B/D(23) B/D(22) B/D(21) B/D(20) B/D(19)

B/D(18) B/D(17) RS12 (6B)

SYMBOL

POSITION

NAME AND DESCRIPTION

D(24)

RS12.7

Signaling Bit D in Channel 24

A(1)

RS1.0

Signaling Bit A in Channel 1

Each Receive Signaling Register (RS1 to RS12) reports the incoming Robbed-Bit signaling from eight

DS0 channels. In the ESF framing mode, there can be up to 4 signaling bits per channel (A, B, C, and D).

In the D4 framing mode, there are only 2 framing bits per channel (A and B). In the D4 framing mode,

the DS2151Q will replace the C and D signaling bit positions with the A and B signaling bits from the

previous multiframe. Hence, whether the DS2151Q is operated in either framing mode, the user needs

only to retrieve the signaling bits every 3ms. The bits in the Receive Signaling Registers are updated on

multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status

Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers are

frozen and not updated during a loss of sync condition (SR1.0 = 1). They will contain the most recent

signaling information before the “OOF” occurred.

32 of 60

DS2151Q

TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address = 70 to 7B Hex)

(MSB)

A(8)

(LSB)

A(1)

A(7)

A(15)

A(23)

B(7)

A(6)

A(14)

A(22)

B(6)

A(5)

A(13)

A(21)

B(5)

A(4)

A(12)

A(20)

B(4)

A(3)

A(11)

A(19)

B(3)

A(2)

A(10)

A(18)

B(2)

TS1 (70)

TS2 (71)

TS3 (72)

TS4 (73)

TS5 (74)

TS6 (75)

TS7 (76)

TS8 (77)

TS9 (78)

TS10 (79)

TS11 (7A)

TS12 (7B)

A(16)

A(24)

B(8)

A(9)

A(17)

B(1)

B(16)

B(24)

A/C(8)

B(15)

B(23)

A/C(7)

B(14)

B(22)

A/C(6)

B(13)

B(21)

A/C(5)

B(12)

B(20)

A/C(4)

B(11)

B(19)

A/C(3)

B(10)

B(18)

A/C(2)

B(9)

B(17)

A/C(1)

A/C(16) A/C(15) A/C(14) A/C(13) A/C(12) A/C(11) A/C(10) A/C(9)

A/C(24) A/C(23) A/C(22) A/C(1) A/C(20) A/C(19) A/C(18) A/C(17)

B/D(8)

B/D(7)

B/D(6)

B/D(5)

B/D(4)

B/D(3)

B/D(2)

B/D(1)

B/D(16) B/D(15) B/D(14) B/D(13) B/D(12) B/D(11) B/D(10) B/D(9)

B/D(24) B/D(23) B/D(22) B/D(21) B/D(20) B/D(19) B/D(18) B/D(17)

SYMBOL

POSITION

NAME AND DESCRIPTION

D(24)

TS12.7

Signaling Bit D in Channel 24

A(1)

TS1.0

Signaling Bit A in Channel 1

Each Transmit Signaling Register (TS1 to TS12) contains the Robbed-Bit signaling for eight DS0

channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF framing

mode, there can be up to 4 signaling bits per channel (A, B, C, and D). On multiframe boundaries, the

DS2151Q will load the values present in the Transmit Signaling Register into an outgoing signaling shift

register that is internal to the device. The user can utilize the Transmit Multiframe Interrupt in Status

Register 2 (SR2.6) to know when to update the signaling bits. In the ESF framing mode, the interrupt will

come every 3ms and the user has a full 3ms to update the TSRs. In the D4 framing mode, there are only 2

framing bits per channel (A and B). However in the D4 framing mode, the DS2151Q uses the C and D bit

positions as the A and B bit positions for the next multiframe. The DS2151Q will load the values in the

TSRs into the outgoing shift register every other D4 multiframe.

33 of 60

DS2151Q

9 TRANSMIT TRANSPARENCY AND IDLE REGISTERS

There is a set of seven registers in the DS2151Q that can be used to custom tailor the data that is to be

transmitted onto the T1 line, on a channel-by-channel basis. Each of the 24 T1 channels can be either

forced to be transparent or to have a user defined idle code inserted into them. Each of these special

registers is defined below.

TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (Address = 39

to 3B Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH1

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

TTR1 (39)

TTR2 (3A)

TTR3 (3B)

CH9

CH17

SYMBOL

POSITION

NAME AND DESCRIPTION

CH24

TTR3.7

Transmit Transparency Registers.

0 = this DS0 channel is not transparent

CH1

TTR1.0

1 = this DS0 channel is transparent

Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represents a DS0

channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or

clear). If a DS0 is programmed to be clear, no Robbed-Bit signaling will be inserted nor will the channel

have Bit 7 stuffing performed. However, in the D4 framing mode, Bit 2 will be overwritten by a 0 when a

Yellow Alarm is transmitted. Also the user has the option to prevent the TTR registers from determining

which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set to 1, then all

24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR registers are

programmed. In this manner, the TTR registers are only affecting which channels are to have Robbed-Bit

signaling inserted into them. See Figure 14-9 for more details.

TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address = 3C to 3E Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH1

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

TIR1 (3C)

TIR2 (3D)

TIR3 (3E)

CH9

CH17

SYMBOL

POSITION

NAME AND DESCRIPTION

CH24

TIR3.7

Transmit Idle Registers.

0 = do not insert the Idle Code into this DS0 channel

1 = insert the Idle Code into this channel

CH1

TIR1.0

34 of 60

DS2151Q

TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 3F Hex)

(MSB)

(LSB)

TIDR7

TIDR6

TIDR5

TIDR4

TIDR3

TIDR2

TIDR1

TIDR0

SYMBOL

POSITION

NAME AND DESCRIPTION

MSB of the Idle Code

TIDR7

TIDR0

TIDR.7

TIDR.0

LSB of the Idle Code

Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in

the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code

contained in the Transmit Idle Definition Register (TIDR). Robbed-Bit signaling and Bit 7 stuffing will

occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit

Transparency Registers.

35 of 60

DS2151Q

10 CLOCK BLOCKING REGISTERS

The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking

Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins, respectively. The

RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low during

individual channels. These outputs can be used to block clocks to a USART or LAPD controller in

Fractional T1 or ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and

TCHCLK pins will be held high during the entire corresponding channel time. See the timing diagrams in

Section 14 for an example.

RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS

(Address = 6C to 6E Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH1

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

RCBR1 (6C)

RCBR2 (6D)

RCBR3 (6E)

CH9

CH17

SYMBOL

POSITION

NAME AND DESCRIPTION

CH24

RCBR3.7

Receive Channel Blocking Registers

0 = force the RCHBLK pin to remain low during this

channel time

CH1

RCBR1.0

1 = force the RCHBLK pin high during this channel time

TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS

(Address = 32 to 34 Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH1

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

TCBR1 (32)

TCBR2 (33)

TCBR3 (34)

CH9

CH17

SYMBOL

POSITION

NAME AND DESCRIPTION

Transmit Channel Blocking Registers.

CH24

TCBR3.7

0 = force the TCHBLK pin to remain low during this

channel time

CH1

TCBR1.0

1 = force the TCHBLK pin high during this channel time

36 of 60

DS2151Q

11 ELASTIC STORES OPERATION

The DS2151Q has two on-board two-frame (386 bits) elastic stores. These elastic stores have two main

purposes. First, they can be used to rate-convert the T1 data stream to 2.048Mbps (or a multiple of

2.048Mbps), which is the E1 rate. Secondly, they can be used to absorb the differences in frequency and

phase between the T1 data stream and an asynchronous (i.e., not frequency locked) backplane clock. Both

elastic stores contain full controlled slip capability, which is necessary for this second purpose. The

receive side elastic store can be enabled via CCR1.2 and the transmit side elastic store is enabled via

CCR1.7. The elastic stores can be forced to a known depth via the Elastic Store Reset bit (CCR3.6).

11.1Receive Side

If the receive side elastic store is enabled (CCR1.2 = 1), then the user must provide either a 1.544MHz

(CCR1.3 = 0) or 2.048MHz (CCR1.3 = 1) clock at the SYSCLK pin. The user has the option of either

providing a frame sync at the RSYNC pin (RCR2.3 = 1) or having the RSYNC pin provide a pulse on

frame boundaries (RCR2.3 = 0). If the user wishes to obtain pulses at the frame boundary, then RCR2.4

must be set to 0 and if the user wishes to have pulses occur at the multiframe boundary, then RCR2.4

must be set to 1. If the user selects to apply a 2.048 MHz clock to the SYSCLK pin, then the data output

at RSER will be forced to all 1s every fourth channel and the F-bit will be deleted. Hence, channels 1, 5,

9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) will be forced to a 1.

Also, in 2.048MHz applications, the RCHBLK output will be forced high during the same channels as the

RSER pin. See Section 16 for more details. This is useful in T1 to CEPT (E1) conversion applications. If

the 386-bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a

full frame of data (193 bits) will be repeated at RSER and the SR1.4 and RIR1.3 bits will be set to a 1. If

the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR1.4 bits will be set to a 1.

11.2Transmit Side

The transmit side elastic store can only be used if the receive side elastic store is enabled. The operation

of the transmit elastic store is very similar to the receive side; both have controlled slip operation and both

can operate with either a 1.544MHz or a 2.048MHz SYSCLK. When the transmit elastic store is enabled,

both the SYSCLK and RSYNC signals are shared by both the elastic stores. Hence, they will have the

same backplane PCM frame and data structure. Controlled slips in the transmit elastic store are reported

in the RIR2.5 bit and the direction of the slip is reported in the RIR2.3 and RIR2.4 bits.

11.3Minimum Delay Synchronous SYSCLK Mode

In applications where the DS2151Q is connected to backplanes that are frequency-locked to the recovered

T1 clock (i.e., the RCLK output), the full two-frame depth of the onboard elastic stores is really not

needed. In fact, in some delay-sensitive applications the normal two-frame depth may be excessive. If the

CCR3.7 bit is set to 1, then the receive elastic store (and also the transmit elastic store if it is enabled) will

be forced to a maximum depth of 32 bits instead of the normal 386 bits. In this mode, the SYSCLK must

be frequency-locked to RCLK and all of the slip contention logic in the DS2151Q is disabled (since slips

cannot occur). Also, since the buffer depth is no longer two frames deep, the DS2151Q must be set up to

source either a frame or multiframe pulse at the RSYNC pin. On power-up after the SYSCLK has locked

to the RCLK signal, the Elastic Store Reset bit (CCR3.6) should be toggled from a 0 to a 1 to ensure

proper operation.

37 of 60

DS2151Q

12 RECEIVE MARK REGISTERS

The DS2151Q can replace the incoming data on a channel-by-channel basis with either an idle code (7F

hex) or the digital milliwatt code, which is an 8-byte repeating pattern that represents a 1kHz sine wave

(1E/0B/0B/1E/9E/8B/8B/9E). The RCR2.7 bit will determine which code is used. Each bit in the RMRs,

represents a particular channel. If a bit is set to a 1, then the receive data in that channel will be replaced

with one of the two codes. If a bit is set to 0, no replacement occurs.

RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address=2D to 2F Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH1

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

RMR1 (2D)

RMR2 (2E)

RMR3 (2F)

CH9

CH17

SYMBOL

POSITION

NAME AND DESCRIPTION

Receive Channel Blocking Registers.

CH24

RMR3.7

0 = do not affect the receive data associated with this

channel

CH1

RMR1.0

1 = replace the receive data associated with this channel

with either the idle code or the digital milliwatt code

(depends on the RCR2.7 bit)

38 of 60

DS2151Q

13 LINE INTERFACE FUNCTIONS

The line interface function in the DS2151Q contains three sections: the receiver, which handles clock and

data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of

these three sections is controlled by the Line Interface Control Register (LICR), which is described

below.

LICR: LINE INTERFACE CONTROL REGISTER (Address = 7C Hex)

(MSB)

(LSB)

LB2

LB1

LB0

EGL

JAS

JABDS

DJA

TPD

LICR

SYMBOL

POSITION

NAME AND DESCRIPTION

LB2

LB1

LB0

EGL

LICR.7

Line Build-Out Select Bit 2. Sets the transmitter build

out; see the Table 13-2.

LICR.6

LICR.5

LICR.4

Line Build-Out Select Bit 1. Sets the transmitter build

out; see the Table 13-2.

Line Build-Out Select Bit 0. Sets the transmitter build

out; see the Table 13-2.

Receive Equalizer Gain Limit.

0 = -36dB

1 = -30dB

JAS

LICR.3

Jitter Attenuator Select.

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

JABDS

DJA

LICR.2

LICR.1

Jitter Attenuator Buffer Depth Select.

0 = 128 bits

1 = 32 bits (use for delay sensitive applications)

Disable Jitter Attenuator.

0 = jitter attenuator enabled

1 = jitter attenuator disabled

TPD

LICR.0

Transmit Power Down.

0 = normal transmitter operation

1 = powers down the transmitter and tri-states the TTIP

and TRING pins

39 of 60

DS2151Q

13.1Receive Clock and Data Recovery

The DS2151Q contains a digital clock recovery system. See Figure 1-1 and Figure 13-1 for more details.

The DS2151Q couples to the receive T1 twisted pair via a 1:1 transformer. See Table 13-3 for

transformer details. The DS2151Q automatically adjusts to the T1 signal being received at the RTIP and

RRING pins and can handle T1 lines from 0 feet to over 6000 feet in length. The crystal attached at the

XTAL1 and XTAL2 pins is multiplied by 4 via an internal PLL and fed to the clock recovery system. The

clock recovery system uses both edges of the clock from the PLL circuit to form a 32 times oversampler

which is used to recover the clock and data. This oversampling technique offers outstanding jitter

tolerance (see Figure 13-2). The EGL bit in the Line Interface Control Register is used to limit the

sensitivity of the receiver in the DS2151Q. For most CPE applications, a receiver sensitivity of -30dB is

wholly sufficient and hence the EGL bit should be set to 1. In some applications, more sensitivity than

-30dB may be required and the DS2151Q will allow the receiver to go as low as -36dB if the EGL bit is

set to 0. However, when the EGL bit is set to 0, the DS2151Q will be more susceptible to crosstalk and its

jitter tolerance will suffer.

Normally, the clock that is output at the RCLK pin is the recovered clock from the T1 AMI waveform

presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a Receive

Carrier Loss (RCL) condition will occur and the RCLK can be sourced from either the ACLKI pin or

from the crystal attached to the XTAL1 and XTAL2 pins. The DS2151Q will sense the ACLKI pin to

determine if a clock is present. If no clock is applied to the ACLKI pin, then it should be tied to RVSS to

prevent the device from falsely sensing a clock. See Table 13-1. If the jitter attenuator is either placed in

the transmit path or is disabled, the RCLK output can exhibit short high cycles of the clock. This is due to

the highly oversampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path

(as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty

cycle. See the receive AC timing characteristics in Section 16 for more details.

Table 13-1. Source of RCLK Upon RCL

RECEIVE SIDE JITTER

ATTENUATOR

TRANSMIT SIDE JITTER

ATTENUATOR

ACLKI PRESENT?

Yes

No

ACLKI via the jitter attenuator

Centered crystal

ACLKI

TCLK via the jitter attenuator

40 of 60

DS2151Q

13.2 Transmit Waveshaping and Line Driving

The DS2151Q uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter

(DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the

DS2151Q meet the latest ANSI, AT&T, and CCITT specifications. See Figure 13-3. The user will select

which waveform is to be generated by properly programming the L0 to L2 bits in the Line Interface

Control Register (LICR).

Table 13-2. LBO Select in LICR

L2

0

L1

0

L0

0

LINE BUILD-OUT

0 to 133 feet/0dB

133 to 266 feet

266 to 399 feet

399 to 533 feet

533 to 655 feet

-7.5dB

APPLICATION

DSX-1/CSU

DSX-1

0

1

0

1

0

DSX-1

0

1

DSX-1

1

0

DSX-1

1

0

1

CSU

1

0

-15dB

CSU

1

-22.5dB

CSU

Due to the nature of the design of the transmitter in the DS2151Q, very little jitter (less than 0.005UI_P-P

broadband from 10Hz to 100kHz) is added to the jitter present on TCLK. Also, the waveforms that they

create are independent of the duty cycle of TCLK. The transmitter in the DS2151Q couples to the T1

transmit twisted pair via a 1:1.15 or 1:1.36 step-up transformer as shown in Figure 13-1. For the devices

to create the proper waveforms, the transformer used must meet the specifications listed in Table 13-3.

Table 13-3. Transformer Specifications

SPECIFICATION

Turns Ratio

Primary Inductance

Leakage Inductance

Intertwining Capacitance

DC Resistance

RECOMMENDED VALUE

1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ±5%

600µH minimum

1.0µH maximum

40pF maximum

1.2Ω maximum

41 of 60

DS2151Q

13.3 Jitter Attenuator

The DS2151Q contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via

the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications

where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.

The characteristics of the attenuation are shown in Figure 13-4. The jitter attenuator can be placed in

either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.

Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA-bit in the LICR. In order

for the jitter attenuator to operate properly, a crystal with the specifications listed in Table 13-4 below

must be connected to the XTAL1 and XTAL2 pins. The jitter attenuator divides the clock provided by the

6.176MHz crystal at the XTAL1 and XTAL2 pins to create an output clock that contains very little jitter.

On-board circuitry will pull the crystal (by switching in or out load capacitance) to keep it long-term

averaged to the same frequency as the incoming T1 signal. If the incoming jitter exceeds either 120UI_P-P

(buffer depth is 128 bits) or 28UI_P-P(buffer depth is 32 bits), then the DS2151Q will divide the attached

crystal by either 3.5 or 4.5 instead of the normal 4 to keep the buffer from overflowing. When the device

divides by either 3.5 or 4.5, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive

Information Register 2 (RIR2.2).

Table 13-4. Crystal Selection Guidelines

PARAMETER

Parallel Resonant Frequency

Mode

SPECIFICATION

6.176MHz

Fundamental

Load Capacitance

Tolerance

18pF to 20pF (18.5pF nominal)

±50ppm

Pullability

C_L= 10pF, delta frequency = +175ppm to

+250ppm

C_L= 45pF, delta frequency = -175ppm to -250ppm

Effective Series Resistance

Crystal Cut

40Ω maximum

AT

42 of 60

DS2151Q

Figure 13-1. External Analog Connections

NOTE: SEE THE SEPARATE APPLICATION NOTE FOR DETAILS ON HOW TO CONSTRUCT A PROTECTED INTERFACE.

Figure 13-2. Jitter Tolerance

43 of 60

DS2151Q

Figure 13-3. Transmit Waveform Template

44 of 60

DS2151Q

Figure 13-4. Jitter Attenuation

45 of 60

DS2151Q

14 TIMING DIAGRAMS

Figure 14-1. Receive Side D4 Timing

NOTE 1: RSYNC IN THE FRAME MODE (RCR2.4 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RCR2.5 = 0).

NOTE 2: RSYNC IN THE FRAME MODE (RCR2.4 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (RCR2.5 = 1).

NOTE 3: RSYNC IN THE MULTIFRAME MODE (RCR2.4 = 1).

NOTE 4: RLINK DATA (S-BIT) IS UPDATED 1 BIT PRIOR TO EVEN FRAMES AND HELD FOR TWO FRAMES.

Figure 14-2. Receive Side ESF Timing

NOTE 1: RSYNC IN THE FRAME MODE (RCR2.4 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RCR2.5 = 0).

NOTE 2: RSYNC IN THE FRAME MODE (RCR2.4 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (RCR2.5 = 1).

NOTE 3: RSYNC IN THE MULTIFRAME MODE (RCR2.4 = 1).

NOTE 4: ZBTSI MODE DISABLED (RCR2.6 = 0).

NOTE 5: RLINK DATA (FDL BITS) IS UPDATED 1 BIT-TIME BEFORE ODD FRAMES AND HELD FOR TWO FRAMES.

NOTE 6: ZBTSI MODE IS ENABLED (RCR2.6 = 1).

NOTE 7: RLINK DATA (Z BITS) IS UPDATED 1 BIT-TIME BEFORE ODD FRAME AND HELD FOR FOUR FRAMES.

46 of 60

DS2151Q

Figure 14-3. Receive Side Boundary Timing with Elastic Store(s) Disabled

NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.

NOTE 2: AN ESF BOUNDARY IS SHOWN.

Figure 14-4. 1.544MHz Boundary Timing with Elastic Store(s) Enabled

NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0).

NOTE 2: RSYNC IS IN THE INPUT MODE (RCR2.3 = 1).

NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.

47 of 60

DS2151Q

Figure 14-5. 2.048MHz Boundary Timing with Elastic Store(s) Enabled

NOTE 1: RSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO 1; TSER IGNORED DURING THESE CHANNELS.

NOTE 2: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0).

NOTE 3: RSYNC IS IN THE INPUT MODE (RCR2.3 = 1).

NOTE 4: RCHBLK IS FORCED TO 1 IN THE SAME CHANNELS AS RSER (SEE NOTE 1).

Figure 14-6. Transmit Side D4 Timing

NOTE 1: TSYNC IN THE FRAME MODE (TCR2.3 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TCR2.4 = 0).

NOTE 2: TSYNC IN THE FRAME MODE (TCR2.3 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TCR2.4 = 1).

NOTE 3: TSYNC IN THE MULTIFRAME MODE (TCR2.3 = 1).

NOTE 4: TLINK DATA (S-BIT) IS SAMPLED DURING THE F-BIT POSITION OF EVEN FRAMES FOR INSERTION INTO THE OUTGOING T1

STREAM WHEN ENABLED VIA TCR1.2.

48 of 60

DS2151Q

Figure 14-7. Transmit Side ESF Timing

NOTE 1: TSYNC IN THE FRAME MODE (TCR2.3 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TCR2.4 = 0).

NOTE 2: TSYNC IN THE FRAME MODE (TCR2.3 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TCR2.4 = 1).

NOTE 3: TSYNC IN THE MULTIFRAME MODE (TCR2.4 = 1).

NOTE 4: ZBTSI MODE DISABLED (TCR2.5 = 0).

NOTE 5: TLINK DATA (FDL BITS) IS SAMPLED DURING THE F-BIT TIME OF ODD FRAME AND INSERTED INTO THE OUTGOING T1 STREAM

IF ENABLED VIA TCR1.2.

NOTE 6: ZBTSI MODE IS ENABLED (TCR2.5 = 1).

NOTE 7: TLINK DATA (Z BITS) IS SAMPLED DURING THE F-BIT TIME OF FRAME 1, 5, 9, 13, 17, AND 21 AND INSERTED INTO THE

OUTGOING STREAM IF ENABLED VIA TCR1.2.

49 of 60

DS2151Q

Figure 14-8. Transmit Side Boundary Timing with Elastic Store(s) Disabled

NOTE 1: TSYNC IS IN THE INPUT MODE (TCR2.2 = 0).

NOTE 2: TSYNC IS IN THE OUTPUT MODE (TCR2.2 = 1).

NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.

NOTE 4: SEE Figure 14-4 AND Figure 14-5 FOR DETAILS ON TIMING WITH THE TRANSMIT SIDE ELASTIC STORE ENABLED.

50 of 60

DS2151Q

Figure 14-9. Transmit Data Flow

51 of 60

DS2151Q

15 DC CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +7.0V

Operating Temperature Range

Commercial…………………………………………………………...………..……...0°C to +70°C

Industrial…………………………………………………………………………….-40°C to +85°C

Storage Temperature ………………………………………………………………………-55°C to +125°C

Soldering Temperature...………………………………………..See IPC/JEDEC J-STD-020 Specification

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect

reliability.

Table 15-1. Recommended DC Characteristics

(T_A= 0°C to +70°C for DS2151Q, T_A= -40°C to +85°C for DS2151QN.)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Logic 1

Logic 0

Supply

V_IH

2.0

-0.3

4.75

V_DD+ 0.3

V

V_IL

+0.8

V

V_DD

5.25

V

1

Table 15-2. Capacitance

(T_A= +25°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Input Capacitance

Output Capacitance

C_IN

C_OUT

5

7

pF

Table 15-3. DC Characteristics

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2151Q, T_A= -40°C to +85°C for DS2151QN.)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Supply Current at 5V

I_DD

65

mA

µA

mA

2

3

4

Input Leakage

I_IL

-1.0

+1.0

1.0

Output Leakage

Output Current (2.4V)

Output Current (0.4V)

I_LO

I_OH

I_OL

-1.0

+4.0

NOTES:

1) Applies to RVDD, TVDD, and DVDD.

2) TCLK = 1.544MHz.

3) 0V < V_IN< V_DD.

4) Applies to INT1 and INT1 when tri-stated.

52 of 60

DS2151Q

16 AC CHARACTERISTICS

Table 16-1. AC Characteristics—Parallel Port

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2151Q, T_A= -40°C to +85°C for DS2151QN.)

(See Figure 16-1, Figure 16-2, and Figure 16-3.)

PARAMETER

Cycle Time

SYMBOL

MIN

250

TYP

MAX

UNITS NOTES

t_CYC

ns

Pulse Width, DS Low or RD

PW_EL

150

ns

High

Pulse Width, DS High or RD

Low

PW_EH

100

ns

Input Rise/Fall Times

t_R, t_F

t_RWH

30

ns

10

50

R/ W Hold Time

R/ W Setup Time before DS

t_RWS

ns

High

CS Setup Time before DS,

WR or RD Active

CS Hold Time

t_CS

20

ns

t_CH

t_DHR

t_DHW

t_ASL

t_AHL

0

10

0

ns

Read Data Hold Time

Write Data Hold Time

Muxed Address Valid to AS

or ALE Fall

50

20

10

25

40

20

ns

Muxed Address Hold Time

Delay Time DS, WR or RD

t_ASD

to AS or ALE Rise

Pulse Width AS or ALE High

Delay Time, AS or ALE to

DS, WR or RD

PW_ASH

t_ASED

Output Data Delay Time from

DS or RD

Data Setup Time

t_DDR

t_DSW

20

80

100

ns

53 of 60

DS2151Q

Figure 16-1. Intel Bus Read AC Timing

Figure 16-2. Intel Bus Write AC Timing

54 of 60

DS2151Q

Figure 16-3. Motorola Bus AC Timing

55 of 60

DS2151Q

Table 16-2. AC Characteristics—Receive Side

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2151Q, T_A= -40°C to +85°C for DS2151QN.)

(See Figure 16-4.)

PARAMETER

ACLKI/RCLK Period

SYMBOL

MIN

TYP

648

324

MAX

UNITS NOTES

t_CP

t_CH

t_CL

t_CH

t_CL

t_SP

t_SH

t_SL

ns

230

115

RCLK Pulse Width

SYSCLK Period

1

2

648

488

3

4

75

SYSCLK Pulse Width

RSYNC Setup to SYSCLK

Falling

t_SU

25

50

t_SH-5

ns

RSYNC Pulse Width

SYSCLK Rise/Fall Times

Delay RCLK or SYSCLK to

RSER Valid

t_PW

t_R, t_F

ns

25

80

t_DD

t_D1

t_D2

t_D3

10

ns

Delay RCLK or SYSCLK to

RCHCLK

90

80

Delay RCLK or SYSCLK to

RCHBLK

Delay RCLK or SYSCLK to

RSYNC

Delay RCLK to RLCLK

Delay RCLK to RLINK Valid

t_D4

t_D5

10

80

110

ns

NOTES:

1) Jitter attenuator enabled in the receive side path.

2) Jitter attenuator disabled or enabled in the transmit path.

3) SYSCLK = 1.544MHz.

4) SYSCLK = 2.048MHz.

56 of 60

DS2151Q

Figure 16-4. Receive Side AC Timing

NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0).

NOTE 2: RSYNC IS IN THE INPUT MODE (RCR2.3 = 1).

NOTE 3: RLCLK AND RLINK ONLY HAVE A TIMING RELATIONSHIP TO RCLK.

NOTE 4: RCLK CAN EXHIBIT A SHORT HIGH TIME IF THE JITTER ATTENUATOR IS EITHER DISABLED OR IN THE TRANSMIT PATH.

57 of 60

DS2151Q

Table 16-3. AC Characteristics—Transmit Side

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2151Q, T_A= -40°C to +85°C for DS2151QN.)

(See Figure 16-5.)

PARAMETER

TCLK Period

SYMBOL

MIN

TYP

648

MAX

UNITS NOTES

t_P

t_CH

t_CL

ns

75

TCLK Pulse Width

TSER and TLINK Set up to

TCLK Falling

t_SU

t_HD

t_SU

25

ns

1

TSER and TLINK Hold from

TCLK Falling

25

ns

TSYNC Set up to TCLK

Falling

25

50

t_CH-5

TSYNC Pulse Width

TCLK Rise/Fall Times

Delay TCLK to TCHCLK

Delay TCLK to TCHBLK

Delay TCLK to TSYNC

Delay TCLK to TLCLK

t_PW

t_R, t_F

t_D1

25

60

70

60

ns

10

t_D2

t_D3

t_D4

NOTES:

1) If the transmit side elastic store is enabled, then TSER is sampled on the falling edge of SYSCLK and

the parameters t_SUand t_HDstill apply.

58 of 60

DS2151Q

Figure 16-5. Transmit Side AC Timing

NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR2.2 = 1).

NOTE 2: TSYNC IS IN THE INPUT MODE (TCR2.2 = 0).

NOTE 3: TSER IS SAMPLED ON THE FALLING EDGE OF SYSCLK IF THE TRANSMIT SIDE ELASTIC STORE IS ENABLED.

59 of 60

DS2151Q

17 PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for

each package is a link to the latest package outline information.)

17.1 44-Pin PLCC (56-G4003-001)

60 of 60

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.


型号：	DS2151QBX2
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Framer, CMOS, PQCC44, 0.652 INCH, PLASTIC, LCC-44 电信电信集成电路
文件：	总62页 (文件大小：921K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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