DS2152L+_技术文档

DS2152

Enhanced T1 Single-Chip Transceiver

www.maxim-ic.com

FEATURES

PIN CONFIGURATION

ꢀ Complete DS1/ISDN-PRI Transceiver

Functionality

TOP VIEW

ꢀ Line Interface can Handle Both Long- and

Short-Haul Trunks

ꢀ 32-Bit or 128-Bit Crystal-Less Jitter

Attenuator

DS2152

ꢀ Generates DSX-1 and CSU Line Build-Outs

ꢀ Frames to D4, ESF, and SLC-96^RFormats

ꢀ Dual On-Board Two-Frame Elastic Store Slip

Buffers That can Connect to Asynchronous

Backplanes Up to 8.192MHz

ꢀ 8-Bit Parallel Control Port That can be Used

Directly on Either Multiplexed or

Nonmultiplexed Buses (Intel or Motorola)

ꢀ Extracts and Inserts Robbed-Bit Signaling

ꢀ Detects and Generates Yellow (RAI) and

Blue (AIS) Alarms

ꢀ Programmable Output Clocks for Fractional

T1

1

LQFP

ꢀ Fully Independent Transmit and Receive

Functionality

(14mm x 14mm)

ꢀ Integral HDLC Controller with 16-Byte

Buffers for the FDL

ORDERING INFORMATION

ꢀ Generates and Detects In-Band Loop Codes

from 1 to 8 bits in Length Including CSU

Loop Codes

TEMP

PIN-

PART

RANGE

PACKAGE

100 LQFP

DS2152L

0°C to +70°C

-40°C to +85°C

ꢀ Contains ANSI Ones Density Monitor and

Enforcer

DS2152L+

DS2152LN

DS2152LN+

ꢀ Large Path and Line Error Counters Including

BPV, CV, CRC6, and Framing Bit Errors

ꢀ Pin Compatible with DS2154 E1 Enhanced

Single-Chip Transceiver

+Denotes lead-free/RoHS-compliant package.

ꢀ 5V Supply; Low-Power CMOS

ꢀ 100-Pin, 14mm²LQFP Package

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

1 of 97

REV: 011706

DS2152

TABLE OF CONTENTS

1 DETAILED DESCRIPTION....................................................................................................6

1.1 INTRODUCTION................................................................................................................................6

1.1.1

New Features......................................................................................................................................... 6

1.2 FUNCTIONAL DESCRIPTION..............................................................................................................7

1.3 READER’S NOTE..............................................................................................................................7

2 PIN DESCRIPTION................................................................................................................9

2.1 TRANSMIT SIDE DIGITAL PINS ........................................................................................................11

2.2 RECEIVE SIDE DIGITAL PINS ..........................................................................................................12

2.3 PARALLEL CONTROL PORT PINS....................................................................................................13

2.4 LINE INTERFACE PINS....................................................................................................................14

2.5 SUPPLY PINS ................................................................................................................................14

3 PARALLEL PORT...............................................................................................................18

4 CONTROL, ID, AND TEST REGISTERS ............................................................................18

4.1 PAYLOAD LOOPBACK.....................................................................................................................24

4.2 FRAMER LOOPBACK ......................................................................................................................24

4.3 PULSE DENSITY ENFORCER...........................................................................................................24

4.4 LOCAL LOOPBACK .........................................................................................................................24

4.5 POWER-UP SEQUENCE .................................................................................................................30

4.6 REMOTE LOOPBACK ......................................................................................................................30

5 STATUS AND INFORMATION REGISTERS......................................................................31

6 ERROR COUNT REGISTERS.............................................................................................40

6.1 LINE CODE VIOLATION COUNT REGISTER (LCVCR) .......................................................................40

6.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR)......................................................................41

6.3 MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR) ............................................................41

7 DS0 MONITORING FUNCTION ..........................................................................................43

8 SIGNALING OPERATION...................................................................................................47

8.1 PROCESSOR-BASED SIGNALING ....................................................................................................47

8.2 HARDWARE-BASED SIGNALING ......................................................................................................49

8.2.1

8.2.2

Receive Side........................................................................................................................................ 49

Transmit Side....................................................................................................................................... 49

9 PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK .....................................50

9.1 TRANSMIT SIDE CODE GENERATION ..............................................................................................50

9.1.1

9.1.2

Simple Idle Code Insertion and Per-Channel Loopback...................................................................... 50

Per-Channel Code Insertion ................................................................................................................ 51

9.2 RECEIVE SIDE CODE GENERATION ................................................................................................52

9.2.1

9.2.2

Simple Code Insertion.......................................................................................................................... 52

Per-Channel Code Insertion ................................................................................................................ 52

10 CLOCK BLOCKING REGISTERS....................................................................................54

11 ELASTIC STORES OPERATION.....................................................................................55

11.1

11.2

11.3

RECEIVE SIDE............................................................................................................................55

TRANSMIT SIDE..........................................................................................................................55

MINIMUM DELAY SYNCHRONOUS RSYSCLK/TSYSCLK MODE...................................................56

12 FDL/FS EXTRACTION AND INSERTION........................................................................57

12.1

HDLC AND BOC CONTROLLER FOR THE FDL.............................................................................57

12.1.1 Status Register for the FDL ................................................................................................................. 57

12.1.2 Basic Operation Details........................................................................................................................ 58

2 of 97

DS2152

12.1.3 Receive an HDLC Message or a BOC................................................................................................. 59

12.1.4 Transmit an HDLC Message................................................................................................................ 59

12.1.5 Transmit a BOC ................................................................................................................................... 59

12.1.6 HDLC/BOC Register Description......................................................................................................... 60

12.2

LEGACY FDL SUPPORT..............................................................................................................67

12.2.1 Receive Section ................................................................................................................................... 67

12.2.2 Transmit Section .................................................................................................................................. 68

12.3

D4/SLC-96 OPERATION .........................................................................................................69

13 PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION........................70

14 TRANSMIT TRANSPARENCY.........................................................................................74

15 LINE INTERFACE FUNCTION.........................................................................................75

15.1

15.2

15.3

RECEIVE CLOCK AND DATA RECOVERY.......................................................................................76

TRANSMIT WAVESHAPING AND LINE DRIVING ..............................................................................76

JITTER ATTENUATOR..................................................................................................................77

16 TIMING DIAGRAMS.........................................................................................................80

17 DC CHARACTERISTICS..................................................................................................86

18 AC CHARACTERISTICS..................................................................................................87

19 PACKAGE INFORMATION..............................................................................................97

19.1

100-PIN LQFP (56-G5002-000)................................................................................................97

3 of 97

DS2152

LIST OF FIGURES

Figure 1-1. DS2152 Enhanced T1 Single-Chip Transceiver ......................................................................8

Figure 15-1. External Analog Connections...............................................................................................78

Figure 15-2. Jitter Tolerance ....................................................................................................................78

Figure 15-3. Transmit Waveform Template..............................................................................................79

Figure 15-4. Jitter Attenuation ..................................................................................................................79

Figure 16-1. Receive Side D4 Timing.......................................................................................................80

Figure 16-2. Receive Side Boundary Timing (with Elastic Store Disabled)..............................................80

Figure 16-3. Receive Side Boundary Timing (with Elastic Store Disabled)..............................................81

Figure 16-4. Receive Side 1.544MHz Boundary Timing (with Elastic Store Enabled) .............................81

Figure 16-5. Receive Side 2.048MHz Boundary Timing (with Elastic Store Enabled) .............................82

Figure 16-6. Transmit Side D4 Timing......................................................................................................82

Figure 16-7. Transmit Side Timing ...........................................................................................................83

Figure 16-8. Transmit Side Boundary Timing...........................................................................................83

Figure 16-9. Transmit Side 1.544MHz Boundary Timing (with Elastic Store Enabled) ............................84

Figure 16-10. Transmit Side 2.048MHz Boundary Timing (with Elastic Store Enabled) ..........................84

Figure 16-11. Transmit Data Flow............................................................................................................85

Figure 18-1. Intel Bus Read AC Timing (BTS = 0/MUX = 1) ....................................................................87

Figure 18-2. Intel Bus Write AC Timing (BTS = 0/MUX = 1).....................................................................88

Figure 18-3. Motorola Bus AC Timing (BTS = 1/MUX = 1).......................................................................88

Figure 18-4. Receive Side AC Timing ......................................................................................................90

Figure 18-5. Receive System Side AC Timing .........................................................................................91

Figure 18-6. Receive Line Interface AC Timing........................................................................................91

Figure 18-7. Transmit Side AC Timing .....................................................................................................93

Figure 18-8. Transmit System Side AC Timing ........................................................................................94

Figure 18-9. Transmit Line Interface Side AC Timing...............................................................................94

Figure 18-10. Intel Bus Read AC Timing (BTS = 0/MUX = 0) ..................................................................95

Figure 18-11. Intel Bus Write AC Timing (BTS=0/MUX=0).......................................................................96

Figure 18-12. Motorola Bus Read AC Timing (BTS = 1/MUX = 0) ...........................................................96

Figure 18-13. Motorola Bus Write AC Timing (BTS = 1/MUX = 0) ...........................................................96

4 of 97

DS2152

LIST OF TABLES

Table 2-1. Register Map...........................................................................................................................15

Table 4-1. Output Pin Test Modes............................................................................................................22

Table 5-1. Receive T1 Level Indication ....................................................................................................34

Table 5-2. Alarm Criteria ..........................................................................................................................36

Table 6-1. Line Code Violation Counting Arrangements ..........................................................................40

Table 6-2. Path Code Violation Counting Arrangements..........................................................................41

Table 6-3. Multiframes Out of Sync Counting Arrangements ...................................................................42

Table 12-1. HDLC/BOC Controller Register List ......................................................................................57

Table 13-1. Transmit Code Length...........................................................................................................71

Table 13-2. Receive Code Length............................................................................................................71

Table 15-1. Line Build-Out Select in LICR................................................................................................76

Table 15-2. Transformer Specifications....................................................................................................77

Table 17-1. Recommended DC Operating Conditions.............................................................................86

Table 17-2. Capacitance ..........................................................................................................................86

Table 17-3. DC Characteristics ................................................................................................................86

Table 18-1. AC Characteristics—Multiplexed Parallel Port (MUX = 1).....................................................87

Table 18-2. AC Characteristics—Receive Side........................................................................................89

Table 18-3. AC Characteristics—Transmit Side.......................................................................................92

Table 18-4. AC Characteristics—Nonmultiplexed Parallel Port (MUX = 0) ..............................................95

5 of 97

DS2152

1 DETAILED DESCRIPTION

The DS2152 T1 enhanced single-chip transceiver (SCT) contains all the necessary functions for

connection to T1 lines, whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry

automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both

DSX-1 line build-outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The on-board jitter

attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data

paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It

is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set

of internal registers that the user can access and control the operation of the unit. Quick access via the

parallel control port allows a single controller to handle many T1 lines. The device fully meets all the

latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90),

AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.

1.1 Introduction

The DS2152 is a superset version of the popular DS2151 T1 single-chip transceiver offering the new

features listed below. All of the original features of the DS2151 have been retained and software created

for the original devices is transferable into the DS2152.

1.1.1 New Features

ꢀ Option for non-multiplexed bus operation

ꢀ Crystal-less jitter attenuation

ꢀ Additional hardware signaling capability including:

– Receive signaling reinsertion to a backplane multiframe sync

– Availability of signaling in a separate PCM data stream

– Signaling freezing

– Interrupt generated on change of signaling data

ꢀ Per-channel code insertion in both transmit and receive paths

ꢀ Full HDLC controller for the FDL with 16-byte buffers in both transmit and receive paths

ꢀ RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state

ꢀ 8.192MHz clock synthesizer

ꢀ Per-channel loopback

ꢀ Addition of hardware pins to indicate carrier loss and signaling freeze

ꢀ Line interface function can be completely decoupled from the framer/formatter to allow:

– Interface to optical, HDSL, and other NRZ interfaces

– Ability to “tap” the transmit and receive bipolar data streams for monitoring purposes

– Ability to corrupt data and insert framing errors, CRC errors, etc.

ꢀ Transmit and receive elastic stores now have independent backplane clocks

ꢀ Ability to monitor one DS0 channel in both the transmit and receive paths

ꢀ Access to the data streams in between the framer/formatter and the elastic stores

ꢀ AIS generation in the line interface that is independent of loopbacks

ꢀ Ability to calculate and check CRC6 according to the Japanese standard

ꢀ Ability to pass the F-bit position through the elastic stores in the 2.048MHz backplane mode

ꢀ Programmable in-band loop code generator and detector

6 of 97

DS2152

1.2 Functional Description

The analog AMI/B8ZS waveform off the T1 line is transformer-coupled into the RRING and RTIP pins

of the DS2152. The device recovers clock and data from the analog signal and passes it through the jitter

attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the

framing/multi-frame pattern. The DS2152 contains an active filter that reconstructs the analog received

signal for the non-linear losses that occur in transmission. The device has a usable receive sensitivity of

0dB to -36dB, which allows the device to operate on cables up to 6000 feet in length. The receive side

framer locates D4 (SLC-96) or ESF multiframe boundaries as well as detects incoming alarms, including

carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the receive side elastic store

can be enabled in order to absorb the phase and frequency differences between the recovered T1 data

stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock

applied at the RSYSCLK input can be either a 2.048MHz clock or a 1.544MHz clock. The RSYSCLK

can be a bursty clock with speeds up to 8.192MHz.

The transmit side of the DS2152 is totally independent from the receive side in both the clock

requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic

store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for

T1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter

attenuation mux to the waveshaping and line driver functions. The DS2152 will drive the T1 line from the

TTIP and TRING pins via a coupling transformer. The line driver can handle both long (CSU) and short

haul (DSX-1) lines.

1.3 Reader’s Note

This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125µs frame,

there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by

channel 1. Each channel is made up of 8 bits that are numbered 1 to 8. Bit number 1 is the MSB and is

transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the

following abbreviations are used:

D4

Superframe (12 frames per multiframe) Multiframe Structure

Subscriber Loop Carrier - 96 Channels (SLC-96 is an AT&T registered trademark)

Extended Superframe (24 frames per multiframe) Multiframe Structure

Bipolar with 8 0 Substitution

SLC-96

ESF

B8ZS

CRC

Ft

Cyclical Redundancy Check

Terminal Framing Pattern in D4

Fs

Signaling Framing Pattern in D4

FPS

MF

Framing Pattern in ESF

Multiframe

BOC

HDLC

FDL

Bit Oriented Code

High Level Data Link Control

Facility Data Link

7 of 97

DS2152

Figure 1-1. DS2152 Enhanced T1 Single-Chip Transceiver

8 of 97

DS2152

2 PIN DESCRIPTION

NAME

TYPE

FUNCTION

1

RCHBLK

O

Receive Channel Block

2, 4, 5,

7–10, 15, 23,

N.C.

—

No Connection. These pins should be left open circuited.

26, 27, 28,

36, 54, 76

3

8MCLK

RCL

O

I

8.192MHz Clock

6

Receive Carrier Loss

11

BTS

Bus Type Select

12

LIUC

I

Line Interface Connect

Eight Times Clock

13

8XCLK

TEST

O

I

14

Test

16

RTIP

I

Receive Analog Tip Input

Receive Analog Ring Input

Receive Analog Positive Supply

Receive Analog Signal Ground

Master Clock Input

17

RRING

RVDD

RVSS

18

—

I

19, 20, 24

21

MCLK

XTALD

INT

22

O

—

O

I

Quartz Crystal Driver

Active-Low Interrupt

25

29

TTIP

TVSS

Transmit Analog Tip Output

Transmit Analog Signal Ground

Transmit Analog Positive Supply

Transmit Analog Ring Output

Transmit Channel Block

Transmit Link Clock

30

31

TVDD

TRING

TCHBLK

TLCLK

TLINK

TSYNC

TPOSI

TNEGI

TCLKI

TCLKO

TNEGO

TPOSO

32

33

34

35

Transmit Link Data

Transmit Sync

37

I/O

I

38

Transmit Positive Data Input

Transmit Negative Data Input

Transmit Clock Input

39

I

40

41

O

Transmit Clock Output

Transmit Negative Data Output

Transmit Positive Data Output

42

43

44, 61, 81,

DVDD

—

Digital Positive Supply

83

45, 60, 80,

DVSS

—

Digital Signal Ground

84

46

47

48

49

50

51

52

53

55

56

TCLK

TSER

I

Transmit Clock

Transmit Serial Data

TSIG

I

Transmit Signaling Input

Transmit Elastic Store Output

Transmit Data

TESO

O

I

TDATA

TSYSCLK

TSSYNC

TCHCLK

MUX

I

Transmit System Clock

Transmit System Sync

Transmit Channel Clock

Bus Operation

O

I

D0/AD0

I/O

Data Bus Bit 0/Address/Data Bus Bit 0

9 of 97

DS2152

57

NAME

D1/AD1

D2/AD2

D3/AD3

D4/AD4

D5/AD5

D6/AD6

D7/AD7

A0–A6

TYPE

I/O

I

FUNCTION

Data Bus Bit 1/Address/Data Bus Bit 1

Data Bus Bit 2/Address/Data Bus Bit 2

Data Bus Bit 3/Address/Data Bus Bit 3

Data Bus Bit 4/Address/Data Bus Bit 4

Data Bus Bit 5/Address/Data Bus Bit 5

Data Bus Bit 6/Address/Data Bus Bit 6

Data Bus Bit 7/Address/Data Bus Bit 7

Address Bus Bit 0

58

59

62

63

64

65

66–72

73

A7/ALE

RD(DS)

I

Address Bus Bit 7/Address Latch Enable

Active-Low Read Input (Data Strobe)

74

I

CS

75

I

Active-Low Chip Select

77

WR(R/W)

I

Active-Low Write Input (Read/Write)

78

79

82

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

RLINK

RLKCLK

RCLK

O

I

O

I/O

O

I

Receive Link Data

Receive Link Clock

Receive Clock

RDATA

RPOSI

Receive Data

Receive Positive Data Input

Receive Negative Data Input

Receive Clock Input

RNEGI

RCLKI

RCLKO

RNEGO

RPOSO

RCHCLK

RSIGF

Receive Clock Output

Receive Negative Data Output

Receive Positive Data Output

Receive Channel Clock

Receive Signaling Freeze Output

Receive Signaling Output

Receive Serial Data

RSIG

RSER

RMSYNC

RFSYNC

RSYNC

RLOS/LOTC

RSYSCLK

Receive Multiframe Sync

Receive Frame Sync

Receive Sync

Receive Loss of Sync/Loss of Transmit Clock

Receive System Clock

10 of 97

DS2152

2.1 Transmit Side Digital Pins

NAME

FUNCTION

Transmit Clock. A 1.544MHz primary clock. Used to clock data through the transmit

side formatter.

Transmit Serial Data. Transmit NRZ serial data. Sampled on the falling edge of

TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of

TSYSCLK when the transmit side elastic store is enabled.

46

TCLK

47

53

TSER

Transmit Channel Clock. A 192kHz clock that pulses high during the LSB of each

channel. Synchronous with TCLK when the transmit side elastic store is disabled.

Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for

parallel to serial conversion of channel data.

TCHCLK

Transmit Channel Block. A user-programmable output that can be forced high or low

during any of the 24 T1 channels. Synchronous with TCLK when the transmit side

elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic

store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in

applications where not all T1 channels are used such as Fractional T1, 384kbps (H0),

768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert

applications, for external per-channel loopback, and for per-channel conditioning. See

Section 10 for details.

33

TCHBLK

Transmit System Clock. 1.544MHz or 2.048MHz clock. Only used when the transmit

51

34

35

TSYSCLK side elastic store function is enabled. Should be tied low in applications that do not use

the transmit side elastic store. Can be burst at rates up to 8.192MHz.

Transmit Link Clock. 4 kHz or 2kHz (ZBTSI) demand clock for the TLINK input. See

TLCLK

Section 12 for details. Transmit Link Data [TLINK].

Transmit Link Data. If enabled via TCR1.2, this pin will be sampled on the falling

TLINK

edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position

(D4) or the Z-bit position (ZBTSI). See Section 12 for details.

Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries

for the transmit side. Via TCR2.2, the DS2152 can be programmed to output either a

frame or multiframe pulse at this pin. If this pin is set to output pulses at frame

boundaries, it can also be set via TCR2.4 to output double-wide pulses at signaling

frames. See Section 16 for details.

37

TSYNC

Transmit System Sync. Only used when the transmit side elastic store is enabled. A

pulse at this pin will establish either frame or multiframe boundaries for the transmit

side. Should be tied low in applications that do not use the transmit side elastic store.

Transmit Signaling Input. When enabled, this input will sample signaling bits for

insertion into outgoing PCM T1 data stream. Sampled on the falling edge of TCLK

when the transmit side elastic store is disabled. Sampled on the falling edge of

TSYSCLK when the transmit side elastic store is enabled.

52

48

TSSYNC

TSIG

Transmit Elastic Store Data Output. Updated on the rising edge of TCLK with data

out of the transmit side elastic store whether the elastic store is enabled or not. This pin

is normally tied to TDATA.

49

50

43

42

TESO

TDATA

TPOSO

TNEGO

Transmit Data. Sampled on the falling edge of TCLK with data to be clocked through

the transmit side formatter. This pin is normally tied to TESO.

Transmit Positive Data Output. Updated on the rising edge of TCLKO with the

bipolar data out of the transmit side formatter. Can be programmed to source NRZ data

via the Output Data Format (CCR1.6) control bit. This pin is normally tied to TPOSI.

Transmit Negative Data Output. Updated on the rising edge of TCLKO with the

bipolar data out of the transmit side formatter. This pin is normally tied to TNEGI.

Transmit Clock Output. Buffered clock that is used to clock data through the transmit

side formatter (i.e., either TCLK or RCLKI). This pin is normally tied to TCLKI.

Transmit Positive Data Input. Sampled on the falling edge of TCLKI for data to be

41

38

TCLKO

TPOSI

11 of 97

DS2152

NAME

FUNCTION

transmitted out onto the T1 line. Can be internally connected to TPOSO by tying the

LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.

Transmit Negative Data Input. Sampled on the falling edge of TCLKI for data to be

transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the

LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications.

Transmit Clock Input. Line interface transmit clock. Can be internally connected to

TCLKO by tying the LIUC pin high.

39

40

TNEGI

TCLKI

2.2 Receive Side Digital Pins

78

NAME

RLINK

RLCLK

RCLK

FUNCTION

Receive Link Data. Updated with either FDL data (ESF) or Fs bits (D4) or Z bits

(ZBTSI) one RCLK before the start of a frame. See Section 16 for details.

Receive Link Clock. A 4kHz or 2 kHz (ZBTSI) clock for the RLINK output.

Receive Clock. 1.544MHz clock that is used to clock data through the receive side

framer.

79

82

Receive Channel Clock. A 192kHz clock that pulses high during the LSB of each

channel. Synchronous with RCLK when the receive side elastic store is disabled.

Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for

parallel to serial conversion of channel data.

92

1

RCHCLK

Receive Channel Block. A user-programmable output that can be forced high or low

during any of the 24 T1 channels. Synchronous with RCLK when the receive side elastic

store is disabled. Synchronous with RSYSCLK when the receive side elastic store is

enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications

where not all T1 channels are used, such as Fractional T1, 384kbps service, 768kbps, or

ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications,

for external per-channel loopback, and for per-channel conditioning. See Section 10 for

details.

RCHBLK

Receive Serial Data. Received NRZ serial data. Updated on rising edges of RCLK

when the receive side elastic store is disabled. Updated on the rising edges of

RSYSCLK when the receive side elastic store is enabled.

95

98

RSER

Receive Sync. An extracted pulse, one RCLK wide, is output at this pin, which

identifies either frame (RCR2.4 = 0) or multiframe (RCR2.4 = 1) boundaries. If set to

output frame boundaries then via RCR2.5, RSYNC can also be set to output double-

wide pulses on signaling frames. If the receive side elastic store is enabled via CCR1.2,

then this pin can be enabled to be an input via RCR2.3 at which a frame or multiframe

boundary pulse is applied. See Section 16 for details.

RSYNC

Receive Frame Sync. An extracted 8kHz pulse 1 RCLK wide is output at this pin that

identifies frame boundaries.

97

96

RFSYNC

RMSYNC

RDATA

Receive Multiframe Sync. Only used when the receive side elastic store is enabled. An

extracted pulse, 1 RSYSCLK wide, is output at this pin, which identifies multiframe

boundaries. If the receive side elastic store is disabled, then this output will output

multiframe boundaries associated with RCLK.

Receive Data. Updated on the rising edge of RCLK with the data out of the receive side

framer.

85

Receive System Clock. 1.544MHz or 2.048MHz clock. Only used when the elastic

100

RSYSCLK store function is enabled. Should be tied low in applications that do not use the elastic

store. Can be burst at rates up to 8.192MHz.

Receive Signaling Output. Outputs signaling bits in a PCM format. Updated on rising

94

RSIG

edges of RCLK when the receive side elastic store is disabled. Updated on the rising

edges of RSYSCLK when the receive side elastic store is enabled.

12 of 97

DS2152

NAME

FUNCTION

Receive Loss of Sync/Loss of Transmit Clock. A dual function output that is

controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high

when the synchronizer is searching for the frame and multiframe or to toggle high if the

TCLK pin has not been toggled for 5µs.

Receive Carrier Loss. Set high when the line interface detects a loss of carrier.

Receive Signaling Freeze. Set high when the signaling data is frozen via either

automatic or manual intervention. Used to alert downstream equipment of the condition.

8MHz Clock. A 8.192MHz output clock that is referenced to the clock that is output at

the RCLK pin and is used to clock data through the receive side framer.

Receive Positive Data Output. Updated on the rising edge of RCLKO with the bipolar

data out of the line interface. This pin is normally tied to RPOSI.

Receive Negative Data Output. Updated on the rising edge of RCLKO with the bipolar

data out of the line interface. This pin is normally tied to RNEGI.

Receive Clock Output. Buffered recovered clock from the T1 line. This pin is normally

tied to RCLKI.

99

RLOS/LOTC

6

RCL

93

RSIGF

3

8MCLK

RPOSO

RNEGO

RCLKO

91

90

89

Receive Positive Data Input. Sampled on the falling edge of RCLKI for data to be

clocked through the receive side framer. RPOSI and RNEGI can be tied together for a

NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.

Receive Negative Data Input. Sampled on the falling edge of RCLKI for data to be

clocked through the receive side framer. RPOSI and RNEGI can be tied together for a

NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.

Receive Clock Input. Clock used to clock data through the receive side framer. This pin

is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC

pin high.

86

87

88

RPOSI

RNEGI

RCLKI

2.3 Parallel Control Port Pins

NAME

FUNCTION

Interrupt. Flags host controller during conditions and change of conditions defined in

the Status Registers 1 and 2 and the FDL Status Register. Active-low, open-drain

output.

25

INT

Tri-State Control. Set high to tri-state all output and I/O pins (including the parallel

control port). Set low for normal operation. Useful in board-level testing.

Bus Operation. Set low to select nonmultiplexed bus operation. Set high to select

multiplexed bus operation.

14

55

TEST

MUX

Data Bus or Address/Data Bus. In nonmultiplexed bus operation (MUX = 0), serves as

the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed

address/data bus.

D0–D7/

56–65

66–72

11

AD0–AD7

Address Bus. In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In

multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.

Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus

timing. This pin controls the function of the RD ( DS), ALE(AS), and WR (R/ W ) pins.

If BTS = 1, then these pins assume the function listed in parentheses.

A0–A6

BTS

Read Input (Data Strobe). RD and DS are active-low signals when MUX = 1. DS is

74

75

RD(DS)

active high when MUX = 0. See bus timing diagrams.

CS

Chip Select. Must be low to read or write to the device. CS is an active-low signal.

A7 or Address Latch Enable (Address Strobe). In non-multiplexed bus operation

(MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1),

serves to demultiplex the bus on a positive-going edge.

73

77

ALE(AS)

WR(R/W)

Write Input (Read/Write). WR is an active-low signal.

13 of 97

DS2152

2.4 Line Interface Pins

NAME

FUNCTION

Master Clock Input. A 1.544MHz (±50ppm) clock source with TTL levels is applied at

this pin. This clock is used internally for both clock/data recovery and for jitter

attenuation. A quartz crystal of 1.544MHz may be applied across MCLK and XTALD

instead of the TTL level clock source.

21

MCLK

Quartz Crystal Driver. A quartz crystal of 1.544MHz may be applied across MCLK

22

13

XTALD and XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a

TTL clock source is applied at MCLK.

Eight Times Clock. A 12.352MHz clock that is frequency locked to the 1.544MHz

clock provided from the clock/data recovery block (if the jitter attenuator is enabled on

8XCLK

the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit

side). Can be internally disabled via the TEST2 register if not needed.

Line Interface Connect. Tie low to separate the line interface circuitry from the

framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/

RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter

12

LIUC

circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When

LIUC is tied high, the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be

tied low.

RTIP,

RRING

TTIP,

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect

via a 1:1 transformer to the T1 line. See Section 15 for details.

16, 17

29, 32

Transmit Tip and Ring. Analog line driver outputs. These pins connect via a 1:1.15 or

1:1.36 step-up transformer to the T1 line. See Section 15 for details.

TRING

2.5 Supply Pins

NAME

FUNCTION

44, 61,

81, 83

DVDD

Digital Positive Supply. 5.0V ±5%. Should be tied to the RVDD and TVDD pins.

Receive Analog Positive Supply. 5.0V ±5%. Should be tied to the DVDD and TVDD

18

RVDD

TVDD

DVSS

pins.

Transmit Analog Positive Supply. 5.0V ±5%. Should be tied to the RVDD and DVDD

31

pins.

45, 60,

80, 84

19, 20,

24

Digital Signal Ground. Should be tied to the RVSS and TVSS pins.

RVSS

TVSS

Receive Analog Signal Ground. 0V. Should be tied to the DVSS and TVSS pins.

Transmit Analog Ground. 0V. Should be tied to the RVSS and DVSS pins.

30

14 of 97

DS2152

Table 2-1. Register Map

REGISTER

ADDRESS

R/W

DESCRIPTION

NAME

FDLC

00

01

R/W FDL Control

R/W FDL Status

FDLS

02

R/W FDL Interrupt Mask

FIMR

03

R/W Receive Performance Report Message

R/W Receive Bit Oriented Code

RPRM

RBOC

RFFR

04

05

R

Receive FDL FIFO

06

R/W Transmit Performance Report Message

R/W Transmit Bit Oriented Code

TPRM

TBOC

TFFR

07

08

W

Transmit FDL FIFO

09

R/W Test 2

TEST2 (set to 00h)

CCR7

0A

0B–0E

0F

10

R/W Common Control 7

—

R

Not present

Deceive ID

—

IDR

R/W Receive Information 3

R/W Common Control 4

RIR3

11

CCR4

12

R/W In-Band Code Control

R/W Transmit Code Definition

R/W Receive Up Code Definition

R/W Receive Down Code Definition

R/W Transmit Channel Control 1

R/W Transmit Channel Control 2

R/W Transmit Channel Control 3

R/W Common Control 5

IBCC

13

TCD

14

RUPCD

RDNCD

TCC1

15

16

17

TCC2

18

TCC3

19

CCR5

1A

1B

1C

1D

1E

1F

20

R

Transmit DS0 Monitor

TDS0M

RCC1

R/W Receive Channel Control 1

R/W Receive Channel Control 2

R/W Receive Channel Control 3

R/W Common Control 6

RCC2

RCC3

CCR6

R

Receive DS0 Monitor

RDS0M

SR1

R/W Status 1

21

22

R/W Status 2

R/W Receive Information 1

SR2

RIR1

23

24

25

26

27

R

Line Code Violation Count 1

Line Code Violation Count 2

Path Code Violation Count 1

Path Code Violation Count 2

Multiframe Out of Sync Count 2

Receive FDL Register

LCVCR1

LCVCR2

PCVCR1

PCVCR2

MOSCR2

RFDL

28

29

R/W Receive FDL Match 1

R/W Receive FDL Match 2

R/W Receive Control 1

R/W Receive Control 2

R/W Receive Mark 1

R/W Receive Mark 2

R/W Receive Mark 3

R/W Common Control 3

R/W Receive Information 2

R/W Transmit Channel Blocking 1

RMTCH1

RMTCH2

RCR1

2A

2B

2C

2D

2E

2F

30

RCR2

RMR1

RMR2

RMR3

CCR3

31

32

RIR2

TCBR1

15 of 97

DS2152

REGISTER

ADDRESS

R/W

DESCRIPTION

NAME

TCBR2

TCBR3

TCR1

TCR2

CCR1

CCR2

TTR1

TTR2

TTR3

TIR1

TIR2

TIR3

TIDR

TC9

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

R/W Transmit Channel Blocking 2

R/W Transmit Channel Blocking 3

R/W Transmit Control 1

R/W Transmit Control 2

R/W Common Control 1

R/W Common Control 2

R/W Transmit Transparency 1

R/W Transmit Transparency 2

R/W Transmit Transparency 3

R/W Transmit Idle 1

R/W Transmit Idle 2

R/W Transmit Idle 3

R/W Transmit Idle Definition

R/W Transmit Channel 9

R/W Transmit Channel 10

R/W Transmit Channel 11

R/W Transmit Channel 12

R/W Transmit Channel 13

R/W Transmit Channel 14

R/W Transmit Channel 15

R/W Transmit Channel 16

R/W Transmit Channel 17

R/W Transmit Channel 18

R/W Transmit Channel 19

R/W Transmit Channel 20

R/W Transmit Channel 21

R/W Transmit Channel 22

R/W Transmit Channel 23

R/W Transmit Channel 24

R/W Transmit Channel 1

R/W Transmit Channel 2

R/W Transmit Channel 3

R/W Transmit Channel 4

R/W Transmit Channel 5

R/W Transmit Channel 6

R/W Transmit Channel 7

R/W Transmit Channel 8

R/W Receive Channel 1

R/W Receive Channel 18

R/W Receive Channel 19

R/W Receive Channel 20

R/W Receive Channel 21

R/W Receive Channel 22

TC10

TC11

TC12

TC13

TC14

TC15

TC16

TC17

TC18

TC19

TC20

TC21

TC22

TC23

TC24

TC1

TC2

TC3

TC4

TC5

TC6

TC7

TC8

RC17

RC18

RC19

RC20

RC21

RC22

RC23

RC24

RS1

R/W

Receive Channel 23

R/W Receive Channel 24

R

Receive Signaling 1

Receive Signaling 2

Receive Signaling 3

Receive Signaling 4

Receive Signaling 5

Receive Signaling 6

RS2

RS3

RS4

RS5

RS6

16 of 97

DS2152

REGISTER

ADDRESS

R/W

DESCRIPTION

Receive Signaling 7

Receive Signaling 8

Receive Signaling 9

Receive Signaling 10

Receive Signaling 11

Receive Signaling 12

NAME

RS7

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

R

RS8

RS9

RS10

RS11

RS12

RCBR1

RCBR2

RCBR3

IMR2

TS1

R/W Receive Channel Blocking 1

R/W Receive Channel Blocking 2

R/W Receive Channel Blocking 3

R/W Interrupt Mask 2

R/W Transmit Signaling 1

R/W Transmit Signaling 2

R/W Transmit Signaling 3

R/W Transmit Signaling 4

R/W Transmit Signaling 5

R/W Transmit Signaling 6

R/W Transmit Signaling 7

R/W Transmit Signaling 8

R/W Transmit Signaling 9

R/W Transmit Signaling 10

R/W Transmit Signaling 11

R/W Transmit Signaling 12

R/W Line Interface Control

R/W Test 1

TS2

TS3

TS4

TS5

TS6

TS7

TS8

TS9

TS10

TS11

TS12

LICR

TEST1 (set to 00h)

TFDL

IMR1

RC1

R/W Transmit FDL Register

R/W Interrupt Mask Register 1

R/W Receive Channel 1

R/W Receive Channel 2

R/W Receive Channel 3

R/W Receive Channel 4

R/W Receive Channel 5

R/W Receive Channel 6

R/W Receive Channel 7

R/W Receive Channel 8

R/W Receive Channel 9

R/W Receive Channel 10

R/W Receive Channel 11

R/W Receive Channel 12

R/W Receive Channel 13

R/W Receive Channel 14

RC2

RC3

RC4

RC5

RC6

RC7

RC8

RC9

RC10

RC11

RC12

RC13

RC14

RC15

RC16

R/W

Receive Channel 15

R/W Receive Channel 16

Note 1: Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all 0s) on power-up initialization to ensure proper

operation.

Note 2: Register banks 9xh, Axh, Bxh, Cxh, Dxh, Exh, and Fxh are not accessible.

17 of 97

DS2152

3 PARALLEL PORT

The DS2152 is controlled via either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an

external microcontroller or microprocessor. The DS2152 can operate with either Intel or Motorola bus

timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola

timing will be selected. All Motorola bus signals are listed in parentheses. See the timing diagrams in the

AC Electrical Characteristics in Section 18 for more details.

4 CONTROL, ID, AND TEST REGISTERS

The operation of the DS2152 is configured via a set of 11 control registers. Typically, the control

registers are only accessed when the system is first powered up. Once the DS2152 has been initialized,

the control registers will only need to be accessed when there is a change in the system configuration.

There are two Receive Control Register (RCR1 and RCR2), two Transmit Control Registers (TCR1 and

TCR2), and seven Common Control Registers (CCR1 to CCR7). Each of the 11 registers is described in

this section.

There is a device Identification Register (IDR) at address 0Fh. The MSB of this read-only register is fixed

to a 0 indicating that the DS2152 is present. The E1 pin-for-pin compatible version of the DS2152 is the

DS2154, which also has an ID register at address 0Fh. The user can read the MSB to determine which

chip is present since in the DS2152 the MSB will be set to 0 and in the DS2154 it will be set to 1. The

lower 4 bits of the IDR are used to display the die revision of the chip.

IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex)

(MSB)

(LSB)

T1E1

0

POSITION

IDR.7

0

ID3

ID2

ID1

ID0

SYMBOL

NAME AND DESCRIPTION

T1E1

T1 or E1 Chip Determination Bit.

0 = T1 chip

1 = E1 chip

ID3

IDR.3

Chip Revision Bit 3. MSB of a decimal code that represents the

chip revision.

ID2

ID1

ID0

IDR.1

IDR.2

IDR.0

Chip Revision Bit 2.

Chip Revision Bit 1.

Chip Revision Bit 0. LSB of a decimal code that represents the

chip revision.

The two Test Registers at addresses 09 and 7D hex are used by the factory in testing the DS2152. On

power-up, the Test Registers should be set to 00 hex for the DS2152 to operate properly.

18 of 97

DS2152

RCR1: RECEIVE CONTROL REGISTER 1 (Address = 2B Hex)

(MSB)

(LSB)

RESYNC

LCVCRF

ARC

OOF1

POSITION

RCR1.7

OOF2

SYNCC

SYNCT

SYNCE

SYMBOL

NAME AND DESCRIPTION

LCVCRF

ARC

Line Code Violation Count Register Function Select.

0 = do not count excessive 0s

1 = count excessive 0s

RCR1.6

RCR1.5

RCR1.4

RCR1.3

Auto Resync Criteria.

0 = Resync on OOF or RCL event

1 = Resync on OOF only

OOF1

Out Of Frame Select 1.

0 = 2/4 frame bits in error

1 = 2/5 frame bits in error

OOF2

Out Of Frame Select 2.

0 = follow RCR1.5

1 = 2/6 frame bits in error

SYNCC

Sync Criteria.

In D4 Framing Mode

0 = search for Ft pattern, then search for Fs pattern

1 = cross couple Ft and Fs pattern

In ESF Framing Mode

0 = search for FPS pattern only

1 = search for FPS and verify with CRC6

SYNCT

SYNCE

RCR1.2

RCR1.1

RCR1.0

Sync Time.

0 = qualify 10 bits

1 = qualify 24 bits

Sync Enable.

0 = auto resync enabled

1 = auto resync disabled

RESYNC

Resync. When toggled from low to high, a resynchronization of

the receive side framer is initiated. Must be cleared and set again

for a subsequent resync.

19 of 97

DS2152

RCR2: RECEIVE CONTROL REGISTER 2 (Address = 2C Hex)

(MSB)

(LSB)

MOSCRF

RCS

RZBTSI

RSDW

RSM

RSIO

RD4YM

FSBE

SYMBOL

RCS

POSITION

NAME AND DESCRIPTION

RCR2.7

Receive Code Select. See Section 9 for more details.

0 = idle code (7F Hex)

1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)

RZBTSI

RSDW

RCR2.6

RCR2.5

Receive Side ZBTSI Enable.

0 = ZBTSI disabled

1 = ZBTSI enabled

RSYNC Double-Wide. (Note: This bit must be set to 0 when

RCR2.4 = 1 or when RCR2.3 = 1.)

0 = do not pulse double-wide in signaling frames

1 = do pulse double-wide in signaling frames

RSM

RSIO

RCR2.4

RCR2.3

RSYNC Mode Select. (A don’t care if RSYNC is programmed

as an input.)

0 = frame mode (see the timing diagrams in Section 16)

1 = multiframe mode (see the timing diagrams in Section 16)

RSYNC I/O Select. (Note: This bit must be set to 0 when

CCR1.2 = 0.)

0 = RSYNC is an output

1 = RSYNC is an input (only valid if elastic store enabled)

RD4YM

FSBE

RCR2.2

RCR2.1

RCR2.0

Receive Side D4 Yellow Alarm Select.

0 = 0s in bit 2 of all channels

1 = a 1 in the S-bit position of frame 12

PCVCR Fs-Bit Error Report Enable.

0 = do not report bit errors in Fs-bit position; only Ft bit position

1 = report bit errors in Fs-bit position as well as Ft bit position

MOSCRF

Multiframe Out of Sync Count Register Function Select.

0 = count errors in the framing bit position

1 = count the number of multiframes out of sync

20 of 97

DS2152

TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 35 Hex)

(MSB)

(LSB)

TYEL

LOTCMC

TFPT

TCPT

TSSE

GB7S

TFDLS

TBL

SYMBOL

POSITION

NAME AND DESCRIPTION

LOTCMC

TCR1.7

Loss Of Transmit Clock Mux Control. Determines whether

the transmit side formatter should switch to the ever present

RCLKO if the TCLK input should fail to transition

(see Figure 1-1 for details).

0 = do not switch to RCLKO if TCLK stops

1 = switch to RCLKO if TCLK stops

TFPT

TCPT

TSSE

TCR1.6

TCR1.5

TCR1.4

Transmit F-Bit Pass Through. (See note below.)

0 = F bits sourced internally

1 = F bits sampled at TSER

Transmit CRC Pass Through. (See note below.)

0 = source CRC6 bits internally

1 = CRC6 bits sampled at TSER during F-bit time

Software Signaling Insertion Enable. (See note below.)

0 = no signaling is inserted in any channel from the TS1–TS12

registers

1 = signaling is inserted in all channels from the TS1–TS12

registers (the TTR registers can be used to block insertion on a

channel-by-channel basis)

GB7S

TCR1.3

TCR1.2

Global Bit 7 Stuffing. (See note below.)

0 = allow the TTR registers to determine which channels

containing all 0s are to be Bit 7 stuffed

1 = force Bit 7 stuffing in all 0-byte channels regardless of how

the TTR registers are programmed

TFDLS

TFDL Register Select. (See note below.)

0 = source FDL or Fs bits from the internal TFDL register

(legacy FDL support mode)

1 = source FDL or Fs bits from the internal HDLC/BOC

controller or the TLINK pin

TBL

TCR1.1

TCR1.0

Transmit Blue Alarm. (See note below.)

0 = transmit data normally

1 = transmit an unframed all 1s code at TPOSO and TNEGO

TYEL

Transmit Yellow Alarm. (See note below.)

0 = do not transmit yellow alarm

1 = transmit yellow alarm

Note: For a description of how the bits in TCR1 affect the transmit side formatter, see Figure 16-11.

21 of 97

DS2152

TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 36 Hex)

(MSB)

(LSB)

TB7ZS

TEST1

TEST0

TZBTSI

TSDW

TSM

TSIO

TD4YM

SYMBOL

TEST1

POSITION

NAME AND DESCRIPTION

TCR2.7

TCR2.6

TCR2.5

Test Mode Bit 1 for Output Pins. See Table 4-1.

Test Mode Bit 0 for Output Pins. See Table 4-1.

TEST0

TZBTSI

Transmit Side ZBTSI Enable.

0 = ZBTSI disabled

1 = ZBTSI enabled

TSDW

TCR2.4

TSYNC Double-Wide. (Note: this bit must be set to 0 when

TCR2.3 = 1 or when TCR2.2 = 0.)

0 = do not pulse double-wide in signaling frames

1 = do pulse double-wide in signaling frames

TSM

TSIO

TCR2.3

TCR2.2

TCR2.1

TCR2.0

TSYNC Mode Select.

0 = frame mode (see the timing diagrams in Section 16)

1 = multiframe mode (see the timing diagrams in Section 16)

TSYNC I/O Select.

0 = TSYNC is an input

1 = TSYNC is an output

TD4YM

TB7ZS

Transmit Side D4 Yellow Alarm Select.

0 = 0s in bit 2 of all channels

1 = a 1 in the S-bit position of frame 12

Transmit Side Bit 7 Zero Suppression Enable.

0 = no stuffing occurs

1 = Bit 7 force to a 1 in channels with all 0s

Table 4-1. Output Pin Test Modes

TEST 1

TEST 0

EFFECT ON OUTPUT PINS

0

1

0

1

0

1

Operate normally

Force all output pins tri-state (including all I/O pins and parallel port pins)

Force all output pins low (including all I/O pins except parallel port pins)

Force all output pins high (including all I/O pins except parallel port pins)

22 of 97

DS2152

CCR1: COMMON CONTROL REGISTER 1 (Address = 37 Hex)

(MSB)

(LSB)

FLB

TESE

ODF

RSAO

POSITION

CCR1.7

TSCLKM RSCLKM

RESE

PLB

SYMBOL

TESE

NAME AND DESCRIPTION

Transmit Elastic Store Enable.

0 = elastic store is bypassed

1 = elastic store is enabled

ODF

CCR1.6

CCR1.5

Output Data Format.

0 = bipolar data at TPOSO and TNEGO

1 = NRZ data at TPOSO; TNEGO = 0

RSAO

Receive Signaling All 1s. This bit should not be enabled if

hardware signaling is being utilized. See Section 8 for more

details.

0 = allow robbed signaling bits to appear at RSER

1 = force all robbed signaling bits at RSER to 1

TSCLKM

RSCLKM

RESE

CCR1.4

CCR1.3

CCR1.2

CCR1.1

CCR1.0

TSYSCLK Mode Select.

0 = if TSYSCLK is 1.544MHz

1 = if TSYSCLK is 2.048MHz

RSYSCLK Mode Select.

0 = if RSYSCLK is 1.544MHz

1 = if RSYSCLK is 2.048MHz

Receive Elastic Store Enable.

0 = elastic store is bypassed

1 = elastic store is enabled

PLB

Payload Loopback.

0 = loopback disabled

1 = loopback enabled

FLB

Framer Loopback.

0 = loopback disabled

1 = loopback enabled

23 of 97

DS2152

4.1 Payload Loopback

When CCR1.1 is set to 1, the DS2152 is forced into Payload Loopback (PLB). Normally, this loopback is

only enabled when ESF framing is being performed but can be enabled also in D4 framing applications.

In a PLB situation, the DS2152 loops the 192 bits of payload data (with BPVs corrected) from the receive

section back to the transmit section. The FPS framing pattern, CRC6 calculation, and the FDL bits are not

looped back, rather, they are reinserted by the DS2152. When PLB is enabled, the following occurs:

1) Data is transmitted from the TPOSO and TNEGO pins synchronous with RCLK instead of TCLK.

2) All the receive side signals continue to operate normally.

3) The TCHCLK and TCHBLK signals are forced low.

4) Data at the TSER, TDATA, and TSIG pins is ignored.

5) The TLCLK signal becomes synchronous with RCLK instead of TCLK.

4.2 Framer Loopback

When CCR1.0 is set to 1, the DS2152 enters a Framer Loopback (FLB) mode. This loopback is useful in

testing and debugging applications. In FLB, the DS2152 loops data from the transmit side back to the

receive side. When FLB is enabled, the following occurs:

1) An unframed all-1s code is transmitted at TPOSO and TNEGO.

2) Data at RPOSI and RNEGI is ignored.

3) All receive side signals take on timing synchronous with TCLK instead of RCLKI.

Note that it is not acceptable to have RCLK tied to TCLK during this loopback because this causes an

unstable condition.

4.3 Pulse Density Enforcer

The SCT always examines both the transmit and receive data streams for violations of the following rules

which are required by ANSI T1.403:

•

No more than 15 consecutive 0s,

At least N 1s in each and every time window of 8 x (N + 1) bits where N = 1 through 23,

Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits,

respectively. When the CCR3.3 is set to 1, the DS2152 forces the transmitted stream to meet this

requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should

be set to 0 since B8ZS encoded data streams cannot violate the pulse density requirements.

4.4 Local Loopback

When CCR5.6 is set to 1, the DS2152 is forced into Local Loopback (LLB). In this loopback, data

continues to be transmitted as normal through the transmit side of the DS2152 (unless LIAIS = 1). Data

being received at RTIP and RRING is replaced with the data being transmitted. Data in this loopback

passes through the jitter attenuator. See Figure 1-1 for more details. Note that it is not acceptable to have

RCLKO tied to TCLKI during this loopback because this causes an unstable condition. Also, it is

recommended that the jitter attenuator be placed on the transmit side during this loopback.

24 of 97

DS2152

CCR2: COMMON CONTROL REGISTER 2 (Address = 38 Hex)

(MSB)

(LSB)

RFDL

TFM

TB8ZS

TSLC96

TFDL

RFM

RB8ZS

RSLC96

SYMBOL

TFM

POSITION

NAME AND DESCRIPTION

CCR2.7

CCR2.6

CCR2.5

Transmit Frame Mode Select.

0 = D4 framing mode

1 = ESF framing mode

TB8ZS

Transmit B8ZS Enable.

0 = B8ZS disabled

1 = B8ZS enabled

TSLC96

Transmit SLC-96/Fs-Bit Loading Enable. Only set this bit to a

1 in D4 framing applications. Must be set to 1 to source the Fs

pattern. See Section 12 for details.

0 = SLC-96/Fs-bit loading disabled

1 = SLC-96/Fs-bit loading enabled

TFDL

CCR2.4

Transmit FDL 0 Stuffer Enable. Set this bit to 0 if using the

internal HDLC/BOC controller instead of the legacy support for

the FDL. See Section 12 for details.

0 = 0 stuffer disabled

1 = 0 stuffer enabled

RFM

CCR2.3

CCR2.2

CCR2.1

Receive Frame Mode Select.

0 = D4 framing mode

1 = ESF framing mode

RB8ZS

RSLC96

Receive B8ZS Enable.

0 = B8ZS disabled

1 = B8ZS enabled

Receive SLC-96 Enable. Only set this bit to a 1 in D4/SLC-96

framing applications. See Section 12 for details.

0 = SLC-96 disabled

1 = SLC-96 enabled

RFDL

CCR2.0

Receive FDL 0 Destuffer Enable. Set this bit to 0 if using the

internal HDLC/BOC controller instead of the legacy support for

the FDL. See Section 12 for details.

0 = 0 destuffer disabled

1 = 0 destuffer enabled

25 of 97

DS2152

CCR3: COMMON CONTROL REGISTER 3 (Address = 30 Hex)

(MSB)

(LSB)

ESMDM

ESR

RLOSF

RSMS

PDE

ECUS

TLOOP

—

SYMBOL

POSITION

NAME AND DESCRIPTION

ESMDM

CCR3.7

Elastic Store Minimum Delay Mode. See Section 11.3 for

details.

0 = elastic stores operate at full two-frame depth

1 = elastic stores operate at 32-bit depth

ESR

CCR3.6

Elastic Store Reset. Setting this bit from a 0 to a 1 will force the

elastic stores to a known depth. Should be toggled after

RSYSCLK and TSYSCLK have been applied and are stable.

Must be cleared and set again for a subsequent reset.

RLOSF

RSMS

CCR3.5

CCR3.4

Function of the RLOS/LOTC Output.

0 = Receive Loss of Sync (RLOS)

1 = Loss of Transmit Clock (LOTC)

RSYNC Multiframe Skip Control. Useful in framing format

conversions from D4 to ESF. This function is not available when

the receive side elastic store is enabled.

0 = RSYNC will output a pulse at every multiframe

1 = RSYNC will output a pulse at every other multiframe

Note: for this bit to have any affect, the RSYNC must be set to

output multiframe pulses (RCR2.4 = 1 and RCR2.3 = 0).

PDE

ECUS

TLOOP

CCR3.3

CCR3.2

CCR3.1

Pulse Density Enforcer Enable.

0 = disable transmit pulse density enforcer

1 = enable transmit pulse density enforcer

Error Counter Update Select. See Section 6 for details.

0 = update error counters once a second

1 = update error counters every 42ms (333 frames)

Transmit Loop Code Enable. See Section 13 for details.

0 = transmit data normally

1 = replace normal transmitted data with repeating code as

defined in TCD register

—

CCR3.0

Not Assigned. Must be set to 0 when written.

26 of 97

DS2152

CCR4: COMMON CONTROL REGISTER 4 (Address = 11 Hex)

(MSB)

(LSB)

TIRFS

RSRE

RPCSI

RFSA1

RFE

RFF

THSE

TPCSI

SYMBOL

POSITION NAME AND DESCRIPTION

RSRE

CCR4.7

CCR4.6

Receive Side Signaling Reinsertion Enable. See Section 8.2 for

details.

0 = do not re-insert signaling bits into the data stream presented at the

RSER pin

1 = re-insert the signaling bits into data stream presented at the RSER

RPCSI

Receive Per-Channel Signaling Insert. See Section 8.2 for more

details.

0 = do not use RCHBLK to determine which channels should have

signaling re-inserted

1 = use RCHBLK to determine which channels should have signaling

re-inserted

RFSA1

RFE

CCR4.5

CCR4.4

Receive Force Signaling All 1s. See Section 8.2 for more details.

0 = do not force extracted robbed-bit signaling bit positions to a 1

1 = force extracted robbed-bit signaling bit positions to a 1

Receive Freeze Enable. See Section 8.2 for details.

0 = no freezing of receive signaling data will occur

1 = allow freezing of receive signaling data at RSIG (and RSER if

CCR4.7 = 1).

RFF

CCR4.3

CCR4.2

Receive Force Freeze. Freezes receive side signaling at RSIG (and

RSER if CCR4.7 = 1); will override Receive Freeze Enable (RFE). See

Section 8.2 for details.

0 = do not force a freeze event

1 = force a freeze event

THSE

Transmit Hardware Signaling Insertion Enable. See Section 8.2 for

details.

0 = do not insert signaling from the TSIG pin into the data stream

presented at the TSER pin

1 = insert the signaling from the TSIG pin into data stream presented at

the TSER pin

TPCSI

TIRFS

CCR4.1

CCR4.0

Transmit Per-Channel Signaling Insert. See Section 8.2 for details.

0 = do not use TCHBLK to determine which channels should have

signaling inserted from TSIG

1 = use TCHBLK to determine which channels should have signaling

inserted from TSIG

Transmit Idle Registers (TIR) Function Select. See Section 9 for

timing details.

0 = TIRs define in which channels to insert idle code

1 = TIRs define in which channels to insert data from RSER (i.e., Per-

Channel Loopback function)

27 of 97

DS2152

CCR5: COMMON CONTROL REGISTER 5 (Address = 19 Hex)

(MSB)

(LSB)

TCM0

TJC

LLB

LIAIS

POSITION

CCR5.7

TCM4

TCM3

TCM2

TCM1

SYMBOL

TJC

NAME AND DESCRIPTION

Transmit Japanese CRC6 Enable.

0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)

1 = use Japanese standard JT-G704 CRC6 calculation

LLB

CCR5.6

CCR5.5

Local Loopback.

0 = loopback disabled

1 = loopback enabled

LIAIS

Line Interface AIS Generation Enable. See Figure 1-1 for

details.

0 = allow normal data from TPOSI/TNEGI to be transmitted at

TTIP and TRING

1 = force unframed all 1s to be transmitted at TTIP and TRING

TCM4

CCR5.4

Transmit Channel Monitor Bit 4. MSB of a channel decode

that determines which transmit channel data will appear in the

TDS0M register. See Section 7 for details.

TCM3

TCM2

TCM1

TCM0

CCR5.3

CCR5.2

CCR5.1

CCR5.0

Transmit Channel Monitor Bit 3.

Transmit Channel Monitor Bit 2.

Transmit Channel Monitor Bit 1.

Transmit Channel Monitor Bit 0. LSB of the channel decode.

28 of 97

DS2152

CCR6: COMMON CONTROL REGISTER 6 (Address = 1E Hex)

(MSB)

(LSB)

RCM0

RJC

—

POSITION

CCR6.7

RCM4

RCM3

RCM2

RCM1

SYMBOL

RJC

NAME AND DESCRIPTION

Receive Japanese CRC6 Enable.

0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)

1 = use Japanese standard JT-G704 CRC6 calculation

—

CCR6.6

CCR6.5

CCR6.4

Not Assigned. Should be set to 0 when written.

RCM4

Receive Channel Monitor Bit 4. MSB of a channel decode that

determines which receive channel data will appear in the

RDS0M register. See Section 7 for details.

RCM3

RCM2

RCM1

RCM0

CCR6.3

CCR6.2

CCR6.1

CCR6.0

Receive Channel Monitor Bit 3.

Receive Channel Monitor Bit 2.

Receive Channel Monitor Bit 1.

Receive Channel Monitor Bit 0. LSB of the channel decode.

CCR7: COMMON CONTROL REGISTER 7 (Address = 0A Hex)

(MSB)

(LSB)

LIRST

RLB

—

POSITION

CCR7.7

—

SYMBOL

LIRST

NAME AND DESCRIPTION

Line Interface reset. Setting this bit from a 0 to a 1 will initiate

an internal reset that affects the clock recovery state machine and

jitter attenuator. Normally this bit is only toggled on power-up.

Must be cleared and set again for a subsequent reset.

RLB

—

CCR7.6

Remote Loopback.

0 = loopback disabled

1 = loopback enabled

CCR7.5 to

CCR7.0

Not Assigned. Should be set to 0 when written to.

29 of 97

DS2152

4.5 Power-Up Sequence

On power-up, after the supplies are stable, the DS2152 should be configured for operation by writing to

all the internal registers (this includes setting the Test Registers to 00 hex) since the contents of the

internal registers cannot be predicted on power-up. Finally, after the TSYSCLK and RSYSCLK inputs

are stable, the ESR bit should be toggled from 0 to 1 (this step can be skipped if the elastic stores are

disabled).

4.6 Remote Loopback

When CCR7.6 is set to 1, the DS2152 is forced into Remote Loopback (RLB). In this loopback, data

input via the RPOSI and RNEGI pins is transmitted back to the TPOSO and TNEGO pins. Data continues

to pass through the receive side framer of the DS2152 as it would normally, and the data from the

transmit side formatter is ignored. See Figure 1-1 for more details.

30 of 97

DS2152

5 STATUS AND INFORMATION REGISTERS

There is a set of nine registers that contain information on the current real-time status of the DS2152:

Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers 1 to 3

(RIR1/RIR2/RIR3), and a set of four registers for the on-board HDLC and BOC controller for the FDL.

The specific details on the four registers pertaining to the FDL are covered in Section 12.1, but they

operate the same as the other status registers in the DS2152, described below.

When a particular event has occurred (or is occurring), the appropriate bit in one of these nine registers is

set to 1. All the bits in SR1, SR2, RIR1, RIR2, and RIR3 registers operate in a latched fashion. This

means that if an event or an alarm occurs and a bit is set to 1 in any of the registers, it remains set until the

user reads that bit. The bit is cleared when it is read and it is not set again until the event has occurred

again (or in the case of the RBL, RYEL, LRCL, and RLOS alarms, the bit remains set if the alarm is still

present). The bits in the four FDL status registers that are not latched are listed in Section 12.1.

The user will always precede a read of any of the nine registers with a write. The byte written to the

register will inform the DS2152 which bits the user wishes to read and have cleared. The user will write a

byte to one of these registers, with a 1 in the bit positions he or she wishes to read and a 0 in the bit

positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit location,

the read register will be updated with the latest information. When a 0 is written to a bit position, the read

register will not be updated and the previous value will be held. A write to the status and information

registers will be immediately followed by a read of the same register. The read result should be logically

ANDed with the mask byte that was just written, and this value should be written back into the same

register to ensure that bit does indeed clear. This second write step is necessary because the alarms and

events in the status registers occur asynchronously in respect to their access via the parallel port. This

write-read-write scheme allows an external microcontroller or microprocessor to individually poll certain

bits without disturbing the other bits in the register. This operation is key in controlling the DS2152 with

higher-order software languages.

The SR1, SR2, and FDLS registers have the unique ability to initiate a hardware interrupt via the INT

output pin. Each of the alarms and events in the SR1, SR2, and FDLS can be either masked or unmasked

from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and

FDL Interrupt Mask Register (FIMR) respectively. The FIMR register is covered in Section 12.1.

The interrupts caused by alarms in SR1 (namely RYEL, LRCL, RBL, and RLOS) act differently than the

interrupts caused by events in SR1 and SR2 (namely LUP, LDN, LOTC, RSLIP, RMF, TMF, SEC,

RFDL, TFDL, RMTCH, RAF, and RSC) and FIMR. The alarm caused interrupts will force the INT pin

low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear

criteria in Table 5-2). The INT pin will be allowed to return high (if no other interrupts are present) when

the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present.

The event caused interrupts will force the INT pin low when the event occurs. The INT pin will be

allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the

interrupt to occur.

31 of 97

DS2152

RIR1: RECEIVE INFORMATION REGISTER 1 (Address = 22 Hex)

(MSB)

(LSB)

FBE

COFA

8ZD

16ZD

POSITION

RIR1.7

RESF

RESE

SEFE

B8ZS

SYMBOL

COFA

NAME AND DESCRIPTION

Change of Frame Alignment. Set when the last resync resulted

in a change of frame or multiframe alignment.

8ZD

RIR1.6

RIR1.5

Eight-0 Detect. Set when a string of at least eight consecutive 0s

(regardless of the length of the string) have been received at

RPOSI and RNEGI.

16ZD

16-Zero Detect. Set when a string of at least 16 consecutive 0s

(regardless of the length of the string) have been received at

RPOSI and RNEGI.

RESF

RESE

SEFE

B8ZS

RIR1.4

RIR1.3

RIR1.2

RIR1.1

Receive Elastic Store Full. Set when the receive elastic store

buffer fills and a frame is deleted.

Receive Elastic Store Empty. Set when the receive elastic store

buffer empties and a frame is repeated.

Severely Errored Framing Event. Set when 2 out of 6 framing

bits (Ft or FPS) are received in error.

B8ZS Codeword Detect. Set when a B8ZS codeword is

detected at RPOS and RNEG independent of whether the B8ZS

mode is selected or not via CCR2.6. Useful for automatically

setting the line coding.

FBE

RIR1.0

Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit

is received in error.

32 of 97

DS2152

RIR2: RECEIVE INFORMATION REGISTER 2 (Address = 31 Hex)

(MSB)

(LSB)

TPDV

RLOSC

LRCLC

TESF

TESE

TSLIP

RBLC

RPDV

SYMBOL

RLOSC

POSITION

NAME AND DESCRIPTION

RIR2.7

RIR2.6

RIR2.5

RIR2.4

RIR2.3

RIR2.2

RIR2.1

Receive Loss of Sync Clear. Set when the framer achieves

synchronization; will remain set until read.

LRCLC

TESF

Line Interface Receive Carrier Loss Clear. Set when the

carrier signal is restored; will remain set until read. See Table 5-2.

Transmit Elastic Store Full. Set when the transmit elastic store

buffer fills and a frame is deleted.

TESE

Transmit Elastic Store Empty. Set when the transmit elastic

store buffer empties and a frame is repeated.

TSLIP

RBLC

RPDV

Transmit Elastic Store Slip Occurrence. Set when the transmit

elastic store has either repeated or deleted a frame.

Receive Blue Alarm Clear. Set when the Blue Alarm (AIS) is no

longer detected; will remain set until read. See Table 5-2.

Receive Pulse Density Violation. Set when the receive data

stream does not meet the ANSI T1.403 requirements for pulse

density.

TPDV

RIR2.0

Transmit Pulse Density Violation. Set when the transmit data

stream does not meet the ANSI T1.403 requirements for pulse

density.

33 of 97

DS2152

RIR3: RECEIVE INFORMATION REGISTER 3 (Address = 10 Hex)

(MSB)

(LSB)

RL1

RL0

JALT

POSITION

RIR3.7

LORC

FRCL

—

SYMBOL

RL1

NAME AND DESCRIPTION

Receive Level Bit 1. See Table 5-1.

Receive Level Bit 0. See Table 5-1.

RL0

RIR3.6

JALT

RIR3.5

Jitter Attenuator Limit Trip. Set when the jitter attenuator

FIFO reaches to within 4 bits of its limit; useful for debugging

jitter attenuation operation.

LORC

FRCL

RIR3.4

RIR3.3

Loss of Receive Clock. Set when the RCLKI pin has not

transitioned for at least 2µs (3µs ±1µs).

Framer Receive Carrier Loss. Set when 192 consecutive 0s

have been received at the RPOSI and RNEGI pins; allowed to be

cleared when 14 or more 1s out of 112 possible bit positions are

received.

—

RIR3.2, RIR3.1, Not Assigned. Could be any value when read.

RIR3.0

Table 5-1. Receive T1 Level Indication

TYPICAL LEVEL

RL1

RL0

RECEIVED

(dB)

0

1

0

1

0

1

+2 to -7.5

-7.5 to -15

-15 to -22.5

less than -22.5

34 of 97

DS2152

SR1: STATUS REGISTER 1 (Address = 20 Hex)

(MSB)

(LSB)

RLOS

LUP

LDN

LOTC

POSITION

SR1.7

RSLIP

RBL

RYEL

LRCL

SYMBOL

LUP

NAME AND DESCRIPTION

Loop Up Code Detected. Set when the loop up code as defined

in the RUPCD register is being received. See Section 13 for

details.

LDN

SR1.6

SR1.5

Loop Down Code Detected. Set when the loop down code as

defined in the RDNCD register is being received. See Section 13

for details.

LOTC

Loss of Transmit Clock. Set when the TCLK pin has not

transitioned for one channel time (or 5.2µs). Will force the

RLOS/LOTC pin high if enabled via CCR1.6. Also will force

transmit side formatter to switch to RCLKO if so enabled via

TCR1.7.

RSLIP

RBL

SR1.4

SR1.3

SR1.2

SR1.1

Receive Elastic Store Slip Occurrence. Set when the receive

elastic store has either repeated or deleted a frame.

Receive Blue Alarm. Set when an unframed all 1s code is

received at RPOSI and RNEGI.

RYEL

LRCL

Receive Yellow Alarm. Set when a yellow alarm is received at

RPOSI and RNEGI.

Line Interface Receive Carrier Loss. Set when 192

consecutive 0s have been detected at RTIP and RRING. See

Table 5-2.

RLOS

SR1.0

Receive Loss of Sync. Set when the device is not synchronized

to the receive T1 stream.

35 of 97

DS2152

Table 5-2. Alarm Criteria

ALARM

SET CRITERIA

When over a 3ms window, five or

less 0s are received

CLEAR CRITERIA

Blue Alarm (AIS)

When over a 3ms window, six or

more 0s are received

(See note 1 below)

Yellow Alarm (RAI)

1. D4 bit 2 mode(RCR2.2 = 0)

When bit 2 of 256 consecutive

channels is set to 0 for at least 254 channels is set to 0 for less than 254

occurrences

2. D4 12^thF-bit mode

(RCR2.2=1; this mode is also

referred to as the "Japanese

Yellow Alarm"

When the 12^thframing bit is set to

When the 12^thframing bit is set to 0

1 for two consecutive occurrences for two consecutive occurrences

When 16 consecutive patterns of

00FF appear in the FDL

When 14 or less patterns of 00FF

hex out of 16 possible appear in the

FDL

When 14 or more 1s out of 112

possible bit positions are received

starting with the first one received

3. ESF mode

Red Alarm (LRCL)

When 192 consecutive 0s are

received

(This alarm is also referred to as

Loss Of Signal)

Note 1: The definition of Blue Alarm (or Alarm Indication Signal) is an unframed all 1s signal. Blue alarm detectors should be able to

operate properly in the presence of a 10-3 error rate and they should not falsely trigger on a framed all 1s signal. The blue alarm criteria in

the DS2152 have been set to achieve this performance. It is recommended that the RBL bit be qualified with the RLOS bit.

Note 2: ANSI specifications use a different nomenclature than the DS2152 does; the following terms are equivalent:

RBL = AIS

LRCL = LOS

RLOS = LOF

RYEL = RAI

36 of 97

DS2152

SR2: STATUS REGISTER 2 (Address = 21 Hex)

(MSB)

(LSB)

RSC

RMF

TMF

SEC

POSITION

SR2.7

RFDL

TFDL

RMTCH

RAF

SYMBOL

RMF

NAME AND DESCRIPTION

Receive Multiframe. Set on receive multiframe boundaries.

Transmit Multiframe. Set on transmit multiframe boundaries.

TMF

SR2.6

SEC

SR2.5

1-Second Timer. Set on increments of 1 second based on

RCLK; will be set in increments of 999ms, 999ms, and 1002ms

every 3 seconds.

RFDL

TFDL

RMTCH

RAF

SR2.4

SR2.3

SR2.2

SR2.1

SR2.0

Receive FDL Buffer Full. Set when the receive FDL buffer

(RFDL) fills to capacity (8 bits).

Transmit FDL Buffer Empty. Set when the transmit FDL

buffer (TFDL) empties.

Receive FDL Match Occurrence. Set when the RFDL matches

either RFDLM1 or RFDLM2.

Receive FDL Abort. Set when eight consecutive 1s are received

in the FDL.

RSC

Receive Signaling Change. Set when the DS2152 detects a

change of state in any of the robbed-bit signaling bits.

37 of 97

DS2152

IMR1: INTERRUPT MASK REGISTER 1 (Address = 7F Hex)

(MSB)

(LSB)

RLOS

LUP

LDN

LOTC

POSITION

IMR1.7

SLIP

RBL

RYEL

LRCL

SYMBOL

LUP

NAME AND DESCRIPTION

Loop Up Code Detected.

0 = interrupt masked

1 = interrupt enabled

LDN

LOTC

SLIP

IMR1.6

IMR1.5

IMR1.4

IMR1.3

IMR1.2

IMR1.1

IMR1.0

Loop Down Code Detected.

0 = interrupt masked

1 = interrupt enabled

Loss of Transmit Clock.

0 = interrupt masked

1 = interrupt enabled

Elastic Store Slip Occurrence.

0 = interrupt masked

1 = interrupt enabled

RBL

Receive Blue Alarm.

0 = interrupt masked

1 = interrupt enabled

RYEL

LRCL

RLOS

Receive Yellow Alarm.

0 = interrupt masked

1 = interrupt enabled

Line Interface Receive Carrier Loss.

0 = interrupt masked

1 = interrupt enabled

Receive Loss of Sync.

0 = interrupt masked

1 = interrupt enabled

38 of 97

DS2152

IMR2: INTERRUPT MASK REGISTER 2 (Address = 6F Hex)

(MSB)

(LSB)

RSC

RMF

TMF

SEC

POSITION

IMR2.7

RFDL

TFDL

RMTCH

RAF

SYMBOL

RMF

NAME AND DESCRIPTION

Receive Multiframe.

0 = interrupt masked

1 = interrupt enabled

TMF

SEC

IMR2.6

IMR2.5

IMR2.4

IMR2.3

IMR2.2

IMR2.1

IMR2.0

Transmit Multiframe.

0 = interrupt masked

1 = interrupt enabled

1-Second Timer.

0 = interrupt masked

1 = interrupt enabled

RFDL

TFDL

RMTCH

RAF

Receive FDL Buffer Full.

0 = interrupt masked

1 = interrupt enabled

Transmit FDL Buffer Empty.

0 = interrupt masked

1 = interrupt enabled

Receive FDL Match Occurrence.

0 = interrupt masked

1 = interrupt enabled

Receive FDL Abort.

0 = interrupt masked

1 = interrupt enabled

RSC

Receive Signaling Change.

0 = interrupt masked

1 = interrupt enabled

39 of 97

DS2152

6 ERROR COUNT REGISTERS

There are a set of three counters in the DS2152 that record bipolar violations, excessive 0s, errors in the

CRC6 codewords, framing bit errors, and number of multiframes that the device is out of receive

synchronization. Each of these three counters is automatically updated on either 1-second boundaries

(CCR3.2 = 0) or every 42ms (CCR3.2 = 1) as determined by the timer in Status Register 2 (SR2.5).

Hence, these registers contain performance data from either the previous second or the previous 42ms.

The user can use the interrupt from the 1-second timer to determine when to read these registers. The user

has a full second (or 42ms) to read the counters before the data is lost. All three counters will saturate at

their respective maximum counts and they will not rollover (note: only the Line Code Violation Count

Register has the potential to overflow but the bit error would have to exceed 10^-2before this would

occur).

6.1 Line Code Violation Count Register (LCVCR)

Line Code Violation Count Register 1 High (LCVCR1) is the most significant word and LCVCR2 is the

least significant word of a 16-bit counter that records code violations (CVs). CVs are defined as Bipolar

Violations (BPVs) or excessive 0s. See Table 6-1 for details of exactly what the LCVCRs count. If the

B8ZS mode is set for the receive side via CCR2.2, then B8ZS codewords are not counted. This counter is

always enabled; it is not disabled during receive loss of synchronization (RLOS = 1) conditions.

LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address = 23 Hex)

LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address = 24 Hex)

(MSB)

LCV15

LCV7

(LSB)

LCV8

LCV0

LCV14

LCV6

LCV13 LCV12 LCV11

LCV10

LCV2

LCV9

LCV1

LCVCR1

LCVCR2

LCV5

LCV4

LCV3

SYMBOL

POSITION

LCVCR1.7

LCVCR2.0

NAME AND DESCRIPTION

LCV15

LCV0

MSB of the 16-bit code violation count.

LSB of the 16-bit code violation count.

Table 6-1. Line Code Violation Counting Arrangements

COUNT

B8ZS

ENABLED?

(CCR2.2)

No

WHAT IS COUNTED IN THE

LCVCRs

EXCESSIVE 0S?

(RCR1.7)

No

BPVs

Yes

No

BPVs + 16 consecutive 0s

No

Yes

BPVs (B8ZS codewords not counted)

BPVs + 8 consecutive 0s

Yes

40 of 97

DS2152

6.2 Path Code Violation Count Register (PCVCR)

When the receive side of the DS2152 is set to operate in the ESF framing mode (CCR2.3 = 1), PCVCR

will automatically be set as a 12-bit counter that will record errors in the CRC6 codewords. When set to

operate in the D4 framing mode (CCR2.3 = 0), PCVCR will automatically count errors in the Ft framing

bit position. Via the RCR2.1 bit, the DS2152 can be programmed to also report errors in the Fs framing

bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1) conditions.

See Table 6-2 for a detailed description of exactly what errors the PCVCR counts.

PCVCR1: PATH VIOLATION COUNT REGISTER 1 (Address = 25 Hex)

PCVCR2: PATH VIOLATION COUNT REGISTER 2 (Address = 26 Hex)

(MSB)

(LSB)

CRC/FB11

CRC/FB10

(Note 1)

CRC/FB9 CRC/FB8

PCVCR1

PCVCR2

CRC/FB7 CRC/FB6 CRC/FB5 CRC/FB4 CRC/FB3 CRC/FB2 CRC/FB1 CRC/FB0

SYMBOL

CRC/FB11

CRC/FB0

POSITION NAME AND DESCRIPTION

PCVCR1.3 MSB of the 12-Bit CRC6 Error or Frame Bit Error Count (Note 2)

PCVCR2.0 LSB of the 12-Bit CRC6 Error or Frame Bit Error Count (Note 2)

Note 1: The upper nibble of the counter at address 25 is used by the Multiframes Out of Sync Count Register.

Note 2: PCVCR counts either errors in CRC codewords (in the ESF framing mode; CCR2.3 = 1) or errors in the framing bit position (in the

D4 framing mode; CCR2.3 = 0).

Table 6-2. Path Code Violation Counting Arrangements

FRAMING MODE COUNT Fs ERRORS?

WHAT IS COUNTED IN THE

(CCR2.3)

D4

(RCR2.1)

No

PCVCRs

Errors in the Ft pattern

Errors in both the Ft and Fs patterns

Errors in the CRC6 codewords

D4

Yes

Don’t Care

ESF

6.3 Multiframes Out of Sync Count Register (MOSCR)

Normally, the MOSCR is used to count the number of multiframes that the receive synchronizer is out of

sync (RCR2.0 = 1). This number is useful in ESF applications needing to measure the parameters Loss Of

Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the

MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS = 1)

conditions. The MOSCR has alternate operating mode whereby it will count either errors in the Ft

framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the

MOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOS = 1)

conditions. See Table 6-3 for a detailed description of what the MOSCR is capable of counting.

41 of 97

DS2152

MOSCR1: MULTIFRAMES OUT OF SYNC COUNT REGISTER 1

(Address = 25 Hex)

MOSCR2: MULTIFRAMES OUT OF SYNC COUNT REGISTER 2

(Address = 27 Hex)

(MSB)

(LSB)

MOS/FB MOS/FB MOS/FB MOS/FB (Note 1) (Note 1) (Note 1) (Note 1) MOSCR

11

10

9

8

1

MOS/FB MOS/FB MOS/FB MOS/FB MOS/FB MOS/FB MOS/F MOS/FB MOSCR

7

6

5

4

3

2

B1

0

2

SYMBOL

POSITION NAME AND DESCRIPTION

MOS/FB11 MOSCR1.7 MSB of the 12-Bit Multiframes Out of Sync or F-Bit Error Count

(Note 2)

MOS/FB0

MOSCR2.0 LSB of the 12-Bit Multiframes Out of Sync or F-Bit Error Count

(Note 2)

Note 1: The lower nibble of the counter at address 25 is used by the Path Code Violation Count Register.

Note 2: MOSCR counts either errors in framing bit position (RCR2.0 = 0) or the number of multiframes out of sync (RCR2.0 = 1).

Table 6-3. Multiframes Out of Sync Counting Arrangements

FRAMING MODE

COUNT MOS OR F-BIT

WHAT IS COUNTED IN THE

(CCR2.3)

D4

ERRORS (RCR2.0)

MOSCRs

MOS

F-Bit

MOS

F-Bit

Number of multiframes out of sync

Errors in the Ft pattern

Number of multiframes out of sync

Errors in the FPS pattern

D4

ESF

42 of 97

DS2152

7 DS0 MONITORING FUNCTION

The DS2152 can monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the

receive direction at the same time. In the transmit direction, the user determines which channel is to be

monitored by properly setting the TCM0 to TCM4 bits in the CCR5 register. In the receive direction, the

RCM0 to RCM4 bits in the CCR6 register need to be properly set. The DS0 channel pointed to by the

TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel

pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register.

The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the

appropriate T1 channel. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in

the receive direction needed to be monitored, then the following values would be programmed into CCR5

and CCR6:

TCM4 = 0

TCM3 = 0

TCM2 = 1

TCM1 = 0

TCM0 = 1

RCM4 = 0

RCM3 = 1

RCM2 = 1

RCM1 = 1

RCM0 = 0

43 of 97

DS2152

CCR5: COMMON CONTROL REGISTER 5 (Address = 19 Hex)

(Repeated here from Section 4 for convenience.)

(MSB)

(LSB)

TCM0

TJC

SYMBOL

TJC

LLB

LIAIS

TCM4

TCM3

TCM2

TCM1

POSITION NAME AND DESCRIPTION

CCR5.7

CCR5.6

CCR5.5

CCR5.4

Transmit Japanese CRC Enable. See Section 4 for details.

Local Loopback. See Section 4 for details.

LLB

LIAIS

TCM4

Line Interface AIS Generation Enable. See Section 4 for details.

Transmit Channel Monitor Bit 4. MSB of a channel decode that

determines which transmit DS0 channel data will appear in the TDS0M

register.

TCM3

TCM2

TCM1

TCM0

CCR5.3

CCR5.2

CCR5.1

CCR5.0

Transmit Channel Monitor Bit 3.

Transmit Channel Monitor Bit 2.

Transmit Channel Monitor Bit 1.

Transmit Channel Monitor Bit 0. LSB of the channel decode that

determines which transmit DS0 channel data will appear in the TDS0M

register.

44 of 97

DS2152

TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address = 1A Hex)

(MSB)

(LSB)

B8

B1

B2

B3

B4

B5

B6

B7

SYMBOL

POSITION

NAME AND DESCRIPTION

B1

TDS0M.7

Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first

bit to be transmitted).

B2

B3

B4

B5

B6

B7

B8

TDS0M.6

TDS0M.5

TDS0M.4

TDS0M.3

TDS0M.2

TDS0M.1

TDS0M.0

Transmit DS0 Channel Bit 2.

Transmit DS0 Channel Bit 3.

Transmit DS0 Channel Bit 4.

Transmit DS0 Channel Bit 5.

Transmit DS0 Channel Bit 6.

Transmit DS0 Channel Bit 7.

Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit

to be transmitted).

CCR6: COMMON CONTROL REGISTER 6 (Address = 1E Hex)

(Repeated here from Section 4 for convenience.)

(MSB)

(LSB)

RJC

—

POSITION

CCR6.7

RCM4

RCM3

RCM2

RCM1

RCM0

SYMBOL

RJC

NAME AND DESCRIPTION

Receive Japanese CRC Enable. See Section 4 for details.

Not Assigned. Should be set to 0 when written.

—

CCR6.6,

CCR6.5

CCR6.4

RCM4

Receive Channel Monitor Bit 4. MSB of a channel decode that

determines which receive DS0 channel data will appear in the

RDS0M register.

RCM3

RCM2

RCM1

RCM0

CCR6.3

CCR6.2

CCR6.1

CCR6.0

Receive Channel Monitor Bit 3.

Receive Channel Monitor Bit 2.

Receive Channel Monitor Bit 1.

Receive Channel Monitor Bit 0. LSB of the channel decode

that determines which receive DS0 channel data will appear in

the RDS0M register.

45 of 97

DS2152

RDS0M: RECEIVE DS0 MONITOR REGISTER (Address = 1F Hex)

(MSB)

(LSB)

B8

B1

B2

B3

POSITION

RDS0M.7

B4

B5

B6

B7

SYMBOL

B1

NAME AND DESCRIPTION

Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit

to be received).

B2

B3

B4

B5

B6

B7

B8

RDS0M.6

RDS0M.5

RDS0M.4

RDS0M.3

RDS0M.2

RDS0M.1

RDS0M.0

Receive DS0 Channel Bit 2.

Receive DS0 Channel Bit 3.

Receive DS0 Channel Bit 4.

Receive DS0 Channel Bit 5.

Receive DS0 Channel Bit 6.

Receive DS0 Channel Bit 7.

Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit to

be received).

46 of 97

DS2152

8 SIGNALING OPERATION

The DS2152 contains provisions for both processor based (i.e., software based) signaling bit access and

for hardware-based access. Both the processor-based access and the hardware-based access can be used

simultaneously if necessary. The processor based signaling is covered in Section 8.1 and the hardware

based signaling is covered in Section 8.2.

8.1 Processor-Based Signaling

The robbed-bit signaling bits embedded in the T1 stream can be extracted from the receive stream and

inserted into the transmit stream by the DS2152. There is a set of 12 registers for the receive side (RS1 to

RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below.

The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to 0,

then the robbed signaling bits will appear at the RSER pin in their proper position as they are received. If

CCR1.5 is set to 1, the robbed-signaling bit positions are forced to 1 at RSER. If hardware-based

signaling is being used, then CCR1.5 must be set to 0.

RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address = 60 to 6B Hex)

(MSB)

A(8)

(LSB)

A(1)

A(7)

A(15)

A(23)

B(7)

A(6)

A(14)

A(22)

B(6)

A(5)

A(13)

A(21)

B(5)

A(4)

A(12)

A(20)

B(4)

A(3)

A(11)

A(19)

B(3)

A(2)

A(10)

A(18)

B(2)

RS1 (60)

RS2 (61)

RS3 (62)

RS4 (63)

RS5 (64)

RS6 (65)

RS7 (66)

RS8 (67)

A(16)

A(24)

B(8)

A(9)

A(17)

B(1)

B(16)

B(24)

A/C(8)

B(15)

B(23)

A/C(7)

B(14)

B(22)

A/C(6)

B(13)

B(21)

A/C(5)

B(12)

B(20)

A/C(4)

B(11)

B(19)

A/C(3)

B(10)

B(18)

A/C(2)

B(9)

B(17)

A/C(1)

A/C(16) A/C(15) A/C(14) A/C(13) A/C(12) A/C(11) A/C(10) A/C(9)

A/C(24) A/C(23) A/C(22) A/C(21) A/C(20) A/C(19) A/C(18) A/C(17) RS9 (68)

B/D(8)

B/D(7)

B/D(6)

B/D(5)

B/D(4)

B/D(3)

B/D(2)

B/D(1) RS10 (69)

B/D(16) B/D(15) B/D(14) B/D(13) B/D(12) B/D(11) B/D(10) B/D(9) RS11 (6A)

B/D(24) B/D(23) B/D(22) B/D(21) B/D(20) B/D(19) B/D(18) B/D(17) RS12 (6B)

SYMBOL

D(24)

POSITION NAME AND DESCRIPTION

RS12.7

RS1.0

Signaling Bit D in Channel 24

Signaling Bit A in Channel 1

A(1)

Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed-bit signaling from eight

DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A–D). In the

D4 framing mode, there are only two signaling bits per channel (A and B). In the D4 framing mode, the

DS2152 replaces the C and D signaling bit positions with the A and B signaling bits from the previous

multiframe. Hence, whether the DS2152 is operated in either framing mode, the user needs only to

retrieve the signaling bits every 3ms. The bits in the Receive Signaling Registers are updated on

multiframe boundaries so the user can use the Receive Multiframe Interrupt in the Receive Status

Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers are

frozen and not updated during a loss of sync condition (SR1.0 = 1). They will contain the most recent

signaling information before the “OOF” occurred. The signaling data reported in RS1 to RS12 is also

available at the RSIG and RSER pins.

47 of 97

DS2152

A change in the signaling bits from one multiframe to the next will cause the RSC status bit (SR2.0) to be

set. The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the

IMR2.0 bit. Once a signaling change has been detected, the user has at least 2.75ms to read the data out of

the RS1 to RS12 registers before the data will be lost.

TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address = 70 to 7B Hex)

(MSB)

A(8)

(LSB)

A(1)

A(7)

A(15)

A(23)

B(7)

A(6)

A(14)

A(22)

B(6)

A(5)

A(13)

A(21)

B(5)

A(4)

A(12)

A(20)

B(4)

A(3)

A(11)

A(19)

B(3)

A(2)

A(10)

A(18)

B(2)

TS1 (70)

TS2 (71)

TS3 (72)

TS4 (73)

TS5 (74)

TS6 (75)

TS7 (76)

TS8 (77)

A(16)

A(24)

B(8)

A(9)

A(17)

B(1)

B(16)

B(24)

A/C(8)

B(15)

B(23)

A/C(7)

B(14)

B(22)

A/C(6)

B(13)

B(21)

A/C(5)

B(12)

B(20)

A/C(4)

B(11)

B(19)

A/C(3)

B(10)

B(18)

A/C(2)

B(9)

B(17)

A/C(1)

A/C(16) A/C(15) A/C(14) A/C(13) A/C(12) A/C(11) A/C(10) A/C(9)

A/C(24) A/C(23) A/C(22) A/C(21) A/C(20) A/C(19) A/C(18) A/C(17) TS9 (78)

B/D(8)

B/D(7)

B/D(6)

B/D(5)

B/D(4)

B/D(3)

B/D(2)

B/D(1) TS10 (79)

B/D(16) B/D(15) B/D(14) B/D(13) B/D(12) B/D(11) B/D(10) B/D(9) TS11 (7A)

B/D(24) B/D(23) B/D(22) B/D(21) B/D(20) B/D(19) B/D(18) B/D(17) TS12 (7B)

SYMBOL

D(24)

POSITION NAME AND DESCRIPTION

TS12.7

TS1.0

Signaling Bit A in Channel 24

Signaling Bit D in Channel 1

A(1)

Each Transmit Signaling Register (TS1 to TS12) contains the robbed-bit signaling for eight DS0 channels

that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF framing mode,

there can be up to four signaling bits per channel (A–D). On multiframe boundaries, the DS2152 will load

the values present in the Transmit Signaling Register into an outgoing signaling shift register that is

internal to the device. The user can utilize the Transmit Multiframe Interrupt in Status Register 2 (SR2.6)

to know when to update the signaling bits. In the ESF framing mode, the interrupt will come every 3 ms

and the user has a full 3ms to update the TSRs. In the D4 framing mode, there are only 2 signaling bits

per channel (A and B). However, in the D4 framing mode the DS2152 uses the C and D bit positions as

the A and B bit positions for the next multiframe. The DS2152 loads the values in the TSRs into the

outgoing shift register every other D4 multiframe.

48 of 97

DS2152

8.2 Hardware-Based Signaling

8.2.1 Receive Side

In the receive side of the hardware based signaling, there are two operating modes for the signaling

buffer: signaling extraction and signaling reinsertion. Signaling extraction involves pulling the signaling

bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in

a serial PCM fashion on a channel-by-channel basis at the RSIG output. This mode is always enabled. In

this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then

the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF framing mode, the

ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated

once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are

output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as

bits 7 and 8, respectively, in each channel. The RSIG data is updated once a multiframe (1.5ms) unless a

freeze is in effect. See the timing diagrams in Section 16 for some examples.

The other hardware-based signaling operating mode called signaling reinsertion can be invoked by setting

the RSRE control bit high (CCR4.7 = 1). In this mode, the user will provide a multiframe sync at the

RSYNC pin and the signaling data will be re-aligned at the RSER output according to this applied

multiframe boundary. In this mode, the elastic store must be enabled however the backplane clock can be

either 1.544MHz or 2.048MHz.

If the signaling reinsertion mode is enabled, the user can control which channels have signaling

reinsertion performed on a channel-by-channel basis by setting the RPCSI control bit high (CCR4.6) and

then programming the RCHBLK output pin to go high in the channels in which the signaling reinsertion

should not occur. If the RPCSI bit is set low, then signaling reinsertion will occur in all channels when

the signaling reinsertion mode is enabled (RSRE = 1). How to control the operation of the RCHBLK

output pin is covered in Section 10. In signaling reinsertion mode, the user has the option to replace all of

the extracted robbed-bit signaling bit positions with 1s. This option is enabled via the RFSA1 control bit

(CCR4.5) and it can be invoked on a per-channel basis by setting the RPCSI control bit (CCR4.6) high

and then programming RCHBLK appropriately just like the per-channel signaling reinsertion operates.

The signaling data in the four-multiframe buffer will be frozen in a known good state upon either a loss of

synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore

TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit

(CCR4.4) should be set high. The user can force a freeze by setting the RFF control bit (CCR4.3) high.

The RSIGF output pin provides a hardware indication that a freeze is in effect. The four-multiframe

buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER

pin if RSRE = 1). When freezing is enabled (RFE = 1), the signaling data will be held in the last known

good state until the corrupting error condition subsides. When the error condition subsides, the signaling

data will be held in the old state for at least an additional 9ms (or 4.5ms in D4 framing mode) before

being allowed to be updated with new signaling data.

8.2.2 Transmit Side

Via the THSE control bit (CCR4.2), the DS2152 can be set up to take the signaling data presented at the

TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The

user can control which channels are to have signaling data from the TSIG pin inserted into them on a

channel-by-channel basis by setting the TPCSI control bit (CCR4.1) high. When TPCSI is enabled,

channels in which the TCHBLK output has been programmed to be set high in, will not have signaling

data from the TSIG pin inserted into them. The hardware signaling insertion capabilities of the DS2152

are available whether the transmit side elastic store is enabled or disabled. If the elastic store is enabled,

the backplane clock (TSYSCLK) can be either 1.544 MHz or 2.048 MHz.

49 of 97

DS2152

9 PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK

The DS2152 can replace data on a channel-by-channel basis in both the transmit and receive directions.

The transmit direction is from the backplane to the T1 line and is covered in Section 9.1. The receive

direction is from the T1 line to the backplane and is covered in Section 9.2.

9.1 Transmit Side Code Generation

In the transmit direction there are two methods by which channel data from the backplane can be

overwritten with data generated by the DS2152. The first method, which is covered in Section 9.1.1, was

a feature contained in the original DS2151 while the second method, which is covered in Section 9.1.2, is

a new feature of the DS2152.

9.1.1 Simple Idle Code Insertion and Per-Channel Loopback

The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which of the 24 T1

channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).

This method allows the same 8-bit code to be placed into any of the 24 T1 channels. If this method is

used, then the CCR4.0 control bit must be set to 0.

Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in

the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code

contained in the Transmit Idle Definition Register (TIDR). Robbed-bit signaling and Bit 7 stuffing will

occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit

Transparency Registers.

The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per-Channel

Loop-Back (PCLB). If the TIRFS control bit (CCR4.0) is set to 1, then the TIRs will determine which

channels (if any) from the backplane should be replaced with the data from the receive side or, in other

words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must

be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to

TSYNC.

TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address = 3C to 3E Hex)

(Also used for Per-Channel Loopback.)

(MSB)

CH8

(LSB)

CH1

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

TIR1 (3C)

TIR2 (3D)

TIR3 (3E)

CH16

CH24

CH9

CH17

SYMBOL

POSITION NAME AND DESCRIPTION

CH24

TIR3.7

Transmit Idle Registers.

0 = do not insert the Idle Code in the TIDR into this channel

CH1

TIR1.0

1 = insert the Idle Code in the TIDR into this channel

Note: If CCR4.0 = 1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies that channel data is to be

sourced from the output of the receive side framer (i.e., Per-Channel Loopback; see Figure 1-1).

50 of 97

DS2152

TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 3F Hex)

(MSB)

(LSB)

TIDR0

TIDR7

TIDR6

TIDR5

TIDR4

TIDR3

TIDR2

TIDR1

SYMBOL POSITION NAME AND DESCRIPTION

TIDR7

TIDR0

TIDR.7

TIDR.0

MSB of the Idle Code (this bit is transmitted first).

LSB of the Idle Code (this bit is transmitted last).

9.1.2 Per-Channel Code Insertion

The second method involves using the Transmit Channel Control Registers (TCC1/2/3) to determine

which of the 24 T1 channels should be overwritten with the code placed in the Transmit Channel

Registers (TC1 to TC24). This method is more flexible than the first in that it allows a different 8-bit code

to be placed into each of the 24 T1 channels.

TC1 TO TC24: TRANSMIT CHANNEL REGISTERS

(Address = 40 to 4F and 50 to 57 Hex)

(For brevity, only channel 1 is shown; see Table 2-1 for other register address.)

(MSB)

(LSB)

C7

C6

C5

C4

C3

C2

C1

C0

TC1 (50)

SYMBOL POSITION NAME AND DESCRIPTION

C7

TC1.7

MSB of the Code (this bit is transmitted first).

C0

TC1.0

LSB of the Code (this bit is transmitted last).

TCC1/TCC2/TCC3: TRANSMIT CHANNEL CONTROL REGISTER

(Address = 16 to 18 Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

CH1

CH9

TCC1 (16)

TCC2 (17)

TCC3 (18)

CH17

SYMBOL POSITION NAME AND DESCRIPTION

CH24

TCC3.7

Transmit Channel 24 Code Insertion Control Bit

0 = do not insert data from the TC1 register into the transmit data

stream

1 = insert data from the TC1 register into the transmit data stream

CH1

TCC1.0

Transmit Channel 1 Code Insertion Control Bit

0 = do not insert data from the TC32 register into the transmit data

stream

1 = insert data from the TC32 register into the transmit data stream

51 of 97

DS2152

9.2 Receive Side Code Generation

In the receive direction there are also two methods by which channel data to the backplane can be

overwritten with data generated by the DS2152. The first method, which is covered in Section 9.2.1, was

a feature contained in the original DS2151, while the second method, which is covered in Section 9.2.2, is

a new feature of the DS2152.

9.2.1 Simple Code Insertion

The first method on the receive side involves using the Receive Mark Registers (RMR1/2/3) to determine

which of the 24 T1 channels should be overwritten with either a 7Fh idle code or with a digital milliwatt

pattern. The RCR2.7 bit will determine which code is used. The digital milliwatt code is an 8-byte

repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the RMRs

represents a particular channel. If a bit is set to a 1, then the receive data in that channel will be replaced

with one of the two codes. If a bit is set to 0, no replacement occurs.

RMR1/RMR2/RMR3: RECEIVE MARK REGISTERS (Address = 2D to 2F Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH1

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

RMR1(2D)

RMR2(2E)

RMR3(2F)

CH9

CH17

SYMBOL

POSITION NAME AND DESCRIPTION

CH24

RMR3.7

Receive MARK Registers.

0 = do not affect the receive data associated with this channel

CH1

RMR1.0

1 = replace the receive data associated with this channel with

either the idle code or the digital milliwatt code (depends on the

RCR2.7 bit)

9.2.2 Per-Channel Code Insertion

The second method involves using the Receive Channel Control Registers (RCC1/2/3) to determine

which of the 24 T1 channels off the T1 line and going to the backplane should be overwritten with the

code placed in the Receive Channel Registers (RC1 to RC24). This method is more flexible than the first

in that it allows a different 8-bit code to be placed into each of the 24 T1 channels.

RC1 TO RC24: RECEIVE CHANNEL REGISTERS

(Address = 58 to 5F and 80 to 8F Hex)

(For brevity, only channel 1 is shown; see Table 2-1 for other register address.)

(MSB)

(LSB)

C7

C6

C5

C4

C3

C2

C1

C0

RC1 (58)

SYMBOL

POSITION NAME AND DESCRIPTION

C7

RC1.7

RC1.0

MSB of the Code (this bit is sent first to the backplane)

LSB of the Code (this bit is sent last to the backplane)

C0

52 of 97

DS2152

RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER

(Address = 1B to 1D Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

CH1

CH9

RCC1 (1B)

RCC2 (1C)

RCC3 (1D)

CH17

SYMBOL

POSITION NAME AND DESCRIPTION

CH24

RCC3.7

Receive Channel 24 Code Insertion Control Bit

0 = do not insert data from the RC24 register into the receive

data stream

1 = insert data from the RC24 register into the receive data

stream

CH1

RCC1.0

Receive Channel 1 Code Insertion Control Bit

0 = do not insert data from the RC1 register into the receive data

stream

1 = insert data from the RC1 register into the receive data stream

53 of 97

DS2152

10 CLOCK BLOCKING REGISTERS

The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking

Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins, respectively. The

RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low during

individual channels. These outputs can be used to block clocks to a USART or LAPD controller in

Fractional T1 or ISDN-PRI applications. When the appropriate bits are set to 1, the RCHBLK and

TCHCLK pins will be held high during the entire corresponding channel time. See the timing diagrams in

Section 16 for an example.

RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS

(Address = 6C to 6E Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH1

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

RCBR1 (6C)

RCBR2 (6D)

RCBR3 (6E)

CH9

CH17

SYMBOL

POSITION NAME AND DESCRIPTION

CH24

RCBR3.7

RCBR1.0

Receive Channel Blocking Registers.

0 = force the RCHBLK pin to remain low during this channel

time

CH1

1 = force the RCHBLK pin high during this channel time

TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS

(Address = 32 to 34 Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

CH1

TCBR1 (32)

TCBR1 (33)

TCBR1 (34)

CH9

CH17

SYMBOL

POSITION NAME AND DESCRIPTION

CH24

TCBR3.7

Transmit Channel Blocking Registers.

0 = force the TCHBLK pin to remain low during this channel

time

CH1

TCBR1.0

1 = force the TCHBLK pin high during this channel time

54 of 97

DS2152

11 ELASTIC STORES OPERATION

The DS2152 contains dual two-frame (386 bits) elastic stores: one for the receive direction and one for

the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert

the T1 data stream to 2.048Mbps (or a multiple of 2.048Mbps), which is the E1 rate. Secondly, they can

be used to absorb the differences in frequency and phase between the T1 data stream and an

asynchronous (i.e., not frequency locked) backplane clock (which can be 1.544MHz or 2.048MHz). The

backplane clock can burst at rates up to 8.192MHz. Both elastic stores contain fully controlled slip

capability, which is necessary for this second purpose. The receive side elastic store can be enabled via

CCR1.2 and the transmit side elastic store is enabled via CCR1.7. The elastic stores can be forced to a

known depth via the Elastic Store Reset bit (CCR3.6). Toggling the CCR3.6 bit forces the read and write

pointers into opposite frames. Both elastic stores within the DS2152 are fully independent and no

restrictions apply to the sourcing of the various clocks that are applied to them. The transmit side elastic

store can be enabled whether the receive elastic store is enabled or disabled and vice versa. Also, each

elastic store can interface to either a 1.544MHz or 2.048MHz backplane without regard to the backplane

rate the other elastic store is interfacing.

11.1Receive Side

If the receive side elastic store is enabled (CCR1.2 = 1), then the user must provide either a 1.544MHz

(CCR1.3 = 0) or 2.048MHz (CCR1.3 = 1) clock at the RSYSCLK pin. The user has the option of either

providing a frame/multiframe sync at the RSYNC pin (RCR2.3 = 1) or having the RSYNC pin provide a

pulse on frame boundaries (RCR2.3 = 0). If the user wishes to obtain pulses at the frame boundary, then

RCR2.4 must be set to 0; if the user wishes to have pulses occur at the multiframe boundary, then

RCR2.4 must be set to 1. The DS2152 always indicates frame boundaries via the RFSYNC output

whether the elastic store is enabled or not. If the elastic store is enabled, then multiframe boundaries will

be indicated via the RMSYNC output. If the user selects to apply a 2.048MHz clock to the RSYSCLK

pin, then the data output at RSER will be forced to all 1s every fourth channel and the F-bit will be placed

in the MSB bit position of channel 1. Hence, channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8,

12, 16, 20, 24, and 28) are forced to 1. Also, in 2.048MHz applications, the RCHBLK output is forced

high during the same channels as the RSER pin. See Section 16 for more details. This is useful in T1 to

CEPT (E1) conversion applications. If the 386-bit elastic buffer either fills or empties, a controlled slip

occurs. If the buffer empties, a full frame of data (193 bits) is repeated at RSER, and the SR1.4 and

RIR1.3 bits are set to 1, except the MSB of channel 1. See Figure 16-5. If the buffer fills, a full frame of

data is deleted, and the SR1.4 and RIR1.4 bits are set to 1.

11.2Transmit Side

The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic

store is enabled via CCR1.7. A 1.544MHz (CCR1.4 = 0) or 2.048MHz (CCR1.4 = 1) clock can be

applied to the TSYSCLK input. If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then

the data input at TSER will be ignored every fourth channel. Hence, channels 1, 5, 9, 13, 17, 21, 25, and

29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are ignored. The F-bit may be sampled at the MSB of

channel 1. See Figure 16-10. The user must supply an 8kHz frame sync pulse to the TSSYNC input.

Also, in 2.048MHz applications the TCHBLK output is forced high during the channels ignored by the

DS2152. See Section 16 for more details. Controlled slips in the transmit elastic store are reported in the

RIR2.3 bit, and the direction of the slip is reported in the RIR2.5 and RIR2.4 bits.

55 of 97

DS2152

11.3 Minimum Delay Synchronous RSYSCLK/TSYSCLK Mode

In applications where the DS2152 is connected to backplanes that are frequency-locked to the recovered

T1 clock (i.e., the RCLK output), the full two-frame depth of the on-board elastic stores is really not

needed. In fact, in some delay-sensitive applications the normal two-frame depth may be excessive. If the

CCR3.7 bit is set to 1, then the receive elastic store (and also the transmit elastic store if it is enabled) will

be forced to a maximum depth of 32 bits instead of the normal 386 bits. In this mode, RSYSCLK and

TSYSCLK must be tied together and they must be frequency-locked to RCLK. All the slip contention

logic in the DS2152 is disabled (since slips cannot occur). Also, since the buffer depth is no longer two

frames deep, the DS2152 must be set up to source a frame pulse at the RSYNC pin and this output must

be tied to the TSSYNC input. On power-up after the RSYSCLK and TSYSCLK signals have locked to

the RCLK signal, the elastic store reset bit (CCR3.6) should be toggled from 0 to 1 to ensure proper

operation.

56 of 97

DS2152

12 FDL/FS EXTRACTION AND INSERTION

The DS2152 can extract/insert data from/into the Facility Data Link (FDL) in the ESF framing mode and

from/into Fs-bit position in the D4 framing mode. Because SLC-96 uses the Fs-bit position, this

capability can also be used in SLC-96 applications. The DS2152 contains a complete HDLC and BOC

controller for the FDL. See Section 12.1 for this operation. To allow for backward compatibility between

the DS2152 and earlier devices, the DS2152 maintains some legacy functionality for the FDL (see

Section 12.2). Section 12.3 covers D4 and SLC-96 operation. Contact the factory for a copy of C

language source code for implementing the FDL on the DS2152.

12.1 HDLC and BOC Controller for the FDL

The DS2152 contains a complete HDLC controller with 16-byte buffers in both the transmit and receive

directions as well as separate dedicated hardware for Bit Oriented Codes (BOC). The HDLC controller

performs all the necessary overhead for generating and receiving Performance Report Messages (PRM)

as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller

automatically generates and detects flags, generates and checks the CRC check sum, generates and

detects abort sequences, stuffs and destuffs 0s (for transparency), and byte-aligns to the FDL data stream.

The 16-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or

transmitted without host intervention. The BOC controller will automatically detect incoming BOC

sequences and alert the host. When the BOC ceases, the DS2152 will also alert the host. The user can set

the device up to send any of the possible 6-bit BOC codes.

There are nine registers that the host will use to operate and control the operation of the HDLC and BOC

controllers. A brief description of the registers is shown in Table 12-1.

Table 12-1. HDLC/BOC Controller Register List

NAME

FUNCTION

FDL Control Register (FDLC)

FDL Status Register (FDLS)

General control over the HDLC and BOC controllers key

status information for both transmit and receive directions

FDL Interrupt Mask Register (FIMR) allows/stops status bits to/from causing an interrupt.

Receive PRM Register (RPRM)

Receive BOC Register (RBOC)

Receive FDL FIFO Register (RFFR)

Transmit PRM Register (TPRM)

Transmit BOC Register (TBOC)

Status information on receive HDLC controller status

information on receive BOC controller access to 16-byte

HDLC FIFO in receive direction.

Status information on transmit HDLC controller

enables/disables transmission of BOC codes access to 16-byte

Transmit FDL FIFO Register (TFFR) HDLC FIFO in transmit direction.

12.1.1 Status Register for the FDL

Four of the HDLC/BOC controller registers (FDLS, RPRM, RBOC, and TPRM) provide status

information. When a particular event has occurred (or is occurring), the appropriate bit in one of these

four registers will be set to a 1. Some of the bits in these four FDL status registers are latched and some

are real-time bits that are not latched. Section 12 contains register descriptions that list which bits are

latched and which are not. With the latched bits, when an event occurs and a bit is set to a 1, it will

remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again

until the event has occurred again. The real-time bits report the current instantaneous conditions that are

occurring, and the history of these bits is not latched.

57 of 97

DS2152

Like the other status registers in the DS2152, the user will always precede a read of any of the four

registers with a write. The byte written to the register will inform the DS2152 which of the latched bits

the user wishes to read and have cleared (the real-time bits are not affected by writing to the status

register). The user will write a byte to one of these registers, with a 1 in the bit positions he or she wishes

to read and a 0 in the bit positions he or she does not wish to obtain the latest information on. When a 1 is

written to a bit location, the read register will be updated with current value and it will be cleared. When a

0 is written to a bit position, the read register will not be updated and the previous value will be held. A

write to the status and information registers will be immediately followed by a read of the same register.

The read result should be logically ANDed with the mask byte that was just written and this value should

be written back into the same register to insure that bit does indeed clear. This second write step is

necessary because the alarms and events in the status registers occur asynchronously in respect to their

access via the parallel port. This write-read-write (for polled driven access) or write-read (for interrupt-

driven access) scheme allows an external microcontroller or microprocessor to individually poll certain

bits without disturbing the other bits in the register. This operation is key in controlling the DS2152 with

higher-order software languages.

Like the SR1 and SR2 status registers, the FDLS register has the unique ability to initiate a hardware

interrupt via the INT output pin. Each of the events in the FDLS can be either masked or unmasked from

the interrupt pin via the FDL Interrupt Mask Register (FIMR). Interrupts will force the INT pin low when

the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the

user reads the event bit that caused the interrupt to occur.

12.1.2 Basic Operation Details

To allow the DS2152 to properly source/receive data from/to the HDLC and BOC controller the legacy

FDL circuitry (which is described in Section 12.2) should be disabled and the following bits should be

programmed as shown:

TCR1.2 = 1 (source FDL data from the HDLC and BOC controller)

TBOC.6 = 1 (enable HDLC and BOC controller)

CCR2.5 = 0 (disable SLC-96 and D4 Fs-bit insertion)

CCR2.4 = 0 (disable legacy FDL 0 stuffer)

CCR2.1 = 0 (disable SLC-96 reception)

CCR2.0 = 0 (disable legacy FDL 0 stuffer)

IMR2.4 = 0 (disable legacy receive FDL buffer full interrupt)

IMR2.3 = 0 (disable legacy transmit FDL buffer empty interrupt)

IMR2.2 = 0 (disable legacy FDL match interrupt)

IMR2.1 = 0 (disable legacy FDL abort interrupt)

As a basic guideline for interpreting and sending both HDLC messages and BOC messages, the following

sequences can be applied:

58 of 97

DS2152

12.1.3 Receive an HDLC Message or a BOC

1) Enable RBOC and RPS interrupts.

2) Wait for interrupt to occur.

3) If RBOC = 1, then follow steps 5 and 6.

4) If RPS = 1, then follow steps 7 thru 12.

5) If LBD = 1, a BOC is present, then read the code from the RBOC register and take action as needed.

6) If BD = 0, a BOC has ceased, take action as needed and then return to step 1.

7) Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt.

8) Read RPRM to obtain REMPTY status.

a. If REMPTY = 0, then record OBYTE, CBYTE, and POK bits and then read the FIFO .

a1. If CBYTE = 0 then skip to step 9.

a2. If CBYTE = 1 then skip to step 11.

b. If REMPTY = 1, then skip to step 10.

9) Repeat step 8.

10) Wait for interrupt, skip to step 8.

11) If POK = 0, then discard whole packet, if POK = 1, accept the packet.

12) Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.

12.1.4 Transmit an HDLC Message

1) Make sure HDLC controller is finished sending any previous messages and is currently sending flags

by checking that the FIFO is empty by reading the TEMPTY status bit in the TPRM register.

2) Enable either the THALF or TNF interrupt.

3) Read TPRM to obtain TFULL status.

a. If TFULL = 0, then write a byte into the FIFO and skip to next step (special case occurs when the

last byte is to be written, in this case set TEOM = 1 before writing the byte and then skip to step

6).

b. If TFULL = 1, then skip to step 5.

4) Repeat step 3.

5) Wait for interrupt, skip to step 3.

6) Disable THALF or TNF interrupt and enable TMEND interrupt.

7) Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.

12.1.5 Transmit a BOC

1) Write 6-bit code into TBOC.

2) Set SBOC bit in TBOC = 1.

59 of 97

DS2152

12.1.6 HDLC/BOC Register Description

FDLC: FDL CONTROL REGISTER (Address = 00 Hex)

(MSB)

(LSB)

TCRCF

RBR

RHR

TFS

POSITION

FDLC.7

THR

TABT

TEOM

TZSD

SYMBOL

RBR

NAME AND DESCRIPTION

Receive BOC Reset. A 0 to 1 transition will reset the BOC

circuitry. Must be cleared and set again for a subsequent reset.

RHR

TFS

FDLC.6

FDLC.5

Receive HDLC Reset. A 0 to 1 transition will reset the HDLC

controller. Must be cleared and set again for a subsequent reset.

Transmit Flag/Idle Select.

0 = 7Eh

1 = FFh

THR

FDLC.4

FDLC.3

Transmit HDLC Reset. A 0 to 1 transition will reset both the

HDLC controller and the transmit BOC circuitry. Must be

cleared and set again for a subsequent reset.

TABT

Transmit Abort. A 0 to 1 transition will cause the FIFO

contents to be dumped and one FEh abort to be sent followed by

7Eh or FFh flags/idle until a new packet is initiated by writing

new data into the FIFO. Must be cleared and set again for a

subsequent abort to be sent.

TEOM

FDLC.2

Transmit End of Message. Should be set to a 1 just before the

last data byte of a HDLC packet is written into the transmit

FIFO at TFFR. This bit will be cleared by the HDLC controller

when the last byte has been transmitted.

TZSD

FDLC.1

FDLC.0

Transmit 0 Stuffer Defeat. Overrides internal enable.

0 = enable the 0 stuffer (normal operation)

1 = disable the 0 stuffer

TCRCD

Transmit CRC Defeat.

0 = enable CRC generation (normal operation)

1 = disable CRC generation

60 of 97

DS2152

FDLS: FDL STATUS REGISTER (Address = 01 Hex)

(MSB)

(LSB)

TMEND

RBOC

RPE

RPS

POSITION

FDLS.7

RHALF

RNE

THALF

TNF

SYMBOL

RBOC

NAME AND DESCRIPTION

Receive BOC Detector Change of State. Set whenever the

BOC detector sees a change of state from a BOC Detected to a

No Valid Code seen or vice versa. The setting of this bit prompt

the user to read the RBOC register for details.

RPE

FDLS.6

Receive Packet End. Set when the HDLC controller detects

either the finish of a valid message (i.e., CRC check complete)

or when the controller has experienced a message fault such as a

CRC checking error, or an overrun condition, or an abort has

been seen. The setting of this bit prompts the user to read the

RPRM register for details.

RPS

RHALF

RNE

FDLS.5

FDLS.4

FDLS.3

FDLS.2

FDLS.1

FDLS.0

Receive Packet Start. Set when the HDLC controller detects an

opening byte. The setting of this bit prompts the user to read the

RPRM register for details.

Receive FIFO Half Full. Set when the receive 16-byte FIFO

fills beyond the halfway point. The setting of this bit prompts the

user to read the RPRM register for details.

Receive FIFO Not Empty. Set when the receive 16-byte FIFO

has at least 1 byte available for a read. The setting of this bit

prompts the user to read the RPRM register for details.

THALF

TNF

Transmit FIFO Half Empty. Set when the transmit 16-byte

FIFO empties beyond the halfway point. The setting of this bit

prompts the user to read the TPRM register for details.

Transmit FIFO Not Full. Set when the transmit 16-byte FIFO

has at least 1 byte available. The setting of this bit prompts the

user to read the TPRM register for details.

TMEND

Transmit Message End. Set when the transmit HDLC

controller has finished sending a message. The setting of this bit

prompts the user to read the TPRM register for details.

Note: The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.

61 of 97

DS2152

FIMR: FDL INTERRUPT MASK REGISTER (Address = 02 Hex)

(MSB)

(LSB)

TMEND

RBOC

RPE

RPS

POSITION

FIMR.7

RHALF

RNE

THALF

TNF

SYMBOL

RBOC

NAME AND DESCRIPTION

Receive BOC Detector Change of State.

0 = interrupt masked

1 = interrupt enabled

RPE

RPS

FIMR.6

FIMR.5

FIMR.4

FIMR.3

FIMR.2

FIMR.1

FIMR.0

Receive Packet End.

0 = interrupt masked

1 = interrupt enabled

Receive Packet Start.

0 = interrupt masked

1 = interrupt enabled

RHALF

RNE

Receive FIFO Half Full.

0 = interrupt masked

1 = interrupt enabled

Receive FIFO Not Empty.

0 = interrupt masked

1 = interrupt enabled

THALF

TNF

Transmit FIFO Half Empty.

0 = interrupt masked

1 = interrupt enabled

Transmit FIFO Not Full.

0 = interrupt masked

1 = interrupt enabled

TMEND

Transmit Message End.

0 = interrupt masked

1 = interrupt enabled

62 of 97

DS2152

RPRM: RECEIVE RPM REGISTER (Address = 03 Hex)

(MSB)

(LSB)

OBYTE

RABT

RCRCE

ROVR

RVM

REMPTY

POK

CBYTE

SYMBOL

POSITION

NAME AND DESCRIPTION

RABT

RPRM.7

Abort Sequence Detected. Set whenever the HDLC controller

sees seven or more 1s in a row.

RCRCE

ROVR

RPRM.6

RPRM.5

CRC Error. Set when the CRC checksum is in error.

Overrun. Set when the HDLC controller has attempted to write

a byte into an already full receive FIFO.

RVM

REMPTY

POK

RPRM.4

RPRM.3

RPRM.2

Valid Message. Set when the HDLC controller has detected and

checked a complete HDLC packet.

Empty. A real-time bit that is set high when the receive FIFO is

empty.

Packet OK. Set when the byte available for reading in the

receive FIFO at RFDL is the last byte of a valid message (and

hence no abort was seen, no overrun occurred, and the CRC was

correct).

CBYTE

OBYTE

RPRM.1

RPRM.0

Closing Byte. Set when the byte available for reading in the

receive FIFO at RFDL is the last byte of a message (whether the

message was valid or not).

Opening Byte. Set when the byte available for reading in the

receive FIFO at RFDL is the first byte of a message.

Note: The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.

63 of 97

DS2152

RBOC: RECEIVE BOC REGISTER (Address = 04 Hex)

(MSB)

(LSB)

BOC0

LBD

BD

BOC5

BOC4

BOC3

BOC2

BOC1

SYMBOL

POSITION

NAME AND DESCRIPTION

LBD

RBOC.7

Latched BOC Detected. A latched version of the BD status bit

(RBOC.6). Will be cleared when read.

BD

RBOC.6

BOC Detected. A real-time bit that is set high when the BOC

detector is presently seeing a valid sequence and set low when

no BOC is currently being detected.

BOC5

BOC4

BOC3

BOC2

BOC1

BOC0

RBOC.5

RBOC.4

RBOC.3

RBOC.2

RBOC.1

RBOC.0

BOC Bit 5. Last bit received of the 6-bit codeword.

BOC Bit 4.

BOC Bit 3.

BOC Bit 2.

BOC Bit 1.

BOC Bit 0. First bit received of the 6-bit codeword.

Note 1: The LBD bit is latched and will be cleared when read.

Note 2: The RBOC0 to RBOC5 bits display the last valid BOC code verified; these bits will be set to all 1s on reset.

RFFR: RECEIVE FDL FIFO REGISTER (Address = 05 Hex)

(MSB)

(LSB)

FDL7

FDL6

FDL5

FDL4

FDL3

FDL2

FDL1

FDL0

SYMBOL

POSITION

NAME AND DESCRIPTION

FDL7

RFFR.7

FDL Data Bit 7. MSB of a HDLC packet data byte.

FDL Data Bit 6.

FDL6

FDL5

FDL4

FDL3

FDL2

FDL1

FDL0

RFFR.6

RFFR.5

RFFR.4

RFFR.3

RFFR.2

RFFR.1

RFFR.0

FDL Data Bit 5.

FDL Data Bit 4.

FDL Data Bit 3.

FDL Data Bit 2.

FDL Data Bit 1.

FDL Data Bit 0. LSB of a HDLC packet data byte.

64 of 97

DS2152

TPRM: TRANSMIT PRM REGISTER (Address = 06 Hex)

(MSB)

(LSB)

UDR

—

TEMPTY

NAME AND DESCRIPTION

Not Assigned. Could be any value when read.

TFULL

SYMBOL

—

POSITION

TPRM.7 to

TPRM.3

TPRM.2

TEMPTY

Transmit FIFO Empty. A real-time bit that is set high when

the FIFO is empty.

TFULL

UDR

TPRM.1

TPRM.0

Transmit FIFO Full. A real-time bit that is set high when the

FIFO is full.

Underrun. Set when the transmit FIFO unwantedly empties out

and an abort is automatically sent.

Note: The UDR bit is latched and will be cleared when read.

TBOC: TRANSMIT BOC REGISTER (Address = 07 Hex)

(MSB)

(LSB)

SBOC

HBEN

BOC5

BOC4

BOC3

BOC2

BOC1

BOC0

SYMBOL

SBOC

POSITION

NAME AND DESCRIPTION

TBOC.7

Send BOC. Rising edge triggered. Must be transitioned from a 0

to a 1 transmit the BOC code placed in the BOC0 to BOC5 bits

instead of data from the HDLC controller.

HBEN

TBOC.6

Transmit HDLC & BOC Controller Enable.

0 = source FDL data from the TLINK pin

1 = source FDL data from the on-board HDLC and BOC

controller

BOC5

BOC4

BOC3

BOC2

BOC1

BOC0

TBOC.5

TBOC.4

TBOC.3

TBOC.2

TBOC.1

TBOC.0

BOC Bit 5. Last bit transmitted of the 6-bit codeword.

BOC Bit 4.

BOC Bit 3.

BOC Bit 2.

BOC Bit 1.

BOC Bit 0. First bit transmitted of the 6-bit codeword.

65 of 97

DS2152

TFFR: TRANSMIT FDL FIFO REGISTER (Address = 08 Hex)

(MSB)

(LSB)

FDL0

FDL7

SYMBOL

FDL7

FDL6

FDL5

FDL4

FDL3

FDL2

FDL1

FDL0

FDL6

FDL5

POSITION

TFFR.7

FDL4

FDL3

FDL2

FDL1

NAME AND DESCRIPTION

FDL Data Bit 7. MSB of a HDLC packet data byte.

FDL Data Bit 6.

TFFR.6

TFFR.5

FDL Data Bit 5.

TFFR.4

FDL Data Bit 4.

TFFR.3

FDL Data Bit 3.

TFFR.2

FDL Data Bit 2.

TFFR.1

FDL Data Bit 1.

TFFR.0

FDL Data Bit 0. LSB of a HDLC packet data byte.

66 of 97

DS2152

12.2Legacy FDL Support

In order to provide backward compatibility to the older DS2151 device, the DS2152 maintains the

circuitry that existed in the previous generation of T1 single-chip transceivers. This section covers the

circuitry and operation of this legacy functionality. In new applications, it is recommended that the

HDLC controller and BOC controller described in Section 12.1 be used. On the receive side, it is possible

to have both the new HDLC/BOC controller and the legacy hardware working at the same time.

However, this is not possible on the transmit side since their can be only one source the of the FDL data

internal to the device.

12.2.1 Receive Section

In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL

register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2ms (8 times 250µs). The

DS2152 will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via

IMR2.4, the INT pin will toggle low indicating that the buffer has filled and needs to be read. The user

has 2ms to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed

into the RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT pin will toggled

low if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs

pattern until an important event occurs.

The DS2152 also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403 and

TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states

that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or

closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2152 will

automatically look for five 1s in a row, followed by a 0. If it finds such a pattern, it will automatically

remove the 0. If the 0 destuffer sees six or more 1s in a row followed by a 0, the 0 is not removed. The

CCR2.0 bit should always be set to a 1 when the DS2152 is extracting the FDL. More on how to use the

DS2152 in FDL applications in this legacy support mode is covered in a separate application note.

RFDL: RECEIVE FDL REGISTER (Address = 28 Hex)

(MSB)

(LSB)

RFDL7

RFDL6

RFDL5

RFDL4

RFDL3

RFDL2

RFDL1

RFDL0

SYMBOL

POSITION NAME AND DESCRIPTION

RFDL7

RFDL0

RFDL.7

RFDL.0

MSB of the Received FDL Code

LSB of the Received FDL Code

The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs

bits. The LSB is received first.

67 of 97

DS2152

RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex)

RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex)

(MSB)

(LSB)

RFDL0

RFDL7

RFDL6

RFDL5

RFDL4

RFDL3

RFDL2

RFDL1

SYMBOL

POSITION NAME AND DESCRIPTION

RFDL7

RFDL0

RFDL.7

RFDL.0

MSB of the FDL Match Code

LSB of the FDL Match Code

When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers

(RFDLM1/RFDLM2), RSR2.2 will be set to 1 and the INT will go active if enabled via IMR2.2.

12.2.2 Transmit Section

The transmit section will shift out into the T1 data stream either the FDL (in the ESF framing mode) or

the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value

is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing

T1 data stream. After the full 8 bits have been shifted out, the DS2152 will signal the host microcontroller

that the buffer is empty and that more data is needed by setting the SR2.3 bit to 1. The INT will also

toggle low if enabled via IMR2.3. The user has 2ms to update the TFDL with a new value. If the TFDL is

not updated, the old value in the TFDL will be transmitted once again.

The DS2152 also contains a 0 stuffer which is controlled via the CCR2.4 bit. In both ANSI T1.403 and

TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states

that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or

closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the DS2152 will

automatically look for five 1s in a row. If it finds such a pattern, it will automatically insert a 0 after the

five 1s. The CCR2.0 bit should always be set to a 1 when the DS2152 is inserting the FDL. More on how

to use the DS2152 in FDL applications is covered in a separate application note.

TFDL: TRANSMIT FDL REGISTER (Address = 7E Hex)

(Also used to insert Fs framing pattern in D4 framing mode; see Section 12.3)

(MSB)

(LSB)

TFDL7

TFDL6

TFDL5

TFDL4

TFDL3

TFDL2

TFDL1

TFDL0

SYMBOL

POSITION NAME AND DESCRIPTION

TFDL7

TFDL0

TFDL.7

TFDL.0

MSB of the FDL code to be transmitted.

LSB of the FDL code to be transmitted.

The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be

inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.

68 of 97

DS2152

12.3D4/SLC-96 OPERATION

In the D4 framing mode, the DS2152 uses the TFDL register to insert the Fs framing pattern. To allow

the device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be

programmed to 1Ch and the following bits must be programmed as shown:

TCR1.2 = 0 (source Fs data from the TFDL register)

CCR2.5 = 1 (allow the TFDL register to load on multiframe boundaries)

Since the SLC-96 message fields share the Fs-bit position, the user can access these message fields via

the TFDL and RFDL registers. See the separate application note for a detailed description of how to

implement an SLC-96 function.

69 of 97

DS2152

13 PROGRAMMABLE IN-BAND CODE GENERATION AND DETECTION

The DS2152 can generate and detect a repeating bit pattern that is from 1 to 8 bits in length. To transmit a

pattern, the user will load the pattern to be sent into the Transmit Code Definition (TCD) register and

select the proper length of the pattern by setting the TC0 and TC1 bits in the In-Band Code Control

(IBCC) register. Once this is accomplished, the pattern will be transmitted as long as the TLOOP control

bit (CCR3.1) is enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit

position) the DS2152 will overwrite the repeating pattern once every 193 bits to allow the F-bit position

to be sent. See Figure 16-11 for more details. As an example, if the user wished to transmit the standard

“loop up” code for Channel Service Units which is a repeating pattern of ...10000100001... then 80h

would be loaded into TDR and the length would set to 5 bits.

The DS2152 can detect two separate repeating patterns to allow for both a “loop up” code and a “loop

down” code to be detected. The user will program the codes to be detected in the Receive Up Code

Definition (RUPCD) register and the Receive Down Code Definition (RDNCD) register and the length of

each pattern will be selected via the IBCC register. The DS2152 will detect repeating pattern codes in

both framed and unframed circumstances with bit error rates as high as 10**-2. The code detector has a

nominal integration period of 48ms. Hence, after about 48 ms of receiving either code, the proper status

bit (LUP at SR1.7 and LDN at SR1.6) will be set to a 1. Normally codes are sent for a period of 5

seconds. It is recommend that the software poll the DS2152 every 100ms to 1000ms until 5 seconds has

elapsed to insure that the code is continuously present.

IBCC: IN-BAND CODE CONTROL REGISTER (Address = 12 Hex)

(MSB)

(LSB)

TC1

TC0

RUP2

POSITION

IBCC.7

RUP1

RUP0

RDN2

RDN1

RDN0

SYMBOL

TC1

NAME AND DESCRIPTION

Transmit Code Length Definition Bit 1. See Table 13-1.

Transmit Code Length Definition Bit 0. See Table 13-1.

Receive Up Code Length Definition Bit 2. See Table 13-2.

Receive Up Code Length Definition Bit 1. See Table 13-2.

Receive Up Code Length Definition Bit 0. See Table 13-2.

Receive Down Code Length Definition Bit 2. See Table 13-2.

Receive Down Code Length Definition Bit 1. See Table 13-2.

Receive Down Code Length Definition Bit 0. See Table 13-2.

TC0

IBCC.6

RUP2

RUP1

RUP0

RDN2

RDN1

RDN0

IBCC.5

IBCC.4

IBCC.3

IBCC.2

IBCC.1

IBCC.0

70 of 97

DS2152

Table 13-1. Transmit Code Length

LENGTH

TC1

TC0

SELECTED (BITS)

0

1

0

1

0

1

5

6/3

7

8/4/2/1

Table 13-2. Receive Code Length

LENGTH

RUP2/ RUP1/ RUP0/

SELECTED

RDN2 RDN1 RDN0

(BITS)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

TCD: TRANSMIT CODE DEFINITION REGISTER (Address = 13 Hex)

(MSB)

(LSB)

C0

C7

C6

C5

C4

C3

C2

C1

SYMBOL

POSITION

NAME AND DESCRIPTION

C7

TCD.7

Transmit Code Definition Bit 7. First bit of the repeating

pattern.

C6

C5

C4

C3

C2

TCD.6

TCD.5

TCD.4

TCD.3

TCD.2

Transmit Code Definition Bit 6.

Transmit Code Definition Bit 5.

Transmit Code Definition Bit 4.

Transmit Code Definition Bit 3.

Transmit Code Definition Bit 2. A Don’t Care if a 5-bit length

is selected.

C1

C0

TCD.1

TCD.0

Transmit Code Definition Bit 1. A Don’t Care if a 5 or 6-bit

length is selected.

Transmit Code Definition Bit 0. A Don’t Care if a 5, 6 or 7-bit

length is selected.

71 of 97

DS2152

RUPCD: RECEIVE UP CODE DEFINITION REGISTER (Address = 14 Hex)

(MSB)

(LSB)

C0

C7

C6

C5

POSITION

RUPCD.7

C4

C3

C2

C1

SYMBOL

NAME AND DESCRIPTION

C7

Receive Up Code Definition Bit 7. First bit of the repeating

pattern.

C6

C5

C4

C3

C2

C1

C0

RUPCD.6

RUPCD.5

RUPCD.4

RUPCD.3

RUPCD.2

RUPCD.1

RUPCD.0

Receive Up Code Definition Bit 6. A Don’t Care if a 1-bit

length is selected.

Receive Up Code Definition Bit 5. A Don’t Care if a 1 or 2-bit

length is selected.

Receive Up Code Definition Bit 4. A Don’t Care if a 1 to 3-bit

length is selected.

Receive Up Code Definition Bit 3. A Don’t Care if a 1 to 4-bit

length is selected.

Receive Up Code Definition Bit 2. A Don’t Care if a 1 to 5-bit

length is selected.

Receive Up Code Definition Bit 1. A Don’t Care if a 1 to 6-bit

length is selected.

Receive Up Code Definition Bit 0. A Don’t Care if a 1 to 7-bit

length is selected.

72 of 97

DS2152

RDNCD: RECEIVE DOWN CODE DEFINITION REGISTER (Address = 15 Hex)

(MSB)

(LSB)

C7

C6

C5

C4

C3

C2

C1

C0

SYMBOL

POSITION NAME AND DESCRIPTION

C7

C6

RDNCD.7 Receive Down Code Definition Bit 7. First bit of the repeating pattern.

RDNCD.6 Receive Down Code Definition Bit 6. A Don’t Care if a 1-bit length is

selected.

C5

C4

C3

C2

C1

C0

RDNCD.5 Receive Down Code Definition Bit 5. A Don’t Care if a 1 or 2-bit

length is selected.

RDNCD.4 Receive Down Code Definition Bit 4. A Don’t Care if a 1 to 3-bit length

is selected.

RDNCD.3 Receive Down Code Definition Bit 3. A Don’t Care if a 1 to 4-bit length

is selected.

RDNCD.2 Receive Down Code Definition Bit 2. A Don’t Care if a 1 to 5-bit length

is selected.

RDNCD.1 Receive Down Code Definition Bit 1. A Don’t Care if a 1 to 6-bit length

is selected.

RDNCD.0 Receive Down Code Definition Bit 0. A Don’t Care if a 1 to 7-bit length

is selected.

73 of 97

DS2152

14 TRANSMIT TRANSPARENCY

Each of the 24 T1 channels in the transmit direction of the DS2152 can be either forced to be transparent

or, in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting the data

in the channels. Transparency can be invoked on a channel-by-channel basis by properly setting the

TTR1, TTR2, and TTR3 registers.

TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER

(Address = 39 to 3B Hex)

(MSB)

CH8

CH16

CH24

(LSB)

CH1

CH7

CH15

CH23

CH6

CH14

CH22

CH5

CH13

CH21

CH4

CH12

CH20

CH3

CH11

CH19

CH2

CH10

CH18

TTR1 (39)

TTR2 (3A)

TTR3 (3B)

CH9

CH17

SYMBOL

POSITION NAME AND DESCRIPTION

CH24

TTR3.7

Transmit Transparency Registers.

0 = this DS0 channel is not transparent

CH1

TTR1.0

1 = this DS0 channel is transparent

Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represents a DS0

channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or

clear). If a DS0 is programmed to be clear, no robbed-bit signaling will be inserted nor will the channel

have Bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a 0 when a

Yellow Alarm is transmitted. Also, the user has the option to prevent the TTR registers from determining

which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set to 1, then all

24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR registers are

programmed. In this manner, the TTR registers are only affecting which channels are to have robbed-bit

signaling inserted into them. See Figure 16-11 for more details.

74 of 97

DS2152

15 LINE INTERFACE FUNCTION

The line interface function in the DS2152 contains three sections: the receiver, which handles clock and

data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of

these three sections is controlled by the Line Interface Control Register (LICR), which is described

below.

LICR: LINE INTERFACE CONTROL REGISTER (Address = 7C Hex)

(MSB)

(LSB)

L2

L1

L0

EGL

JAS

JABDS

DJA

TPD

LICR

SYMBOL

POSITION

LICR.7

NAME AND DESCRIPTION

L2

Line Build-Out Select Bit 2. Sets the transmitter build out; see

the Table 15-2.

L1

L0

LICR.6

LICR.5

LICR.4

Line Build-Out Select Bit 1. Sets the transmitter build out; see

the Table 15-2.

Line Build-Out Select Bit 0. Sets the transmitter build out; see

the Table 15-2.

EGL

Receive Equalizer Gain Limit.

0 = -36dB

1 = -30dB

JAS

JABDS

DJA

LICR.3

LICR.2

LICR.1

LICR.0

Jitter Attenuator Select.

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

Jitter Attenuator Buffer Depth Select

0 = 128 bits

1 = 32 bits (use for delay sensitive applications)

Disable Jitter Attenuator.

0 = jitter attenuator enabled

1 = jitter attenuator disabled

TPD

Transmit Power Down.

0 = normal transmitter operation

1 = powers down the transmitter and tri-states the TTIP and

TRING pins

75 of 97

DS2152

15.1Receive Clock and Data Recovery

The DS2152 contains a digital clock recovery system. See Figure 1-1 and Figure 15-1 for more details.

The DS2152 couples to the receive T1 twisted pair via a 1:1 transformer. See Table 15-2 for transformer

details. The 1.544MHz clock attached at the MCLK pin is internally multiplied by 16 via an internal PLL

and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to

form a 16 times oversampler which is used to recover the clock and data. This oversampling technique

offers outstanding jitter tolerance (see Figure 15-2).

Normally, the clock that is output at the RCLKO pin is the recovered clock from the T1 AMI/B8ZS

waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING,

a Receive Carrier Loss (LRCL) condition will occur and the RCLKO will be sourced from the clock

applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the

RCLKO output can exhibit slightly shorter high cycles of the clock. This is due to the highly over-

sampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case

in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. See the

Receive AC Timing Characteristics in Section 18 for more details.

15.2 Transmit Waveshaping and Line Driving

The DS2152 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter

(DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the

DS2152 meet the latest ANSI, AT&T, and ITU specifications. See Figure 15-3. The user will select

which waveform is to be generated by properly programming the L2/L1/L0 bits in the Line Interface

Control Register (LICR). The DS2152 can set up in a number of various configurations depending on the

application. See Table 15-1 and Figure 15-1.

Table 15-1. Line Build-Out Select in LICR

L2

L1

L0 LINE BUILD-OUT

APPLICATION

DSX-1/CSU

DSX-1

0

1

0

1

0

1

0

1

0 to 133ft/0dB

133ft to 266ft

266ft to 399ft

399ft to 533ft

533ft to 655ft

-7.5dB

0

1

DSX-1

0

1

DSX-1

1

0

DSX-1

1

0

CSU

1

-15dB

CSU

1

-22.5dB

CSU

Due to the nature of the design of the transmitter in the DS2152, very little jitter (less than 0.005UI_P-P

broadband from 10Hz to 100kHz) is added to the jitter present on TCLKI. Also, the waveforms that they

create are independent of the duty cycle of TCLK. The transmitter in the DS2152 couples to the T1

transmit twisted pair via a 1:1.15 or 1:1.36 step-up transformer as shown in Figure 15-1. For the devices

to create the proper waveforms, this transformer used must meet the specifications listed in Table 15-2.

76 of 97

DS2152

Table 15-2. Transformer Specifications

SPECIFICATION

RECOMMENDED VALUE

Turns Ratio

1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ±5%

600µH minimum

Primary Inductance

Leakage Inductance

Intertwining Capacitance

DC Resistance

1.0µH maximum

40pF maximum

1.2Ω maximum

15.3Jitter Attenuator

The DS2152 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via

the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications

where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.

The characteristics of the attenuation are shown in Figure 15-4. The jitter attenuator can be placed in

either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.

Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order

for the jitter attenuator to operate properly, a 1.544MHz clock (±50ppm) must be applied at the MCLK

pin or a crystal with similar characteristics must be applied across the MCLK and XTALD pins. If a

crystal is applied across the MCLK and XTALD pins, then capacitors should be placed from each leg of

the crystal to the local ground plane as shown in Figure 15-1. On-board circuitry adjusts either the

recovered clock from the clock/data recovery block or the clock applied at the TCLKI pin to create a

smooth jitter-free clock that is used to clock data out of the jitter attenuator FIFO. It is acceptable to

provide a gapped/bursty clock at the TCLKI pin if the jitter attenuator is placed on the transmit side. If the

incoming jitter exceeds either 120UI_P-P(buffer depth is 128 bits) or 28UI_P-P(buffer depth is 32 bits), then

the DS2152 will divide the internal nominal 24.704MHz clock by either 15 or 17 instead of the normal 16

to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter

Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR3.5).

77 of 97

DS2152

Figure 15-1. External Analog Connections

NOTE 1: RESISTOR VALUES ARE ±1%.

NOTE 2: THE R_TRESISTORS ARE USED TO PROTECT THE DEVICE FROM OVERVOLTAGE.

NOTE 3: SEE THE SEPARATE APPLICATION NOTE FOR DETAILS ON HOW TO CONSTRUCT A PROTECTED INTERFACE.

NOTE 4: EITHER A CRYSTAL CAN BE APPLIED ACROSS THE MCLK AND XTALD PINS OR A TTL LEVEL CLOCK CAN BE APPLIED TO JUST MCLK.

NOTE 5: C1 AND C2 SHOULD BE 5PF LOWER THAN 2 TIMES THE NOMINAL LOADING CAPACITANCE OF THE CRYSTAL TO ADJUST FOR THE

INPUT CAPACITANCE OF THE DS2152.

Figure 15-2. Jitter Tolerance

78 of 97

DS2152

Figure 15-3. Transmit Waveform Template

Figure 15-4. Jitter Attenuation

79 of 97

DS2152

16 TIMING DIAGRAMS

Figure 16-1. Receive Side D4 Timing

NOTE 1: RSYNC IN THE FRAME MODE (RCR2.4 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RCR2.5 = 0).

NOTE 2: RSYNC IN THE FRAME MODE (RCR2.4 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (RCR2.5 = 1).

NOTE 3: RSYNC IN THE MULTIFRAME MODE (RCR2.4 = 1).

NOTE 4: RLINK DATA (FS BITS) IS UPDATED 1 BIT PRIOR TO EVEN FRAMES AND HELD FOR TWO FRAMES.

NOTE 5: RLINK AND RLCLK ARE NOT SYNCHRONOUS WITH RSYNC WHEN THE RECEIVE SIDE ELASTIC STORE IS ENABLED.

Figure 16-2. Receive Side Boundary Timing (with Elastic Store Disabled)

NOTE 1: RSYNC IN THE FRAME MODE (RCR2.4 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RCR2.5 = 0).

NOTE 2: RSYNC IN THE FRAME MODE (RCR2.4 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (RCR2.5 = 1).

NOTE 3: RSYNC IN THE MULTIFRAME MODE (RCR2.4 = 1).

NOTE 4: ZBTSI MODE DISABLED (RCR2.6 = 0).

NOTE 5: RLINK DATA (FDL BITS) IS UPDATED 1 BIT-TIME BEFORE ODD FRAMES AND HELD FOR TWO FRAMES.

NOTE 6: ZBTSI MODE IS ENABLED (RCR2.6 = 1).

NOTE 7: RLINK DATA (Z BITS) IS UPDATED 1 BIT-TIME BEFORE ODD FRAMES AND HELD FOR FOUR FRAMES.

NOTE 8: RLINK AND RLCLK ARE NOT SYNCHRONOUS WITH RSYNC WHEN THE RECEIVE SIDE ELASTIC STORE IS ENABLED.

80 of 97

DS2152

Figure 16-3. Receive Side Boundary Timing (with Elastic Store Disabled)

NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.

NOTE 2: SHOWN IS RLINK/RLCLK IN THE ESF FRAMING MODE.

Figure 16-4. Receive Side 1.544MHz Boundary Timing (with Elastic Store

Enabled)

NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0).

NOTE 2: RSYNC IS IN THE INPUT MODE (RCR2.3 = 1).

NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.

81 of 97

DS2152

Figure 16-5. Receive Side 2.048MHz Boundary Timing (with Elastic Store

Enabled)

NOTE 1: RSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO 1.

NOTE 2: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0).

NOTE 3: RSYNC IS IN THE INPUT MODE (RCR2.3 = 1).

NOTE 4: RCHBLK IS FORCED TO 1 IN THE SAME CHANNELS AS RSER (SEE NOTE 1).

NOTE 5: THE F-BIT POSITION IS PASSED THROUGH THE RECEIVE SIDE ELASTIC STORE.

NOTE 6: RCHCLK DOES NOT TRANSITION HIGH IN THE CHANNELS IN WHICH THE RSER DATA IS FORCED TO 1 (SEE NOTE 1).

Figure 16-6. Transmit Side D4 Timing

NOTE 1: TSYNC IN THE FRAME MODE (TCR2.3 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TCR2.4 = 0).

NOTE 2: TSYNC IN THE FRAME MODE (TCR2.3 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TCR2.4 = 1).

NOTE 3: TSYNC IN THE MULTIFRAME MODE (TCR2.3 = 1).

NOTE 4: TLINK DATA (FS BITS) IS SAMPLED DURING THE F-BIT POSITION OF EVEN FRAMES FOR INSERTION INTO THE OUTGOING

T1 STREAM WHEN ENABLED VIA TCR1.2.

NOTE 5: TLINK AND TLCLK ARE NOT SYNCHRONOUS WITH TSSYNC.

82 of 97

DS2152

Figure 16-7. Transmit Side Timing

NOTE 1: TSYNC IN THE FRAME MODE (TCR2.3 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TCR2.4 = 0).

NOTE 2: TSYNC IN THE FRAME MODE (TCR2.3=0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TCR2.4 = 1).

NOTE 3: TSYNC IN THE MULTIFRAME MODE (TCR2.3 = 1).

NOTE 4: ZBTSI MODE DISABLED (TCR2.5 = 0).

NOTE 5: TLINK DATA (FDL BITS) IS SAMPLED DURING THE F-BIT TIME OF ODD FRAME AND INSERTED INTO THE OUTGOING T1 STREAM IF

ENABLED VIA TCR1.2.

NOTE 6: ZBTSI MODE IS ENABLED (TCR2.5 = 1).

NOTE 7: TLINK DATA (Z BITS) IS SAMPLED DURING THE F-BIT TIME OF FRAMES 1, 5, 9, 13, 17, AND 21 AND INSERTED INTO THE OUTGOING

STREAM IF ENABLED VIA TCR1.2.

NOTE 8: TLINK AND TLCLK ARE NOT SYNCHRONOUS WITH TSSYNC.

Figure 16-8. Transmit Side Boundary Timing

NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR2.2 = 1).

NOTE 2: TSYNC IS IN THE INPUT MODE (TCR2.2 = 0).

NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.

NOTE 4: SHOWN IS TLINK/TLCLK IN THE ESF FRAMING MODE.

83 of 97

DS2152

Figure 16-9. Transmit Side 1.544MHz Boundary Timing (with Elastic Store

Enabled)

NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 (IF THE TPCSI BIT IS SET, THEN THE SIGNALING DATA AT TSIG WILL BE

IGNORED DURING CHANNEL 24).

Figure 16-10. Transmit Side 2.048MHz Boundary Timing (with Elastic Store

Enabled)

NOTE 1: TSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED.

NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 31 (IF THE TPCSI BIT IS SET, THEN THE SIGNALING DATA AT TSIG IS IGNORED).

NOTE 3: TCHBLK IS FORCED TO 1 IN THE SAME CHANNELS WHERE TSER IS IGNORED (SEE NOTE 1).

NOTE 4: THE F-BIT POSITION FOR THE T1 FRAME IS SAMPLED AND PASSED THROUGH THE TRANSMIT SIDE ELASTIC STORE (NORMALLY

THE TRANSMIT SIDE FORMATTER OVERWRITES THE F-BIT POSITION UNLESS THE FORMATTER IS PROGRAMMED TO PASS-THROUGH THE

F-BIT POSITION).

NOTE 5: TCHCLK DOES NOT TRANSITION HIGH IN THE CHANNEL IN WHICH THE DATA AT TSER IS IGNORED (SEE NOTE 1).

84 of 97

DS2152

Figure 16-11. Transmit Data Flow

NOTE 1: TCLK SHOULD BE TIED TO RCLK AND TSYNC SHOULD BE TIED TO RFSYNC FOR DATA TO BE PROPERLY SOURCED FROM RSER.

85 of 97

DS2152

17 DC CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +7.0V

Operating Temperature Range

Commercial……………………………………………………………………………0°C to +70°C

Industrial…………………………………………………………………………….-40°C to +85°C

Storage Temperature……………………………………………………………………….-55°C to +125°C

Soldering Temperature……………………………………………See IPC/JEDEC STD-020 Specification

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect

reliability.

Table 17-1. Recommended DC Operating Conditions

(T_A= 0°C to +70°C for DS2152L, T_A= -40°C to +85°C for DS2152LN.)

PARAMETER

SYMBOL

V_IH

MIN

2.0

TYP

MAX

V_DD+ 0.3

+0.8

UNITS NOTES

Logic 1

Logic 0

Supply

V

V_IL

V_DD

-0.3

4.75

5.25

V

1

Table 17-2. Capacitance

(T_A= +25°C)

PARAMETER

Input Capacitance

Output Capacitance

SYMBOL

C_IN

MIN

TYP

MAX

UNITS NOTES

5

7

pF

C_OUT

Table 17-3. DC Characteristics

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2152L, T_A= -40°C to +85°C for DS2152LN.)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Supply Current at 5V

Input Leakage

I_DD

I_IL

75

mA

µA

mA

2

3

4

-1.0

+1.0

1.0

Output Leakage

Output Current (2.4V)

Output Current (0.4V)

I_LO

I_OH

I_OL

-1.0

+4.0

NOTES:

1. Applies to RVDD, TVDD, and DVDD.

2. TCLK = RCLK = TSYSCLK = RSYSCLK = 1.544MHz; outputs open circuited.

3. 0V < V_IN< V_DD.

4. Applied to INT when tri-stated.

86 of 97

DS2152

18 AC CHARACTERISTICS

Table 18-1. AC Characteristics—Multiplexed Parallel Port (MUX = 1)

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2152L, T_A= -40°C to +85°C for DS2152LN.)

(See Figure 18-1, Figure 18-2, and Figure 18-3.)

PARAMETER

SYMBOL MIN TYP MAX UNITS NOTES

Cycle Time

t_CYC

PW_EL

PW_EH

t_R, t_F

t_RWH

t_RWS

200

100

ns

Pulse Width, DS Low or RD High

Pulse Width, DS High or RD Low

Input Rise/Fall Times

R/ W Hold Time

R/ W Setup Time Before DS High

CS Setup Time Before DS, WR or RD

20

50

10

50

ns

t_CS

20

ns

active

t_CH

t_DHR

t_DHW

t_ASL

t_AHL

0

10

0

ns

CS Hold Time

Read Data Hold Time

Write Data Hold Time

Muxed Address Valid to AS or ALE Fall

Muxed Address Hold Time

15

10

Delay Time, DS, WR or RD to AS or ALE

t_ASD

20

ns

Rise

Pulse Width AS or ALE High

Delay Time, AS or ALE to DS, WR or RD

Output Data Delay Time from DS or RD

Data Setup Time

PW_ASH

t_ASED

t_DDR

30

10

20

50

ns

80

t_DSW

Figure 18-1. Intel Bus Read AC Timing (BTS = 0/MUX = 1)

87 of 97

DS2152

Figure 18-2. Intel Bus Write AC Timing (BTS = 0/MUX = 1)

Figure 18-3. Motorola Bus AC Timing (BTS = 1/MUX = 1)

88 of 97

DS2152

Table 18-2. AC Characteristics—Receive Side

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2152L, T_A= -40°C to +85°C for DS2152LN.)

(See Figure 18-4, Figure 18-5, and Figure 18-6.)

PARAMETER

SYMBOL MIN TYP MAX UNITS NOTES

RCLKO Period

t_LP

t_LH

t_LL

t_LH

t_CL

t_CP

t_CH

t_CL

t_SP

t_SH

t_SL

t_SU

t_PW

t_SU

t_HD

t_R, t_F

t_DD

648

324

648

ns

250

200

1

2

RCLKO Pulse Width

RCLKI Period

75

RCLKI Pulse Width

122

50

648

488

3

4

RSYSCLK Period

RSYSCLK Pulse Width

50

RSYNC Setup to RSYSCLK Falling

RSYNC Pulse Width

20

t_SH-5

50

RPOSI/RNEGI Setup to RCLKI Falling

RPOSI/RNEGI Hold From RCLKI Falling

RSYSCLK/RCLKI Rise and Fall Times

Delay RCLKO to RPOSO, RNEGO Valid

Delay RCLK to RSER, RDATA, RSIG,

RLINK Valid

20

25

50

t_D1

50

ns

Delay RCLK to RCHCLK, RSYNC,

RCHBLK, RFSYNC, RLCLK

Delay RSYSCLK to RSER, RSIG Valid

Delay RSYSCLK to RCHCLK, RCHBLK,

RMSYNC, RSYNC

t_D2

t_D3

t_D4

50

ns

NOTES:

1) Jitter attenuator enabled in the receive path.

2) Jitter attenuator disabled or enabled in the transmit path.

3) RSYSCLK = 1.544MHz.

4) RSYSCLK = 2.048MHz.

89 of 97

DS2152

Figure 18-4. Receive Side AC Timing

NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0).

NOTE 2: SHOWN IS RLINK/RLCLK IN THE ESF FRAMING MODE.

NOTE 3: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND THE OTHER SIGNALS IS IMPLIED.

90 of 97

DS2152

Figure 18-5. Receive System Side AC Timing

NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0).

NOTE 2: RSYNC IS IN THE INPUT MODE (RCR2.3 = 1).

Figure 18-6. Receive Line Interface AC Timing

91 of 97

DS2152

Table 18-3. AC Characteristics—Transmit Side

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2152L, T_A= -40°C to +85°C for DS2152LN.)

(See Figure 18-7, Figure 18-8, and Figure 18-9.)

PARAMETER

SYMBOL MIN TYP MAX UNITS NOTES

TCLK Period

t_CP

t_CH

t_CL

t_LP

t_LH

t_LL

t_SP

t_SH

t_SL

648

ns

75

TCLK Pulse Width

TCLKI Period

648

75

122

50

TCLKI Pulse Width

648

448

1

2

TSYSCLK Period

TSYSCLK Pulse Width

50

t_CH-5

or

TSYNC or TSSYNC Setup to TCLK or

TSYSCLK Falling

t_SU

t_PW

t_SU

20

50

20

ns

t_SH-5

TSYNC or TSSYNC Pulse Width

TSER, TSIG, TDATA, TLINK, TPOSI,

TNEGI Setup to TCLK, TSYSCLK,

TCLKI Falling

TSER, TSIG, TDATA, TLINK, TPOSI,

TNEGI Hold from TCLK, TSYSCLK,

TCLKI Falling

t_HD

20

ns

TCLK, TCLKI, or TSYSCLK Rise and

Fall Times

t_R, t_F

25

Delay TCLKO to TPOSO, TNEGO Valid

Delay TCLK to TESO Valid

Delay TCLK to TCHBLK, TCHBLK,

TSYNC, TLCLK

t_DD

t_D1

50

ns

t_D2

t_D3

50

75

ns

Delay TSYSCLK to TCHCLK, TCHBLK

NOTES:

1) TSYSCLK = 1.544MHz.

2) TSYSCLK = 2.048MHz.

92 of 97

DS2152

Figure 18-7. Transmit Side AC Timing

NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR2.2 = 1).

NOTE 2: TSYNC IS IN THE INPUT MODE (TCR2.2 = 0).

NOTE 3: TSER IS SAMPLED ON THE FALLING EDGE OF TCLK WHEN THE TRANSMIT SIDE ELASTIC STORE IS DISABLED.

NOTE 4: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TCLK WHEN THE TRANSMIT SIDE ELASTIC STORE IS DISABLED.

NOTE 5: TLINK IS ONLY SAMPLED DURING F-BIT LOCATIONS.

NOTE 6: NO RELATIONSHIP BETWEEN TCHCLK AND TCHBLK AND THE OTHER SIGNALS IS IMPLIED.

93 of 97

DS2152

Figure 18-8. Transmit System Side AC Timing

NOTE 1: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT SIDE ELASTIC STORE IS ENABLED.

NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT SIDE ELASTIC STORE IS ENABLED.

Figure 18-9. Transmit Line Interface Side AC Timing

94 of 97

DS2152

Table 18-4. AC Characteristics—Nonmultiplexed Parallel Port (MUX = 0)

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2152L, T_A= -40°C to +85°C for DS2152LN.)

(See Figure 18-10, Figure 18-11, Figure 18-12, and Figure 18-13.)

PARAMETER

SYMBOL MIN

TYP

MAX UNITS NOTES

Setup Time for A0 to A7 Valid to CS

t1

t2

t3

t4

t5

t6

t7

t8

t₉

0

ns

Active

Setup Time for CS Active to Either RD ,

WR , or DS Active

0

ns

Delay Time from Either RD or DS

75

20

ns

Active to Data Valid

Hold Time from Either RD , WR , or DS

Inactive to CS Inactive

0

5

Hold Time from CS Inactive to Data

Bus Tri-State

Wait Time from Either WR or DS

Active to Latch Data

75

10

0

Data Setup Time to Either WR or DS

Inactive

Data Hold Time to Either WR or DS

Inactive

Address Hold from Either WR or DS

10

Inactive

Figure 18-10. Intel Bus Read AC Timing (BTS = 0/MUX = 0)

95 of 97

DS2152

Figure 18-11. Intel Bus Write AC Timing (BTS=0/MUX=0)

Figure 18-12. Motorola Bus Read AC Timing (BTS = 1/MUX = 0)

Figure 18-13. Motorola Bus Write AC Timing (BTS = 1/MUX = 0)

96 of 97

DS2152

19 PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for

each package is a link to the latest package outline information.)

19.1 100-Pin LQFP (56-G5002-000)

97 of 97

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.


型号：	DS2152L+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Enhanced T1 Single-Chip Transceiver 电信电信集成电路
文件：	总97页 (文件大小：1272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS2152L+ [MAXIM]

相关型号：

DS2152L-C01

DS2152LN

DS2152LN

DS2152LN+

DS2153Q

DS2153Q+

DS2153Q-A7+T&R

DS2153Q-A7/T&R

DS2153Q-A7/TR+

DS2153QN

DS2153QN+

DS2153QN-A7+