DS2153Q-A7/T&R_技术文档

DS2153Q

E1 Single-Chip Transceiver

www.maxim-ic.com

FEATURES

PIN CONFIGURATION

ꢀ Complete E1 (CEPT) PCM-30/ISDN-PRI

Transceiver Functionality

FUNCTIONAL BLOCKS

ꢀ On-Board Line Interface for Clock/Data

Recovery and Waveshaping

ꢀ 32-Bit or 128-Bit Jitter Attenuator

ꢀ Generates Line Build-Outs for Both 120Ω

and 75Ω Lines

ꢀ Frames to FAS, CAS, and CRC4 Formats

ꢀ Dual On-Board Two-Frame Elastic Store Slip

Buffers That can Connect to Backplanes Up

to 8.192MHz

PARALLEL CONTROL

PORT

ꢀ 8-Bit Parallel Control Port That can be Used

on Either Multiplexed or Nonmultiplexed

Buses

Dallas

ACTUAL SIZE OF 44-PIN PLCC

DS2153Q

ꢀ Extracts and Inserts CAS Signaling

ꢀ Detects and Generates Remote and AIS

Alarms

T1SCT

ꢀ Programmable Output Clocks for Fractional

E1, H0, and H12 Applications

ALE(AS)

WR (R/W)

RLINK

RLCLK

DVSS

7

8

TSER

TCLK

39

38

ꢀ Fully Independent Transmit and Receive

Functionality

9

37

36

35

DVDD

TSYNC

TLINK

TLCLK

TCHBLK

TRING

TVDD

TVSS

DS2153Q

10

ꢀ Full Access to Both Si and Sa Bits

ꢀ Three Separate Loopbacks for Testing

ꢀ Large Counters for Bipolar and Code

Violations, CRC4 Codeword Errors, FAS

Errors, and E Bits

11

12

34

33

RCLK

13

14

15

RCHCLK

RSER

RSYNC

RLOS/LOTC

SYSCLK

32

31

16

17

30

29

ꢀ Pin Compatible with DS2151Q T1 Single-

Chip Transceiver

TTIP

ꢀ 5V Supply; Low-Power CMOS

ORDERING INFORMATION

PLCC

TEMP

PIN-

PART

RANGE

PACKAGE

44 PLCC

DS2153Q

0°C to +70°C

-40°C to +85°C

DS2153Q+

DS2153QN

DS2153QN+

44 PLCC

+Denotes lead-free/RoHS-compliant package.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

1 of 60

REV: 01106

DS2153Q

TABLE OF CONTENTS

1 DETAILED DESCRIPTION....................................................................................................4

1.1 INTRODUCTION................................................................................................................................4

1.2 READER’S NOTE..............................................................................................................................4

2 PIN DESCRIPTION................................................................................................................6

2.1 DS2153Q REGISTER MAP...............................................................................................................8

3 PARALLEL PORT.................................................................................................................9

4 CONTROL AND TEST REGISTERS...................................................................................10

4.1 LOCAL LOOPBACK .........................................................................................................................17

4.2 REMOTE LOOPBACK ......................................................................................................................17

4.3 FRAMER LOOPBACK ......................................................................................................................17

4.4 AUTOMATIC ALARM GENERATION...................................................................................................17

4.5 POWER-UP SEQUENCE .................................................................................................................17

5 STATUS AND INFORMATION REGISTERS......................................................................18

5.1 CRC4 SYNC COUNTER .................................................................................................................20

6 ERROR COUNT REGISTERS.............................................................................................26

6.1 BPV OR CODE VIOLATION COUNTER .............................................................................................26

6.2 CRC4 ERROR COUNTER...............................................................................................................27

6.3 E-BIT COUNTER ............................................................................................................................27

6.4 FAS BIT ERROR COUNTER............................................................................................................28

7 SA DATA LINK CONTROL AND OPERATION..................................................................29

8 SIGNALING OPERATION...................................................................................................30

9 TRANSMIT IDLE REGISTERS............................................................................................32

10 CLOCK BLOCKING REGISTERS....................................................................................33

11 ELASTIC STORES OPERATION.....................................................................................35

12 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION.................................36

13 LINE INTERFACE FUNCTIONS.......................................................................................39

13.1

13.2

13.3

RECEIVE CLOCK AND DATA RECOVERY.......................................................................................40

TRANSMIT WAVESHAPING AND LINE DRIVING ..............................................................................41

JITTER ATTENUATOR..................................................................................................................42

14 TIMING DIAGRAMS.........................................................................................................46

15 DC CHARACTERISTICS..................................................................................................52

16 AC CHARACTERISTICS..................................................................................................53

17 PACKAGE INFORMATION..............................................................................................60

17.1

44-PIN PLCC (56-G4003-001)..................................................................................................60

2 of 60

DS2153Q

LIST OF FIGURES

Figure 1-1. DS2153Q Block Diagram.........................................................................................................5

Figure 13-1. External Analog Connections...............................................................................................43

Figure 13-2. Jitter Tolerance ....................................................................................................................44

Figure 13-3. Transmit Waveform Template..............................................................................................44

Figure 13-4. Jitter Attenuation ..................................................................................................................45

Figure 14-1. Receive Side Timing ............................................................................................................46

Figure 14-2. Receive Side Boundary Timing (with Elastic Stores Disabled) ............................................46

Figure 14-3. 1.544MHz Boundary Timing with Elastic Store(s) Disabled.................................................47

Figure 14-4. 2.048MHz Boundary Timing with Elastic Store(s) Enabled..................................................47

Figure 14-5. Transmit Side Timing ...........................................................................................................48

Figure 14-6. Transmit Side Boundary Timing...........................................................................................48

Figure 14-7. G.802 Timing........................................................................................................................49

Figure 14-8. Synchronization Flowchart...................................................................................................50

Figure 14-9. Transmit Data Flow..............................................................................................................51

Figure 16-1. Intel Bus Read AC Timing....................................................................................................54

Figure 16-2. Intel Bus Write AC Timing....................................................................................................54

Figure 16-3. Motorola Bus AC Timing ......................................................................................................55

Figure 16-4. Receive Side AC Timing ......................................................................................................57

Figure 16-5. Transmit Side AC Timing .....................................................................................................59

LIST OF TABLES

Table 4-1. Sync/Resync Criteria...............................................................................................................11

Table 5-1. Alarm Set and Clear Criteria ...................................................................................................22

Table 13-1. Source of RCLK Upon RCL...................................................................................................40

Table 13-2. LBO Select in LICR ...............................................................................................................41

Table 13-3. Transformer Specifications....................................................................................................41

Table 13-4. Crystal Selection Guidelines .................................................................................................42

Table 15-1. Recommended DC Characteristics.......................................................................................52

Table 15-2. Capacitance ..........................................................................................................................52

Table 15-3. DC Characteristics ................................................................................................................52

Table 16-1. AC Characteristics—Parallel Port .........................................................................................53

Table 16-2. AC Characteristics—Receive Side........................................................................................56

Table 16-3. AC Characteristics—Transmit Side.......................................................................................58

3 of 60

DS2153Q

1 DETAILED DESCRIPTION

The DS2153Q E1 single-chip transceiver (SCT) contains all the necessary functions for connection to E1

lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial

stream. The DS2153Q automatically adjusts to E1 22 AWG (0.6mm) twisted-pair cables from 0 to 1.5km.

The device can generate the necessary G.703 waveshapes for both 75Ω and 120Ω cables. The on-board

jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data

paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It

is also used for extracting and inserting signaling data, Si, and Sa-bit information. The device contains a

set of 71 8-bit internal registers that the user can access to control the operation of the unit. Quick access

via the parallel control port allows a single micro to handle many E1 lines. The device fully meets all the

latest E1 specifications, including ITU G.703, G.704, G.706, G.823, and I.431 as well as ETSI 300 011,

300 233, TBR 12 and TBR 13.

1.1 Introduction

The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of

the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter

attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing

pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency

differences between the recovered E1 data stream and an asynchronous backplane clock which is

provided at the SYSCLK input.

The transmit side of the DS2153Q is totally independent from the receive side in both the clock

requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1

transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation

mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP

and TRING pins via a coupling transformer.

1.2 Reader’s Note

This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit

time slots in E1 systems that are numbered 0 to 31. Time slot 0 is transmitted first and received first.

These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is

identical to channel 1, time slot 1 is identical to channel 2, and so on. Each time slot (or channel) is made

up of 8 bits numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB

and is transmitted last. Throughout this data sheet, the following abbreviations are used:

FAS

CAS

MF

Frame Alignment Signal

Channel Associated Signaling

Multiframe

Si

International Bits

CRC4

CCS

Sa

Cyclical Redundancy Check

Common Channel Signaling

Additional bits

E-bit

CRC4 Error bits

4 of 60

DS2153Q

Figure 1-1. DS2153Q Block Diagram

5 of 60

DS2153Q

2 PIN DESCRIPTION

NAME

TYPE

FUNCTION

1–4,

41–44

5

AD4–AD7,

I/O

Address/Data Bus. An 8-bit multiplexed address/data bus.

Active-Low Read Input (Data Strobe)

AD0–AD3

I

RD (DS)

CS

6

7

8

9

Active-Low Chip Select. Must be low to read or write the port.

Address Latch Enable (Address Strobe). A positive going edge

ALE(AS)

I

serves to demultiplex the bus.

Active-Low Write Input (Read/Write)

WR (R/ W )

RLINK

Receive Link Data. Outputs the full receive data stream including the

O

Sa bits. See Section 14 for timing details.

Receive Link Clock. 4kHz to 20kHz demand clock for the RLINK

output. Controlled by RCR2. See Section 14 for timing details.

Digital Signal Ground. 0.0V. Should be tied to local ground plane.

Receive Clock. Recovered 2.048MHz clock.

10

RLCLK

O

11

12

DVSS

RCLK

—

O

Receive Channel Clock. 256kHz clock that pulses high during the

LSB of each channel. Useful for parallel to serial conversion of

channel data. See Section 14 for timing details.

13

14

RCHCLK

RSER

O

Receive Serial Data. Received NRZ serial data, updated on rising

edges of RCLK or SYSCLK.

Receive Sync. An extracted pulse, one RCLK wide, is output at this

pin, which identifies either frame (RCR1.6 = 0) or multiframe

boundaries (RCR1.6 = 1). If the elastic store is enabled via the

RCR2.1, then this pin can be enabled to be an input via RCR1.5 at

which a frame boundary pulse is applied. See Section 14 for timing

details.

15

RSYNC

I/O

Receive Loss of Sync/Loss of Transmit Clock. A dual function

output. If TCR2.0 = 0, will toggle high when the synchronizer is

searching for the E1 frame and multiframe; if TCR2.0 = 1, will toggle

high if the TCLK pin has not toggled for 5µs.

System Clock. 1.544MHz or 2.048MHz clock. Only used when the

elastic store functions are enabled via either RCR2.1. Should be tied

low in applications that do not use the elastic store. If tied high for at

least 100µs, will force all output pins (including the parallel port) to

tri-state.

16

17

RLOS/LOTC

SYSCLK

O

I

Receive Channel Block. A user-programmable output that can be

forced high or low during any of the 32 E1 channels. Useful for

blocking clocks to a serial UART or LAPD controller in applications

where not all E1 channels are used such as Fractional E1, 384kbps

service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating

individual channels in drop-and-insert applications. See Section 14 for

timing details.

Alternate Clock Input. Upon a receive carrier loss, the clock applied

at this pin (normally 2.048MHz) will be routed to the RCLK pin. If no

clock is routed to this pin, then it should be tied to DVSS via a 1kΩ

resistor.

18

19

RCHBLK

ACLKI

O

I

6 of 60

DS2153Q

NAME

TYPE

FUNCTION

Bus Type Select. Strap high to select Motorola bus timing; strap low to

select Intel bus timing. This pin controls the function of the RD (DS),

20

BTS

I

ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these pins assume the

function listed in parentheses ().

RTIP,

Receive Tip and Ring. Analog inputs for clock recovery circuitry;

21, 22

—

RRING

connects to a 1:1 transformer (see Section 13 for details).

Receive Analog Positive Supply. 5.0V. Should be tied to DVDD and

23

24

RVDD

RVSS

—

TVDD pins.

Receive Signal Ground. 0V. Should be tied to local ground plane.

XTAL1,

Crystal Connections. A pullable 8.192MHz crystal must be applied to

25, 26

—

XTAL2

these pins. See Section 13 for crystal specifications.

Receive Alarm Interrupt 1. Flags host controller during alarm

conditions defined in Status Register 1. Active low, open drain output.

Receive Alarm Interrupt 2. Flags host controller during conditions

defined in Status Register 2. Active low, open drain output.

Transmit Tip. Analog line driver output; connects to a step-up

transformer (see Section 13 for details).

27

28

O

INT1

INT2

29

30

31

TTIP

TVSS

TVDD

—

Transmit Signal Ground. 0V. Should be tied to local ground plane.

Transmit Analog Positive Supply. 5.0V. Should be tied to DVDD and

RVDD pins.

Transmit Ring. Analog line driver outputs; connects to a step-up

transformer (see Section 13 for details).

32

TRING

—

Transmit Channel Block. A user-programmable output that can be

forced high or low during any of the 32 E1 channels. Useful for

blocking clocks to a serial UART or LAPD controller in applications

where not all E1 channels are used such as Fractional E1, 384kbps

service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating

individual channels in drop-and-insert applications. See Section 14 for

timing details.

33

TCHBLK

O

Transmit Link Clock. 4kHz to 20kHz demand clock for the TLINK

input. Controlled by TCR2. See Section 14 for timing details.

Transmit Link Data. If enabled, this pin will be sampled on the falling

edge of TCLK to insert the Sa bits. See Section 14 for timing details.

Transmit Sync. A pulse at this pin will establish either frame or

multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q

can be programmed to output either a frame or multiframe pulse at this

pin. See Section 14 for timing details.

34

35

TLCLK

TLINK

O

I

36

TSYNC

I/O

Digital Positive Supply. 5.0V. Should be tied to RVDD and TVDD

pins.

37

38

39

DVDD

TCLK

TSER

—

I

Transmit Clock. 2.048MHz primary clock.

Transmit Serial Data. Transmit NRZ serial data, sampled on the

falling edge of TCLK.

I

Transmit Channel Clock. 256kHz clock that pulses high during the

LSB of each channel. Useful for parallel to serial conversion of channel

data. See Section 14 for timing details.

40

TCHCLK

O

7 of 60

DS2153Q

2.1 DS2153Q Register Map

ADDRESS R/W

REGISTER NAME

ADDRESS R/W

REGISTER NAME

00

01

02

03

04

05

06

07

08

10

11

12

13

14

15

16

17

18

19

1A

1B

1E

1F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

R

BPV or Code Violation Count 1

BPV or Code Violation Count 2

CRC4 Count 1/FAS Error Count 1

CRC4 Error Count 2

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

R/W Transmit Align Frame

R/W Transmit Non-Align Frame

R/W Transmit Channel Blocking 1

R/W Transmit Channel Blocking 2

R/W Transmit Channel Blocking 3

R/W Transmit Channel Blocking 4

R/W Transmit Idle 1

E-Bit Count 1/FAS Error Count 2

E-Bit Count 2

Status 1

Status 2

R/W Transmit Idle 2

R/W Receive Information

R/W Receive Control 1

R/W Receive Control 2

R/W Transmit Control 1

R/W Transmit Control 2

R/W Common Control 1

R/W Test 1

R/W Interrupt Mask 1

R/W Interrupt Mask 2

R/W Line Interface Control

R/W Test 2

R/W Transmit Idle 3

R/W Transmit Idle 4

R/W Transmit Idle Definition

R/W Receive Channel Blocking 1

R/W Receive Channel Blocking 2

R/W Receive Channel Blocking 3

R/W Receive Channel Blocking 4

R

Receive Align Frame

Receive Signaling 1

Receive Signaling 2

Receive Signaling 3

Receive Signaling 4

Receive Signaling 5

Receive Signaling 6

Receive Signaling 7

Receive Signaling 8

Receive Signaling 9

Receive Signaling 10

Receive Signaling 11

Receive Signaling 12

Receive Signaling 13

Receive Signaling 14

Receive Signaling 15

Receive Signaling 16

R/W Common Control 2

R/W Common Control 3

R

Synchronizer Status

Receive Non-Align Frame

R/W Transmit Signaling 1

R/W Transmit Signaling 2

R/W Transmit Signaling 3

R/W Transmit Signaling 4

R/W Transmit Signaling 5

R/W Transmit Signaling 6

R/W Transmit Signaling 7

R/W Transmit Signaling 8

R/W Transmit Signaling 9

R/W Transmit Signaling 10

R/W Transmit Signaling 11

R/W Transmit Signaling 12

R/W Transmit Signaling 13

R/W Transmit Signaling 14

R/W Transmit Signaling 15

R/W Transmit Signaling 16

Note: Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all 0s) on power-up initialization to ensure

proper operation.

8 of 60

DS2153Q

3 PARALLEL PORT

The DS2153Q is controlled via a multiplexed bidirectional address/data bus by an external

microcontroller or microprocessor. The DS2153Q can operate with either Intel or Motorola bus timing

configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will

be selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in Section 14

for more details. The multiplexed bus on the DS2153Q saves pins because the address information and

data information share the same signal paths. The addresses are presented to the pins in the first portion of

the bus cycle and data will be transferred on the pins during second portion of the bus cycle. Addresses

must be valid prior to the falling edge of ALE (AS), at which time the DS2153Q latches the address from

the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS

or WR pulses. In a read cycle, the DS2153Q outputs a byte of data during the latter portion of the DS or

RD pulses. The read cycle is terminated and the bus returns to a high-impedance state as RD transitions

high in Intel timing or as DS transitions low in Motorola timing.

9 of 60

DS2153Q

4 CONTROL AND TEST REGISTERS

The operation of the DS2153Q is configured via a set of seven registers. Typically, the control registers

are only accessed when the system is first powered up. Once the DS2153Q has been initialized, the

control registers only need to be accessed when there is a change in the system configuration. There are

two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2),

and three Common Control Registers (CCR1, CCR2, and CCR3). Each of the seven registers is described

in this section. The LICR is described in Section 13.

The Test Registers at addresses 15 and 19 hex are used by the factory in testing the DS2153Q. On power-

up, the Test Registers should be set to 00 hex in order for the DS2153Q to operate properly.

RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10B Hex)

(MSB)

(LSB)

RSMF

RSM

RSIO

—

FRC

SYNCE

RESYNC

SYMBOL

POSITION NAME AND DESCRIPTION

RSMF

RCR1.7

RSYNC Multiframe Function. Only used if the RSYNC pin is

programmed in the multiframe mode (RCR1.6 = 1).

0 = RSYNC outputs CAS multiframe boundaries

1 = RSYNC outputs CRC4 multiframe boundaries

RSM

RSIO

RCR1.6

RCR1.5

RSYNC Mode Select.

0 = frame mode (see the timing in Section 14)

1 = multiframe mode (see the timing in Section 14)

RSYNC I/O Select.

0 = RSYNC is an output (depends on RCR1.6)

1 = RSYNC is an input (only valid if elastic store enabled) (Note:

this bit must be set to 0 when RCR2.1 = 0)

—

FRC

RCR1.4

RCR1.3

RCR1.2

Not Assigned. Should be set to 0 when written.

Frame Resync Criteria.

0 = resync if FAS received in error 3 consecutive times

1 = resync if FAS or bit 2 of non-FAS is received in error 3

consecutive times

SYNCE

RCR1.1

RCR1.0

Sync Enable.

0 = auto resync enabled

1 = auto resync disabled

RESYNC

Resync. When toggled from low to high, a resync is initiated. Must

be cleared and set again for a subsequent resync.

10 of 60

DS2153Q

Table 4-1. Sync/Resync Criteria

FRAME OR

MULTIFRAME

LEVEL

SYNC CRITERIA

RESYNC CRITERIA

ITU SPEC

FAS present in frames N

and N + 2, and FAS not

present in frame N + 1.

Three consecutive incorrect FAS received.

G.706

4.1.1

4.1.2

Alternate (RCR1.2 = 1) the above criteria

is met or three consecutive incorrect bit 2

of non-FAS received.

FAS

Two valid MF alignment

words found within 8ms.

915 or more CRC4 codewords out of 1000

G.706

4.2

4.3.2

received in error.

CRC4

CAS

Valid MF alignment word

Two consecutive MF alignment words

G.732

5.2

found and previous time slot received in error.

16 contains code other than

all 0s.

RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)

(MSB)

(LSB)

Sa8S

Sa7S

Sa6S

POSITION

RCR2.7

Sa5S

Sa4S

RSCLKM

RESE

—

SYMBOL

Sa8S

NAME AND DESCRIPTION

Sa8 Bit Select. Set to 1 to report the Sa8 bit at the RLINK pin;

set to 0 to not report the Sa8 bit.

Sa7S

Sa6S

RCR2.6

RCR2.5

RCR2.4

RCR2.3

RCR2.2

Sa7 Bit Select. Set to 1to report the Sa7 bit at the RLINK pin;

set to 0 to not report the Sa7 bit.

Sa6 Bit Select. Set to 1 to report the Sa6 bit at the RLINK pin;

set to 0 to not report the Sa6 bit.

Sa5S

Sa5 Bit Select. Set to 1 to report the Sa5 bit at the RLINK pin;

set to 0 to not report the Sa5 bit.

Sa4S

Sa4 Bit Select. Set to 1 to report the Sa4 bit at the RLINK pin;

set to 0 to not report the Sa4 bit.

RSCLKM

Receive Side SYSCLK Mode Select.

0 = if SYSCLK is 1.544MHz

1 = if SYSCLK is 2.048MHz

RESE

—

RCR2.1

RCR2.0

Receive Side Elastic Store Enable.

0=elastic store is bypassed

1=elastic store is enabled

Not Assigned. Should be set to 0 when written.

11 of 60

DS2153Q

TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex)

(MSB)

(LSB)

—

TFPT

T16S

TUA1

TSiS

TSA1

TSM

TSIO

SYMBOL

—

POSITION

NAME AND DESCRIPTION

TCR1.7

TCR1.6

Not Assigned. Should be set to 0 when written to.

TFPT

Transmit Time Slot 0 Pass Through.

0 = FAS bits/Sa bits/Remote Alarm sourced internally from the

TAF and TNAF registers

1 = FAS bits/Sa bits/Remote Alarm sourced from TSER

T16S

TUA1

TSiS

TCR1.5

TCR1.4

TCR1.3

Transmit Time Slot 16 Data Select.

0 = sample time slot 16 at TSER pin

1 = source time slot 16 from TS1 to TS16 registers

Transmit Unframed All Ones.

0 = transmit data normally

1 = transmit an unframed all ones code at TPOS and TNEG

Transmit International Bit Select.

0 = sample Si bits at TSER pin

1 = source Si bits from TAF and TNAF registers (in this mode,

TCR1.6 must be set to 0)

TSA1

TSM

TSIO

TCR1.2

TCR1.1

TCR1.0

Transmit Signaling All Ones.

0 = normal operation

1 = force time slot 16 in every frame to all ones

TSYNC Mode Select.

0 = frame mode (see the timing in Section 14)

1 = CAS and CRC4 multiframe mode (see the timing in Section 14)

TSYNC I/O Select.

0 = TSYNC is an input

1 = TSYNC is an output

Note: For details about how the Transmit Control Registers affect the operation of the DS2153Q, see

Figure 14-9.

12 of 60

DS2153Q

TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex)

(MSB)

(LSB)

Sa8S

Sa7S

Sa6S

Sa5S

Sa4S

—

AEBE

P16F

SYMBOL

POSITION NAME AND DESCRIPTION

Sa8S

Sa7S

Sa6S

Sa5S

Sa4S

TCR2.7

TCR2.6

TCR2.5

TCR2.4

TCR2.3

Sa8 Bit Select. Set to 1 to source the Sa8 bit from the TLINK

pin; set to 0 to not source the Sa8 bit.

Sa7 Bit Select. Set to 1 to source the Sa7 bit from the TLINK

pin; set to 0 to not source the Sa7 bit.

Sa6 Bit Select. Set to 1 to source the Sa6 bit from the TLINK

pin; set to 0 to not source the Sa6 bit.

Sa5 Bit Select. Set to 1 to source the Sa5 bit from the TLINK

pin; set to 0 to not source the Sa5 bit.

Sa4 Bit Select. Set to 1 to source the Sa4 bit from the TLINK

pin; set to 0 to not source the Sa4 bit.

—

TCR2.2

TCR2.1

Not Assigned. Should be set to 0 when written.

AEBE

Automatic E-Bit Enable.

0 = E-bits not automatically set in the transmit direction

1 = E-bits automatically set in the transmit direction

P16F

TCR2.0

Function of Pin 16.

0 = Receive Loss of Sync (RLOS)

1 = Loss of Transmit Clock (LOTC)

13 of 60

DS2153Q

CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex)

(MSB)

(LSB)

RCRC4

FLB

THDB3

TG802

TCRC4

RSM

RHDB3

RG802

SYMBOL

FLB

POSITION

NAME AND DESCRIPTION

CCR1.7

Framer Loopback.

0 = loopback disabled

1 = loopback enabled

THDB3

TG802

TCRC4

RSM

CCR1.6

CCR1.5

CCR1.4

CCR1.3

CCR1.2

CCR1.1

CCR1.0

Transmit HDB3 Enable.

0 = HDB3 disabled

1 = HDB3 enabled

Transmit G.802 Enable. See Figure 14-7 for details.

0 = do not force TCHBLK high during bit 1 of time slot 26

1 = force TCHBLK high during bit 1 of time slot 26

Transmit CRC4 Enable.

0 = CRC4 disabled

1 = CRC4 enabled

Receive Signaling Mode Select.

0 = CAS signaling mode

1 = CCS signaling mode

RHDB3

RG802

RCRC4

Receive HDB3 Enable.

0 = HDB3 disabled

1 = HDB3 enabled

Receive G.802 Enable. See Figure 14-7 for details.

0 = do not force RCHBLK high during bit 1 of time slot 26

1 = force RCHBLK high during bit 1 of time slot 26

Receive CRC4 Enable.

0 = CRC4 disabled

1 = CRC4 enabled

14 of 60

DS2153Q

CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex)

(MSB)

(LSB)

ECUS

VCRFS

AAIS

ARA

RSERC

LOTCMC

RLB

LLB

SYMBOL

ECUS

POSITION

NAME AND DESCRIPTION

CCR2.7

Error Counter Update Select.

0 = update error counters once a second

1 = update error counters every 62.5ms (500 frames)

VCRFS

AAIS

CCR2.6

CCR2.5

CCR2.4

CCR2.3

CCR2.2

VCR Function Select.

0 = count Bipolar Violations (BPVs)

1 = count Code Violations (CVs)

Automatic AIS Generation.

0 = disabled

1 = enabled

ARA

Automatic Remote Alarm Generation.

0 = disabled

1 = enabled

RSERC

LOTCMC

RSER Control.

0 = allow RSER to output data as received under all conditions

1 = force RSER to 1 under loss of frame alignment conditions

Loss of Transmit Clock Mux Control. Determines whether the

transmit side formatter should switch to the ever present RCLK

if the TCLK should fail to transition (see Figure 1-1).

0 = do not switch to RCLK if TCLK stops

1 = switch to RCLK if TCLK stops

RLB

LLB

CCR2.1

CCR2.0

Remote Loopback.

0 = loopback disabled

1 = loopback enabled

Local Loopback.

0 = loopback disabled

1 = loopback enabled

15 of 60

DS2153Q

CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)

(MSB)

(LSB)

TESE

TCBFS

TIRFS

ESR

LIRST

—

TSCLKM

—

SYMBOL

POSITION NAME AND DESCRIPTION

TESE

CCR3.7

CCR3.6

Transmit Elastic Store Enable.

0 = elastic store is disabled

1 = elastic store is enabled

TCBFS

Transmit Channel Blocking Registers (TCBR) Function

Select.

0 = TCBRs define the operation of the TCHBLK output pin

1 = TCBRs define which signaling bits are to be inserted

TIRFS

ESR

CCR3.5

CCR3.4

Transmit Idle Registers (TIR) Function Select.

0 = TIRs define in which channels to insert idle code

1 = TIRs define in which channels to insert data from RSER

Elastic Stores Reset. Setting this bit from a 1 to a 0 will force

the elastic stores to a known depth. Should be toggled after

SYSCLK has been applied and is stable. Must be set and cleared

again for a subsequent reset. Do not leave this bit set high.

LIRST

CCR3.3

Line Interface Reset. Setting this bit from a 0 to a 1 will initiate

an internal reset that affects the slicer, AGC, clock recovery state

machine, and jitter attenuator. Normally this bit is only toggled

on power-up. Must be cleared and set again for a subsequent

reset.

—

CCR3.2

CCR3.1

Not Assigned. Should be set to 0 when written.

TSCLKM

Transmit Backplane Clock Select. Must be set like RCR2.2.

0 = 1.544MHz

1 = 2.048MHz

—

CCR3.0

Not Assigned. Should be set to 0 when written.

16 of 60

DS2153Q

4.1 Local Loopback

When CCR2.0 is set to a 1, the DS2153Q will be forced into Local Loopback (LLB). In this loopback,

data will continue to be transmitted as normal through the transmit side of the SCT. Data being received

at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass

through the jitter attenuator. See Figure 1-1 for more details.

4.2 Remote Loopback

When CCR2.1 is set to a 1, the DS2153Q will be forced into Remote Loopback (RLB). In this loopback,

data recovered off the E1 line from the RTIP and RRING pins will be transmitted back onto the E1 line

(with any BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to

pass through the receive side of the DS2153Q as it would normally and the data at the TSER input will be

ignored. Data in this loopback will pass through the jitter attenuator. See Figure 1-1 for more details.

4.3 Framer Loopback

When CCR1.7 is set to a 1, the DS2153Q will enter a Framer Loopback (FLB) mode. This loopback is

useful in testing and debugging applications. In FLB, the DS2153Q will loop data from the transmit side

back to the receive side. When FLB is enabled, the following will occur:

1) Data will be transmitted at TTIP and TRING.

2) Data off the E1 line at RTIP and RRING will be ignored.

The RCLK output will be replaced with the TCLK input.

4.4 Automatic Alarm Generation

When either CCR2.4 or CCR2.5 is set to 1, the DS2153Q monitors the receive side to determine if any of

the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) reception,

or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the

DS2153Q will either force an AIS alarm (if CCR2.5 = 1) or a Remote Alarm (CCR2.4 = 1) to be

transmitted via the TTIP and TRING pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to 1

at the same time.

4.5 Power-Up Sequence

On power-up, after the supplies are stable, the DS2153Q should be configured for operation by writing to

all of the internal registers (this includes setting the Test Register) since the contents of the internal

registers cannot be predicted on power-up. Next, the LIRST bit should be toggled from 0 to 1 to reset the

line interface circuitry (it will take the DS2153Q about 40ms to recover from the LIRST being toggled).

Finally, after the SYSCLK input is stable, the ESR bit should be toggled from a 0 to a 1 and back to 0

(this step can be skipped if the elastic stores are disabled).

17 of 60

DS2153Q

5 STATUS AND INFORMATION REGISTERS

There is a set of four registers that contain information on the current real-time status of the DS2153Q:

Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer

Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one

of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion

(except for the SSR). This means that if an event occurs and a bit is set to a 1 in any of the registers, it

will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set

again until the event has occurred again or if the alarm is still present.

The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to

the register will inform the DS2153Q which bits the user wishes to read and have cleared. The user will

write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in

the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit

location, the read register will be updated with current value and it will be cleared. When a 0 is written to

a bit position, the read register will not be updated and the previous value will be held. A write to the

status and information registers will be immediately followed by a read of the same register. The read

result should be logically ANDed with the mask byte that was just written and this value should be

written back into the same register to insure that bit does indeed clear. This second write step is necessary

because the alarms and events in the status registers occur asynchronously in respect to their access via

the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to

individually poll certain bits without disturbing the other bits in the register. This operation is key in

controlling the DS2153Q with higher-order software languages.

The SSR register operates differently than the other three. It is a read-only register and it reports the status

of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of

this register with a write.

The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2

pins, respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked

from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2),

respectively.

18 of 60

DS2153Q

RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex)

(MSB)

(LSB)

TESF

TESE

JALT

RESF

RESE

CRCRC

FASRC

CASRC

SYMBOL

POSITION NAME AND DESCRIPTION

TESF

TESE

JALT

RIR.7

RIR.6

RIR.5

Transmit Elastic Store Full. Set when the elastic store fills and

a frame is deleted.

Transmit Elastic Store Empty. Set when the elastic store

empties and a frame is repeated.

Jitter Attenuator Limit Trip. Set when the jitter attenuator

FIFO reaches to within 4 bits of its limit; useful for debugging

jitter attenuation operation.

RESF

RESE

RIR.4

RIR.3

RIR.2

RIR.1

RIR.0

Elastic Store Full. Set when the elastic store buffer fills and a

frame is deleted.

Elastic Store Empty. Set when the elastic store buffer empties

and a frame is repeated.

CRCRC

FASRC

CASRC

CRC Resync Criteria Met. Set when 915/1000 codewords are

received in error.

FAS Resync Criteria Met. Set when three consecutive FAS

words are received in error.

CAS Resync Criteria Met. Set when two consecutive CAS MF

alignment words are received in error.

19 of 60

DS2153Q

SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex)

(MSB)

(LSB)

CSC5

CSC4

CSC3

POSITION

SSR.7

CSC2

CSC0

FASSA

CASSA

CRC4SA

SYMBOL

CSC5

NAME AND DESCRIPTION

CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.

CRC4 Sync Counter Bit 4.

CSC4

SSR.6

CSC3

SSR.5

CRC4 Sync Counter Bit 3.

CSC2

SSR.4

CRC4 Sync Counter Bit 2.

CSC0

SSR.3

CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next

to LSB bit is not accessible. This bit will toggle each time the

CRC4 MF search times out at 8ms.

FASSA

CASSA

CRC4SA

SSR.2

SSR.1

SSR.0

FAS Sync Active. Set while the synchronizer is searching for

alignment at the FAS level.

CAS MF Sync Active. Set while the synchronizer is searching

for the CAS MF alignment word.

CRC4 MF Sync Active. Set while the synchronizer is searching

for the CRC4 MF alignment word.

5.1 CRC4 Sync Counter

The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out. The counter is

cleared when the DS2153Q has successfully obtained synchronization at the CRC4 level. The counter can

also be cleared by disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the

amount of time the DS2153Q has been searching for synchronization at the CRC4 level. Annex B of

CCITT G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then

the search should be abandoned and proper action taken. The CRC4 sync counter will rollover.

20 of 60

DS2153Q

SR1: STATUS REGISTER 1 (Address = 06 Hex)

(MSB)

(LSB)

RSA1

RDMA

RSA0

RSLIP

RUA1

RRA

RCL

RLOS

SYMBOL

RSA1

POSITION

NAME AND DESCRIPTION

SR1.7

SR1.6

Receive Signaling All 1s. Set when the contents of time slot 16

contains less than three 0s over 16 consecutive frames. This alarm

is not disabled in the CCS signaling mode.

RDMA

Receive Distant MF Alarm. Set when bit 6 of time slot 16 in

frame 0 has been set for two consecutive multiframes. This alarm

is not disabled in the CCS signaling mode.

RSA0

RSLIP

RUA1

RRA

SR1.5

SR1.4

SR1.3

SR1.2

SR1.1

SR1.0

Receive Signaling All 0s. Set when over a full MF, time slot 16

contains all 0s.

Receive Elastic Store Slip Occurrence. Set when the elastic store

has either repeated or deleted a frame of data.

Receive Unframed All 1s. Set when an unframed all 1s code is

received at RTIP and RRING.

Receive Remote Alarm. Set when a remote alarm is received at

RTIP and RRING.

RCL

Receive Carrier Loss. Set when 255 consecutive 0s have been

detected at RTIP and RRING.

RLOS

Receive Loss of Sync. Set when the device is not synchronized to

the receive E1 stream.

21 of 60

DS2153Q

Table 5-1. Alarm Set and Clear Criteria

CCITT

SPEC.

ALARM

RSA1

SET CRITERIA

CLEAR CRITERIA

Over 16 consecutive frames (one full Over 16 consecutive frames (one full

G.732

4.2

MF) time slot 16 contains less than

three 0s

MF) time slot 16 contains three or more

0s

(receive signaling

all 1s)

RSA0

Over 16 consecutive frames (one full Over 16 consecutive frames (one full

G.732

5.2

MF) time slot 16 contains all 0s

MF) time slot 16 contains at least a

single 1

(receive signaling

all 0s)

RDMA

Bit 6 in time slot 16 of frame 0 set to Bit 6 in time slot 16 of frame 0 set to 0

O.162

2.1.5

1 for two consecutive MF

for a two consecutive MF

(receive distant

multiframe alarm)

RUA1

Less than three 0s in two frames

(512 bits)

More than two 0s in two frames (512

bits)

O.162

1.6.1.2

(receive unframed

all 1s)

RRA

Bit 3 of non-align frame set to 1 for

three consecutive occasions

Bit 3 of non-align frame set to 0 for

three consecutive occasions

O.162

2.1.4

(receive remote

alarm)

RCL

255 consecutive 0s received

In 255-bit times, at least 32 1s are

received

G.775

(receive carrier

loss)

22 of 60

DS2153Q

SR2: STATUS REGISTER 2 (Address = 07 Hex)

(MSB)

(LSB)

RMF

RAF

TMF

SEC

TAF

LOTC

RCMF

TSLIP

SYMBOL

RMF

POSITION NAME AND DESCRIPTION

SR2.7

SR2.6

SR2.5

SR2.4

SR2.3

SR2.2

SR2.1

SR2.0

Receive CAS Multiframe. Set every 2ms (regardless if CAS

signaling is enabled or not) on receive multiframe boundaries. Used

to alert the host that signaling data is available.

RAF

TMF

Receive Align Frame. Set every 250ms at the beginning of align

frames. Used to alert the host that Si and Sa bits are available in the

RAF and RNAF registers.

Transmit Multiframe. Set every 2µs (regardless if CRC4 is

enabled) on transmit multiframe boundaries. Used to alert the host

that signaling data needs to be updated.

SEC

1-Second Timer. Set on increments of 1 second based on RCLK. If

CCR2.7 = 1, then this bit will be set every 62.5ms instead of once a

second.

TAF

Transmit Align Frame. Set every 250µs at the beginning of align

frames. Used to alert the host that the TAF and TNAF registers

need to be updated.

LOTC

RCMF

TSLIP

Loss of Transmit Clock. Set when the TCLK pin has not

transitioned for one channel time (or 3.9µs). Will force pin 16 high

if enabled via TCR2.0. Based on RCLK.

Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries;

will continue to be set every 2ms on an arbitrary boundary if CRC4

is disabled.

Transmit Elastic Store Slip. Set when the elastic store has either

repeated or deleted a frame of data.

23 of 60

DS2153Q

IMR1: INTERRUPT MASK REGISTER1 (Address = 16 Hex)

(MSB)

(LSB)

RSA1

RDMA

RSA0

RSLIP

RUA1

RRA

RCL

RLOS

SYMBOL

RSA1

POSITION NAME AND DESCRIPTION

IMR1.7

IMR1.6

IMR1.5

IMR1.4

IMR1.3

IMR1.2

IMR1.1

IMR1.0

Receive Signaling All 1s.

0 = interrupt masked

1 = interrupt enabled

RDMA

RSA0

RSLIP

RUA1

RRA

Receive Distant MF Alarm.

0 = interrupt masked

1 = interrupt enabled

Receive Signaling All 0s.

0 = interrupt masked

1 = interrupt enabled

Receive Elastic Store Slip Occurrence.

0 = interrupt masked

1 = interrupt enabled

Receive Unframed All 1s.

0 = interrupt masked

1 = interrupt enabled

Receive Remote Alarm.

0 = interrupt masked

1 = interrupt enabled

RCL

Receive Carrier Loss.

0 = interrupt masked

1 = interrupt enabled

RLOS

Receive Loss of Sync.

0 = interrupt masked

1 = interrupt enabled

24 of 60

DS2153Q

IMR2: INTERRUPT MASK REGISTER 2 (Address = 17 Hex)

(MSB)

(LSB)

RMF

SYMBOL

RMF

RAF

TMF

SEC

TAF

LOTC

RCMF

TSLIP

POSITION NAME AND DESCRIPTION

IMR2.7

IMR2.6

IMR2.5

IMR2.4

IMR2.3

IMR2.2

IMR2.1

IMR2.0

Receive CAS Multiframe.

0 = interrupt masked

1 = interrupt enabled

RAF

TMF

Receive Align Frame.

0 = interrupt masked

1 = interrupt enabled

Transmit Multiframe.

0 = interrupt masked

1 = interrupt enabled

SEC

1-Second Timer.

0 = interrupt masked

1 = interrupt enabled

TAF

Transmit Align Frame.

0 = interrupt masked

1 = interrupt enabled

LOTC

RCMF

TSLIP

Loss Of Transmit Clock.

0 = interrupt masked

1 = interrupt enabled

Receive CRC4 Multiframe.

0 = interrupt masked

1 = interrupt enabled

Transmit Side Elastic Store Slip.

0 = interrupt masked

1 = interrupt enabled

25 of 60

DS2153Q

6 ERROR COUNT REGISTERS

There are a set of four counters in the DS2153Q that record bipolar or code violations, errors in the CRC4

SMF codewords, E bits as reported by the far end, and word errors in the FAS. Each of these four

counters are automatically updated on either 1-second boundaries (CCR2.7 = 0) or every 62.5ms

(CCR2.7 = 1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain

performance data from either the previous second or the previous 62.5ms. The user can use the interrupt

from the timer to determine when to read these registers. The user has a full second (or 62.5ms) to read

the counters before the data is lost.

6.1 BPV or Code Violation Counter

Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of

a 16-bit counter that records either Bipolar Violations (BPVs) or Code Violations (CVs). If CCR2.6 = 0,

then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same

polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 codewords

are not counted as BPVs. If CCR2.6 = 1, then the VCR counts code violations as defined in CCITT

O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most

applications, the DS2153Q should be programmed to count BPVs when receiving AMI code and to count

CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync

conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would

have to be greater than 10**-2 before the VCR would saturate.

VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address = 00

Hex)

VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address = 01

Hex)

(MSB)

(LSB)

V15

V14

V6

V13

V5

V12

V4

V11

V3

V10

V2

V9

V1

V8

VCR1

VCR2

V7

V0

SYMBOL

V15

POSITION

VCR1.7

NAME AND DESCRIPTION

MSB of the 16-bit bipolar or code violation count.

LSB of the 16-bit bipolar or code violation count.

V0

VCR2.0

26 of 60

DS2153Q

6.2 CRC4 Error Counter

CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant

word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the

maximum CRC4 count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled

during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync

occurs at the CAS level.

CRCCR1: CRC4 COUNT REGISTER 1 (Address = 02 Hex)

CRCCR2: CRC4 COUNT REGISTER 2 (Address = 03 Hex)

(MSB)

(LSB)

(See note) (See note) (See note) (See note) (See note) (See note)

CRC9

CRC1

CRC8

CRCCR1

CRCCR2

CRC7

CRC6

CRC5

CRC4

CRC3

CRC2

CRC0

SYMBOL

CRC9

POSITION

CRCCR1.1

CRCCR2.0

NAME AND DESCRIPTION

MSB of the 10-bit CRC4 error count.

LSB of the 10-bit CRC4 error count.

CRC0

Note: The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12-bit FAS error counter.

6.3 E-Bit Counter

E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of

a 10-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15

on E1 lines running with CRC4 multiframe. These count registers will increment once each time the

received E-bit is set to 0. Since the maximum E-bit count in a 1-second period is 1000, this counter

cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will

continue to count if loss of multiframe sync occurs at the CAS level.

EBCR1: E-BIT COUNT REGISTER 1 (Address = 04 Hex)

EBCR2: E-BIT COUNT REGISTER 2 (Address = 05 Hex)

(MSB)

(LSB)

(See note) (See note) (See note) (See note) (See note) (See note)

EB9

EB1

EB8

EBCR1

EBCR2

EB7

EB6

EB5

EB4

EB3

EB2

EB0

SYMBOL

EB9

POSITION

EBCR1.1

EBCR2.0

NAME AND DESCRIPTION

MSB of the 10-bit E-bit count.

LSB of the 10-bit E-bit count.

EB0

Note: The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter.

27 of 60

DS2153Q

6.4 FAS Bit Error Counter

FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word

of a 12-bit counter that records word errors in the Frame Alignment Signal in time slot 0. This counter is

disabled during loss of synchronization conditions, (RLOS = 1). Since the maximum FAS word error

count in a 1-second period is 4000, this counter cannot saturate.

FASCR1: FAS BIT COUNT REGISTER 1 (Address = 02 Hex)

FASCR2: FAS BIT COUNT REGISTER 2 (Address = 04 Hex)

(MSB)

(LSB)

FAS11

FAS10

FAS4

FAS9

FAS3

FAS8

FAS2

FAS7

FAS1

FAS6

FAS0

(Note 1) (Note 1) FASCR1

FAS5

(Note 2) (Note 2) FASCR2

SYMBOL

POSITION

FASCR1.7

FASCR2.2

NAME AND DESCRIPTION

FAS11

FAS0

MSB of the 12-bit FAS error count.

LSB of the 12-bit FAS error count.

Note 1: The lower 2 bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 error counter.

Note 2: The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-bit counter.

28 of 60

DS2153Q

7 Sa DATA LINK CONTROL AND OPERATION

The DS2153Q provides for access to the proposed E1 performance monitor data link in the Sa bit

positions. The device allows access to the Sa bits either via a set of two internal registers (RNAF and

TNAF) or via two external pins (RLINK and TLINK).

On the receive side, the Sa bits are always reported in the internal RNAF register (see Section 12 for more

details). All five Sa bits are always output at the RLINK pin. See Section 14 for detailed timing. Via

RCR2, the user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the

user to create a clock that can be used to capture the needed Sa bits.

On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register

(TCR1.6 = 0) or from the external TLINK pin. Via TCR2, the DS2153Q can be programmed to source

any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits through

the DS2153Q without them being altered, then the device should be set up to source all five Sa bits via

the TLINK pin and the TLINK pin should be tied to the TSER pin. See the timing diagrams and the

transmit data flow diagram in Section 14 for examples.

29 of 60

DS2153Q

8 SIGNALING OPERATION

The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the

receive stream and inserted into the transmit stream by the DS2153Q. Each of the 30 channels has four

signaling bits (A/B/C/D) associated with it. The numbers in parentheses are the channel associated with a

particular signaling bit. The channel numbers have been assigned as described in the ITU documents. For

example, channel 1 is associated with time slot 1 and channel 30 is associated with time slot 31. There is

a set of 16 registers for the receive side (RS1 to RS16) and 16 registers on the transmit side (TS1 to

TS16). The signaling registers are detailed below.

RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address = 30 to 3F Hex)

(MSB)

0

(LSB)

X

0

X

Y

X

RS1 (30)

RS2 (31)

RS3 (32)

RS4 (33)

RS5 (34)

RS6 (35)

RS7 (33)

RS8 (37)

RS9 (38)

RS10 (39)

RS11 (3A)

RS12 (3B)

RS13 (3C)

RS14 (3D)

RS15 (3E)

RS16 (3F)

A(1)

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

A(9)

A(10)

A(11)

A(12)

A(13)

A(14)

A(15)

B(1)

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

B(10)

B(11)

B(12)

B(13)

B(14)

B(15)

C(1)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

C(10)

C(11)

C(12)

C(13)

C(14)

C(15)

D(1)

D(2)

D(3)

D(4)

D(5)

D(6)

D(7)

D(8)

D(9)

D(10)

D(11)

D(12)

D(13)

D(14)

D(15)

A(16)

A(17)

A(18)

A(19)

A(20)

A(21)

A(22)

A(23)

A(24)

A(25)

A(26)

A(27)

A(28)

A(29)

A(30)

B(16)

B(17)

B(18)

B(19)

B(20)

B(21)

B(22)

B(23)

B(24)

B(25)

B(26)

B(27)

B(28)

B(29)

B(30)

C(16)

C(17)

C(18)

C(19)

C(20)

C(21)

C(22)

C(23)

C(24)

C(25)

C(26)

C(27)

C(28)

C(29)

C(30)

D(16)

D(17)

D(18)

D(19)

D(20)

D(21)

D(22)

D(23)

D(24)

D(25)

D(26)

D(27)

D(28)

D(29)

D(30)

SYMBOL

POSITION NAME AND DESCRIPTION

X

Y

A(1)

D(30)

RS1.0/1/3

RS1.2

RS2.7

Spare Bits

Remote Alarm Bit (integrated and reported in SR1.6)

Signaling Bit A for Channel 1

Signaling Bit D for Channel 30

RS16.0

Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two time slots. The

bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the

Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the

signaling bits. The user has a full 2ms to retrieve the signaling bits before the data is lost. The RS

registers are updated under all conditions. Their validity should be qualified by checking for

synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract

signaling information. Via the SR2.7 bit, the user will be informed when the signaling registers have been

loaded with data. The user has 2ms to retrieve the data before it is lost.

30 of 60

DS2153Q

TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address = 40 to 4F Hex)

(MSB)

0

A(1)

A(2)

A(3)

A(4)

A(5)

A(6)

A(7)

A(8)

(LSB)

X

D(16)

0

X

Y

X

TS1 (40)

TS2 (41)

TS3 (42)

TS4 (43)

TS5 (44)

TS6 (45)

TS7 (43)

TS8 (47)

TS9 (48)

TS10 (49)

TS11 (4A)

TS12 (4B)

TS13 (4C)

TS14 (4D)

TS15 (43)

TS16 (4F)

B(1)

B(2)

B(3)

B(4)

B(5)

B(6)

B(7)

B(8)

B(9)

B(10)

B(11)

B(12)

B(13)

B(14)

B(15)

C(1)

C(2)

C(3)

C(4)

C(5)

C(6)

C(7)

C(8)

C(9)

C(10)

C(11)

C(12)

C(13)

C(14)

C(15)

D(1)

D(2)

D(3)

D(4)

D(5)

D(6)

D(7)

D(8)

D(9)

D(10)

D(11)

D(12)

D(13)

D(14)

D(15)

A(31)

A(32)

A(33)

A(34)

A(35)

A(36)

A(37)

A(38)

A(39)

A(40)

A(41)

A(42)

A(43)

A(44)

A(45)

B(16)

B(17)

B(18)

B(19)

B(20)

B(21)

B(22)

B(23)

B(24)

B(25)

B(26)

B(27)

B(28)

B(29)

B(30)

C(16)

C(17)

C(18)

C(19)

C(20)

C(21)

C(22)

C(23)

C(24)

C(25)

C(26)

C(27)

C(28)

C(29)

C(30)

D(17)

D(18)

D(19)

D(20)

D(21)

D(22)

D(23)

D(24)

D(25)

D(26)

D(27)

D(28)

D(29)

D(30)

A(9)

A(10)

A(11)

A(12)

A(13)

A(14)

A(15)

SYMBOL

POSITION NAME AND DESCRIPTION

X

Y

TS1.0/1/3

TS1.2

Spare Bits

Remote Alarm Bit

A(1)

D(30)

TS2.7

TS16.0

Signaling Bit A for Channel 1

Signaling Bit D for Channel 30

Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two time slots that will be

inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the

DS2153Q will load the values present in the Transmit Signaling Register into an outgoing signaling shift

register that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2

(SR2.5) to know when to update the signaling bits. The bit will be set every 2ms and the user has 2ms to

update the TSRs before the old data will be retransmitted.

The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble.

The upper nibble must always be set to 0000, or else the terminal at the far end will lose multiframe

synchronization. If the user wishes to transmit a multiframe alarm to the far end, then the TS1.2 bit

should be set to a 1. If no alarm is to be transmitted, then the TS1.2 bit should be cleared. The three

remaining bits in TS1 are the spare bits. If they are not used, they should be set to 1. In CCS signaling

mode, TS1 to TS16 can also be used to insert signaling information. Via the SR2.5 bit, the user will be

informed when the signaling registers need to be loaded with data. The user has 2ms to load the data

before the old data will be retransmitted. Via the CCR3.6 bit, the user has the option to use the Transmit

Channel Blocking Registers (TCBRs) to determine on a channel by channel basis which signaling bits are

to be inserted via the TSRs (the corresponding bit in the TCBRs = 1) and which are to be sourced from

the TSER pin (the corresponding bit in the TCBRs = 0). See the Transmit Data Flow diagram in

Section 14 for more details.

31 of 60

DS2153Q

9 TRANSMIT IDLE REGISTERS

There is a set of five registers in the DS2153Q that can be used to custom tailor the data that is to be

transmitted onto the E1 line, on a channel-by-channel basis. Each of the 32 E1 channels can be forced to

have a user-defined idle code inserted into them.

TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address = 26 to 29 Hex)

(MSB)

(LSB)

CH8

CH7

CH15

CH23

CH31

CH6

CH14

CH22

CH30

CH5

CH13

CH21

CH29

CH4

CH12

CH20

CH28

CH3

CH11

CH19

CH27

CH2

CH10

CH18

CH26

CH1

TIR1 (26)

TIR2 (27)

TIR3 (28)

TIR4 (29)

CH16

CH24

CH32

CH9

CH17

CH25

SYMBOL

POSITION NAME AND DESCRIPTION

CH32

TIR4.7

Transmit Idle Registers.

0 = do not insert the Idle Code into this channel

1 = insert the Idle Code into this channel

CH1

TIR1.0

Note: If CCR3.5 = 1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies that channel data is to be

sourced from the RSER pin.

TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex)

(MSB)

(LSB)

TIDR7

TIDR6

SYMBOL

TIDR5

TIDR4

TIDR3

TIDR2

TIDR1

TIDR0

POSITION NAME AND DESCRIPTION

MSB of the Idle Code

LSB of the Idle Code

TIDR7

TIDR0

TIDR.7

TIDR.0

Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represents a time slot in

the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code

contained in the Transmit Idle Definition Register (TIDR). In the TIDR, the MSB is transmitted first. Via

the CCR3.5 bit, the user has the option to use the TIRs to determine on a channel-by-channel basis, if data

from the RSER pin should be substituted for data from the TSER pin. In this mode, if the corresponding

bit in the TIRs is set to 1, then data will be sourced from the RSER pin. If the corresponding bit in the

TIRs is set to 0, then data for that channel will sourced from the TSER pin. See the Transmit Data Flow

diagram in Section 14 for more details.

32 of 60

DS2153Q

10 CLOCK BLOCKING REGISTERS

The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel

Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins,

respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either

high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD

controller in ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and

TCHCLK pins will be held high during the entire corresponding channel time. See the timing diagrams in

Section 14 for an example. The TCBRs have an alternate mode of use. Via the CCR3.6 bit, the user has

the option to use the TCBRs to determine on a channel by channel basis, which signaling bits are to be

inserted via the TSRs (the corresponding bit in the TCBRs = 1) and which are to be sourced from the

TSER pin (the corresponding bit in the TCBR = 0). See the Transmit Data Flow diagram in Section 14

for more details.

RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING

REGISTERS (Address = 2B to 2E Hex)

(MSB)

CH8

CH16

CH24

CH32

(LSB)

CH1

CH7

CH15

CH23

CH31

CH6

CH14

CH22

CH30

CH5

CH13

CH21

CH29

CH4

CH12

CH20

CH28

CH3

CH11

CH19

CH27

CH2

CH10

CH18

CH26

RCBR1 (2B)

RCBR2 (2C)

RCBR3 (2D)

RCBR4 (2E)

CH9

CH17

CH25

SYMBOL

POSITION

NAME AND DESCRIPTION

Receive Channel Blocking Registers.

0 = force the RCHBLK pin to remain low during this

channel time

CH32

CH1

RCBR4.7

RCBR1.0

1 = force the RCHBLK pin high during this channel time

TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING

REGISTERS (Address = 22 to 25 Hex)

(MSB)

CH8

CH16

CH24

CH32

(LSB)

CH1

CH7

CH15

CH23

CH31

CH6

CH14

CH22

CH30

CH5

CH13

CH21

CH29

CH4

CH12

CH20

CH28

CH3

CH11

CH19

CH27

CH2

CH10

CH18

CH26

TCBR1 (22)

TCBR2 (23)

TCBR3 (24)

TCBR4 (25)

CH9

CH17

CH25

SYMBOL

POSITION

NAME AND DESCRIPTION

Transmit Channel Blocking Registers.

0 = force the TCHBLK pin to remain low during this

channel time

CH32

TCBR4.7

1 = force the TCHBLK pin high during this channel time

CH1

TCBR1.0

Note: If CCR3.6 = 1, then a 0 in the TCBRs implies that signaling data is to be sourced from TSER and a 1 implies that signaling data for

that channel is to be sourced from the Transmit Signaling (TS) registers.

33 of 60

DS2153Q

TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1

(MSB)

(LSB)

CH20

CH4

CH8

CH12

CH16

CH19

CH23

CH27

CH31

CH3

CH7

CH11

CH15

CH18

CH22

CH26

CH30

CH2

CH6

CH10

CH14

CH17*

CH21

CH25

CH29

CH1*

CH5

TCBR1

CH24

CH28

CH32

TCBR2

TCBR3

TCBR4

CH9

CH13

*CH1 and CH17 should be set to 1 to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote

Alarm bits.

34 of 60

DS2153Q

11 ELASTIC STORES OPERATION

The DS2153Q has an on-board two-frame (512 bits) elastic store. This elastic store can be enabled via

RCR2.1. If the elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544MHz

(RCR2.2 = 0) or 2.048MHz (RCR2.2 = 1) clock at the SYSCLK pin. If the elastic store is enabled, then

the user has the option of either providing a frame sync at the RSYNC pin (RCR1.5 = 1) or having the

RSYNC pin provide a pulse on frame or multiframe boundaries (RCR1.5 = 0). If the user wishes to

obtain pulses at the frame boundary, then RCR1.6 must be set to 0, and if the user wishes to have pulses

occur at the multiframe boundary, then RCR1.6 must be set to 1. If the user selects to apply a 1.544MHz

clock to the SYSCLK pin, then every fourth channel will be deleted and the F-bit position inserted

(forced to 1). Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) will

be deleted. Also, in 1.544MHz applications, the RCHBLK output will not be active in channels 25

through 32 (or in other words, RCBR4 is not active). See Section 14 for more details. If the 512-bit

elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of

data (256 bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to 1. If the buffer fills,

then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to 1.

35 of 60

DS2153Q

12 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION

The DS2153Q provides for access to both the Additional (Sa) and International (Si) bits. On the receive

side, the RAF and RNAF registers will always report the data as it received in the Additional and

International bit locations. The RAF and RNAF registers are updated with the setting of the Receive

Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the

RAF and RNAF registers. It has 250µs to retrieve the data before it is lost.

On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit

Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the

TAF and TNAF registers. It has 250µs to update the data or else the old data will be retransmitted. Data

in the Si bit position will be overwritten if either the DS2153Q is programmed: (1) to source the Si bits

from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa

bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to 1. See the register

descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram in Section 14 for more details.

RAF: RECEIVE ALIGN FRAME REGISTER (Address = 2F Hex)

(MSB)

(LSB)

Si

0

POSITION

RAF.7

1

0

1

SYMBOL

NAME AND DESCRIPTION

International Bit.

Si

0

1

0

1

RAF.6

Frame Alignment Signal Bit.

RAF.5

RAF.4

RAF.3

RAF.2

RAF.1

RAF.0

36 of 60

DS2153Q

RNAF: RECEIVE NON-ALIGN FRAME REGISTER (Address = 1F Hex)

(MSB)

(LSB)

Si

SYMBOL

Si

1

A

POSITION

RNAF.7

RNAF.6

RNAF.5

RNAF.4

RNAF.3

RNAF.2

RNAF.1

RNAF.0

Sa4

Sa5

Sa6

Sa7

Sa8

NAME AND DESCRIPTION

International Bit.

1

Frame Non-Alignment Signal Bit.

Remote Alarm.

A

Sa4

Sa5

Sa6

Sa7

Sa8

Additional Bit 4.

Additional Bit 5.

Additional Bit 6.

Additional Bit 7.

Additional Bit 8.

TAF: TRANSMIT ALIGN FRAME REGISTER (Address = 20 Hex)

(MSB)

(LSB)

Si

0

POSITION

TAF.7

1

0

1

SYMBOL

NAME AND DESCRIPTION

International Bit.

Si

0

1

0

1

TAF.6

Frame Alignment Signal Bit.

TAF.5

TAF.4

TAF.3

TAF.2

TAF.1

TAF.0

37 of 60

DS2153Q

TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address = 21 Hex)

(MSB)

(LSB)

Si

1

A

POSITION

TNAF.7

TNAF.6

TNAF.5

TNAF.4

TNAF.3

TNAF.2

TNAF.1

TNAF.0

Sa4

Sa5

Sa6

Sa7

Sa8

SYMBOL

NAME AND DESCRIPTION

International Bit.

Si

1

Frame Non-Alignment Signal Bit.

Remote Alarm.

A

Sa4

Sa5

Sa6

Sa7

Sa8

Additional Bit 4.

Additional Bit 5.

Additional Bit 6.

Additional Bit 7.

Additional Bit 8.

38 of 60

DS2153Q

13 LINE INTERFACE FUNCTIONS

The line interface function in the DS2153Q contains three sections: the receiver, which handles clock and

data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of

these three sections is controlled by the Line Interface Control Register (LICR), which is described

below.

LICR: LINE INTERFACE CONTROL REGISTER (Address = 18 Hex)

(MSB)

(LSB)

LB2

LB1

LB0

EGL

JAS

JABDS

DJA

TPD

LICR

SYMBOL POSITION NAME AND DESCRIPTION

LB2

LB1

LB0

EGL

LICR.7

LICR.6

LICR.5

LICR.4

Line Build-Out Select Bit 2. Sets the transmitter build

out; see the Table 13-2.

Line Build-Out Select Bit 1. Sets the transmitter build

out; see the Table 13-2.

Line Build-Out Select Bit 0. Sets the transmitter build

out; see the Table 13-2.

Receive Equalizer Gain Limit.

0 = -12dB

1 = -30dB

JAS

LICR.3

Jitter Attenuator Select.

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

JABDS

DJA

LICR.2

LICR.1

Jitter Attenuator Buffer Depth Select.

0 = 128 bits

1 = 32 bits (use for delay sensitive applications)

Disable Jitter Attenuator.

0 = jitter attenuator enabled

1 = jitter attenuator disabled

TPD

LICR.0

Transmit Power Down.

0 = normal transmitter operation

1 = powers down the transmitter and tri-states the TTIP

and TRING pins

39 of 60

DS2153Q

13.1 Receive Clock and Data Recovery

The DS2153Q contains a digital clock recovery system. See Figure 1-1 and Figure 13-1 for more details.

The DS2153Q couples to the receive E1 twisted pair or coax via a 1:1 transformer. See Table 13-3 for

transformer details. The DS2153Q automatically adjusts to the E1 signal being received at the RTIP and

RRING pins and can handle E1 twisted pair cables of 0.6mm (22 AWG) from 0 to 1.5km in length. The

crystal attached at the XTAL1 and XTAL2 pins is multiplied by 4 via an internal PLL and fed to the

clock recovery system. The clock recovery system uses both edges of the clock from the PLL circuit to

form a 32 times oversampler that is used to recover the clock and data. This oversampling technique

offers outstanding jitter tolerance (see Figure 13-2).

Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI waveform

presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a Receive

Carrier Loss (RCL) condition will occur and the RCLK can be sourced from either the ACLKI pin or

from the crystal attached to the XTAL1 and XTAL2 pins. The DS2153Q will sense the ACLKI pin to

determine if a clock is present. If no clock is applied to the ACLKI pin, then it should be tied to RVSS to

prevent the device from falsely sensing a clock. See Table 13-1. If the jitter attenuator is either placed in

the transmit path or is disabled, the RCLK output can exhibit short high cycles of the clock. This is due to

the highly oversampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path

(as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty

cycle. See the receive AC timing characteristics in Section 16 for more details.

Table 13-1. Source of RCLK Upon RCL

RECEIVE SIDE JITTER

ATTENUATOR

TRANSMIT SIDE JITTER

ATTENUATOR

ACLKI PRESENT?

Yes

No

ACLKI via the jitter attenuator

Centered crystal

ACLKI

TCLK via the jitter attenuator

40 of 60

DS2153Q

13.2 Transmit Waveshaping and Line Driving

The DS2153Q uses a set of laser-trimmed delay lines along with a precision digital-to-analog converter

(DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms created by the

DS2153Q meet the ITU specifications. See Figure 13-3. The user will select which waveform is to be

generated by properly programming the L0 to L2 bits in the Line Interface Control Register (LICR). The

DS2153Q can set up in a number of various configurations depending on the application. See Table 13-2

and Figure 1-1.

Table 13-2. LBO Select in LICR

RETURN LOSS

L2

L1

L0

APPLICATION

75Ω normal

TRANSFORMER

Rt (Ω)

(dB)

N.M.

0

1

1:1.15 step-up

0

120Ω normal

75Ω normal with protection

0

1

0

1

1:1.15 step-up

N.M.

8.2

resistors

120Ω normal with protection

resistors

1

0

1

0

1:1.15 step-up

1:1.36 step-up

21

27

18

27

75Ω with high return loss

120Ω with high return loss

N.M. = not meaningful

Due to the nature of the design of the transmitter in the DS2153Q, very little jitter (less than 0.005UI_P-P

broadband from 10Hz to 100kHz) is added to the jitter present on TCLK. Also, the waveforms that they

create are independent of the duty cycle of TCLK. The transmitter in the DS2153Q couples to the E1

transmit shielded twisted pair or coax via a 1:1.15 or 1:1.36 step-up transformer as shown in Figure 13-1.

For the devices to create the proper waveforms, the transformer used must meet the specifications listed

in Table 13-3.

Table 13-3. Transformer Specifications

SPECIFICATION

Turns Ratio

Primary Inductance

Leakage Inductance

Intertwining Capacitance

DC Resistance

RECOMMENDED VALUE

1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ±5%

600µH minimum

1.0µH maximum

60pF maximum

1.2Ω maximum

41 of 60

DS2153Q

13.3 Jitter Attenuator

The DS2153Q contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via

the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications

where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.

The characteristics of the attenuation are shown in Figure 13-4. The jitter attenuator can be placed in

either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.

Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order

for the jitter attenuator to operate properly, a crystal with the specifications listed in Table 13-4 must be

connected to the XTAL1 and XTAL2 pins.

The jitter attenuator divides the clock provided by the 8.192MHz crystal at the XTAL1 and XTAL2 pins

to create an output clock that contains very little jitter. On-board circuitry will pull the crystal (by

switching in or out load capacitance) to keep it long-term averaged to the same frequency as the incoming

E1 signal. If the incoming jitter exceeds either 120UI_P-P(buffer depth is 128 bits) or 28UI_P-P(buffer depth

is 32 bits), then the DS2153Q will divide the attached crystal by either 3.5 or 4.5 instead of the normal 4

to keep the buffer from overflowing. When the device divides by either 3.5 or 4.5, it also sets the Jitter

Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR.5).

Table 13-4. Crystal Selection Guidelines

PARAMETER

Parallel Resonant Frequency

Mode

SPECIFICATION

8.192MHz

Fundamental

Load Capacitance

Tolerance

18pF to 20pF (18.5pF nominal)

±50ppm

Pullability

C_L= 10pF, delta frequency = +175ppm to

+250ppm

C_L= 45pF, delta frequency = -175ppm to -250ppm

Effective Series Resistance

Crystal Cut

30Ω maximum

AT

42 of 60

DS2153Q

Figure 13-1. External Analog Connections

NOTE 1: ALL RESISTOR VALUES ARE ±1%.

NOTE 2: THE R_TRESISTORS ARE USED TO INCREASE THE TRANSMITTER RETURN LOSS OR TO PROTECT THE DEVICE FROM

OVERVOLTAGE.

NOTE 3: THE RR RESISTORS ARE USED TO TERMINATE THE RECEIVE E1 LINE.

NOTE 4: FOR 75Ω TERMINATION, R_R= 37.5Ω/FOR 12Ω TERMINATION R_R= 60Ω.

NOTE 5: SEE THE SEPARATE APPLICATION NOTE FOR DETAILS ON HOW TO CONSTRUCT A PROTECTED INTERFACE.

43 of 60

DS2153Q

Figure 13-2. Jitter Tolerance

Figure 13-3. Transmit Waveform Template

44 of 60

DS2153Q

Figure 13-4. Jitter Attenuation

45 of 60

DS2153Q

14 TIMING DIAGRAMS

Figure 14-1. Receive Side Timing

NOTE 1: RSYNC IN THE FRAME MODE (RCR1.6 = 0).

NOTE 2: RSYNC IN THE MULTIFRAME MODE (RCR1.6 = 1).

NOTE 3: RLCLK IS PROGRAMMED TO OUTPUT JUST THE Sa4 BIT.

NOTE 4: RLINK WILL ALWAYS OUTPUT ALL FIVE Sa BITS AS WELL AS THE REST OF THE RECEIVE DATA STREAM.

NOTE 5: THIS DIAGRAM ASSUMES THE CAS MF BEGINS WITH THE FAS WORD.

Figure 14-2. Receive Side Boundary Timing (with Elastic Stores Disabled)

NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.

NOTE 2: RLINK IS PROGRAMMED TO OUTPUT THE Sa4 BITS.

NOTE 3: RLINK IS PROGRAMMED TO OUTPUT THE Sa4 AND Sa8 BITS.

NOTE 4: RLINK IS PROGRAMMED TO OUTPUT THE Sa5 AND Sa7 BITS.

NOTE 5: SHOWN IS A NON-ALIGN FRAME BOUNDARY.

46 of 60

DS2153Q

Figure 14-3. 1.544MHz Boundary Timing with Elastic Store(s) Disabled

NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO

CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO 1).

NOTE 2: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0).

NOTE 3: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1).

NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.

Figure 14-4. 2.048MHz Boundary Timing with Elastic Store(s) Enabled

NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0).

NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1).

NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.

47 of 60

DS2153Q

Figure 14-5. Transmit Side Timing

NOTE 1: TSYNC IN THE FRAME MODE (TCR1.1 = 0).

NOTE 2: TSYNC IN THE MULTIFRAME MODE (TCR1.1 = 1).

NOTE 3: TLINK IS PROGRAMMED TO SOURCE ONLY THE Sa4 BIT.

NOTE 4: THIS DIAGRAM ASSEMBLES BOTH THE CAS MF AND THE CRC4 BEGIN WITH THE ALIGN FRAME.

Figure 14-6. Transmit Side Boundary Timing

NOTE 1: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).

NOTE 2: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1).

NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.

NOTE 4: TLINK IS PROGRAMMED TO SOURCE THE SA4 BITS.

NOTE 5: TLINK IS PROGRAMMED TO SOURCE THE SA7 AND SA8 BITS.

NOTE 6: SHOWN IS A NON-ALIGN FRAME BOUNDARY.

NOTE 7: SEE Figure 14-3 AND Figure 14-4 FOR DETAILS ON TIMING WITH THE TRANSMIT SIDE ELASTIC STORE ENABLED.

48 of 60

DS2153Q

Figure 14-7. G.802 Timing

NOTE 1: RCHBLK OR TCHBLK IS PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 TO 15, 17 TO 25, AND

DURING BIT 1 OF TIME SLOT 26.

49 of 60

DS2153Q

Figure 14-8. Synchronization Flowchart

50 of 60

DS2153Q

Figure 14-9. Transmit Data Flow

NOTE 1: TCLK MUST BE TIED TO RCLK (OR SYSCLK IF THE ELASTIC STORE IS ENABLED) AND TSYNC MUST BE TIED

TO RSYNC FOR DATA TO BE PROPERLY SOURCED FROM RSER.

51 of 60

DS2153Q

15 DC CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +7.0V

Operating Temperature Range

Commercial……………………………………………………………...……………...0°C to 70°C

Industrial…………………………………………………………………………….-40°C to +85°C

Storage Temperature ………………………………………………………………………-55°C to +125°C

Soldering Temperature...………………………………………..See IPC/JEDEC J-STD-020 Specification

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect

reliability.

Table 15-1. Recommended DC Characteristics

(T_A= 0°C to +70°C for DS2153Q, T_A= -40°C to +85°C for DS2153QN.)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Logic 1

Logic 0

Supply

V_IH

2.0

-0.3

4.75

4.80

V_DD+ 0.3

V

V_IL

+0.8

V

DS2153Q

DS2153QN

5.25

V_DD

V

1

Table 15-2. Capacitance

(T_A= +25°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Input Capacitance

Output Capacitance

C_IN

C_OUT

5

7

pF

Table 15-3. DC Characteristics

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2153Q; V_DD= 5V +5%/-4%, T_A= -40°C to +85°C for

DS2153QN.)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Supply Current at 5V

I_DD

65

mA

µA

mA

2

3

4

Input Leakage

I_IL

-1.0

+1.0

1.0

Output Leakage

Output Current (2.4V)

Output Current (0.4V)

I_LO

I_OH

I_OL

-1.0

+4.0

NOTES:

1) Applies to RVDD, TVDD, and DVDD.

2) TCLK =2.048MHz.

3) 0V < V_IN< V_DD.

4) Applies to INT1 and INT1 when tri-stated.

52 of 60

DS2153Q

16 AC CHARACTERISTICS

Table 16-1. AC Characteristics—Parallel Port

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2153Q; V_DD= 5V +5%/-4%, T_A= -40°C to +85°C for

DS2153QN.) (See Figure 16-1, Figure 16-2, and Figure 16-3.)

PARAMETER

Cycle Time

SYMBOL

MIN

250

TYP

MAX

UNITS NOTES

t_CYC

ns

Pulse Width, DS Low or RD

PW_EL

150

ns

High

Pulse Width, DS High or RD

Low

PW_EH

100

ns

Input Rise/Fall Times

t_R, t_F

t_RWH

30

ns

10

50

R/ W Hold Time

R/ W Setup Time before DS

t_RWS

ns

High

CS Setup Time before DS,

WR or RD Active

CS Hold Time

t_CS

20

ns

t_CH

t_DHR

t_DHW

t_ASL

t_AHL

0

10

0

ns

Read Data Hold Time

Write Data Hold Time

Muxed Address Valid to AS

or ALE Fall

50

20

10

25

40

20

ns

Muxed Address Hold Time

Delay Time DS, WR or RD

t_ASD

to AS or ALE Rise

Pulse Width AS or ALE High

Delay Time, AS or ALE to

DS, WR or RD

PW_ASH

t_ASED

Output Data Delay Time from

DS or RD

Data Setup Time

t_DDR

t_DSW

20

80

100

ns

53 of 60

DS2153Q

Figure 16-1. Intel Bus Read AC Timing

Figure 16-2. Intel Bus Write AC Timing

54 of 60

DS2153Q

Figure 16-3. Motorola Bus AC Timing

55 of 60

DS2153Q

Table 16-2. AC Characteristics—Receive Side

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2153Q; V_DD= 5V +5%/-4%, T_A= -40°C to +85°C for

DS2153QN.) (See Figure 16-4.)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

ACLKI/RCLK Period

t_CP

t_CH

t_CL

t_CH

t_CL

t_SP

t_SH

t_SL

488

244

648

488

ns

180

90

ns

RCLK Pulse Width

SYSCLK Period

1

2

ns

200

ns

3

4

50

SYSCLK Pulse Width

RSYNC Setup to SYSCLK

Falling

t_SU

25

50

t_SH-5

ns

RSYNC Pulse Width

SYSCLK Rise/Fall Times

Delay RCLK or SYSCLK to

RSER Valid

t_PW

t_R, t_F

ns

25

70

t_DD

t_D1

t_D2

t_D3

ns

Delay RCLK or SYSCLK to

RCHCLK

50

Delay RCLK or SYSCLK to

RCHBLK

Delay RCLK or SYSCLK to

RSYNC

Delay RCLK to RLCLK

Delay RCLK to RLINK Valid

t_D4

t_D5

50

ns

NOTES:

1) Jitter attenuator enabled in the receive side path.

2) Jitter attenuator disabled or enabled in the transmit path.

3) SYSCLK = 1.544MHz.

4) SYSCLK = 2.048MHz.

56 of 60

DS2153Q

Figure 16-4. Receive Side AC Timing

NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0).

NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1).

NOTE 3: RLCLK AND RLINK ONLY HAVE A TIMING RELATIONSHIP TO RCLK. NO TIMING RELATIONSHIP BETWEEN RLCLK/RLINK

AND RSYNC IS IMPLIED.

NOTE 4: RCLK CAN EXHIBIT A SHORT HIGH TIME IF THE JITTER ATTENUATOR IS EITHER DISABLED OR IN THE TRANSMIT PATH.

57 of 60

DS2153Q

Table 16-3. AC Characteristics—Transmit Side

(V_DD= 5V ±5%, T_A= 0°C to +70°C for DS2153Q; V_DD= 5V +5%/-4%, T_A= -40°C to +85°C for

DS2153QN.) (See Figure 16-5.)

PARAMETER

TCLK Period

SYMBOL

MIN

TYP

488

MAX

UNITS NOTES

t_P

t_CH

t_CL

ns

75

TCLK Pulse Width

TSER and TLINK Set up to

TCLK Falling

t_SU

t_HD

t_SU

25

ns

1

TSER and TLINK Hold from

TCLK Falling

ns

TSYNC Set up to TCLK

Falling

t_CH-5

TSYNC Pulse Width

TCLK Rise/Fall Times

Delay TCLK to TCHCLK

Delay TCLK to TCHBLK

Delay TCLK to TSYNC

Delay TCLK to TLCLK

t_PW

t_R, t_F

t_D1

25

50

ns

t_D2

t_D3

t_D4

NOTES:

1) If the transmit side elastic store is enabled, then TSER is sampled on the falling edge of SYSCLK and

the parameters t_SUand t_HDstill apply.

58 of 60

DS2153Q

Figure 16-5. Transmit Side AC Timing

NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1).

NOTE 2: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).

NOTE 3: NO TIMING RELATIONSHIP BETWEEN TSYNC AND TLCLK/TLINK IS IMPLIED.

NOTE 4: TSER IS SAMPLED ON THE FALLING EDGE OF SYSCLK IF THE TRANSMIT SIDE ELASTIC STORE IS ENABLED

59 of 60

DS2153Q

17 PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for

each package is a link to the latest package outline information.)

17.1 44-Pin PLCC (56-G4003-001)

60 of 60

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.


型号：	DS2153Q-A7/T&R
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Framer, CMOS, PQCC44, 0.652 INCH, PLASTIC, LCC-44 PC 电信电信集成电路
文件：	总62页 (文件大小：808K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DS2153Q-A7/T&R [MAXIM]

相关型号：

DS2153Q-A7/TR+

DS2153QN

DS2153QN+

DS2153QN-A7+

DS2153QN-A7+T&R

DS2153QN-A7/T&R

DS2153QN-A7/TR+

DS2154

DS2154L

DS2154LA2

DS2154LA2+

DS2154LD1