DS2482S-100/T&R [MAXIM]
Buffer/Inverter Based Peripheral Driver, PDSO8, 0.150 INCH, SOP-8;
| 型号： | DS2482S-100/T&R |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Buffer/Inverter Based Peripheral Driver, PDSO8, 0.150 INCH, SOP-8 控制器 |
| 文件： | 总24页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4930; Rev 8; 11/09
Single-Channel 1-Wire Master
DS482-10
General Description
Features
♦ I C Host Interface Supports 100kHz and 400kHz
2
®
2
The DS2482-100 is an I C-to-1-Wire bridge device
that interfaces directly to standard (100kHz max) or fast
2
I C Communication Speeds
2
(400kHz max) I C masters to perform bidirectional pro-
2
♦ 1-Wire Master IO with Selectable Active or
tocol conversion between the I C master and any
Passive 1-Wire Pullup
downstream 1-Wire slave devices. Relative to any
attached 1-Wire slave device, the DS2482-100 is a
1-Wire master. Internal, factory-trimmed timers relieve
the system host processor from generating time-critical
1-Wire waveforms, supporting both standard and over-
drive 1-Wire communication speeds. To optimize
1-Wire waveform generation, the DS2482-100 performs
slew-rate control on rising and falling 1-Wire edges and
provides additional programmable features to match
drive characteristics to the 1-Wire slave environment.
Programmable, strong pullup features support 1-Wire
power delivery to 1-Wire devices such as EEPROMs
and sensors. The DS2482-100 combines these features
with an output to control an external MOSFET for
♦ Provides Reset/Presence, 8-Bit, Single-Bit, and
3-Bit 1-Wire IO Sequences
♦ Standard and Overdrive 1-Wire Communication
Speeds
♦ Slew-Controlled 1-Wire Edges
♦ Strong 1-Wire Pullup Provided by an Internal Low-
Impedance Signal Path
♦ PCTLZ Output to Optionally Control an External
MOSFET for Stronger Pullup Requirements
2
♦ Two Address Inputs for I C Address Assignment
2
enhanced strong pullup application. The I C slave
♦ Operating Range: 2.9V to 5.5V, -40°C to +85°C
♦ 8-Pin (150 mils) SO and 9-Bump WLP Packages
address assignment is controlled by two binary
address inputs, resolving potential conflicts with other
2
I C slave devices in the system.
Applications
Ordering Information
Printers
Industrial Sensors
PART
TEMP RANGE PIN-PACKAGE
Medical Instruments
Cell Phones, PDAs
DS2482S-100+
-40°C to +85°C 8 SO (150 mils)
DS2482S-100+T&R -40°C to +85°C 8 SO (150 mils)
DS2482X-100+T -40°C to +85°C 9 WLP (2.5k pieces)
Pin Configurations appear at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T/T&R = Tape and reel.
Typical Operating Circuit
V
CC
CURRENT-LIMITING
RESISTOR
R *
P
REFER TO APPLICATION
NOTE 4206
SDA
SCL
2
(I C PORT)
PCTLZ
OPTIONAL
CIRCUITRY
μC
DS2482-100
1-Wire LINE
AD0
AD1
IO
1-Wire
DEVICE
1-Wire
DEVICE
1-Wire
DEVICE
2
*R = I C PULLUP RESISTOR (SEE THE APPLICATIONS INFORMATION SECTION FOR R SIZING).
P
P
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Single-Channel 1-Wire Master
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground.........-0.5V to +6V
Maximum Current into Any Pin.......................................... 20mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DS482-10
ELECTRICAL CHARACTERISTICS
CC
(V
= 2.9V to 5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.9
4.5
TYP
3.3
MAX
3.7
UNITS
3.3V
Supply Voltage
V
CC
V
mA
V
5V
5.0
5.5
Operating Current
I
(Note 1)
3.3V
0.75
CC
1.9
3.4
1-Wire Input High (Notes 2, 3)
V
IH1
5V
3.3V
0.9
1.2
1675
0.4
2.7
0.6
0.3
0.5
4.2
22.1
6.5
40
1-Wire Input Low (Notes 2, 3)
V
V
IL1
5V
1-Wire Weak Pullup Resistor
1-Wire Output Low
R
WPU
(Note 4)
At 4mA load
Standard
Overdrive
1000
ꢀ
V
V
OL1
2.3
0.4
2.5
0.5
Active Pullup On Time
(Notes 4, 5)
t
μs
V
APUOT
V
CC
V
CC
ꢁ 3.2V, 1.5mA load
Strong Pullup Voltage Drop
ꢂV
STRPU
ꢁ 5.2V, 3mA load
Standard (3.3V ±10%)
Overdrive (3.3V ±10%)
Standard (5.0V ±10%)
Overdrive (5.0V ±10%)
Standard (3.3V ±10%)
Overdrive (3.3V ±10%)
Standard (5.0V ±10%)
Overdrive (5.0V ±10%)
1
5
Pulldown Slew Rate (Note 6)
PD
V/μs
SRC
2
10
0.8
2.7
1.3
3.4
4
20
Pullup Slew Rate (Note 6)
Power-On Reset Trip Point
PU
V/μs
V
SRC
6
31
V
2.2
POR
1-Wire TIMING (Note 5) (See Figures 4, 5, and 6)
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive
7.6
0.9
8
8.4
1.1
Write-One/Read Low Time
Read Sample Time
1-Wire Time Slot
t
μs
μs
μs
W1L
1
13.3
1.4
14
15
t
MSR
1.5
69.3
10.5
1.8
65.8
9.9
72.8
11.0
t
SLOT
2
_______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.9V to 5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
Standard (3.3V to 0V)
MIN
0.54
0.10
0.55
0.09
60
TYP
MAX
3.0
UNITS
Overdrive (3.3V to 0V)
Standard (5.0V to 0V)
Overdrive (5.0V to 0V)
Standard
0.59
2.2
Fall Time High-to-Low
(Notes 6, 7)
t
F1
μs
0.44
68
64
7.5
5.3
3.0
600
72
Write-Zero Low Time
t
μs
μs
μs
μs
μs
μs
W0L
Overdrive
7.1
7.9
Standard
5.0
5.6
Write-Zero Recovery Time
Reset Low Time
t
REC0
Overdrive
2.8
3.2
Standard
570
68.4
66.5
7.1
630
75.6
73.5
7.9
t
RSTL
Overdrive
Standard
70
Presence-Detect Sample Time
Sampling for Short and Interrupt
Reset High Time
t
MSP
Overdrive
7.5
8
Standard
7.6
8.4
t
SI
Overdrive
0.7
0.75
584
74
0.8
Standard
554.8
70.3
613.2
77.7
t
RSTH
Overdrive
CONTROL PIN (PCTLZ)
Output Low Voltage
V
V
= 2.9V, 1.2mA load current
0.4
V
V
OLP
CC
V
0.5V
-
CC
Output High Voltage
V
0.4mA load current
OHP
2
I C PINS (SCL, SDA, AD0, AD1) (Note 8) (See Figure 9)
0.25 ×
V
= 2.9V to 3.7V
= 4.5V to 5.5V
-0.5
CC
CC
V
CC
Low-Level Input Voltage
V
V
IL
0.22 ×
V
-0.5
V
CC
0.7 ×
V
0.5V
+
CC
High-Level Input Voltage
V
V
V
V
IH
V
CC
Hysteresis of Schmitt Trigger
Inputs
0.05 ×
V
HYS
V
CC
Low-Level Output Voltage at
3mA Sink Current
V
0.4
250
50
OL
OF
SP
Output Fall Time from V
to
IH(MIN)
V
with a Bus Capacitance
t
60
ns
ns
IL(MAX)
from 10pF to 400pF
Pulse Width of Spikes That Are
Suppressed by the Input Filter
t
SDA and SCL pins only
(Notes 9, 10)
Input Current Each Input/Output
Pin with an Input Voltage
I
-10
+10
μA
I
Between 0.1 x V
and
CC(MAX)
0.9 x V
CC(MAX)
_______________________________________________________________________________________
3
Single-Channel 1-Wire Master
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.9V to 5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
10
UNITS
pF
Input Capacitance
C
(Note 9)
I
SCL Clock Frequency
f
400
kHz
SCL
Hold Time (Repeated) START
Condition (After this period, the
first clock pulse is generated.)
t
0.6
μs
HD:STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
1.3
0.6
μs
μs
LOW
DS482-10
t
HIGH
Setup Time for a Repeated
START Condition
t
0.6
μs
SU:STA
Data Hold Time
t
t
t
(Notes 11, 12)
(Note 13)
0.9
μs
ns
μs
HD:DAT
SU:DAT
SU:STO
Data Setup Time
250
0.6
Setup Time for STOP Condition
Bus Free Time Between a STOP
and START Condition
t
1.3
μs
BUF
Capacitive Load for Each Bus
Line
C
(Note 14)
(Note 15)
400
100
pF
μs
B
Oscillator Warmup Time
t
OSCWUP
Note 1: Operating current with 1-Wire write-byte sequence followed by continuously reading the Status Register at 400kHz in overdrive.
Note 2: With standard speed, the total capacitive load of the 1-Wire bus should not exceed 1nF. Otherwise, the passive pullup on
threshold V may not be reached in the available time. With overdrive speed, the capacitive load on the 1-Wire bus must
IL1
not exceed 300pF.
Note 3: Active pullup guaranteed to turn on between V
and V
.
IH1(MIN)
IL1(MAX)
Note 4: Active or resistive pullup choice is configurable.
Note 5: Except for t , all 1-Wire timing specifications and t
are derived from the same timing circuit. Therefore, if one of
APUOT
F1
these parameters is found to be off the typical value, it is safe to assume that all these parameters deviate from their typi-
cal value in the same direction and by the same degree.
Note 6: These values apply at full load, i.e., 1nF at standard speed and 0.3nF at overdrive speed. For reduced load, the pulldown
slew rate is slightly faster.
Note 7: Fall time high-to-low (t ) is derived from PD
, referenced from 0.9 x V
to 0.1 x V
.
F1
SRC
CC
CC
2
Note 8: All I C timing values are referred to V
and V
levels.
IH(MIN)
IL(MAX)
Note 9: Applies to SDA, SCL, AD0 and AD1.
Note 10: The input/output pins of the DS2482-100 do not obstruct the SDA and SCL lines if V
is switched off.
CC
Note 11: The DS2482-100 provides a hold time of at least 300ns for the SDA signal (referred to the V
of the SCL signal) to
IH(MIN)
bridge the undefined region of the falling edge of SCL.
Note 12: The maximum t
need only be met if the device does not stretch the low period (t
) of the SCL signal.
LOW
HD:DAT
2
2
Note 13: A fast-mode I C bus device can be used in a standard-mode I C bus system, but the requirement t
≥ 250ns must
SU:DAT
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
250 = 1250ns (according to the standard-mode I C bus specification) before the SCL line is released.
+ t
= 1000 +
R(MAX)
SU:DAT
2
2
Note 14: C —Total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall times according to I C-
B
Bus Specification Version 2.1 are allowed.
Note 15: I C communication should not take place for the max t
2
time following a power-on reset.
OSCWUP
4
_______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
Pin Description
PIN
NAME
FUNCTION
SO
1
WLP
B3
V
CC
Power-Supply Input
2
C3
IO
Input/Output Driver for 1-Wire Line
3
C2
GND
SCL
SDA
Ground Reference
2
4
B1
I C Serial Clock Input. Must be connected to V through a pullup resistor.
CC
2
5
B2
I C Serial Data Input/Output. Must be connected to V through a pullup resistor.
CC
Active-Low Control Output for an External p-Channel MOSFET. Provides extra power to the 1-Wire
line, e.g., for use with 1-Wire devices that require a higher current temporarily to operate.
6
A1
PCTLZ
2
2
7
8
A2
A3
AD1
AD0
I C Address Inputs. Must be connected to V or GND. These inputs determine the I C slave
CC
address of the device (see Figure 8).
CONFIGURATION
T-TIME OSC
REGISTER
INPUT/OUTPUT
CONTROLLER
LINE
XCVR
2
IO
I C
SDA
INTERFACE
SCL
CONTROLLER
PCTLZ
STATUS
REGISTER
AD0
AD1
DS2482-100
READ DATA
REGISTER
Figure 1. Block Diagram
time-critical 1-Wire communication functions such as
reset/presence-detect cycle, read-byte, write-byte, sin-
gle-bit R/W, and triplet for ROM Search, without requir-
ing interaction with the host processor. The host obtains
feedback (completion of a 1-Wire function, presence
pulse, 1-Wire short, search direction taken) through the
Status Register and data through the Read Data
Register. The DS2482-100 communicates with a host
Detailed Description
The DS2482-100 is a self-timed 1-Wire master that sup-
ports advanced 1-Wire waveform features including
standard and overdrive speeds, active pullup, and
strong pullup for power delivery. The active pullup
affects rising edges on the 1-Wire side. The strong
pullup function uses the same pullup transistor as the
active pullup, but with a different control algorithm. In
addition, the strong pullup activates the PCTLZ pin,
controlling optional external circuitry to deliver addition-
al power beyond the capabilities of the on-chip pullup
transistor. Once supplied with command and data, the
input/output controller of the DS2482-100 performs
2
processor through its I C bus interface in standard
mode or in fast mode. The logic state of two address pins
2
determines the I C slave address of the DS2482-100,
allowing up to four devices operating on the same bus
segment without requiring a hub. See Figure 1 for a block
diagram.
_______________________________________________________________________________________
5
Single-Channel 1-Wire Master
Active Pullup (APU)
The APU bit controls whether an active pullup (con-
trolled slew-rate transistor) or a passive pullup (R
resistor) is used to drive a 1-Wire line from low to high.
When APU = 0, active pullup is disabled (resistor
mode). Active pullup should always be selected unless
there is only a single slave on the 1-Wire line. The
active pullup does not apply to the rising edge of a
presence pulse or a recovery after a short on the
1-Wire line.
Device Registers
2
The DS2482-100 has three registers that the I C host
WPU
can read: Configuration, Status, and Read Data. These
registers are addressed by a read pointer. The position
of the read pointer, i.e., the register that the host reads
in a subsequent read access, is defined by the instruc-
tion the DS2482-100 executed last. To enable certain
1-Wire features, the host has read and write access to
the Configuration Register.
Configuration Register
The DS2482-100 supports three 1-Wire features that
are enabled or selected through the Configuration
Register. These features are:
The circuit that controls rising edges (Figure 2) oper-
DS482-10
ates as follows: At t , the pulldown (from DS2482-100
1
or 1-Wire slave) ends. From this point on, the 1-Wire
bus is pulled high through R
internal to the
WPU
DS2482-100. V
and the capacitive load of the 1-Wire
CC
• Active Pullup (APU)
• Strong Pullup (SPU)
• 1-Wire Speed (1WS)
line determine the slope. In case that active pullup is
disabled (APU = 0), the resistive pullup continues, as
represented by the solid line. With active pullup
enabled (APU = 1), and when at t the voltage has
2
These features can be selected in any combination.
While APU and 1WS maintain their state, SPU returns to
its inactive state as soon as the strong pullup has ended.
reached a level between V
and V
, the
IH1(MIN)
IL1(MAX)
DS2482-100 actively pulls the 1-Wire line high, applying
a controlled slew rate as represented by the dashed
After a device reset (power-up cycle or initiated by the
Device Reset command), the Configuration Register
reads 00h. When writing to the Configuration Register,
the new data is accepted only if the upper nibble (bits 7
to 4) is the one’s complement of the lower nibble (bits 3
to 0). When read, the upper nibble is always 0h.
line. The active pullup continues until t
is expired
APUOT
at t . From that time on the resistive pullup continues.
3
See the Strong Pullup (SPU) section for a way to keep
the pullup transistor conducting beyond t .
3
Configuration Register Bit Assignment
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1WS
SPU
1
APU
1WS
SPU
0
APU
V
CC
APU = 1
APU = 0
V
IH1(MIN)
V
IL1(MAX)
0V
t
1-Wire BUS IS DISCHARGED
APUOT
t
1
t
t
3
2
Figure 2. Rising Edge Pullup
6
_______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
Strong Pullup (SPU)
typical case); the SPU bit in the Configuration Register
is written to 0; or the DS2482-100 receives the Device
Reset command. As long as the strong pullup is active,
the PCTLZ output is low. When the strong pullup ends,
the SPU bit is automatically reset to 0. Using the strong
pullup feature does not change the state of the APU bit
in the Configuration Register.
The SPU bit is used to activate the strong pullup func-
tion prior to a 1-Wire Write Byte or 1-Wire Single Bit
command. Strong pullup is commonly used with 1-Wire
EEPROM devices when copying scratchpad data to the
main memory or when performing an SHA-1 computa-
tion and with parasitically powered temperature sen-
sors or A/D converters. The respective device data
sheets specify the location in the communications pro-
tocol after which the strong pullup should be applied.
The SPU bit must be set immediately prior to issuing
the command that puts the 1-Wire device into the state
where it needs the extra power. The strong pullup uses
the same internal pullup transistor as the active pullup
feature. For cases where the internal strong pullup has
insufficient strength, the PCTLZ pin can be used to con-
trol an external p-channel MOSFET to supply additional
power beyond the drive capability of the DS2482-100 to
1-Wire Speed (1WS)
The 1WS bit determines the timing of any 1-Wire com-
munication generated by the DS2482-100. All 1-Wire
slave devices support standard speed (1WS = 0),
where the transfer of a single bit (t
in Figure 3) is
SLOT
completed within 65µs. Many 1-Wire devices can also
communicate at a higher data rate, called overdrive
speed. To change from standard to overdrive speed, a
1-Wire device needs to receive an Overdrive-Skip ROM
or Overdrive-Match ROM command, as explained in
the 1-Wire device data sheets. The change in speed
occurs immediately after the 1-Wire device has
received the speed-changing command code. The
DS2482-100 must take part in this speed change to
stay synchronized. This is accomplished by writing to
the Configuration Register with the 1WS bit as 1 imme-
diately after the 1-Wire Byte command that changes the
speed of a 1-Wire device. Writing to the Configuration
Register with the 1WS bit as 0, followed by a 1-Wire
Reset command, changes the DS2482-100 and any
1-Wire devices on the active 1-Wire line back to stan-
dard speed.
the 1-Wire line. See the ΔV
parameter in the
STRPU
Electrical Characteristics to determine if the internal
strong pullup is sufficient given the current load on the
device.
If SPU is 1, the DS2482-100 treats the rising edge of the
time slot in which the strong pullup starts as if the active
pullup was activated. However, in contrast to the active
pullup, the strong pullup, i.e., the internal pullup transis-
tor, remains conducting, as shown in Figure 3, until one
of three events occurs: the DS2482-100 receives a
command that generates 1-Wire communication (the
LAST BIT OF 1-Wire WRITE BYTE OR 1-Wire SINGLE BIT FUNCTION
WRITE-ONE CASE
V
CC
NEXT
TIME SLOT
OR 1-Wire
RESET
WRITE-ZERO CASE
0V
t
SLOT
PCTLZ
DS2482-100 RESISTIVE PULLUP
DS2482-100 PULLDOWN
DS2482-100 STRONG PULLUP
Figure 3. Low-Impedance Pullup Timing
_______________________________________________________________________________________
7
Single-Channel 1-Wire Master
Status Register Bit Assignment
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DIR
TSB
SBR
RST
LL
SD
PPD
1WB
Logic Level (LL)
Status Register
The LL bit reports the logic state of the active 1-Wire
line without initiating any 1-Wire communication. The
1-Wire line is sampled for this purpose every time the
Status Register is read. The sampling and updating of
the LL bit takes place when the host processor has
addressed the DS2482-100 in read mode (during the
acknowledge cycle), provided that the read pointer is
positioned at the Status Register.
The read-only Status Register is the general means for
the DS2482-100 to report bit-type data from the 1-Wire
side, 1-Wire busy status, and its own reset status to the
host processor. All 1-Wire communication commands
and the Device Reset command position the read
pointer at the Status Register for the host processor to
read with minimal protocol overhead. Status information
is updated during the execution of certain commands
only. Details are given in the description of the various
status bits that follow.
DS482-10
Device Reset (RST)
If the RST bit is 1, the DS2482-100 has performed an
internal reset cycle, either caused by a power-on reset
or from executing the Device Reset command. The RST
bit is cleared automatically when the DS2482-100 exe-
cutes a Write Configuration command to restore the
selection of the desired 1-Wire features.
1-Wire Busy (1WB)
The 1WB bit reports to the host processor whether the
1-Wire line is busy. During 1-Wire communication 1WB
is 1; once the command is completed, 1WB returns to
its default 0. Details on when 1WB changes state and
for how long it remains at 1 are found in the Function
Commands section.
Single Bit Result (SBR)
The SBR bit reports the logic state of the active 1-Wire line
sampled at t
of a 1-Wire Single Bit command or the
Presence-Pulse Detect (PPD)
The PPD bit is updated with every 1-Wire Reset com-
mand. If the DS2482-100 detects a presence pulse from
MSR
first bit of a 1-Wire Triplet command. The power-on default
of SBR is 0. If the 1-Wire Single Bit command sends a 0
bit, SBR should be 0. With a 1-Wire Triplet command,
SBR could be 0 as well as 1, depending on the response
of the 1-Wire devices connected. The same result applies
to a 1-Wire Single Bit command that sends a 1 bit.
a 1-Wire device at t
during the presence-detect
MSP
cycle, the PPD bit is set to 1. This bit returns to its default
0 if there is no presence pulse or if the 1-Wire line is
shorted during a subsequent 1-Wire Reset command.
Triplet Second Bit (TSB)
Short Detected (SD)
The SD bit is updated with every 1-Wire Reset com-
mand. If the DS2482-100 detects a logic 0 on the
The TSB bit reports the logic state of the active 1-Wire
line sampled at t
of the second bit of a 1-Wire
MSR
Triplet command. The power-on default of TSB is 0.
This bit is updated only with a 1-Wire Triplet command
and has no function with other commands.
1-Wire line at t during the presence-detect cycle, the
SI
SD bit is set to 1. This bit returns to its default 0 with a
subsequent 1-Wire Reset command provided that the
short has been removed. If SD is 1, PPD is 0. The
DS2482-100 cannot distinguish between a short and a
DS1994 or DS2404 signaling a 1-Wire interrupt. For this
reason, if a DS2404 or DS1994 is used in the applica-
tion, the interrupt function must be disabled. The inter-
rupt signaling is explained in the respective 1-Wire
device data sheets.
Branch Direction Taken (DIR)
Whenever a 1-Wire Triplet command is executed, this
bit reports to the host processor the search direction
that was chosen by the third bit of the triplet. The
power-on default of DIR is 0. This bit is updated only
with a 1-Wire Triplet command and has no function with
other commands. For additional information, see the
description of the 1-Wire Triplet command and
Application Note 187: 1-Wire Search Algorithm.
8
_______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
The function commands are as follows:
Function Commands
1) Device Reset
5) 1-Wire Single Bit
6) 1-Wire Write Byte
7) 1-Wire Read Byte
8) 1-Wire Triplet
The DS2482-100 understands eight function com-
2
mands that fall into four categories: device control, I C
2) Set Read Pointer
3) Write Configuration
4) 1-Wire Reset
communication, 1-Wire setup, and 1-Wire communica-
tion. The feedback path to the host is controlled by a
read pointer, which is set automatically by each func-
tion command for the host to efficiently access relevant
information. The host processor sends these com-
mands and applicable parameters as strings of one or
Table 1. Valid Pointer Codes
2
2
two bytes using the I C interface. The I C protocol
requires that each byte be acknowledged by the
receiving party to confirm acceptance or not be
acknowledged to indicate an error condition (invalid
code or parameter) or to end the communication. See
REGISTER SELECTION
CODE
F0h
Status Register
Read Data Register
E1h
Configuration Register
C3h
2
2
the I C Interface section for details of the I C protocol
including acknowledge.
Device Reset
Command Code
F0h
Command Parameter
None
Performs a global reset of device state machine logic. Terminates any ongoing 1-Wire
communication.
Description
Typical Use
Device initialization after power-up; reinitialization (reset) as desired.
None (can be executed at any time).
Restriction
Error Response
Command Duration
1-Wire Activity
None
Maximum 525ns. Counted from falling SCL edge of the command code acknowledge bit.
Ends maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Status Register (for busy polling).
Read Pointer Position
Status Bits Affected
RST set to 1; 1WB, PPD, SD, SBR, TSB, DIR set to 0.
Configuration Bits Affected 1WS, APU, SPU set to 0.
Set Read Pointer
Command Code
E1h
Command Parameter
Pointer Code (see Table 1)
Sets the read pointer to the specified register. Overwrites the read pointer position of any 1-Wire
communication command in progress.
Description
To prepare reading the result from a 1-Wire Read Byte command; random read access of
registers.
Typical Use
Restriction
None (can be executed at any time).
If the pointer code is not valid, the pointer code is not acknowledged and the command is
ignored.
Error Response
Command Duration
1-Wire Activity
None. The read pointer is updated on the rising SCL edge of the pointer code acknowledge bit.
Not affected.
Read Pointer Position
Status Bits Affected
As specified by the pointer code.
None
Configuration Bits Affected None
_______________________________________________________________________________________
9
Single-Channel 1-Wire Master
Write Configuration
Command Code
D2h
Command Parameter
Configuration Byte
Writes a new configuration byte. The new settings take effect immediately. Note: When writing to
the Configuration Register, the new data is accepted only if the upper nibble (bits 7 to 4) is the
one’s complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
Description
Typical Use
Restriction
Defining the features for subsequent 1-Wire communication.
1-Wire activity must have ended before the DS2482-100 can process this command.
Command code and parameter are not acknowledged if 1WB = 1 at the time the command code
is received and the command is ignored.
Error Response
DS482-10
None. The Configuration Register is updated on the rising SCL edge of the configuration-byte
acknowledge bit.
Command Duration
1-Wire Activity
None
Read Pointer Position
Status Bits Affected
Configuration Register (to verify write).
RST set to 0.
Configuration Bits Affected 1WS, SPU, APU updated.
1-Wire Reset
Command Code
B4h
Command Parameter
None
Generates a 1-Wire reset/presence-detect cycle (Figure 4) at the 1-Wire line. The state of the
Description
1-Wire line is sampled at t and t
and the result is reported to the host processor through the
MSP
SI
Status Register, bits PPD and SD.
Typical Use
Restriction
To initiate or end any 1-Wire communication sequence.
1-Wire activity must have ended before the DS2482-100 can process this command.
Command code is not acknowledged if 1WB = 1 at the time the command code is received and
the command is ignored.
Error Response
t
+ t
+ maximum 262.5ns, counted from the falling SCL edge of the command code
RSTL
RSTH
Command Duration
acknowledge bit.
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Status Register (for busy polling).
Read Pointer Position
Status Bits Affected
1WB (set to 1 for t
+ t
), PPD is updated at t
+ t
, SD is updated at t + t .
RSTL SI
RSTL
RSTH
RSTL
MSP
Configuration Bits Affected 1WS and APU apply.
10 ______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
1-Wire Single Bit
Command Code
87h
Command Parameter
Bit Byte
Generates a single 1-Wire time slot with a bit value “V” as specified by the bit byte at the 1-Wire
line (see Table 2). A V value of 0b generates a write-zero time slot (Figure 5); a V value of 1b
generates a write-one time slot, which also functions as a read-data time slot (Figure 6). In either
Description
case, the logic level at the 1-Wire line is tested at t
and SBR is updated.
MSR
To perform single-bit writes or reads at the 1-Wire line when single bit communication is
necessary (the exception).
Typical Use
Restriction
1-Wire activity must have ended before the DS2482-100 can process this command.
Command code and bit byte are not acknowledged if 1WB = 1 at the time the command code is
received and the command is ignored.
Error Response
Command Duration
1-Wire Activity
t
+ maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of the bit byte.
SLOT
Begins maximum 262.5ns after the falling SCL edge of the MSB of the bit byte.
Status Register (for busy polling and data reading).
Read Pointer Position
Status Bits Affected
1WB (set to 1 for t
), SBR is updated at t
, DIR (may change its state).
SLOT
MSR
Configuration Bits Affected 1WS, APU, SPU apply.
Table 2. Bit Allocation in the Bit Byte
BIT 7
V
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
x
x
x
x
x
x
x
x = Don’t care.
RESET PULSE
PRESENCE/SHORT DETECT
PRESENCE PULSE
t
MSP
t
SI
V
CC
APU CONTROLLED
EDGE
V
IH1
V
IL1
RESISTIVE PULLUP
0V
t
F1
t
t
RSTH
RSTL
PULLUP
DS2482-100 PULLDOWN
1-Wire SLAVE PULLDOWN
Figure 4. 1-Wire Reset/Presence-Detect Cycle
______________________________________________________________________________________ 11
Single-Channel 1-Wire Master
t
WOL
t
MSR
V
CC
V
IH1
V
IL1
0V
t
F1
t
REC0
DS482-10
t
SLOT
PULLUP (SEE FIGURE 2)
DS2482-100 PULLDOWN
Figure 5. Write-Zero Time Slot
t
MSR
t
W1L
V
CC
V
IH1
V
IL1
0V
t
F1
t
SLOT
PULLUP (SEE FIGURE 2)
DS2482-100 PULLDOWN
1-Wire SLAVE PULLDOWN
NOTE: DEPENDING ON ITS INTERNAL STATE, A 1-Wire SLAVE DEVICE TRANSMITS DATA TO ITS MASTER (e.g. THE DS2482-100). WHEN RESPONDING WITH A 0,
A 1-Wire SLAVE STARTS PULLING THE LINE LOW DURING t . ITS INTERNAL TIMING GENERATOR DETERMINES WHEN THIS PULLDOWN ENDS AND THE VOLTAGE
W1L
STARTS RISING AGAIN. WHEN RESPONDING WITH A 1, A 1-Wire SLAVE DOES NOT HOLD THE LINE LOW AT ALL, AND THE VOLTAGE STARTS RISING AS SOON AS t
W1L
IS OVER. 1-Wire DEVICE DATA SHEETS USE THE TERM t INSTEAD OF t
TO DESCRIBE A READ-DATA TIME SLOT. TECHNICALLY, t AND t
HAVE IDENTICAL
RL
W1L
RL
W1L
SPECIFICATIONS AND CANNOT BE DISTINGUISHED FROM EACH OTHER.
Figure 6. Write-One and Read-Data Time Slot
12 ______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
1-Wire Write Byte
Command Code
Command Parameter
Description
A5h
Data Byte
Writes a single data byte to the 1-Wire line.
To write commands or data to the 1-Wire line. Equivalent to executing eight 1-Wire Single Bit
commands, but faster due to less I C traffic.
Typical Use
2
Restriction
1-Wire activity must have ended before the DS2482-100 can process this command.
Command code and data byte are not acknowledged if 1WB = 1 at the time the command code is
received and the command is ignored.
Error Response
Command Duration
8 x t
+ maximum 262.5ns, counted from falling edge of the last bit (LSB) of the data byte.
SLOT
Begins maximum 262.5ns after falling SCL edge of the LSB of the data byte (i.e., before the data
2
byte acknowledge). Note: The bit order on the I C bus and the 1-Wire line is different (1-Wire: LSB
1-Wire Activity
2
first; I C: MSB first). Therefore, 1-Wire activity cannot begin before the DS2482-100 has received
the full data byte.
Read Pointer Position
Status Bits Affected
Status Register (for busy polling).
1WB (set to 1 for 8 x t
).
SLOT
Configuration Bits Affected 1WS, SPU, APU apply.
1-Wire Read Byte
Command Code
96h
Command Parameter
None
Generates eight read-data time slots on the 1-Wire line and stores result in the Read Data
Register.
Description
To read data from the 1-Wire line. Equivalent to executing eight 1-Wire Single Bit commands with
V = 1 (write-one time slot), but faster due to less I C traffic.
Typical Use
2
Restriction
1-Wire activity must have ended before the DS2482-100 can process this command.
Command code is not acknowledged if 1WB = 1 at the time the command code is received and
the command is ignored.
Error Response
8 x t
acknowledge bit.
+ maximum 262.5ns, counted from the falling SCL edge of the command code
SLOT
Command Duration
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Status Register (for busy polling). Note: To read the data byte received from the 1-Wire line, issue
the Set Read Pointer command and select the Read Data Register. Then access the DS2482-100
in read mode.
Read Pointer Position
Status Bits Affected
1WB (set to 1 for 8 x t
).
SLOT
Configuration Bits Affected 1WS, APU apply.
______________________________________________________________________________________ 13
Single-Channel 1-Wire Master
1-Wire Triplet
Command Code
78h
Command Parameter
Direction Byte
Generates three time slots: two read time slots and one write time slot at the 1-Wire line. The type
of write time slot depends on the result of the read time slots and the direction byte. The direction
byte determines the type of write time slot if both read time slots are 0 (a typical case). In this
case, the DS2482-100 generates a write-one time slot if V = 1 and a write-zero time slot if V = 0.
See Table 3.
Description
If the read time slots are 0 and 1, they are followed by a write-zero time slot.
If the read time slots are 1 and 0, they are followed by a write-one time slot.
If the read time slots are both 1 (error case), the subsequent write time slot is a write-one.
DS482-10
To perform a 1-Wire Search ROM sequence; a full sequence requires this command to be
executed 64 times to identify and address one device.
Typical Use
Restriction
1-Wire activity must have ended before the DS2482-100 can process this command.
Command code and direction byte is not acknowledged if 1WB = 1 at the time the command
code is received and the command is ignored.
Error Response
3 x t
direction byte.
+ maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of the
SLOT
Command Duration
1-Wire Activity
Begins maximum 262.5ns after the falling SCL edge of the MSB of the direction byte.
Status Register (for busy polling).
Read Pointer Position
1WB (set to 1 for 3 x t
), SBR is updated at the first t
, TSB and DIR are updated at the
SLOT
SLOT
MSR
Status Bits Affected
second t
(i.e., at t
+ t
).
MSR
MSR
Configuration Bits Affected 1WS, APU apply.
Table 3. Bit Allocation in the Direction Byte
BIT 7
V
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
x
x
x
x
x
x
x
x = Don’t care.
14 ______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
MSB FIRST
MSB
LSB
MSB
LSB
SDA
SCL
SLAVE
ADDRESS
R/W
8
ACK
9
DATA
ACK
9
DATA
ACK/
NACK
1–7
1–7
8
1–7
8
9
IDLE
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
STOP CONDITION
REPEATED START
2
Figure 7. I C Protocol Overview
2
transmitted first. After each byte follows an acknowledge
bit to allow synchronization between master and slave.
I C Interface
General Characteristics
2
Slave Address
The slave address to which the DS2482-100 responds
is shown in Figure 8. The logic state at the address pins
AD0 and AD1 determines the value of the address bits
A0 and A1. The address pins allow the device to
respond to one of four possible slave addresses. The
slave address is part of the slave address/control byte.
The last bit of the slave address/control byte (R/W)
defines the data direction. When set to 0, subsequent
data flows from master to slave (write access); when
set to 1, data flows from slave to master (read access).
The I C bus uses a data line (SDA) plus a clock signal
(SCL) for communication. Both SDA and SCL are bidi-
rectional lines, connected to a positive supply voltage
through a pullup resistor. When there is no communica-
tion, both lines are high. The output stages of devices
connected to the bus must have an open drain or open
collector to perform the wired-AND function. Data on
2
the I C bus can be transferred at rates of up to
100kbps in standard mode and up to 400kbps in fast
mode. The DS2482-100 works in both modes.
A device that sends data on the bus is defined as a
transmitter, and a device receiving data is defined as a
receiver. The device that controls the communication is
called a master. The devices that are controlled by the
master are slaves. To be individually accessed, each
device must have a slave address that does not conflict
with other devices on the bus.
7-BIT SLAVE ADDRESS
A6
0
A5
0
A4
1
A3
1
A2
0
A1
A0
AD1 AD0 R/W
Data transfers can be initiated only when the bus is not
busy. The master generates the serial clock (SCL), con-
trols the bus access, generates the START and STOP
conditions, and determines the number of data bytes
transferred between START and STOP (Figure 7). Data
is transferred in bytes with the most significant bit being
MSB
AD1, AD0
PIN STATES
DETERMINES
READ OR WRITE
Figure 8. DS2482-100 Slave Address
______________________________________________________________________________________ 15
Single-Channel 1-Wire Master
SDA
t
BUF
t
t
SP
F
t
HD:STA
t
LOW
SCL
DS482-10
t
HIGH
SPIKE
SUPPRESSION
t
SU:STA
t
t
R
t
HD:STA
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IL(MAX)
IH(MIN)
2
Figure 9. I C Timing Diagram
2
before the rising edge of SCL; see Figure 9). There
is one clock pulse per bit of data. Data is shifted into
the receiving device during the rising edge of SCL.
I C Definitions
The following terminology is commonly used to
describe I C data transfers. The timing references are
2
defined in Figure 9.
When finished with writing, the master must release
the SDA line for a sufficient amount of setup time
Bus Idle or Not Busy: Both SDA and SCL are inac-
(minimum t
+ t in Figure 9) before the next
R
tive and in their logic-high states.
SU:DAT
rising edge of SCL to start reading. The slave shifts
out each data bit on SDA at the falling edge of the
previous SCL pulse and the data bit is valid at the
rising edge of the current SCL pulse. The master
generates all SCL clock pulses, including those
needed to read from a slave.
START Condition: To initiate communication with a
slave, the master must generate a START condition.
A START condition is defined as a change in state of
SDA from high to low while SCL remains high.
STOP Condition: To end communication with a
slave, the master must generate a STOP condition. A
STOP condition is defined as a change in state of
SDA from low to high while SCL remains high.
Acknowledge: Typically a receiving device, when
addressed, is obliged to generate an acknowledge
after the receipt of each byte. The master must gen-
erate a clock pulse that is associated with this
acknowledge bit. A device that acknowledges must
pull SDA low during the acknowledge clock pulse in
such a way that SDA is stable low during the high
period of the acknowledge-related clock pulse plus
Repeated START Condition: Repeated STARTs are
commonly used for read accesses to select a spe-
cific data source or address to read from. The mas-
ter can use a repeated START condition at the end
of a data transfer to immediately initiate a new data
transfer following the current one. A repeated START
condition is generated the same way as a normal
START condition, but without leaving the bus idle
after a STOP condition.
the required setup and hold time (t
after the
HD:DAT
before the rising
falling edge of SCL and t
edge of SCL).
SU:DAT
Not Acknowledged by Slave: A slave device may
be unable to receive or transmit data, for example,
because it is busy performing some real-time func-
tion. In this case, the slave device does not acknowl-
edge its slave address and leaves the SDA line high.
A slave device that is ready to communicate
acknowledges at least its slave address. However,
Data Valid: With the exception of the START and
STOP condition, transitions of SDA can occur only
during the low state of SCL. The data on SDA must
remain valid and unchanged during the entire high
pulse of SCL plus the required setup and hold time
(t
after the falling edge of SCL and t
SU:DAT
HD:DAT
16 ______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
2
some time later the slave may refuse to accept data,
possibly because of an invalid command code or
parameter. In this case, the slave device does not
acknowledge any of the bytes that it refuses and
leaves SDA high. In either case, after a slave has
failed to acknowledge, the master first should gener-
ate a repeated START condition or a STOP condition
followed by a START condition to begin a new data
transfer.
I C Communication Examples
2
See Tables 4 and 5 for the I C communication legend
and data direction codes.
2
Table 4. I C Communication—Legend
SYMBOL
S
DESCRIPTION
START Condition
AD, 0
AD, 1
Sr
Select DS2482-100 for Write Access
Select DS2482-100 for Read Access
Repeated START Condition
STOP Condition
Not Acknowledged by Master: At some time when
receiving data, the master must signal an end of
data to the slave device. To achieve this, the master
does not acknowledge the last byte that it has
received from the slave. In response, the slave
releases SDA, allowing the master to generate the
STOP condition.
P
A
Acknowledged
A\
Not Acknowledged
(Idle)
<byte>
DRST
SRP
Bus Not Busy
Writing to the DS2482-100
To write to the DS2482-100, the master must access
the device in write mode, i.e., the slave address must
be sent with the direction bit set to 0. The next byte to
be sent is a command code, which, depending on the
command, may be followed by a command parameter.
The DS2482-100 acknowledges valid command codes
and expected/valid command parameters. Additional
bytes or invalid command parameters are never
acknowledged.
Transfer of One Byte
Command “Device Reset”, F0h
Command “Set Read Pointer”, E1h
Command “Write Configuration”, D2h
Command “1-Wire Reset”, B4h
Command “1-Wire Single Bit”, 87h
Command “1-Wire Write Byte”, A5h
Command “1-Wire Read Byte”, 96h
Command “1-Wire Triplet”, 78h
WCFG
1WRS
1WSB
1WWB
1WRB
1WT
Reading from the DS2482-100
To read from the DS2482-100, the master must access
the device in read mode, i.e., the slave address must
be sent with the direction bit set to 1. The read pointer
determines the register that the master reads from. The
master can continue reading the same register over
and over again, without having to readdress the device,
e.g., to watch the 1WB changing from 1 to 0. To read
from a different register, the master must issue the Set
Read Pointer command and then access the DS2482-
100 again in read mode.
Table 5. Data Direction Codes
Master-to-Slave Slave-to-Master
______________________________________________________________________________________ 17
Single-Channel 1-Wire Master
2
I C Communication Examples (continued)
Device Reset (After Power-Up)
S
AD,0
A
DRST
A
Sr
AD,1
A
<byte> A\
P
Activities that are underlined denote an optional read access to verify the success of the command.
Set Read Pointer (To Read from Another Register)
Case A: Valid Read Pointer Code
S
AD,0
A
SRP
A
C3h
A
P
DS482-10
C3h is the valid read pointer code for the Configuration Register.
Case B: Invalid Read Pointer Code
S
AD,0
A
SRP
A
E5h
A\
P
E5h is an invalid read pointer code.
Write Configuration (Before Starting 1-Wire Activity)
Case A: 1-Wire Idle (1WB = 0)
S
AD,0
A
WCFG
A
<byte>
A
Sr
AD,1
A
<byte> A\
P
Activities that are underlined denote an optional read access to verify the success of the command.
Case B: 1-Wire Busy (1WB = 1)
S
AD,0
A
WCFG
A\
P
The master should stop and restart as soon as the DS2482-100 does not acknowledge the command code.
1-Wire Reset (To Begin or End 1-Wire Communication)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling to Read the Result
S
AD,0
A
1WRS
A
P
(Idle)
S
AD,1
A
<byte> A\
P
In the first cycle, the master sends the command. Then the master waits (Idle) for the 1-Wire reset to complete. In
the second cycle, the DS2482-100 is accessed to read the result of the 1-Wire reset from the Status Register.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed, then Read the Result
S
AD,0
A
1WRS
A
Sr
AD,1
A
<byte>
A
<byte> A\
P
REPEAT UNTIL THE 1WB BIT HAS CHANGED TO 0.
Case C: 1-Wire Busy (1WB = 1)
S
AD,0
A
1WRS
A\
P
The master should stop and restart as soon as the DS2482-100 does not acknowledge the command code.
18 ______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
2
I C Communication Examples (continued)
1-Wire Single Bit (To Generate a Single Time Slot on the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S
AD,0
A
1WSB
A
<byte>
A
P
(Idle)
S
AD,1
A
<byte> A\
P
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the
result from the 1-Wire Single Bit command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S
AD,0
A
1WSB
A
<byte>
A
REPEAT UNTIL THE 1WB BIT
HAS CHANGED TO 0.
Sr
AD,1
A
<byte>
A
<byte> A\
P
When 1WB has changed from 1 to 0, the Status Register holds the valid result of the 1-Wire Single Bit command.
Case C: 1-Wire Busy (1WB = 1)
S
AD,0
A
1WSB
A\
P
The master should stop and restart as soon as the DS2482-100 does not acknowledge the command code.
1-Wire Write Byte (To Send a Command Code to the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S
AD,0
A
1WWB
A
33h
A
P
(Idle)
33h is the valid 1-Wire ROM function command for Read ROM. The idle time is needed for the 1-Wire function to
complete. There is no data read back from the 1-Wire line with this command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed.
S
AD,0
A
1WWB
A
33h
A
REPEAT UNTIL THE 1WB BIT
HAS CHANGED TO 0.
Sr
AD,1
A
<byte>
A
<byte> A\
P
When 1WB has changed from 1 to 0, the 1-Wire Write Byte command is completed.
Case C: 1-Wire Busy (1WB = 1)
S
AD,0
A
1WWB
A\
P
The master should stop and restart as soon as the DS2482-100 does not acknowledge the command code.
______________________________________________________________________________________ 19
Single-Channel 1-Wire Master
2
I C Communication Examples (continued)
1-Wire Read Byte (To Read a Byte from the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer After Idle Time
S
AD,0
A
1WRB
A
P
(Idle)
S
AD,0
A
SRP
A
E1h
A
Sr
AD,1
A
<byte> A\
P
The idle time is needed for the 1-Wire function to complete. Then set the read pointer to the Read Data Register
(code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line.
DS482-10
Case B: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer Before Idle Time
S
AD,0
A
1WRB
A
Sr
AD,0
A
SRP
A
E1h
A
P
(Idle)
S
AD,1
A
<byte> A\
P
The read pointer is set to the Read Data Register (code E1h) while the 1-Wire Read Byte command is still in
progress. Then, after the 1-Wire function is completed, the device is accessed to read the data byte that was
obtained from the 1-Wire line.
Case C: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S
AD,0
A
1WRB
A
REPEAT UNTIL THE 1WB BIT
HAS CHANGED TO 0.
Sr
AD,1
A
A
<byte>
A
<byte> A\
Sr
AD,0
A
SRP
E1h
A
Sr
AD,1
A
<byte> A\
P
Poll the Status Register until the 1WB bit has changed from 1 to 0. Then set the read pointer to the Read Data
Register (code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line.
Case D: 1-Wire Busy (1WB = 1)
S
AD,0
A
1WRB
A\
P
The master should stop and restart as soon as the DS2482-100 does not acknowledge the command code.
20 ______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
2
I C Communication Examples (continued)
1-Wire Triplet (To Perform a Search ROM Function on the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S
AD,0
A
1WT
A
<byte>
A
P
(Idle)
S
AD,1
A
<byte> A\
P
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the
result from the 1-Wire Triplet command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S
AD,0
A
1WT
A
<byte>
A
REPEAT UNTIL THE 1WB BIT
HAS CHANGED TO 0.
Sr
AD,1
A
<byte>
A
<byte> A\
P
When 1WB has changed from 1 to 0, the Status Register holds the valid result of the 1-Wire Triplet command.
Case C: 1-Wire Busy (1WB = 1)
S
AD,0
A
1WT
A\
P
The master should stop and restart as soon as the DS2482-100 does not acknowledge the command code.
time must not exceed 1000ns at standard speed and
Applications Information
300ns at fast speed. Assuming maximum rise time, the
SDA and SCL Pullup Resistors
SDA is an open-drain output on the DS2482-100 that
requires a pullup resistor to realize high-logic levels.
Because the DS2482-100 uses SCL only as input (no
clock stretching), the master can drive SCL either
through an open-drain/-collector output with a pullup
resistor or a push-pull output.
maximum resistor value at any given capacitance C is
B
calculated as:
R
= 1000ns/[C x ln(7/3)] (standard speed)
B
PMAXS
R
= 300ns/[C x ln(7/3)] (fast speed)
B
PMAXF
For a bus capacitance of 400pF, the maximum pullup
resistor values are 2.95kΩ at standard speed and 885Ω
at fast speed. A value between 1.7kΩ and 2.95kΩ
meets all requirements at standard speed.
Pullup Resistor R Sizing
P
2
According to the I C specification, a slave device must
be able to sink at least 3mA at a V of 0.4V. This DC
Because an 885Ω pullup resistor, as would be required
to meet the rise time specification at fast speed and
OL
condition determines the minimum value of the pullup
resistor as:
400pF bus capacitance, is lower than R
at 5.5V, a
P(MIN)
different approach is necessary. The “MAX LOAD AT
R
= (V
- 0.4V)/3mA
P(MIN)
CC
MIN R FAST MODE” line in Figure 11 is generated by
P
With an operating voltage of 5.5V, the minimum value
first calculating the minimum pullup resistor at any
for the pullup resistor is 1.7kΩ. The “MINIMUM R ” line
P
given operating voltage (“MINIMUM R ” line) and then
P
in Figure 11 shows how the minimum pullup resistor
changes with the operating voltage.
calculating the respective bus capacitance that yields a
300ns rise time.
2
For I C systems, the rise time and fall time are mea-
Only for pullup voltages of 3V and lower can the maximum
permissible bus capacitance of 400pF be maintained. A
sured from 30% to 70% of the pullup voltage. The maxi-
mum bus capacitance, C , is 400pF. The maximum rise
B
______________________________________________________________________________________ 21
Single-Channel 1-Wire Master
reduced bus capacitance of 300pF is acceptable for
pullup voltages of 4V and lower. For fast speed operation
at any pullup voltage, the bus capacitance must not
exceed 200pF. The corresponding pullup resistor value
at the voltage is indicated by the “MINIMUM R ” line.
P
V
CC
CURRENT-LIMITING
RESISTOR
R *
P
REFER TO APPLICATION
NOTE 4206
SDA
SCL
2
(I C PORT)
PCTLZ
IO
DS482-10
μC
DS2482-100
1-Wire DEVICE #1
1-Wire LINE
AD0
AD1
(WITH SPECIAL POWER
REQUIREMENTS)
V
CC
SDA
SCL
PCTLZ
DS2482-100
1-Wire LINE
1-Wire
DEVICE #2
V
CC
AD0
AD1
IO
2
*R = I C PULLUP RESISTOR (SEE THE APPLICATIONS INFORMATION SECTION FOR R SIZING).
P
P
Figure 10. Application Schematic
2000
1600
1200
800
500
400
300
200
100
0
MINIMUM R
P
MAX LOAD AT MIN R FAST MODE
P
400
0
1
2
3
4
5
PULLUP VOLTAGE (V)
2
Figure 11. I C Fast Mode Pullup Resistor Selection Chart
22 ______________________________________________________________________________________
Single-Channel 1-Wire Master
DS482-10
Pin Configurations
TOP VIEW
TOP MARK
(BUMP SIDE DOWN)
DS2482-100
DS2482-100
1
2
3
1
2
3
TOP VIEW
+
+
+
A
B
C
A
B
C
V
1
2
3
4
8
7
6
5
AD0
CC
IO
PCTLZ
SCL
AD1
SDA
AD0
2 4 8 2 1
y y w w r r
# # # x x
AD1
DS2482-100
GND
SCL
PCTLZ
SDA
V
CC
GND
IO
SO (150 mils)
WLP
WLP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
8 SO (150 mils)
9 WLP
PACKAGE CODE
S8+4
DOCUMENT NO.
21-0041
W92A1+1
21-0067
______________________________________________________________________________________ 23
Single-Channel 1-Wire Master
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
Updated the Features bullets.
Updated the V and R values in the Electrical Characteristics table.
1
2
IL1
WPU
Minor corrections to Figure 1; updated the Detailed Description section to
clarify information about the active pullup and strong pullup.
5
061208
5
Replaced the Strong Pullup (SPU) section description and replaced Figure 4.
Removed timing inaccuracies in Figure 8.
Created newer template-style data sheet.
Replaced Figure 8.
7
DS482-10
14
All
16
6
7/08
Deleted the 1-Wire line termination resistor and references to it in the Typical
Operating Circuit and in Figure 11.
7
8
8/08
1, 23
• Corrected the recommendation for using active pullup (APU).
• Removed the references to presence-pulse masking.
1–9, 11–14, 18, 23,
24
11/09
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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