DS2741 [MAXIM]
Current Monitor and Accumulator with Integrated Sense Resistor; 电流监测器和累加器，内置检流电阻
| 型号： | DS2741 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Current Monitor and Accumulator with Integrated Sense Resistor |
| 文件： | 总9页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 8/08
Current Monitor and Accumulator with
Integrated Sense Resistor
DS2741
General Description
Features
♦ Complete, Low-Cost, Integrated Current-Sensing
and Accumulation Solution with Serial Digital
Output
The DS2741 current monitor/accumulator is a complete
current-sensing, measuring, and accumulation device
tailored for cost-sensitive, battery-powered applications
in a small 3mm x 3mm TDFN package. As a result, the
DS2741 is a key component in battery-charge control
and remaining capacity-estimation applications.
♦ On-Board 38mΩ Sense Resistor
♦ Current Measurement:
Signed 10-Bit Bidirectional Measurement
±±2.A Dꢀnamic Range
2
Through its I C interface, the DS2741 gives the host
system access to current measurement and accumula-
tion registers. The 7-bit slave address is factory pro-
grammable, allowing up to 128 devices to be individually
addressed by the host system.
1% Error at +±.°C
±% Error Over Temperature
♦ Current Accumulation:
02±47mAhr LSB
Applications
±821Ahrs ꢁull-Scale Range
Cell Phones
±
♦ Industrꢀ-Standard I C Interface with ꢁactorꢀ-
PDAs
Programmable Slave Address
Battery Monitor/Rechargers
♦ ±2.V to 42.V Single-Supplꢀ Operation
♦ Low-Power Consumption:
Active Current: 60µA (tꢀp)
Sleep Current: 1µA (tꢀp)
Ordering Information
PART
TEMP RANGE
-20°C to +70°C
-20°C to +70°C
PIN-PACKAGE
14 TDFN-EP*
14 TDFN-EP*
DS2741N+
DS2741N+T
♦ -±0°C to +70°C Operating Range
♦ 14-Pin TDꢁN (3mm x 3mm x 028mm)
+Denotes a lead-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Typical Operating Circuit
Pin Configuration
TOP VIEW
RS- RS- RS- RS- SLP GND DNC
14 13 12 11 10
9
8
CHARGER/
LOAD
RS+
RS-
DC-DC
CONVERTER
Li +
BATTERY
DS2741
V
CC
1.8V
DS2741
SLP
2.2kΩ
2.2kΩ
EP*
0.1μF
SDA
SCL
MICROPROCESSOR
GND
1
2
3
4
5
6
7
RS+ RS+ RS+ RS+ SDA SCL
V
CC
TDꢁN
*EXPOSED PAD
________________________________________________________________ Maxim Integrated Products
1
ꢁor pricing, deliverꢀ, and ordering information, please contact Maxim Direct at 1-888-6±9-464±,
or visit Maxim’s website at www2maxim-ic2com2
Current Monitor and Accumulator with
Integrated Sense Resistor
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
Relative to GND ...............-0.5V to +6.0V
Pulsed Internal Sense Resistor
CC
Voltage Range on SDA, SCL,
RS+, RS-, SLP Relative to GND.....-0.5V to (V + 0.5V), not to
Current.................................. 10A for <100µs/s, <1000 pulses
Operating Temperature Range ...........................-20°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
CC
exceed +6.0V
Continuous Internal Sense Resistor Current ...................... 2.7A
DS2741
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -20°C to +70°C.)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
2.5
1.5
TYP
MAX
UNITS
V
CC
(Note 1)
4.5
V
V
V
Input Logic-High: SCL, SDA
Input Logic-Low: SCL, SDA
V
IH
V
0.4
IL
0.7 x
Input Logic-High: SLP
V
V
V
IH
V
CC
0.3 x
Input Logic-Low: SLP
V
IL
V
CC
Power-Up Ramp Time from
t
25
ms
RAMP
0V to V
CCMIN
DC ELECTRICAL CHARACTERISTICS
(2.5V ≤ V
≤ 4.5V, T = -20°C to +70°C.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
SLP = SCL = SDA = V
MIN
TYP
60
1
MAX
90
UNITS
μA
Active Current
I
ACTIVE
CC
Sleep-Mode Current
Output Logic-Low: SDA
I
SLP = 0V
= 4mA (Note 1)
2
μA
SLEEP
V
I
0.4
V
OL
OL
Internal Current-Sense Resistor
Value
R
+25°C
38
45
mꢀ
SNS
Current Resolution
I
2.64
2.7
1
mA
A
LSB
Current Full-Scale Magnitude
Current-Sense Accuracy at +25°C
I
(Note 2)
2.54
FS
A
I
at 1.5A
2
4
%
TL
SENSE
Current-Sense Accuracy from
0°C to +70°C
A
I
at 1.5A
2
%
TL
SENSE
Current Sampling Rate
Accumulator Resolution
t
(Note 3)
200
0.247
±1
μs
CSR
q
mAh
CA
t
t
(Note 4)
(Note 4)
±3
ERR1
ERR2
Internal Time-Base Accuracy
Current-Sense Offset
%
±6.5
+10
Measured with RS+ and RS- shorted
-10
mA
±
_______________________________________________________________________________________
Current Monitor and Accumulator with
Integrated Sense Resistor
DS2741
TEMPERATURE SENSOR CHARACTERISTICS
(V
CC
= +2.5V to +4.5V, T = -20°C to +70°C, unless otherwise noted.)
A
PARAMETER
Temperature Error
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5
°C
±
AC ELECTRICAL CHARACTERISTICS: I C INTERꢁACE
(2.5V ≤ V
≤ 4.5V, T = -20°C to +70°C, timing referenced to V
and V
. See Figure 4.)
IH(MIN)
CC
A
IL(MAX)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 5)
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
μs
μs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
0
μs
μs
μs
ns
μs
LOW
t
HIGH
t
0.9
HD:DAT
Data Setup Time
START Setup Time
t
100
0.6
SU:DAT
t
SU:STA
20 +
SDA and SCL Rise Time
t
(Note 6)
(Note 6)
300
300
ns
R
0.1C
B
20 +
SDA and SCL Fall Time
STOP Setup Time
t
ns
μs
pF
F
0.1C
B
t
0.6
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 6)
400
B
Note 1: All voltages are referenced to GND. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note ±: Compensation of the internal sense resistor value for initial tolerance and temperature coefficient of -20°C to +70°C can
reduce the maximum reportable magnitude to 2.5A.
Note 3: Current sampling ceases for 2.5ms every 144ms to allow the ADC to measure temperature.
Note 4: Typical value for t
is specified at 3.6V and +25°C, max value is specified for 0°C to +50°C. Max value for t
is
ERR1
ERR2
specified for -20°C to +70°C.
Note .: Interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with standard-mode
2
I C timing.
Note 6: C —Total capacitance of one bus line in pF; timing referenced to 0.1 x V
and 0.9 x V
.
B
CC
CC
_______________________________________________________________________________________
3
Current Monitor and Accumulator with
Integrated Sense Resistor
Typical Operating Characteristics
(V
CC
= +2.5V to +4.5V, T = -20°C to +70°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SLEEP-MODE CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
70
2.0
1.5
1.0
0.5
0
70
60
50
40
30
20
10
0
SLP = SDA = SCL = V
SLP = SDA = SCL = V = +3.5V
CC
7
SDA = SCL = V
SLP = GND
CC
CC
T
A
= +25°C
60
50
40
30
20
10
0
T
A
= +25°C
2.5
3.0
3.5
4.0
4.5
2.5
3.0
3.5
4.0
4.5
-20 -10
0
10 20 30 40 50 60 70
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT
vs. SCL FREQUENCY
DISTRIBUTION OF CURRENT-SENSE
OFFSET
INITIAL CURRENT-SENSE ACCURACY
DISTRIBUTION
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
247 SAMPLES
I
AT 1.5A
SENSE
SLP = SDA = SCL = V = +3.5V
CC
247 SAMPLES
T
= +25°C
A
0
50 100 150 200 250 300 350 400
SCL FREQUENCY (kHz)
-10
-7
-4
-1
2
5
8
-2.0 -1.4 -0.8 -0.2 0.4 1.0 1.6
CURRENT-SENSE ACCURACY (%)
CURRENT-SENSE OFFSET (mA)
4
_______________________________________________________________________________________
Current Monitor and Accumulator with
Integrated Sense Resistor
DS2741
Pin Description
PIN
NAME
FUNCTION
Sense Resistor High Side. Connection to high side of internal 38mꢀ sense resistor. All RS+ pins
must be connected together.
1–4
RS+
2
Serial Data Input/Output. SDA is the input/output pin for the I C serial interface. The SDA pin is an
open-drain output and requires an external pullup resistor.
5
SDA
SCL
2
6
7
8
9
Serial Clock Input. SCL is used to synchronize data movement on the I C serial interface.
V
CC
Supply Voltage. Power-supply input.
Do Not Connect
DNC
GND
Ground
Sleep Input (Active Low). When taken low, the DS2741 is placed in a low-power sleep state where
2
all internal circuitry including the I C bus is disabled. Toggling the SLP pin low and then back high
10
SLP
2
resets the device and the I C bus logic.
Sense Resistor Low Side. Connection to low side of internal 38mꢀ sense resistor. All RS- pins
must be connected together.
11–14
—
RS-
EP
Exposed Pad. Can be left floating.
Block Diagram
V
CC
SLP
2
SDA
SCL
I C
VOLTAGE
REFERENCE
POWER
CONTOL
INTERFACE
CURRENT REGISTER
10-BIT PLUS SIGN
A/D CONVERTER
CURRENT ACCUMULATOR
REGISTER
DS2741
TEMPERATURE
REGISTER
38mΩ
GND
RS+
RS-
_______________________________________________________________________________________
.
Current Monitor and Accumulator with
Integrated Sense Resistor
to be the filtered voltage drop across the sense resis-
Detailed Description
tor. A positive V value indicates current is flowing into
RS
The DS2741 is a small, low-cost, current-sensing and
accumulation IC that is intended for current-monitoring
applications. The differential voltage measured across
the on-chip 38mΩ sense resistor is digitized by an
internal ADC that provides an accurately scaled digital
signed 10-bit value that represents bidirectional current
up to 2.5A. The measured current result is reported in
an internal SRAM register that can be read using the
the battery (charging), while a negative V value indi-
RS
cates current is flowing out of the battery (discharging).
V
is measured with a signed resolution of 10 bits.
RS
The current register is updated in two’s-complement
format every 22.7ms with an average of eight readings.
Current measurements outside the register range are
reported at the range limit. Figure 1 shows the format of
the current register.
DS2741
2
I C interface. After each current measurement, the
signed result value is added to an accumulator in order
to maintain a signed accumulated current value with a
0.247mAhr LSB and a full-scale range of 8.1Ahrs. The
device can be placed into a low-power sleep mode
when current measurements are not needed.
The DS2741 maintains the current register in units of
amps, with a resolution of 2.64mA and full-scale range
of no less than 2.5A. The DS2741 automatically com-
pensates for internal sense resistor process variations
and temperature effects when reporting current.
Power Modes
The DS2741 has two power modes: active and sleep.
While in active mode, the DS2741 continually measures
and accumulates current and provides data to the host
Current Accumulator
The current accumulator facilitates remaining capacity
estimation by tracking the net current flow into and out of
the battery. Current flow into the battery increments the
current accumulator, while current flow out of the battery
decrements it. The DS2741 maintains the current accu-
mulator 0.247mAhrs resolution and full-scale value of
8.1Ahrs range. Data is maintained in the current accu-
mulator in two’s-complement format. Figure 2 shows the
format of the current accumulator. The current accumu-
lator is a read/write register that can be altered by the
host system as needed. The Current Accumulator regis-
ter is not reset when the DS2741 is in sleep mode.
2
system through its I C interface. In sleep mode, the
DS2741 ceases these activities. The DS2741 enters
sleep mode whenever an active-low signal is applied to
the SLP pin and remains in sleep as long as the SLP
pin is held low. Active mode resumes when the SLP pin
is returned to a logic-high level. The SLP pin resets the
Current and Temperature registers, but not the Current
Accumulator register.
Current Measurement
In active mode, the DS2741 continually measures the cur-
rent flow into and out of the battery by measuring the volt-
age drop across the internally integrated 38mΩ
current-sense resistor. The DS2741 considers the voltage
Temperature Measurement
The on-board temperature sensor measures tempera-
tures from +127°C to -128°C. The LSb of register 14h
has a 1°C bit weight. See Figure 3 for the temperature
register’s two’s-complement format.
difference between pins RS+ and RS- (V = V
RS
- V
)
RS+
RS-
MSB—ADDRESS 16h
LSB—ADDRESS 17h
9
8
7
6
5
4
3
2
1
0
S
2
2
2
2
2
2
2
2
2
2
X
X
X
X
X
MSb
LSb
MSb
LSb
Figure 1. Current Register Format
MSB—ADDRESS 10h
LSB—ADDRESS 11h
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MSb
LSb
MSb
LSb
Figure 2. Current Accumulator Register Format
ADDRESS 14h
6
5
4
3
2
1
0
S
2
2
2
2
2
2
2
MSb
LSb
Figure 3. Temperature Register Format
_______________________________________________________________________________________
6
Current Monitor and Accumulator with
Integrated Sense Resistor
DS2741
Slave Devices: Slave devices send and receive
Registers
The DS2741 has 2-byte registers for current measure-
ment and accumulation. When the MSB of a 2-byte reg-
ister is read, both the MSB and LSB are latched and
held for the duration of the read data command to pre-
vent updates during the read and ensure synchroniza-
tion between the two register bytes. For consistent
results, always read the MSB and the LSB of a 2-byte
register during the same read data command sequence.
data at the master’s request.
Bus Idle or Not Busꢀ: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. When the bus is idle
it often initiates a low-power mode for slave devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low, while SCL
remains high, generates a START condition. See
Figure 4 for applicable timing.
Table 12 Register Map
ADDRESS
(HEX)
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high, while SCL
remains high, generates a STOP condition. See
Figure 4 for applicable timing.
DESCRIPTION
READ/WRITE
00h to 0Fh Reserved
—
R/W
—
R
10h and 11h Current Accumulator Register
12h and 13h Reserved
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one.
Repeated STARTs are commonly used during read
operations to identify a specific memory address to
begin a data transfer. A repeated START condition
is issued identically to a normal START condition.
See Figure 4 for applicable timing.
14h
15h
Temperature Register
Reserved
—
R
16h and 17h Current Register
18h to FFh Reserved
—
2
I C Bus Interface
2
I C Definitions
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain
valid and unchanged during the entire high pulse of
SCL plus the setup and hold-time requirements (see
Figure 4). Data is shifted into the device during the
rising edge of the SCL.
The following terminology is commonly used to
2
describe I C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
SDA
t
BUF
t
t
F
SP
t
HD:STA
t
LOW
SCL
t
HIGH
t
SU:STA
t
t
R
t
HD:STA
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 4. I C Timing Diagram
_______________________________________________________________________________________
7
Current Monitor and Accumulator with
Integrated Sense Resistor
Bit Read: At the end a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 4) before the next rising edge
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse, and the data bit is valid at the rising
edge of the current SCL pulse. Remember that the
master generates all SCL clock pulses, including
when it is reading bits from the slave.
7-BIT SLAVE ADDRESS
0
1
1
0
1
0
0
R/W
MOST
SIGNIFICANT BIT
DETERMINES
READ OR WRITE
DS2741
Figure 5. DS2741 Slave Address Byte
2
Acknowledgement (ACK and NACK): An acknowl-
edgement (ACK) or not acknowledge (NACK) is
always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read
or the slave during a write operation) performs an
ACK by transmitting a zero during the 9th bit. A
device performs a NACK by transmitting a one dur-
ing the 9th bit. Timing for the ACK and NACK is
identical to all other bit writes (see Figure 4). An
ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a
read sequence or as an indication that the device is
not receiving data.
I C device and ignores the communications until the
next start condition is sent. This value can be
changed at the factory to match the user’s need.
2
Contact the factory for more details on custom I C
device addresses for the DS2741.
2
Memorꢀ Address: During an I C write operation,
the master must transmit a memory address to iden-
tify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following
the slave address byte.
2
I C Communication
Bꢀte Write: A byte write consists of 8 bits of infor-
mation transferred from the master to the slave
(most significant bit first) plus a 1-bit acknowledge-
ment from the slave to the master. The 8 bits trans-
mitted by the master are done according to the
bit-write definition and the acknowledgement is read
using the bit-read definition.
2
See Figure 6 for examples of I C communication.
Writing a Single Bꢀte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the
byte of data, and generate a STOP condition.
Remember that the master must read the slave’s
acknowledgement during all byte-write operations.
Bꢀte Read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit-read definition, and the master
transmits an ACK using the bit-write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so that the slave returns control of SDA to the master.
Writing Multiple Bꢀtes to a Slave: To write multiple
bytes to a slave, the master generates a START con-
dition, writes the slave address byte (R/W = 0),
writes the memory address, writes up to 8 data
bytes, and generates a STOP condition.
Reading a Single Bꢀte from a Slave: Unlike the
write operation that uses the memory address byte
to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the
slave the master generates a START condition,
writes the slave address byte with R/W = 1, reads
the data byte with a NACK to indicate the end of the
transfer, and generates a STOP condition.
2
Slave Address Bꢀte: Each slave on the I C bus
responds to a slave addressing byte sent immedi-
ately following a START condition. The slave
address byte (Figure 5) contains the slave address
in the most significant 7 bits and the R/W bit in the
least significant bit.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master
generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated
START condition, writes the slave address byte
(R/W = 1), reads data with ACK or NACK as applica-
The DS2741’s default factory programmed 7-bit
slave address is 0110100b (binary) or 68h (hex). By
writing the correct slave address with R/W = 0, the
master indicates it will write data to the slave. If
R/W = 1, the master reads data from the slave. If an
incorrect slave address is written, the DS2741
assumes the master is communicating with another
8
_______________________________________________________________________________________
Current Monitor and Accumulator with
Integrated Sense Resistor
DS2741
COMMUNICATIONS KEY
NOTES
WHITE BOXES INDICATE THE MASTER IS
CONTROLLING SDA
S
P
START
STOP
A
ACK
1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST.
SHADED BOXES INDICATE THE SLAVE IS
CONTROLLING SDA
2) THE FIRST BYTE SENT AFTER A START CONDITION
IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY
THE READ/WRITE BIT.
N
NACK
REPEATED
START
X
X
X
X
X
X
X
X
8-BIT ADDRESS OR DATA
SR
WRITE TWO BYTES WITH A SINGLE TRANSACTION TO SLAVE ADRESS 68h
MEMORY ADDRESS
S
0
1
1
0
1
0
0
0
A
A
DATA
A
DATA
A
P
N
A
READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER FROM SLAVE ADDRESS 68h
MEMORY ADDRESS SR
S
0
1
1
0
1
0
0
0
A
A
0
1
1
0
1
0
0
1
A
DATA
DATA
P
READ TWO BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER FROM SLAVE ADDRESS 68h
MEMORY ADDRESS SR
S
0
1
1
0
1
0
0
0
A
A
0
1
1
0
1
0
0
1
A
DATA
N
P
2
Figure 6. I C Communications Examples
ble, and generates a STOP condition. See Figure 6
for a read example using the repeated START condi-
tion to specify the starting memory location.
Applications Information
Power-Supply Decoupling
To achieve best results, it is recommended that the power
supply is decoupled with a 0.01µF or a 0.1µF capacitor.
Use high-quality, ceramic, surface-mount capacitors, and
Reading Multiple Bꢀtes from a Slave: The read
operation can be used to read multiple bytes with a
single transfer. When reading bytes from the slave,
the master simply ACKs the data byte if it desires to
read another byte before terminating the transaction.
After the master reads the last byte, it NACKs to
indicate the end of the transfer and generates a
STOP condition. This can be done with or without
modifying the address counter’s location before the
read cycle. The DS2741’s address counter does not
wrap on page boundaries during read operations,
but the counter rolls from its uppermost memory
address FFh to 00h if the last memory location is
read during the read transaction.
mount the capacitors as close as possible to the V and
CC
GND pins to minimize lead inductance.
SDA and SCL Pullup Resistors
SDA is an open-collector output on the DS2741 that
requires a pullup resistor to realize high logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be used
for SCL. Pullup resistor values should be chosen to
ensure that the rise and fall times listed in the AC elec-
trical characteristics are within specification.
Package Information
For the latest package outline information and land patterns, go
to www2maxim-ic2com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO2
14 TDFN-EP
T1433+2
±1-0137
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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