DS28E16X-ST [MAXIM]

1-Wire Secure SHA-3 Authenticator;


型号：	DS28E16X-ST
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	1-Wire Secure SHA-3 Authenticator
文件：	总15页 (文件大小：407K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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DS28E16

1-Wire Secure SHA-3 Authenticator

General Description

The DS28E16 secure authenticator combines FIPS202-

compliant Secure Hash Algorithm (SHA-3) challenge and

response authentication with secured EEPROM.

Beneﬁts and Features

● Robust Countermeasures Protect Against Security

Attacks

• All Stored Data Cryptographically Protected from

Discovery

The device provides a core set of cryptographic tools

derived from integrated blocks including a SHA-3 engine,

256 bits of secured user EEPROM, a decrement-only

counter and a unique 64-bit ROM identification number

(ROM ID). The unique ROM ID is used as a fundamental

input parameter for cryptographic operations and serves

as an electronic serial number within the application. The

● Efficient Secure Hash Algorithm Authenticates

Peripherals

• FIPS 202-Compliant SHA-3 Algorithm for

Challenge/Response Authentication

• FIPS 198-Compliant Keyed-Hash Message

Authentication Code (HMAC)

device communicates over the single-contact 1-Wire bus.

● Supplemental Features Enable Easy Integration into

End Applications

The communication follows the 1-Wire protocol with the

ROM ID acting as node address in the case of a multidevice

1-Wire network.

• 17-Bit One-Time Settable, Nonvolatile Decrement-

Only Counter with Authenticated Read

• Secure Storage for Secrets

• 256 Bits of Secure EEPROM for User Data

• Unique and Unalterable Factory Programmed

64-Bit Identiﬁcation Number (ROM ID)

• Advanced 1-Wire Protocol Minimizes Interface to

Single Contact

Applications

● Medical Tools/Accessories Authentication and

Calibration

● Accessory and Peripheral Secure Authentication

● Battery Authentication and Charge Cycle Tracking

• Full-Time Overdrive Communication Speed

• Internal Parasite Power Capacitor

• Operating Range: 1.71V–3.63V, -40°C to +85°C

• WLP and TDFN-EP Packages

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

• ±8kV HBM ESD Protection (typ)

• 3.5µA (typ) Input Load Current

Typical Application Circuit

Ordering Information appears at end of data sheet.

I C

SDA

SCL

DS2477

PORT

µC

GPIO

GND

DS28E16

GND

19-100438; Rev 1; 3/19

DS28E16

1-Wire Secure SHA-3 Authenticator

Absolute Maximum Ratings

Voltage Range on Any Pin Relative to GND..........-0.5V to 4.0V

Maximum Current into Any Pin........................... -20mA to 20mA

Operating Temperature Range........................... -40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range............................ -40°C to +125°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow).......................................+260°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Information

6 WLP

Package Code

Z60E1+1

Outline Number

21-100327

Land Pattern Number

Thermal Resistance, Four-Layer Board:

Refer to Application Note 1891

Junction to Ambient (θ

)

95.15°C/W

N/A

Junction to Case (θ

)

6 TDFN-EP

Package Code

Outline Number

T633+2

21-0137

90-0058

Land Pattern Number

Thermal Resistance, Single-Layer Board:

Junction to Ambient (θ

)

55°C/W

9°C/W

Junction to Case (θ

)

Thermal Resistance, Four-Layer Board:

Junction to Ambient (θ

)

42°C/W

9°C/W

Junction to Case (θ

)

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.

For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

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DS28E16

1-Wire Secure SHA-3 Authenticator

Electrical Characteristics

(Limits are 100% tested at T = +25ºC and T = +85ºC. Limits over the operating temperature range and relevant supply voltage

range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production

tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)

PARAMETER

IO PIN: GENERAL DATA

1-Wire Pullup Voltage

1-Wire Pullup Resistance

Input Capacitance

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

System requirement

1.71

300

3.63

750

PUP

(Note 1)

PUP

(Notes 1, 2)

1700

3.5

µA

Input Load Current

IO pin at V

PUP

High-to-Low Switching

Threshold

0.65 x

(Notes 3, 4)

(Note 5)

PUP

0.18 x

Input Low Voltage

PUP

Low-to-High Switching

Threshold

0.75 x

(Notes 3, 6)

(Notes 3, 7)

PUP

Switching Hysteresis

Output Low Voltage

IO PIN: 1-Wire INTERFACE

Recovery Time

0.3

= 4mA (Note 8)

0.4

(Note 9)

μs

REC

Time Slot Duration

(Note 10)

SLOT

IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE

Reset Low Time

System requirement

(Note 11)

μs

RSTL

Reset High Time

RSTH

Presence-Detect Sample Time

IO PIN: 1-Wire WRITE

Write-Zero Low Time

Write-One Low Time

IO PIN: 1-Wire READ

Read Low Time

(Note 12)

MSP

(Note 13)

μs

W0L

0.25

W1L

(Note 14)

0.25

2 - δ

μs

Read Sample Time

+ δ

MSR

STRONG PULLUP OPERATION

Strong Pullup Current

Strong Pullup Voltage

Read Memory Time

Write Memory Time

(Note 15)

SPU

1.71

SPU

Short Write Memory Time

Computation Time

WMS

CMP

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DS28E16

1-Wire Secure SHA-3 Authenticator

Electrical Characteristics (continued)

(Limits are 100% tested at T = +25ºC and T = +85ºC. Limits over the operating temperature range and relevant supply voltage

range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production

tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)

PARAMETER

EEPROM

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Write/Erase Cycles (Endurance)

Data Retention

(Note 16)

= +85°C (Note 17)

100K

years

POWER-UP

Power-Up Time

System requirement (Note 18)

OSCWUP

Note 1: System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system

and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire

recovery times.

Note 2: Value represents the typical parasite capacitance when V

is first applied. Once the parasite capacitance is charged, it

PUP

does not affect normal communication.

Note 3:

, V , and V

are a function of the internal supply voltage, which is a function of V

, R

, 1-Wire timing, and

TL TH

PUP PUP

capacitive loading on IO. Lower V

, higher R

, shorter t

, and heavier capacitive loading all lead to lower values

PUP

REC

of V , V , and V

TL TH

Note 4: Voltage below which, during a falling edge on IO, a logic-zero is detected.

Note 5: The voltage on IO must be less than or equal to V at all times the master is driving IO to a logic-zero level.

ILMAX

Note 6: Voltage above which, during a rising edge on IO, a logic-one is detected.

Note 7: After V is crossed during a rising edge on IO, the voltage on IO must drop by at least V

to be detected as logic-zero.

Note 8: The I-V characteristic is linear for voltages less than 1V.

Note 9: System requirement. Applies to a single device attached to a 1-Wire line.

Note 10: Defines maximum possible bit rate. Equal to 1/(t

+ t

W0LMIN

RECMIN

Note 11: An additional reset or communication sequence cannot begin until the reset high time has expired.

Note 12: System requirement. Interval after t during which a bus master can read a logic 0 on IO if there is a device present.

RSTL

The power-up presence detect pulse can be outside this interval, but completes within 2ms after power-up.

Note 13: System requirement. ε in Figure 4 represents the time required for the pullup circuitry to pull the voltage on IO up from V to

. The actual maximum duration for the master to pull the line low is t

+ t - ε and t

+ t - ε, respectively.

W1LMAX

W0LMAX F

Note 14: System requirement. δ in Figure 4 represents the time required for the pullup circuitry to pull the voltage on IO up from V

to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is t

+ t .

RLMAX

Note 15: Current drawn from IO during a SPU operation interval. The pullup circuit on IO during the SPU operation interval should

be such that the voltage at IO is greater than or equal to V . A low-impedance bypass of R activated during the

SPUMIN

PUP

SPU operation is the recommended way to meet this requirement.

Note 16: Write-cycle endurance is tested in compliance with JESD47H.

Note 17: Data retention is tested in compliance with JESD47H.

Note 18: 1-Wire communication should not take place for at least t

.after V

reaches V

min.

OSCWUP.

PUP

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DS28E16

1-Wire Secure SHA-3 Authenticator

Pin Conﬁguration

TOP VIEW

DNC DNC DNC

DS28E16

GND

DS28E16

DNC

TDFN-EP

3mm x 3mm

WLP

IO GND

Pin Description

NAME

FUNCTION

TDFN

1, 4, 5, 6

WLP

—

DNC

Do Not Connect

1-Wire IO

A1, B1

A2, A3,

B2, B3

GND

Ground Reference. Connect all contacts to GND.

Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for proper operation.

Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information

—

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DS28E16

1-Wire Secure SHA-3 Authenticator

Functional Diagram

PARASITE

POWER

DS28E16

64-BIT ROM ID

BUFFER

1-WIRE

INFC

SHA3-256

CMD

SECRET

E2 ARRAY

USER MEMORY

DECREMENT COUNTER

Detailed Description

Design Resource Overview

The DS28E16 integrates the Maxim DeepCover® capabil-

ity to protect all device stored data from invasive discovery.

In addition to the SHA-3 engine for signatures, 256-bit

EEPROM for user memory, SHA-3 secret storage, 17-bit

decrement counter, and control registers. The device oper-

ates from a 1-Wire interface with a parasitic supply by way

of an internal capacitor.

Operation of the DS28E16 involves use of device

EEPROM and execution of device function commands.

The following section provides an overview including the

decrement counter. Refer to the DS28E16 Security User

Guide for details.

DeepCover is a registered trademark of Maxim Integrated

Products, Inc.

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DS28E16

1-Wire Secure SHA-3 Authenticator

Memory

Asecured EEPROM array provides SHA-3 secret storage,

along with a decrement counter, and/or general-purpose,

user-programmable memory. Depending on the memory

space, there are either default or user-programmable

options to set protection modes.

66h

FROM ROM FUNCTIONS

FLOW CHART

MASTER Tx

COMMAND START

COMMAND

START?

MASTER Tx INPUT

LENGTH BYTE

Function Commands

MASTER Tx COMMAND BYTE

After a 1-Wire reset/presence cycle and ROM function

command sequence is successful, a command start

can be accepted and then followed by a device function

command. In general, these commands follow Figure 1.

Within this diagram, the data transfer is verified when writ-

ing and reading by a 16-bit CRC (CRC-16). The CRC-16

is computed as described in Maxim's Application Note 27:

Understanding and Using Cyclic Redundancy Checks

with Maxim 1-Wire and iButton Products..

MASTER Tx

PARAMETER BYTE(S)

MASTER Rx CRC-16 (INVERTED

OF COMMAND START, LENGTH,

COMMAND, AND PARAMETERS)

MASTER Tx RELEASE BYTE

SLAVE Rx AAh

RELEASE BYTE?

Decrement Counter

DELAY WITH STRONG PULLUP

The optional 17-bit decrement counter can be written one

time on a page of memory. A dedicated device function

command is used to decrement the count value by one

with each call. Once the count value reaches a value of

0, no additional decrements are possible.

MASTER Rx FFh DUMMY BYTE

MASTER Rx OUTPUT

LENGTH BYTE

MASTER Rx RESULT BYTE

MASTER Rx DATA BYTE(S)

1-Wire Bus System

The 1-Wire bus is a system that has a single bus master

and one or more slaves. In all instances, the DS28E16 is a

slave device. The bus master is typically a microcontroller

or a coprocessor like the DS2477. The discussion of this

bus system is broken down into three topics: hardware

configuration, transaction sequence, and 1-Wire signaling

(signal types and timing). The 1-Wire protocol defines bus

transactions in terms of the bus state during specific time

slots that are initiated on the falling edge of sync pulses

from the bus master.

MASTER Rx CRC-16 (INVERTED

OF LENGTH, RESULT, AND DATA)

MASTER

Rx 1s

MASTER Tx

RESET?

TO ROM FUNCTIONS

FLOW CHART

Figure 1. Device Function Flow Chart

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DS28E16

1-Wire Secure SHA-3 Authenticator

Hardware Conﬁguration

Transaction Sequence

The 1-Wire bus has only a single line by definition; it is

important that each device on the bus can drive it at the

appropriate time. To facilitate this, each device attached

to the 1-Wire bus must have open-drain or three-state

outputs. The 1-Wire port of the DS28E16 is open drain

with an internal circuit equivalent.

The protocol for accessing the DS28E16 through the

1-Wire port is as follows:

● Initialization

● ROM Function command

● Device Function command

● Transaction/data

A multidrop bus consists of a 1-Wire bus with multiple

slaves attached. The DS28E16 supports overdrive com-

munication speed of 90.9kbps (max). The value of the

pullup resistor primarily depends on the network size and

load conditions. The DS28E16 requires a pullup resistor

of 750Ω (max).

Initialization

All transactions on the 1-Wire bus begin with an initializa-

tion sequence. The initialization sequence consists of a

reset pulse transmitted by the bus master followed by

presence pulse(s) transmitted by the slave(s). The pres-

ence pulse lets the bus master know that the DS28E16 is

on the bus and is ready to operate. For more details, see

the 1-Wire Signaling and Timing section.

The idle state for the 1-Wire bus is high. If for any reason

a transaction needs to be suspended, the bus must be left

in the idle state if the transaction is to resume. If this does

not occur and the bus is left low for more than 16μs one

or more devices on the bus could be reset.

PUP

*SEE NOTE

1-WIRE SLAVE PORT

BUS MASTER

PIOX

PIOY

CTL

PUP

DATA

Rx = RECEIVE

Tx = TRANSMIT

BIDIRECTIONAL

OPEN-DRAIN PORT

100Ω

MOSFET

*NOTE: USE A LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY

Figure 2. Hardware Configuration

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DS28E16

1-Wire Secure SHA-3 Authenticator

Figure 3 shows the initialization sequence required to

begin any communication with the DS28E16. A reset

pulse followed by a presence pulse indicates that the

DS28E16 is ready to receive data, given the correct ROM

and device function command. If the bus master uses

slew-rate control on the falling edge, it must pull down the

1-Wire Signaling and Timing

The DS28E16 requires strict protocols to ensure data

integrity. The protocol consists of four types of signaling

on one line: reset sequence with reset pulse and pres-

ence pulse, write-zero, write-one, and read-data. Except

for the presence pulse, the bus master initiates all falling

edges.

line for t

+ t to compensate for the edge.

RSTL

After the bus master has released the line, it goes into

receive mode. Now, the 1-Wire bus is pulled to V

through the pullup resistor or, in the case of a special

driver chip, through the active circuitry. When the thresh-

To get from idle to active, the voltage on the 1-Wire line

PUP

needs to fall from V

below the threshold V . To get

PUP

from active to idle, the voltage needs to rise from V

ILMAX

past the threshold V . The time it takes for the voltage

old V

is crossed, the DS28E16 waits and then trans-

to make this rise is seen in Figure 3 as ε, and its dura-

mits a presence pulse by pulling the line low. To detect a

presence pulse, the master must test the logical state of

tion depends on the pullup resistor (R

) used and the

PUP

capacitance of the 1-Wire network attached. The voltage

is relevant for the DS28E16 when determining a

the 1-Wire line at t

MSP

ILMAX

logical level, not triggering any events.

Immediately after t

has expired, the DS28E16 is

RSTH

ready for data communication.

MASTER Tx RESET PULSE

MASTER Rx PRESENCE PULSE

MSP

PUP

IHMASTER

ILM AX

REC

RSTL

RSTH

MASTER

1-WIRE SLAVE

RESISTOR (R

)

PUP

Figure 3. Initialization Procedure: Reset and Presence Pulse

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DS28E16

1-Wire Secure SHA-3 Authenticator

line low; its internal timing generator determines when this

pulldown ends and the voltage starts rising again. When

responding with a 1, the DS28E16 does not hold the data

Read/Write Time Slots

Data communication with the DS28E16 takes place in

time slots that carry a single bit each. Write time slots

transport data from bus master to slave. Read time slots

transfer data from slave to master. Figure 4 illustrates the

definitions of the write and read time slots.

line low at all, and the voltage starts rising as soon as t

is over.

The sum of t + δ (rise time) on one side and the internal

timing generator of the DS28E16 on the other side define

All communication begins with the master pulling the data

line low. As the voltage on the 1-Wire line falls below

the master sampling window (t

to t

), in

MSRMIN

MSRMAX

which the master must perform a read from the data line.

For the most reliable communication, t should be as

the threshold V , the DS28E16 starts its internal timing

generator that determines when the data line is sampled

during a write time slot and how long data is valid during

a read time slot.

short as permissible, and the master should read close

to, but no later than t . After reading from the data

MSRMAX

line, the master must wait until t

guarantees sufficient recovery time t

is expired. This

for the DS28E16

SLOT

REC

Master to Slave

For a write-one time slot, the voltage on the data line must

to get ready for the next time slot. Note that t

speci-

REC

have crossed the V

threshold before the write-one low

fied herein applies only to a single DS28E16 attached to a

1-Wire line. For multidevice configurations, t must be

time t

is expired. For a write-zero time slot, the

W1LMAX

REC

voltage on the data line must stay below the V

thresh-

extended to accommodate the additional 1-Wire device

input capacitance. Alternatively, an interface that performs

active pullup during the 1-Wire recovery time such as the

special 1-Wire line drivers can be used.

old until the write-zero low time t

is expired. For

W0LMIN

the most reliable communication, the voltage on the data

line should not exceed V during the entire t or

ILMAX

W0L

window. After the V

threshold has been crossed,

W1L

1-Wire ROM Commands

the DS28E16 needs a recovery time t

ready for the next time slot.

before it is

REC

Once the bus master has detected a presence, it can

issue one of the five ROM function commands that the

DS28E16 supports. All ROM function commands are 8

bits long. For operational details, see Figure 5. A descrip-

tive list of these ROM function commands follows in the

subsequent sections and the commands are summarized

in Table 1.

Slave to Master

A read-data time slot begins like a write-one time slot. The

voltage on the data line must remain below V until the

read low time t is expired. During the t window, when

responding with a 0, the DS28E16 starts pulling the data

Table 1. 1-Wire ROM Commands Summary

ROM FUNCTION COMMAND

CODE

DESCRIPTION

Search for a device

Search ROM

Read ROM

Match ROM

Skip ROM

Resume

F0h

33h

55h

CCh

A5h

Read ROM from device (single drop)

Select a device by ROM number

Select only device on 1-Wire

Selected device with RC bit set

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DS28E16

1-Wire Secure SHA-3 Authenticator

WRITE-ONE TIME SLOT

W1L

PUP

IHMASTER

ILM AX

SLOT

MASTER

RESISTOR (R

)

PUP

WRITE-ZERO TIME SLOT

W0L

PUP

IHMASTER

ILM AX

REC

SLOT

MASTER

RESISTOR (R

)

PUP

READ-DATA TIME SLOT

MSR

PUP

IHMASTER

MASTER SAMPLING

WINDOW

ILM AX

REC

SLOT

MASTER

1-WIRE SLAVE

RESISTOR (R

)

PUP

Figure 4. Read/Write Timing Diagrams

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DS28E16

1-Wire Secure SHA-3 Authenticator

BUS MASTER TX

RESET PULSE

FROM DEVICE FUNCTIONS

FLOW CHART

BUS MASTER TX ROM

SLAVE TX

FUNCTION COMMAND

PRESENCE PULSE

33h

READ ROM

COMMAND?

55h

MATCH ROM

COMMAND?

F0h

SEARCH ROM

COMMAND?

CCh

SKIP ROM

COMMAND?

A5h

RESUME

COMMAND?

RC = 0

RC = 1?

SLAVE TX BIT 0

MASTER TX BIT 0

SLAVE TX

FAMILY CODE

(1 BYTE)

MASTER TX BIT 0

BIT 0 MATCH?

SLAVE TX BIT 1

MASTER TX BIT 0

SLAVE TX

SERIAL NUMBER

(6 BYTES)

MASTER TX BIT 1

MASTER TX

RESET?

BIT 1 MATCH?

SLAVE TX BIT 63

MASTER TX BIT 63

SLAVE TX

CRC BYTE

MASTER TX BIT 63

BIT 63 MATCH?

RC = 1

BIT 63 MATCH?

RC = 1

TO DEVICE FUNCTIONS

FLOW CHART

Figure 5. ROM Function Flow

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DS28E16

1-Wire Secure SHA-3 Authenticator

Search ROM[F0h]

Match ROM[55h]

When a system is initially brought up, the bus master

might not know the number of devices on the 1-Wire bus

or their ROM ID numbers. By taking advantage of the

wired-AND property of the bus, the master can use a pro-

cess of elimination to identify the ID of all slave devices.

For each bit in the ID number, starting with the least sig-

nificant bit, the bus master issues a triplet of time slots.

On the first slot, each slave device participating in the

search outputs the true value of its ID number bit. On the

second slot, each slave device participating in the search

outputs the complemented value of its ID number bit. On

the third slot, the master writes the true value of the bit

to be selected. All slave devices that do not match the

bit written by the master stop participating in the search.

If both of the read bits are zero, the master knows that

slave devices exist with both states of the bit. By choos-

ing which state to write, the bus master branches in the

search tree. After one complete pass, the bus master

knows the ROM ID number of a single device. Additional

passes identify the ID numbers of the remaining devices.

Refer to Application Note 187: 1-Wire Search Algorithm

for a detailed discussion, including an example.

The Match ROM command, followed by a 64-bit ROM

sequence, allows the bus master to address a specific

DS28E16 on a multidrop bus. Only the DS28E16 that

exactly matches the 64-bit ROM sequence responds

to the subsequent device function command. All other

slaves wait for a reset pulse. This command can be used

with a single device or multiple devices on the bus.

Skip ROM [CCh]

This command can save time in a single-drop bus system

by allowing the bus master to access the device functions

without providing the 64-bit ROM ID. If more than one

slave is present on the bus and, for example, a read com-

mand is issued following the Skip ROM command, data

collision occurs on the bus as multiple slaves transmit

simultaneously (open-drain pulldowns produce a wired-

AND result).

Resume [A5h]

To maximize the data throughput in a multidrop environ-

ment, the Resume command is available. This com-

mand checks the status of the RC bit and, if it is set,

directly transfers control to the device function com-

mands, similar to a Skip ROM command. The only way

to set the RC bit is through successfully executing the

Match ROM or Search ROM command. Once the RC bit

is set, the device can repeatedly be accessed through

the Resume command. Accessing another device on

the bus clears the RC bit, preventing two or more

devices from simultaneously responding to the Resume

command.

Read ROM[33h]

The Read ROM command allows the bus master to read

the DS28E16’s 8-bit family code, unique 48-bit serial

number, and 8-bit CRC. This command can only be used

if there is a single slave on the bus. If more than one

slave is present on the bus, a data collision occurs when

all slaves try to transmit at the same time (open drain

produces a wired-AND result). The resultant family code

and 48-bit serial number result in a mismatch of the CRC.

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DS28E16

1-Wire Secure SHA-3 Authenticator

end with a hysteresis at the low-to-high switching thresh-

old V . If a negative glitch crosses V , but does not go

Improved Network Behavior

(Switch-Point Hysteresis)

below V - V , it is not recognized (Figure 6).

In a 1-Wire environment, line termination is possible only

during transients controlled by the bus master (1-Wire

driver). 1-Wire networks, therefore, are susceptible to

noise of various origins. Depending on the physical size

and topology of the network, reflections from end points

and branch points can add up or cancel each other to

some extent. Such reflections are visible as glitches or

ringing on the 1-Wire communication line. Noise coupled

onto the 1-Wire line from external sources can also result

in signal glitching. A glitch during the rising edge of a time

slot can cause a slave device to lose synchronization with

the master and, consequently, result in a Search ROM

command coming to a dead end or cause a device-spe-

cific function command to abort. For better performance

in network applications, the DS28E16 uses a 1-Wire front

PUP

Figure 6. Noise Suppression Scheme

Ordering Information

PART

TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

6 WLP (2.5k pcs)

DS28E16X-S+T

DS28E16Q+T

6 TDFN-EP (2.5k pcs)

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

EP = Exposed pad.

Maxim Integrated

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www.maximintegrated.com

DS28E16

1-Wire Secure SHA-3 Authenticator

Revision History

REVISION REVISION

PAGES

CHANGED

DESCRIPTION

NUMBER

DATE

11/18

3/19

Initial release

—

Updated Beneﬁts and Features section

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2019 Maxim Integrated Products, Inc.

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DS28E16X-ST [MAXIM]

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