DS28E84 [MAXIM]
DeepCover Radiation-Resistant, High-Capacity, 1-Wire Authenticator;
| 型号： | DS28E84 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | DeepCover Radiation-Resistant, High-Capacity, 1-Wire Authenticator |
| 文件： | 总17页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DS28E84
DeepCover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
General Description
Benefits and Features
● High Radiation Resistance Allows User-
Programmable Manufacturing or Calibration Data
Before Medical Sterilization
The DS28E84 is a radiation-resistant secure authentica-
tor that provides a core set of cryptographic tools derived
from integrated asymmetric (ECC-P256) and symmetric
(SHA-256) security functions. In addition to the security
services provided by the hardware implemented crypto
engines, the device integrates a FIPS-compatible true
random number generator (TRNG), 10Kb of secured
OTP, 15Kb of FRAM, one configurable GPIO, and a
unique 64-bit ROM identification number (ROM ID).
• Resistant Up to 50kGy (kiloGray) of Radiation
• 10kb of One Time Programmable (OTP) for User
Data, Keys, and Certificates
• 15Kb of Secure FRAM for User Data and
Certificates
● ECC-P256 Compute Engine
• FIPS 186 ECDSA P256 Signature and Verification
• ECDH Key Exchange for Session Key Establishment
• ECDSAAuthenticated R/W of Configurable Memory
The ECC public/private key capabilities operate from the
NIST defined P-256 curve and include FIPS 186-compliant
ECDSA signature generation and verification to support
a bidirectional asymmetric key authentication model. The
SHA-256 secret key capabilities are compliant with FIPS
180 and are flexibly used either in conjunction with ECDSA
operations or independently for multiple HMAC functions.
● SHA-256 Compute Engine
• FIPS 180 MAC for Secure Download/Boot
• FIPS 198 HMAC for Bidirectional Authentication
and Optional GPIO Control
The GPIO pin can be operated under command control and
include configurability supporting authenticated and nonau-
thenticated operation, including an ECDSA-based crypto-
robust mode to support secure boot of a host processor.
● SHA-256 OTP (One-Time Pad) Encrypted R/W of
Configurable Memory Through ECDH Established Key
● One GPIO Pin with Optional Authentication Control
• Open-Drain, 4mA/0.4V
DeepCover® embedded security solutions cloak sensitive
data under multiple layers of advanced security to provide
the most secure key storage possible. To protect against
device-level security attacks, invasive and noninvasive
countermeasures are implemented including active die
shield, encrypted storage of keys, and algorithmic methods.
• Optional SHA-256 or ECDSA Authenticated On/Off
and State Read
• Optional ECDSA Certificate to Set On/Off After
Multiblock Hash for Secure Download
● TRNG with NIST SP 800-90B Compliant Entropy
Source with Function to Read Out
● Optional Chip Generated Pr/Pu Key Pairs for ECC
Applications
● Medical Consumables Secure Authentication
Operations or Secrets for SHA256 Functions
● 17-Bit One-Time Settable, Nonvolatile Decrement-
● Medical Tools/Accessories Identification and
Only Counter with Authenticated Read
Calibration
● Unique and Unalterable Factory Programmed 64-Bit
Identification Number (ROM ID)
● Accessory and Peripheral Secure Authentication
● Secure Storage of Cryptographic Keys for Host
• Optional Input Data Component to Crypto and Key
Operations
Controllers
● Secure Boot or Download of Firmware and/or System
● Advanced 1-Wire Protocol Minimizes Interface to
Parameters
Just Single Contact
● Operating Range: 3.3V ±10%, 0°C to +50°C
● ±8kV HBM ESD Protection of 1-Wire IO Pin
● 6-Pin, 3mm x 3mm TDFN
DeepCover® is a registered trademark of Maxim Integrated
Products, Inc.
Ordering Information appears at end of data sheet.
19-100469; Rev 1; 1/19
DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
Simplified Block Diagram
C
X
PARASITE
POWER
C
EXT
DS28E84
64-BIT ROM ID
BUFFER
RNG
IO
1-WIRE FUNCTION
ECC-P256
SHA-256
CONTROL
AND
COMMAND
10Kb OTP ARRAY
USER MEMORY
15Kb FRAM ARRAY
USER MEMORY
KEYS & CERTIFICATES
KEYS & CERTIFICATES
DECREMENT COUNTER
COMPUTE
CONTROL
AUTHENTICATED
PIO
GPIO
Maxim Integrated
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
Absolute Maximum Ratings
Voltage Range on Any Pin Relative to GND..........-0.5V to 4.0V
Maximum Current into Any Pin......................... -20mA to +20mA
Operating Temperature Range.................................0°C to 50°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
6 TDFN
Package Code
T633MK+1A
21-0137
Outline Number
Land Pattern Number
90-0058
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
)
55ºC/W
9ºC/W
JA
Junction to Case (θ
)
JC
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
42ºC/W
9ºC/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed
A
by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the
minimum and maximum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
V
R
(Note 1)
2.97
3.3
3.63
V
Ω
PUP
(Notes 1, 2)
(Note 3)
1000
PUP
C
0.1 + C
470
nF
nF
IO
X
Capacitor External
C
(Note 1)
399.5
540.5
360
X
Pre-radiation
Post-radiation
40
Input Load Current
I
IO pin at V
μA
L
PUP
120
High-to-Low Switching
Threshold
0.65 x
V
(Notes 4, 5, 6)
(Notes 4, 7)
V
V
V
TL
V
PUP
0.10 x
Input Low Voltage
V
IL
V
PUP
Low-to-High Switching
Threshold
0.75 x
V
(Notes 4, 5, 8)
(Notes 4, 5, 9)
TH
V
PUP
Switching Hysteresis
Output Low Voltage
V
V
0.3
V
V
HY
I
= 4mA (Note 10)
0.4
OL
OL
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed
A
by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the
minimum and maximum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
IO PIN: 1-Wire Interface
25
100
50
Standard speed, Pre-radiation,
Directly prior to
reset pulse
R
= 1000Ω
PUP
Recovery Time
(Notes 1, 11, 12)
Standard speed, Post-radia-
tion, R = 1000Ω (Note 26)
t
μs
Directly prior to
reset pulse
REC
1500
10
PUP
Overdrive speed,
= 1000Ω
Directly prior to
reset pulse
R
100
PUP
Rising-Edge Hold-off
(Notes 4, 13)
t
Applies to standard speed only
1
μs
μs
REH
Pre-radiation
85
110
16
Standard speed
Overdrive speed
Time Slot Duration
(Notes 1, 14)
Post-radiation
(Note 26)
t
SLOT
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Standard speed
480
48
480
48
15
2
640
μs
Reset Low Time
(Note 1)
t
RSTL
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
80
Reset High Time
(Note 1)
t
μs
RSTH
60
μs
6
Presence Detect High Time
Presence Detect Low Time
t
PDH
60
8
240
μs
t
PDL
FPD
MSP
24
1.25
0.15
Presence Detect Fall Time
(Notes 4, 15)
t
μs
65
7
75
μs
10
Presence-Detect Sample
Time (Notes 1, 16)
t
IO PIN: 1-Wire WRITE
Standard speed
Overdrive speed
Standard speed
Overdrive speed
60
6
120
μs
Write-Zero Low Time
(Notes 1, 17)
t
t
W0L
W1L
15.5
0.25
0.25
15
μs
2
Write-One Low Time
(Notes 1, 17)
IO PIN: 1-Wire READ
Standard speed
Overdrive speed
Standard speed
Overdrive speed
0.25
0.25
15 - δ
μs
Read Low Time
(Notes 1, 18)
t
RL
2 - δ
t
+ δ
15
μs
2
Read Sample Time
(Note 1, 18)
RL
t
MSR
t
+ δ
RL
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed
A
by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the
minimum and maximum operating temperature are guaranteed by design and are not production tested.)
PARAMETER
GPIO PIN
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
GPIO Output Low
PIOV
PIOI = 4mA (Note 10)
0.4
0.15 x V
V
V
OL
OL
GPIO Input Low
PIOV
-0.3
IL
PUP
GPIO Master Sample
GPIO Switching Hysteresis
GPIO Leakage Current
PIOV
0.70 x V
V
+ 0.3
V
IH
PUP
PUP
PIOV
0.3
11
V
HY
PIOI
-10
2.8
+10
μA
L
STRONG PULLUP OPERATION
Strong Pullup Current
Strong Pullup Voltage
Read Memory
I
(Note 19)
(Note 19)
15
2
mA
V
SPU
V
t
SPU
RM
ms
ms
ms
ms
ms
ms
Write Memory
t
100
15
4
WM
Write State
t
WS
Computation Time (HMAC)
Generate ECC Key Pair
Generate ECDSA Signature
t
CMP
t
t
350
80
GKP
GES
Verify ECDSA Signature or
Compute ECDH Time
t
160
ms
VES
TRNG Generation
TRNG On-Demand Check
OTP
t
t
40
65
ms
ms
RNG
ODC
OTP Write Temperature
Data Retention
FRAM
T
50
ºC
OPTW
t
T
= +85°C (Note 21)
A
10
50
Years
DR
FRAM Off Time
t
(Note 22)
ms
OFF_FRAM
FRAM Read/Write
Cycles (Endurance)
N
(T = +50°C (Note 23, 25)
1 Trillion
10
CY_FRAM
DR_FRAM
A
FRAM Data Retention
POWER
t
(T = +50°C (Note 24, 25)
A
Years
ms
Power-Up Time
t
(Notes 1, 20)
2
OSCWUP
Note 1: System requirement.
Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 3: Value represents the internal parasite capacitance when V
is first applied. Once the parasite capacitance is charged, it
PUP
does not affect normal communication. Typically, during normal communication, the internal parasite capacitance is effectively
~100pF.
Note 4: Guaranteed by design and/or characterization only. Not production tested.
Note 5:
V
, V , and V are functions of the internal supply voltage, which is a function of V
, R
, 1-Wire timing, and capacitive
TL TH
HY
PUP PUP
loading on IO. Lower V
, higher R
, shorter t
, and heavier capacitive loading all lead to lower values of V , V , and
PUP
PUP
REC TL TH
V
.
HY
Note 6: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 7: The voltage on IO must be less than or equal to V at all times the master is driving IO to a logic-zero level.
ILMAX
Note 8: Voltage above which, during a rising edge on IO, a logic-one is detected.
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed
A
by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the
minimum and maximum operating temperature are guaranteed by design and are not production tested.)
Note 9: After V is crossed during a rising edge on IO, the voltage on IO must drop by at least V
to be detected as logic-zero.
TH
HY
Note 10: The I-V characteristic is linear for voltages less than 1V.
Note 11: Applies to a single device attached to a 1-Wire line.
Note 12: t
min covers operation at worst-case temperature V
, R
, C , t
, t
, and t . t
can be significantly
REC
PUP PUP
X
RSTL WOL
RL RECMIN
reduced under less extreme conditions. Contact the factory for more information.
Note 13: The earliest recognition of a negative edge is possible at t after V has been previously reached.
REH
TH
Note 14: Defines maximum possible bit rate. Equal to 1/(t
+ t
).
W0LMIN
RECMIN
Note 15: Time from V
= 80% of V
and V
= 20% of V
at the negative edge on IO at the beginning of the presence detect pulse.
(IO)
PUP
(IO)
PUP
Note 16: Interval after t
during which a bus master can read a logic 0 on IO if there is a DS28E84 present.
RSTL
Note 17: ε in Figure 4 represents the time required for the pullup circuitry to pull the voltage on IO up from V to V
.
IL
TH
Note 18: δ in Figure 4 represents the time required for the pullup circuitry to pull the voltage on IO up from V to the input-high
IL
threshold of the bus master.
Note 19: I
is the current drawn from IO during a strong pullup (SPU) operation. The pullup circuit on IO during the SPU operation
SPU
should be such that the voltage at IO is greater than or equal to V
. A low-impedance bypass of R
activated during
SPUMIN
PUP
the SPU operation is the recommended way to meet this requirement.
Note 20: 1-Wire communication should not take place for at least t after V
reaches V min.
PUP
OSCWUP
PUP
Note 21: Data retention is tested in compliance with JESD47G. No elevated radiation level.
Note 22: FRAM off time required between FRAM SPU commands.
Note 23: Total number of read and write cycles defines the minimum value of endurance. FRAM memory operates with a destructive
readout mechanism.
Note 24: Minimum value defines retention time of the first reading after shipment.
Note 25: Data written before performing IR reflow is not guaranteed after IR reflow.
Note 26: Post radiation increases leakage current and requires long recovery times as noted.
Pin Configuration
TOP VIEW
DNC 1
IO 2
GND 3
+
6 CEXT
5 DNC
4 PIO
EP*
*EP =
EXPOSED
PAD
TDFN-EP
(3mm x 3mm)
Pin Description
PIN
1, 5
2
NAME
DNC
IO
FUNCTION
Do Not Connect
1-Wire IO
3
GND
PIO
Ground
4
General-Purpose IO
6
C
Input for External Capacitor
EXT
Exposed Pad (TDFN Only). Solder evenly to the board's ground plane for proper operation. Refer to
Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
—
—
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
Function Commands
Detailed Description
After a 1-Wire reset/presence cycle and ROM function
command sequence is successful, a command start can be
accepted and then followed by a device function command.
In general, these commands follow the state flow diagram
(Figure 1). Within this diagram, the data transfer is verified
when writing and reading by a CRC of 16-bit type (CRC-16).
The CRC-16 is computed as described in Application Note
27: Understanding and Using Cyclic Redundancy Checks
with Maxim 1-Wire and iButton Products.
The DS28E84 provides a core set of cryptographic tools
derived from integrated asymmetric (ECC-P256) and
symmetric (SHA-256) security functions. In addition to the
security services provided by the hardware implemented
crypto engines, the device integrates a FIPS true random
number generator (TRNG), 10Kb of secured OTP, one pin
of configurable GPIO, and a unique 64-bit ROM identifica-
tion number (ROM ID). The DS28E84 also provides an
additional 15Kb of secure FRAM, and a decrement-only
counter.
66h
N
FROM ROM FUNCTIONS
FLOW CHART
MASTER Tx
COMMAND START
COMMAND
START?
Y
MASTER Tx INPUT
LENGTH BYTE
MASTER Tx COMMAND BYTE
MASTER Tx
PARAMETER BYTE(S)
MASTER Rx CRC-16 (INVERTED
OF COMMAND START, LENGTH,
COMMAND, AND PARAMETERS)
MASTER Tx RELEASE BYTE
N
SLAVE Rx AAh
RELEASE BYTE?
Y
DELAY WITH STRONG PULLUP
MASTER Rx FFh DUMMY BYTE
MASTER Rx OUTPUT
LENGTH BYTE
MASTER Rx RESULT BYTE
MASTER Rx DATA BYTE(S)
MASTER Rx CRC-16 (INVERTED
OF LENGTH, RESULT, & DATA)
N
MASTER
Rx 1S
MASTER Tx
RESET?
Y
TO ROM FUNCTIONS
FLOW CHART
Figure 1. Device Function Flow Chart
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
The idle state for the 1-Wire bus is high. If for any reason
a transaction needs to be suspended, the bus must be
left in the idle state if the transaction is to resume. If this
does not occur and the bus is left low for more than 16μs
(overdrive speed) or more than 120μs (standard speed),
one or more devices on the bus could be reset.
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances, the DS28E84 is
a slave device. The bus master is typically a microcon-
troller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing).
The 1-Wire protocol defines bus transactions in terms of
the bus state during specific time slots that are initiated
on the falling edge of sync pulses from the bus master.
Transaction Sequence
The protocol for accessing the DS28E84 through the
1-Wire port is as follows:
● Initialization
Hardware Configuration
● ROM Function command
● Device Function command
● Transaction/data
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus can drive it at the
appropriate time. To facilitate this, each device attached
to the 1-Wire bus must have open-drain or three-state
outputs. The 1-Wire port of the DS28E84 is open drain
with an internal circuit equivalent.
Initialization
All transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that the DS28E84 is
on the bus and is ready to operate. For more details, see
the 1-Wire Signaling and Timing section.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28E84 supports both a standard
and overdrive communication speed of 11.7kbps (max)
and 62.5kbps (max), respectively. The value of the pullup
resistor primarily depends on the network size and load
conditions. The DS28E84 requires a pullup resistor of
1kΩ (max) at any speed.
V
PUP
*SEE NOTE
1-WIRE SLAVE PORT
BUS MASTER
C
X
Tx
PIOX
PIOY
CTL
Rx
R
PUP
Rx
Tx
DATA
I
L
Tx
Rx = RECEIVE
Tx = TRANSMIT
BIDIRECTIONAL
OPEN-DRAIN PORT
100Ω
MOSFET
*NOTE: USE A LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY
Figure 2. Hardware Configuration
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
function command. If the bus master uses slew-rate con-
1-Wire Signaling and Timing
trol on the falling edge, it must pull down the line for t
RSTL
The DS28E84 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and presence
pulse, write-zero, write-one, and read-data. Except for the
presence pulse, the bus master initiates all falling edges.
The DS28E84 can communicate at two speeds: standard
and overdrive. If not explicitly set into the overdrive mode,
the DS28E84 communicates at standard speed. While in
overdrive mode, the fast timing applies to all waveforms.
+ t to compensate for the edge. A t
duration of 480μs
F
RSTL
or longer exits the overdrive mode, returning the device to
standard speed. If the DS28E84 is in overdrive mode and
t
is no longer than 80μs, the device remains in over-
RSTL
drive mode. If the device is in overdrive mode and t
RSTL
is between 80μs and 480μs, the device resets, but the
communication speed is undetermined.
After the bus master has released the line, it goes into
receive mode. Now the 1-Wire bus is pulled to V
through the pullup resistor or, in the case of a special
driver chip, through the active circuitry. When the thresh-
PUP
To get from idle to active, the voltage on the 1-Wire line
needs to fall from V
below the threshold V . To get
PUP
TL
from active to idle, the voltage needs to rise from V
ILMAX
old V is crossed, the DS28E84 waits for t
and then
TH
PDH
past the threshold V . The time it takes for the voltage
TH
transmits a presence pulse by pulling the line low for t
.
PDL
to make this rise is seen in Figure 3 as ε, and its dura-
To detect a presence pulse, the master must test the logi-
cal state of the 1-Wire line at t
tion depends on the pullup resistor (R
) used and the
PUP
.
MSP
capacitance of the 1-Wire network attached. The voltage
is relevant for the DS28E84 when determining a
V
The t
window must be at least the sum of t
PDH-
ILMAX
RSTH
logical level, not triggering any events.
, t
, and t
. Immediately after t
is
MAX PDLMAX
RECMIN
RSTH
expired, the DS28E84 is ready for data communication. In
a mixed population network, t should be extended to
minimum 480μs at standard speed and 48μs at overdrive
Figure 3 shows the initialization sequence required to
begin any communication with the DS28E84. A reset pulse
followed by a presence pulse indicates that the DS28E84
is ready to receive data, given the correct ROM and device
RSTH
speed to accommodate other 1-Wire devices.
MASTER Tx RESET PULSE
MASTER Rx PRESENCE PULSE
t
MSP
ε
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
t
t
t
REC
RSTL
PDH
PDL
t
F
t
RSTH
MASTER
1-WIRE SLAVE
RESISTOR (R
)
PUP
Figure 3. Initialization Procedure: Reset and Presence Pulse
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
Slave-to-Master
Read/Write Time Slots
A read-data time slot begins like a write-one time slot. The
Data communication with the DS28E84 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 4 illustrates the
definitions of the write and read time slots.
voltage on the data line must remain below V until the
TL
read low time t is expired. During the t window, when
RL
RL
responding with a 0, the DS28E84 starts pulling the data
line low; its internal timing generator determines when this
pulldown ends and the voltage starts rising again. When
responding with a 1, the DS28E84 does not hold the data
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below
line low at all, and the voltage starts rising as soon as t
is over.
RL
the threshold V , the DS28E84 starts its internal timing
TL
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
The sum of t + δ (rise time) on one side and the internal
RL
timing generator of the DS28E84 on the other side define
the master sampling window (t
which the master must perform a read from the data line.
For the most reliable communication, t should be as
to t
), in
MSRMIN
MSRMAX
Master-to-Slave
For a write-one time slot, the voltage on the data line must
have crossed the V
RL
threshold before the write-one low
TH
short as permissible, and the master should read close
to but no later than t . After reading from the data
time t
is expired. For a write-zero time slot, the
W1LMAX
MSRMAX
voltage on the data line must stay below the V
old until the write-zero low time t
the most reliable communication, the voltage on the data
line should not exceed V during the entire t or
thresh-
TH
line, the master must wait until t
guarantees sufficient recovery time t
to get ready for the next time slot. Note that t
fied herein applies only to a single DS28E84 attached to a
1-Wire line. For multidevice configurations, t must be
extended to accommodate the additional 1-Wire device
input capacitance. Alternatively, an interface that performs
active pullup during the 1-Wire recovery time such as the
special 1-Wire line drivers can be used.
is expired. This
for the DS28E84
SLOT
REC
is expired. For
W0LMIN
speci-
REC
ILMAX
W0L
t
window. After the V
threshold has been crossed,
W1L
TH
REC
the DS28E84 needs a recovery time t
ready for the next time slot.
before it is
REC
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
WRITE-ONE TIME SLOT
t
W1L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
F
ε
t
SLOT
MASTER
RESISTOR (R
)
PUP
WRITE-ZERO TIME SLOT
t
W0L
V
PUP
V
IHMASTER
V
TH
V
TL
V
ILMAX
0V
t
F
ε
t
REC
t
SLOT
MASTER
RESISTOR (R
)
PUP
READ-DATA TIME SLOT
t
MSR
t
RL
V
PUP
V
IHMASTER
V
TH
MASTER SAMPLING
WINDOW
V
TL
V
ILMAX
0V
t
F
δ
t
REC
t
SLOT
MASTER
1-WIRE SLAVE
RESISTOR (R
)
PUP
Figure 4. Read/Write Timing Diagrams
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
1-Wire ROM Commands
Skip ROM [CCh]
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that
the DS28E84 supports. All ROM function commands are
8 bits long. For operational details, see the flowchart
description in Figure 5 and Figure 6. A descriptive list of
these ROM function commands follows in the subsequent
sections.
This command can save time in a single-drop bus system
by allowing the bus master to access the device functions
without providing the 64-bit ROM ID. If more than one
slave is present on the bus and, for example, a read com-
mand is issued following the Skip ROM command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wired-
AND result).
Read ROM[33h]
Resume [A5h]
The Read ROM command allows the bus master to read
the DS28E84’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used
if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when
all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code
and 48-bit serial number result in a mismatch of the CRC.
To maximize the data throughput in a multidrop environ-
ment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the device function commands, similar
to a Skip ROM command. The only way to set the RC bit
is through successfully executing the Match ROM, Search
ROM, or Overdrive-Match ROM command. Once the RC
bit is set, the device can repeatedly be accessed through
the Resume command. Accessing another device on the
bus clears the RC bit, preventing two or more devices from
simultaneously responding to the Resume command.
Match ROM[55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS28E84 on a multidrop bus. Only the DS28E84 that
exactly matches the 64-bit ROM sequence responds
to the subsequent device function command. All other
slaves wait for a reset pulse. This command can be used
with a single device or multiple devices on the bus.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the device functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM command
sets the DS28E84 into the overdrive mode (OD = 1). All
communication following this command must occur at
overdrive speed until a reset pulse of minimum 480μs
duration resets all devices on the bus to standard speed
(OD = 0).
Search ROM[F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a pro-
cess of elimination to identify the ID of all slave devices.
For each bit in the ID number, starting with the least sig-
nificant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choos-
ing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion, including an example.
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command
sequence. This speeds up the time for the search pro-
cess. If more than one slave supporting overdrive is pres-
ent on the bus and the Overdrive-Skip ROM command
is followed by a read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (open-
drain pulldowns produce a wired-AND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a 64-bit
ROM sequence transmitted at overdrive speed allows the
bus master to address a specific DS28E84 on a multi-
drop bus and to simultaneously set it in overdrive mode.
Only the DS28E84 that exactly matches the 64-bit ROM
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
sequence responds to the subsequent device function
command. Slaves already in overdrive mode from a previ-
ous Overdrive-Skip ROM or successful Overdrive-Match
ROM command remain in overdrive mode. All overdrive-
capable slaves return to standard speed at the next reset
pulse of minimum 480μs duration. The Overdrive-Match
ROM command can be used with a single device or mul-
tiple devices on the bus.
ROM Command Flow
BUS MASTER Tx
RESET PULSE
FROM ROM FUNCTION FLOW PART 2
FROM DEVICE FUNCTIONS
FLOW CHART
N
OD
OD = 0
RESET PULSE?
Y
BUS MASTER Tx
SLAVE Tx
ROM FUNCTION COMMAND
PRESENCE PULSE
33h
55h
F0h
N
CCh
N
N
N
READ ROM
COMMAND?
MATCH ROM
COMMAND?
SEARCH ROM
COMMAND?
SKIP ROM
COMMAND?
TO ROM FUNCTION
FLOW PART 2
Y
Y
Y
Y
RC = 0
RC = 0
RC = 0
RC = 0
SLAVE Tx BIT 0
SLAVE Tx BIT 0
MASTER Tx BIT 0
SLAVE Tx
FAMILY CODE
(1 BYTE)
MASTER Tx BIT 0
N
N
BIT 0 MATCH?
Y
BIT 0 MATCH?
Y
SLAVE Tx BIT 1
SLAVE Tx BIT 1
MASTER Tx BIT 0
SLAVE Tx
SERIAL NUMBER
(6 BYTES)
MASTER Tx BIT 1
Y
N
N
BIT 1 MATCH?
Y
BIT 1 MATCH?
Y
SLAVE Tx BIT 63
SLAVE Tx BIT 63
MASTER Tx BIT 63
SLAVE Tx
CRC BYTE
MASTER Tx BIT 63
N
N
BIT 63 MATCH?
RC = 1
BIT 63 MATCH?
RC = 1
TO ROM FUNCTION
FLOW PART 2
FROM ROM FUNCTION FLOW PART 2
Figure 5. ROM Function Flow (Part 1)
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
TO ROM FUNCTION FLOW PART 1
FROM ROM
FUNCTION
FLOW PART 1
A5h
3Ch
69h
N
N
N
RESUME
COMMAND?
OVERDRIVE-
SKIP ROM?
OVERDRIVE-
MATCH ROM?
Y
Y
Y
RC = 0; OD = 1
RC = 0; OD = 1
N
RC = 1?
MASTER Tx BIT 0
Y
N
MASTER Tx
RESET?
BIT 0 MATCH?
Y
OD = 0
N
MASTER Tx BIT 1
Y
MASTER Tx
RESET?
N
N
BIT 1 MATCH?
Y
OD = 0
SLAVE Tx BIT 63
N
BIT 63 MATCH?
RC = 1
OD = 0
FROM ROM FUNCTION
FLOW PART 1
TO ROM FUNCTION FLOW PART 1
TO DEVICE FUNCTIONS
FLOW CHART
Figure 6. ROM Function (Part 2)
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
The DS28E84’s 1-Wire front end has the following features:
Improved Network Behavior
(Switch-Point Hysteresis)
● The falling edge of the presence pulse has a con-
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up or cancel each other to
some extent. Such reflections are visible as glitches or
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a time
slot can cause a slave device to lose synchronization with
the master and, consequently, result in a Search ROM
command coming to a dead end or cause a device-spe-
cific function command to abort. For better performance
in network applications, the DS28E84 uses a 1-Wire front-
end that is less sensitive to noise.
trolled slew rate to reduce ringing. The slew rate con-
trol is specified by t
.
FPD
● There is a hysteresis at the low-to-high switching
threshold V . If a negative glitch crosses V , but
TH
TH
does not go below V - V , it is not recognized
TH
HY
(Figure 7, Case A). The hysteresis is effective at any
1-Wire speed.
● There is a time window specified by the rising edge
hold-off time t
during which glitches are ignored,
REH
even if they extend below the V - V
threshold
TH
HY
(Figure 7, Case B, t < t
). Deep voltage drops
GL
REH
or glitches that appear late after crossing the V
TH
threshold and extend beyond the t
window can-
REH
not be filtered out and are taken as the beginning of
a new time slot (Figure 7, Case C, t ≥ t ).
GL
REH
t
REH
t
REH
V
PUP
V
TH
V
HY
CASE A
CASE B
CASE C
0V
t
t
GL
GL
Figure 7. Noise Suppression Scheme
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
Typical Application Circuit
V
CC
100kΩ
R
PUP
Q1
1kΩ
V
CC
PIOX
PIOY
IO
PIO
*PMV65XP
BIDIRECTIONAL
OPEN-DRAIN PORT
DS28E84
IO
C
GND
EXT
CX
V
CC
µC
Rp
V
CC
2
IO
I C
PIOA
PIOB
SDA
SCL
PORT
IO
NOTE: USE A Q1 LOW-IMPEDANCE BYPASS
OR EQUALLY DRIVE LOGIC 1 WITH PIOY
DS2476
GND
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS28E84Q+T
0°C to +50°C 6 TDFN-EP (2.5k pcs reel)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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DS28E84
Deep Cover Radiation-Resistant,
High-Capacity, 1-Wire Authenticator
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
1/19
Initial release
—
3
1/19
Updated package code
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
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