DS3070W-100 [MAXIM]
3.3V Single-Piece 16Mb Nonvolatile SRAM with Clock; 3.3V单件16Mb的非易失SRAM时钟
| 型号： | DS3070W-100 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.3V Single-Piece 16Mb Nonvolatile SRAM with Clock |
| 文件： | 总18页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 1; 10/06
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
General Description
Features
The DS3070W consists of a static RAM, a nonvolatile
(NV) controller, a year 2000-compliant real-time clock
(RTC), and an internal rechargeable manganese lithium
(ML) battery. These components are encased in a sur-
face-mount module with a 256-ball BGA footprint.
ꢀ Single-Piece, Reflowable, 27mm x 27mm BGA
Package Footprint
ꢀ Internal Manganese Lithium Battery and Charger
ꢀ Integrated Real-Time Clock
Whenever V
is applied to the module, it recharges
CC
the ML battery, powers the clock and SRAM from the
external power source, and allows the contents of the
ꢀ Unconditionally Write-Protects the Clock and
clock registers or SRAM to be modified. When V
is
SRAM when V
is Out-of-Tolerance
CC
CC
powered down or out-of-tolerance, the controller write-
protects the memory contents and powers the clock
and SRAM from the battery. The DS3070W also con-
tains a power-supply monitor output (RST), as well as a
user-programmable interrupt output (IRQ/FT).
ꢀ Automatically Switches to Battery Supply when
Power Failures Occur
V
CC
ꢀ Reset Output can be Used as a CPU Supervisor
ꢀ Interrupt Output can be Used as a CPU Watchdog
Applications
Gaming
Timer
RAID Systems and Servers
POS Terminals
ꢀ Industrial Temperature Range (-40°C to +85°C)
ꢀ UL Recognized
Fire Alarms
PLCs
Industrial Controllers
Data-Acquisition Systems
Routers/Switches
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
256-ball 27mm x 27mm BGA Module
SPEED
SUPPLY VOLTAGE
DS3070W-100#
100ns
3.3V 0.3V
#Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements.
Typical Operating Circuit
CE
WR
RD
CS
CE
WE
OE
CS
DS3070W
MICROPROCESSOR
2048k x 8
NV SRAM
OR DSP
DATA
DQ0–7
8 BITS
AND RTC
21 BITS
ADDRESS
A0–20
INT
INT
IRQ/FT
RST
Pin Configuration appears at end of data sheet.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground......-0.3V to +4.6V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range...............................-40°C to +85°C
Soldering Temperature Range..........See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +85°C.)
A
PARAMETER
Supply Voltage
Input Logic 1
SYMBOL
CONDITIONS
MIN
3.0
2.2
0.0
TYP
MAX
UNITS
V
3.3
3.6
V
V
V
CC
V
V
CC
IH
Input Logic 0
V
0.4
IL
DC ELECTRICAL CHARACTERISTICS
(V = 3.3V 0.3Vꢀ T = -40°C to +85°C.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
-1.0
-1.0
-1.0
2.0
TYP
MAX
+1.0
+1.0
UNITS
µA
Input Leakage Current
I/O Leakage Current
I
IL
I
CE = CS = V
At 2.4V
µA
IO
CC
Output-Current High
I
mA
mA
mA
mA
OH
Output-Current Low
I
At 0.4V
OL
Output-Current Low RST
Output-Current Low IRQ/FT
I
RST
At 0.4V (Note 1)
8.0
OL
I
IRQ/FT At 0.4V (Note 1)
7.0
OL
I
I
CE = CS = 2.2V
CE = CS = V - 0.2V
0.5
0.2
7
5
CCS1
CCS2
CCO1
Standby Current
mA
CC
Operating Current
I
t
= 200nsꢀ outputs open
50
3.0
mA
V
RC
Write Protection Voltage
V
2.8
2.9
TP
PIN CAPACITANCE
(T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
15
MAX
UNITS
pF
Input Capacitance
C
Not production tested
Not production tested
IN
Input/Output Capacitance
C
15
pF
OUT
2
_____________________________________________________________________
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
AC ELECTRICAL CHARACTERISTICS
(V = 3.3V 0.3Vꢀ T = -40°C to +85°C.)
CC
A
DS3070W-100
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
100
MAX
t
Read Cycle Time
ns
ns
ns
ns
ns
ns
RC
t
Access Time
100
50
ACC
t
OE to Output Valid
OE
t
RTC OE to Output Valid
CE or CS to Output Valid
OE or CE or CS to Output Active
60
OEC
t
100
CO
t
(Note 2)
(Note 2)
5
COE
t
OD
OH
Output High Impedance from
Deselection
40
ns
Output Hold from Address
Write Cycle Time
t
t
5
100
75
0
ns
ns
ns
ns
WC
t
Write Pulse Width
(Note 3)
WP
AW
t
Address Setup Time
t
t
(Note 4)
(Note 5)
5
WR1
WR2
Write Recovery Time
ns
ns
20
Output High Impedance
from WE
t
(Note 2)
40
ODW
t
Output Active from WE
(Note 2)
(Note 6)
(Note 4)
(Note 5)
5
ns
ns
OEW
t
Data Setup Time
40
0
DS
t
DH1
DH2
CCS
Data Hold Time
ns
ns
t
20
40
t
Chip-to-Chip Setup Time
POWER-DOWN/POWER-UP TIMING
(T = -40°C to +85°C.)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Fail Detect to CEꢀ CSꢀ and
CC
t
(Note 7)
1.5
µs
PD
WE Inactive
t
V
V
V
Slew from V to 0V
150
150
µs
µs
F
CC
CC
TP
t
R
Slew from 0V to V
TP
Valid to CEꢀ CSꢀ and WE
CC
t
2
ms
ms
PU
Inactive
V
Valid to End of Write
CC
t
125
REC
Protection
t
t
V
V
Fail Detect to RST Active
(Note 1)
(Note 1)
3.0
µs
RPD
CC
CC
Valid to RST Inactive
40
350
525
ms
RPU
_____________________________________________________________________
3
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
DATA RETENTION
(T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Expected Data-Retention Time
(Per Charge)
t
(Notes 7ꢀ 8)
2
3
years
DR
AC TEST CONDITIONS
Input Pulse Levels:
V
= 0.0Vꢀ V = 2.7V
IH
IL
Input Pulse Rise and Fall Times:
5ns
Input and Output Timing Reference Level: 1.5V
Output Load: 1 TTL Gate + C (100pF) including scope and jig
L
Note 1: IRQ/FT and RST are open-drain outputs and cannot source current. External pullup resistors should be connected to these
pins to realize a logic-high level.
Note 2: These parameters are sampled with a 5pF load and are not 100% tested.
Note 3:
t
is specified as the logical AND of CE with WE for SRAM writesꢀ or CS with WE for RTC writes. t
is measured from
WP
WP
the latter of the two related edges going low to the earlier of the two related edges going high.
Note 4:
Note 5:
Note 6:
t
t
t
and t
and t
are measured from WE going high.
are measured from CE going high for SRAM writes or CS going high for RTC writes.
WR1
WR2
DH1
DH2
is measured from the earlier of CE or WE going high for SRAM writesꢀ or from the earlier of CS or WE going high for
DS
RTC writes.
Note 7: In a power-down conditionꢀ the voltage on any pin may not exceed the voltage on V
.
CC
Note 8: The expected t is defined as accumulative time in the absence of V
starting from the time power is first applied by the
DR
CC
user. Minimum expected data-retention time is based upon a maximum of two +230°C convection reflow exposuresꢀ fol-
lowed by a fully charged cell. Full charge occurs with the initial application of V for a minimum of 96 hours. This parame-
CC
ter is assured by component selectionꢀ process controlꢀ and design. It is not measured directly during production testing.
Note 9: WE is high for any read cycle.
Note 10: OE = V or V . If OE = V during write cycleꢀ the output buffers remain in a high-impedance state.
IH
IL
IH
Note 11: If the CE or CS low transition occurs simultaneously with or latter than the WE low transitionꢀ the output buffers remain in a
high-impedance state during this period.
Note 12: If the CE or CS high transition occurs prior to or simultaneously with the WE high transitionꢀ the output buffers remain in a
high-impedance state during this period.
Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the related CE or CS low transitionꢀ the output
buffers remain in a high-impedance state during this period.
4
_____________________________________________________________________
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
Read Cycle
t
RC
V
V
V
V
V
IH
IH
IH
ADDRESSES
V
IL
IL
IL
t
t
OH
OD
t
ACC
V
IH
V
IH
CE
OR
CS
t
CO
V
IL
t
OEC
V
IH
t
OE
V
IH
OE
V
IL
t
t
OD
COE
t
COE
V
V
V
OH
OH
OUTPUT
DATA VALID
D
OUT
V
OL
OL
(SEE NOTE 9.)
_____________________________________________________________________
5
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
Write Cycle 1
t
WC
V
V
V
V
IH
IL
IH
IL
IH
ADDRESSES
V
V
IL
t
AW
CE
OR
CS
V
IL
V
IL
t
t
WP
WR1
WE
V
IH
V
IH
V
IL
V
IL
t
OEW
t
ODW
HIGH
IMPEDANCE
D
OUT
t
DS
t
DH1
V
IH
V
IH
D
IN
DATA IN STABLE
V
IL
V
IL
(SEE NOTES 2, 3, 4, 6, 10–13.)
Write Cycle 2
t
WC
V
IH
V
V
V
V
IL
IH
IH
ADDRESSES
V
IL
IL
t
t
AW
t
WP
WR2
CE
OR
CS
V
IH
V
V
IH
V
V
V
IL
IL
V
IL
IH
WE
V
IL
IL
t
t
ODW
COE
D
OUT
t
t
DS
DH2
V
IH
V
IH
D
IN
DATA IN STABLE
V
IL
V
IL
(SEE NOTES 2, 3, 5, 6, 10–13.)
6
_____________________________________________________________________
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
Power-Down/Power-Up Condition
V
CC
V
TP
t
DR
~2.5V
t
t
F
R
t
REC
t
PU
t
PD
SLEWS WITH
V
CC
CE,
WE
AND
V
IH
CS
BACKUP CURRENT
SUPPLIED FROM
LITHIUM BATTERY
t
t
RPU
RPD
RST
V
V
OL
OL
(SEE NOTES 1, 7.)
Typical Operating Characteristics
(V
= 3.3Vꢀ T = +25°Cꢀ unless otherwise noted.)
CC
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. OPERATING FREQUENCY
BATTERY CHARGER CURRENT
vs. BATTERY VOLTAGE
8
7
6
5
4
3
2
1
0
12
10
1000
900
800
700
600
500
V
V
= CE = 3.3V,
T
= +25°C
V
= CE = 3.3V
CC
CC
A
= V
,
BAT
CHARGE
OSC = ON
8
6
4
2
5MHz CE-ACTIVATED
50% DUTY CYCLE
1MHz CE-ACTIVATED
50% DUTY CYCLE
5MHz ADDRESS-
ACTIVATED
100% DUTY CYCLE
1MHz ADDRESS-
ACTIVATED
100% DUTY CYCLE
V
CHARGE
0
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
0
0.2
DELTA V BELOW V
CHARGE
0.4
0.6
0.8
(V)
1.0
V
V
CC
CC
_____________________________________________________________________
7
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
Typical Operating Characteristics (continued)
(V
= 3.3Vꢀ T = +25°Cꢀ unless otherwise noted.)
A
CC
V
PERCENT CHANGE
vs. TEMPERATURE
CHARGE
V
vs. TEMPERATURE
DQ V vs. DQ I
OH OH
TP
1.0
3.00
2.95
2.90
2.85
2.80
3.5
3.3
3.1
2.9
2.7
2.5
V
V
= 3.3V,
CC
V
= 3.3V
CC
= V
BAT
CHARGE
0.5
0
-0.5
-1.0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-5
-4
-3
-2
(mA)
-1
0
TEMPERATURE (°C)
TEMPERATURE (°C)
I
OH
IRQ/FT OUTPUT VOLTAGE LOW
vs. OUTPUT CURRENT LOW
DQ V vs. DQ I
OL
OL
0.6
0.5
0.4
0.3
0.2
0.1
0
0.4
V
V
= 3.3V
= 3.3V
CC
CC
0.3
0.2
0.1
0
0
5
10
15
20
0
1
2
3
4
5
I
(mA)
I
(mA)
OL
OL
RST VOLTAGE
vs. V DURING POWER-UP
RST OUTPUT VOLTAGE LOW
vs. OUTPUT CURRENT LOW
CC
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.6
0.5
0.4
0.3
0.2
0.1
0
T
= +25°C
V
= 2.8V
A
CC
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
POWER-UP (V)
0
5
10
15
20
V
I
(mA)
CC
OL
8
_____________________________________________________________________
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
Pin Description
BALLS
NAME
A5
DESCRIPTION
Address Input 5
BALLS
NAME
DESCRIPTION
N17ꢀ N18ꢀ N19ꢀ N20
P17ꢀ P18ꢀ P19ꢀ P20
R17ꢀ R18ꢀ R19ꢀ R20
T17ꢀ T18ꢀ T19ꢀ T20
U17ꢀ U18ꢀ U19ꢀ U20
V17ꢀ V18ꢀ V19ꢀ V20
W17ꢀ W18ꢀ W19ꢀ W20
Y17ꢀ Y18ꢀ Y19ꢀ Y20
A5ꢀ B5ꢀ C5ꢀ D5
A1ꢀ A2ꢀ A3ꢀ A4
GND Ground
A4
Address Input 4
Address Input 3
Address Input 2
Address Input 1
Address Input 0
Interrupt/Frequency Test
Output
B1ꢀ B2ꢀ B3ꢀ B4
IRQ/FT
A3
A2
C1ꢀ C2ꢀ C3ꢀ C4
D1ꢀ D2ꢀ D3ꢀ D4
E1ꢀ E2ꢀ E3ꢀ E4
A15
A16
RST
Address Input 15
Address Input 16
Reset Output
A1
A0
GND Ground
F1ꢀ F2ꢀ F3ꢀ F4
V
Supply Voltage
CC
GND Ground
G1ꢀ G2ꢀ G3ꢀ G4
H1ꢀ H2ꢀ H3ꢀ H4
J1ꢀ J2ꢀ J3ꢀ J4
WE
OE
CE
Write Enable Input
Output Enable Input
SRAM Chip Enable Input
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
A6ꢀ B6ꢀ C6ꢀ D6
A7ꢀ B7ꢀ C7ꢀ D7
K1ꢀ K2ꢀ K3ꢀ K4
DQ7 Data Input/Output 7
DQ6 Data Input/Output 6
DQ5 Data Input/Output 5
DQ4 Data Input/Output 4
DQ3 Data Input/Output 3
DQ2 Data Input/Output 2
DQ1 Data Input/Output 1
DQ0 Data Input/Output 0
GND Ground
A8ꢀ B8ꢀ C8ꢀ D8
L1ꢀ L2ꢀ L3ꢀ L4
A9ꢀ B9ꢀ C9ꢀ D9
M1ꢀ M2ꢀ M3ꢀ M4
N1ꢀ N2ꢀ N3ꢀ N4
P1ꢀ P2ꢀ P3ꢀ P4
A10ꢀ B10ꢀ C10ꢀ D10
A11ꢀ B11ꢀ C11ꢀ D11
A12ꢀ B12ꢀ C12ꢀ D12
A13ꢀ B13ꢀ C13ꢀ D13
A14ꢀ B14ꢀ C14ꢀ D14
A15ꢀ B15ꢀ C15ꢀ D15
A16ꢀ B16ꢀ C16ꢀ D16
U5ꢀ V5ꢀ W5ꢀ Y5
V
Supply Voltage
CC
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
R1ꢀ R2ꢀ R3ꢀ R4
T1ꢀ T2ꢀ T3ꢀ T4
U1ꢀ U2ꢀ U3ꢀ U4
V1ꢀ V2ꢀ V3ꢀ V4
A19
A20
CS
Address Input 19
Address Input 20
RTC Chip Select Input
W1ꢀ W2ꢀ W3ꢀ W4
Y1ꢀ Y2ꢀ Y3ꢀ Y4
GND Ground
GND Ground
U6ꢀ V6ꢀ W6ꢀ Y6
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
N.C. No Connection
A17ꢀ A18ꢀ A19ꢀ A20
B17ꢀ B18ꢀ B19ꢀ B20
C17ꢀC18ꢀC19ꢀ C20
D17ꢀ D18ꢀ D19ꢀ D20
E17ꢀ E18ꢀ E19ꢀ E20
F17ꢀ F18ꢀ F19ꢀ F20
G17ꢀ G18ꢀ G19ꢀ G20
H17ꢀ H18ꢀ H19ꢀ H20
J17ꢀ J18ꢀ J19ꢀ J20
K17ꢀ K18ꢀ K19ꢀ K20
L17ꢀ L18ꢀ L19ꢀ L20
M17ꢀ M18ꢀ M19ꢀ M20
GND Ground
U7ꢀ V7ꢀ W7ꢀ Y7
A18
A17
A14
A13
A12
A11
A10
A9
Address Input 18
Address Input 17
Address Input 14
Address Input 13
Address Input 12
Address Input 11
Address Input 10
Address Input 9
Address Input 8
Address Input 7
Address Input 6
U8ꢀ V8ꢀ W8ꢀ Y8
U9ꢀ V9ꢀ W9ꢀ Y9
U10ꢀ V10ꢀ W10ꢀ Y10
U11ꢀ V11ꢀ W11ꢀ Y11
U12ꢀ V12ꢀ W12ꢀ Y12
U13ꢀ V13ꢀ W13ꢀ Y13
U14ꢀ V14ꢀ W14ꢀ Y14
U15ꢀ V15ꢀ W15ꢀ Y15
U16ꢀ V16ꢀ W16ꢀ Y16
A8
A7
A6
_____________________________________________________________________
9
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
Functional Diagram
IRQ/FT
32.768kHz
CS
CS
CE
A0-A3
REAL-TIME
CLOCK
WE
OE
RST
DELAY TIMING
CIRCUITRY
V
REF
TP
UNINTERRUPTED
POWER SUPPLY
FOR THE SRAM
AND RTC
CHARGER
CURRENT-LIMITING
RESISTOR
V
CC
V
CC
CE
OE
WE
SRAM
DQ0–7
V
REF
SW
REDUNDANT LOGIC
REDUNDANT
SERIES FET
CURRENT-LIMITING
ML
RESISTOR
BATTERY-CHARGING/SHORTING
PROTECTION CIRCUITRY (U.L. RECOGNIZED)
GND
DS3070W
OE
WE
A0–A20
10
____________________________________________________________________
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
ually updatedꢀ regardless of the state of the external
Detailed Description
registersꢀ assuring that accurate RTC information is
The DS3070W is a 16Mb (2048k x 8 bits) fully staticꢀ NV
always maintained.
memory similar in function and organization to the
DS1270W NV SRAMꢀ but also containing an RTC and
rechargeable ML battery. The DS3070W NV SRAM con-
The DS3070W contains interrupt (IRQ/FT) and reset
(RST) outputsꢀ which can be used to control CPU activ-
ity. The IRQ/FT interrupt output can be used to gener-
ate an external interrupt when the RTC register values
match user-programmed alarm values. The interrupt is
always available while the device is powered from the
system supplyꢀ and it can be programmed to occur
when in the battery-backed state to serve as a system
wake-up. The IRQ/FT output can also be used as a
CPU watchdog timer. CPU activity is monitored and an
interrupt can be activated if the correct activity is not
detected. The RST output can be used to detect a sys-
tem power-down or failure and hold the CPU in a safe
state until normal power returns.
stantly monitors V
for an out-of-tolerance condition.
CC
When such a condition occursꢀ the lithium energy source
is automatically switched on and write protection is
unconditionally enabled to prevent data corruption. There
is no limit to the number of write cycles that can be exe-
cutedꢀ and no additional support circuitry is required for
microprocessor interfacing. This device can be used in
place of SRAMꢀ EEPROMꢀ or flash components.
User access to either the SRAM or the real-time clock
registers is accomplished with a byte-wide interface
and discrete control inputsꢀ allowing for a direct inter-
face to many 3.3V microprocessor devices.
The DS3070W constantly monitors the voltage of the
internal battery. The battery-low flag (BLF) in the RTC
FLAGS register is not writeable and should always be a
0 when read. Should a 1 ever be presentꢀ the battery
voltage is below ∼2V and the contents of the clock and
SRAM are questionable.
The DS3070W RTC contains a full-functionꢀ year 2000-
compliant (Y2KC) clock/calendar with an RTC alarmꢀ
watchdog timerꢀ battery monitorꢀ and power monitor.
RTC registers contain centuryꢀ yearꢀ monthꢀ dateꢀ dayꢀ
hoursꢀ minutesꢀ and seconds data in a 24-hour BCD
format. Corrections for day of the month and leap year
are made automatically.
The DS3070W module is constructed on a standard 256-
ballꢀ 27mm x 27mm BGA substrate. Unlike other sur-
face-mount NV memory modules that require the battery
to be removable for solderingꢀ the internal ML battery
can tolerate exposure to convection reflow soldering
temperaturesꢀ allowing this single-piece component to
be handled with standard BGA assembly techniques.
The DS3070W RTC registers are double-buffered into
an internal and external set. The user has direct access
to the external set. Clock/calendar updates to the exter-
nal set of registers can be disabled and enabled to
allow the user to access static data. Assuming the
internal oscillator is onꢀ the internal registers are contin-
Table 1. RTC/Memory Operational Truth Table
CS
0
WE
1
CE
1
OE
0
MODE
ICC
Active
Active
Active
Active
Active
Active
Standby
Active
OUTPUTS
Active
RTC Read
RTC Read
RTC Write
SRAM Read
SRAM Read
SRAM Write
Standby
0
1
1
1
High Impedance
High Impedance
Active
0
0
1
X
1
1
0
0
1
1
0
1
High Impedance
High Impedance
High Impedance
Invalid
1
0
0
X
1
X
1
X
0
X
0
X
Invalid
(1)
X = Don’t care.
= See Figure 4.
(1)
____________________________________________________________________ 11
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
SRAM Read Mode
The DS3070W executes an SRAM read cycle whenever
CS (RTC chip select) and WE (write enable) are inactive
(high) and CE (SRAM chip enable) is active (low). The
unique address specified by the 21 address inputs (A0
to A20) defines which of the 2ꢀ097ꢀ152 bytes of SRAM
data is to be accessed. Valid data will be available to the
SRAM Write Mode
The DS3070W executes an SRAM write cycle whenever
CS is inactive (high) and the CE and WE signals are
active (low) after address inputs are stable. The later-
occurring falling edge of CE or WE determines the start of
the write cycle. The write cycle is terminated by the earlier
rising edge of CE or WE. All address inputs must be kept
valid throughout the write cycle. WE must return to the
eight data output drivers within t
(access time) after
ACC
the last address input signal is stableꢀ providing that CE
and OE (output enable) access times are also satisfied.
If CE and OE access times are not satisfiedꢀ then data
access must be measured from the later occurring sig-
high state for a minimum recovery time (t ) before
WR
another cycle can be initiated. The CS and OE control
signal should be kept inactive (high) during SRAM write
cycles to avoid bus contention. Howeverꢀ if the output dri-
vers have been enabled (CE and OE active) then WE dis-
nal (CE or OE) and the limiting parameter is either t
for
CO
CE or t for OE rather than address access.
ables the outputs in t
from its falling edge.
OE
ODW
Clock Operations
Table 2. RTC Register Map
DATA
ADDRESS
FUNCTION/RANGE
B7
B6
B5
10 YEAR
B4
B3
B2
B1
B0
xxxxFh
xxxxEh
xxxxDh
xxxxCh
xxxxBh
xxxxAh
xxxx9h
xxxx8h
xxxx7h
xxxx6h
xxxx5h
YEAR
YEAR
MONTH
00–99
01–12
01–31
01–07
00–23
00–59
00–59
00–39
X
X
X
X
X
10 M
10 DATE
MONTH
DATE
DATE
X
FT
X
X
X
X
DAY
HOUR
DAY
X
10 HOUR
HOUR
X
10 MINUTES
10 SECONDS
MINUTES
SECONDS
CENTURY
MINUTES
SECONDS
CONTROL
WATCHDOG
INTERRUPTS
ALARM DATE
OSC
W
R
BMB4
Y
10 CENTURY
BMB3 BMB2
ABE
10 DATE
WDS
AE
AM4
BMB1
Y
BMB0
RB1
RB0
Y
Y
Y
Y
Y
DATE
01–31
ALARM
HOURS
xxxx4h
xxxx3h
xxxx2h
AM3
AM2
AM1
Y
10 HOURS
HOURS
00–23
00–59
00–59
ALARM
MINUTES
10 MINUTES
MINUTES
ALARM
SECONDS
10 SECONDS
SECONDS
xxxx1h
xxxx0h
Y
Y
Y
0
Y
Y
0
Y
Y
0
Y
0
UNUSED
FLAGS
WF
AF
BLF
0
x = Don’t care address bits.
AE = Alarm flag enable.
X = Unused. Read/writeable under write and read bit control.
FT = Frequency test bit.
OSC = Oscillator start/stop bit.
W = Write bit.
Y = Unused. Read/writeable without write and read bit control.
ABE = Alarm in backup mode enable.
AM1–AM4 = Alarm mask bits.
WF = Watchdog flag.
R = Read bit.
AF = Alarm flag.
WDS = Watchdog steering bit.
BMB0–BMB4 = Watchdog multiplier bits.
RB0, RB1 = Watchdog resolution bits.
0 = Reads as a 0 and cannot be changed.
BLF = Battery low flag.
12
____________________________________________________________________
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
External updates are halted by writing a 1 to the read
bit (R). As long as a 1 remains in the R bitꢀ updating is
inhibited. After a halt is issuedꢀ the registers reflect the
RTC count (dayꢀ dateꢀ and time) that was current at the
moment the halt command was issued. Normal
updates to the external set of registers resume within 1
second after the R bit is set to a 0 for a minimum of
500µs. The R bit must be a 0 for a minimum of 500µs to
ensure the external registers have fully updated.
RTC Read Mode
The DS3070W executes an RTC read cycle whenever
CE (SRAM chip enable) and WE (write enable) are
inactive (high) and CS (RTC chip select) is active (low).
The least significant 4 address inputs (A0 to A3) define
which of the 16 RTC registers is to be accessed (see
Table 2). Valid data is available to the eight data output
drivers within t
(access time) after the last address
ACC
input signal is stableꢀ providing that CS and OE (output
enable) access times are also satisfied. If CS and OE
access times are not satisfiedꢀ then data access must
be measured from the later occurring signal (CS or OE)
Setting the Clock
As with a clock readꢀ it is also recommended to halt
updates prior to setting new time values. Setting the
write bit (W) to a 1 halts updates of the external RTC
registers 8h to Fh. After setting the W bit to a 1ꢀ the RTC
registers can be loaded with the desired count (dayꢀ
dateꢀ and time) in BCD format. Setting the W bit to a 0
then transfers the values written to the internal registers
and allows normal clock operation to resume.
and the limiting parameter is either t
for CS or t
OEC
CO
for OE rather than address access.
RTC Write Mode
The DS3070W executes an RTC write cycle whenever
CE is inactive (high) and the CS and WE signals are
active (low) after address inputs are stable. The later-
occurring falling edge of CS or WE determines the start
of the write cycle. The write cycle is terminated by the
earlier rising edge of CS or WE. All address inputs must
be kept valid throughout the write cycle. WE must return
Frequency Test Mode
The DS3070W frequency test mode uses the IRQ/FT
open-drain output. With the oscillator runningꢀ the
IRQ/FT output toggles at 512Hz when the FT bit is a 1ꢀ
the alarm-flag enable bit (AE) is a 0ꢀ and the watchdog-
enable bit (WDS) is a 1 or the WATCHDOG register is
written to 00h (FT • AE • (WDS + WATCHDOG)). The
IRQ/FT output and the frequency test mode can be
used to measure the actual frequency of the 32.768kHz
RTC oscillator. The FT bit is reset to a 0 on power-up.
to the high state for a minimum recovery time (t
)
WR
before another cycle can be initiated. The CE and OE
control signals should be kept inactive (high) during RTC
write cycles to avoid bus contention. Howeverꢀ if the out-
put drivers have been enabled (CS and OE active) then
WE disables the outputs in t
from its falling edge.
ODW
Clock Oscillator Mode
Using the Clock Alarm
The alarm settings and control for the DS3070W reside
within RTC registers 2h–5h. The INTERRUPTS register
(6h) contains two alarm-enable bits: alarm enable (AE)
and alarm in backup enable (ABE). The AE and ABE
bits must be set as described below for the IRQ/FT out-
put to be activated when an alarm match occurs.
The oscillator can be turned off to minimize battery cur-
rent drain. The OSC bit is the MSB of the SECONDS
registerꢀ and must be initialized to a 0 to start the oscil-
lator upon first power application. The OSC bit is facto-
ry set to a 1 prior to shipment. Oscillator operation and
frequency can be verified by setting the FT bit to a 1
and monitoring the IRQ/FT output for 512Hz.
The alarm can be programmed to activate on a specific
day of the month or repeat every dayꢀ hourꢀ minuteꢀ or
second. It can also be programmed to go off while the
DS3070W is in the Data Retention Mode to serve as a
system wake-up. Alarm mask bits AM1 to AM4 control
the alarm mode (see Table 3). Configurations not listed
in the table will default to the once-per-second mode to
notify the user of an incorrect alarm setting.
Reading the Clock
When reading the RTC dataꢀ it is recommended to halt
updates to the external set of double-buffered RTC reg-
isters. This puts the external registers into a static stateꢀ
allowing the data to be read without register values
changing during the read process. Normal updates to
the internal registers continue while in this state.
____________________________________________________________________ 13
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
Table 3. Alarm Mask Bits
AM4
AM3
AM2
AM1
ALARM RATE
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Once per second
When seconds match
When minutes and seconds match
When hoursꢀ minutesꢀ and seconds match
When dateꢀ hoursꢀ minutesꢀ and seconds match
When the RTC register values match alarm register set-
tingsꢀ the alarm flag (AF) is set to a 1. If AE is also a 1ꢀ
the alarm condition activates the IRQ/FT output. When
CS is activeꢀ the IRQ/FT signal can be cleared by hold-
The IRQ/FT output can also be activated during battery
backup mode. The IRQ/FT goes low if an alarm occurs
and both AE and ABE are set to 1. The AE and ABE
bits are reset to 0 during the power-up transitionꢀ but an
alarm generated during power-up will set AF to a 1.
Thereforeꢀ the AF bit can be read after system power-
up to determine if an alarm was generated during the
power-up sequence. Figure 3 illustrates alarm timing
during battery backup mode and power-up states.
ing the FLAGS register address stable for t
and forc-
RC
ing either OE or WE active (see Figure 1). The flag does
not change state until the end of the read/write cycle
and after the IRQ/FT signal has deasserted. To avoid
inadvertently clearing the IRQ/FT signal while preparing
for subsequent write/read cycles at other register
addressesꢀ assure that t
address (see Figure 2).
is met for that subsequent
AW
CE
WE OR OE
CS
t
RC
MAX
ADDRESS 0h
A0–A3
HIGH
IMPEDANCE
IRQ/FT
Figure 1. Clearing Active IRQ Waveforms
14
____________________________________________________________________
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
CE
t
AS
INTENTIONAL WRITE OR
READ AT ADDRESS Xh
INADVERTENT WRITE OR READ OF
RTC FLAGS REGISTER
WE OR OE
WILL RESET IRQ/FT
CS
A0–A3
ADDRESS 0h
ADDRESS Xh
HIGH
IMPEDANCE
IRQ/FT
Figure 2. Prevent Accidental Clearing of IRQ Waveforms
V
TP
V
CC
ABE, AE
AF
HIGH
IMPEDANCE
HIGH
IMPEDANCE
IRQ/FT
Figure 3. Battery Back-up Mode Alarm Waveforms
____________________________________________________________________ 15
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
source to the clock and SRAM to maintain time and
retain data. During power-upꢀ when V rises above
Using the Watchdog Timer
The watchdog timer can be used to detect an out-of-
control processor. The user programs the watchdog
timer by setting the desired timeout delay into the
WATCHDOG register. The five high-order WATCHDOG
register bits store a binary multiplier and the two lower-
order WATCHDOG bits select the resolutionꢀ where 00
= 1/ secondꢀ 01 = 1/ secondꢀ 10 = 1 secondꢀ and 11
= 4 seconds. The watchdog timeout value is then
determined by multiplication of the 5-bit multiplier value
with the 2-bit resolution value. (For example: writing
00001110 (0Eh) into the WATCHDOG register = 3 x 1
secondꢀ or 3 seconds.) If the processor does not reset
the timer within the specified periodꢀ the watchdog flag
(WF) is set to a 1 and a processor interrupt is generat-
ed and stays active until either WF is read or the
WATCHDOG register is read or written.
CC
V
ꢀ the power-switching circuit connects external V
SW
CC
to the clock and SRAMꢀ and disconnects the lithium
energy source. Normal clock or SRAM operation can
resume after V
exceeds V for a minimum duration
TP
CC
of t
.
REC
16
4
Battery Charging
is greater than V an internal regulator will
TP
When V
CC
charge the battery. The UL-approved charger circuit
includes short-circuit protection and a temperature-sta-
bilized voltage reference for on-demand charging of
the internal battery. Typical data retention expectations
greater than 2 years per charge cycle are achievable.
A maximum of 96 hours of charging time is required to
fully charge a depleted battery.
The MSB of the WATCHDOG register is the watchdog
steering bit (WDS). When WDS is set to a 0ꢀ the watch-
dog activates the IRQ/FT output when the watchdog
times out. WDS should not be written to a 1ꢀ and should
be initialized to a 0 if the watchdog function is enabled.
System Power Monitoring
When the external V
supply falls below the selected
CC
out-of-tolerance trip pointꢀ the output RST is forced
active (low). Once activeꢀ the RST is held active until
the V
supply has fallen below that of the internal bat-
CC
The watchdog timer resets when the processor per-
forms a read or write of the WATCHDOG register. The
timeout period then starts over. The watchdog timer is
disabled by writing a value of 00h to the WATCHDOG
register. The watchdog function is automatically dis-
abled upon power-up and the WATCHDOG register is
cleared to 00h.
tery. On power-upꢀ the RST output is held active until
the external supply is greater than the selected trip
point and one reset timeout period (t
) has elapsed.
RPU
This is sufficiently longer than t
to ensure that the
REC
RTC and SRAM are ready for access by the micro-
processor.
Freshness Seal and Shipping
The DS3070W is shipped from Dallas Semiconductor
with the RTC oscillator disabled and the lithium battery
electrically disconnectedꢀ guaranteeing that no battery
capacity has been consumed during transit or storage.
As shippedꢀ the lithium battery is ~60% chargedꢀ and
no pre-assembly charging operations should be
attempted.
Clock Accuracy
The DS3070W modules are trimmed at the factory to an
accuracy of 1 minute per month at +25°C.
Power-On Default States
Upon each application of power to the deviceꢀ the fol-
lowing register bits are automatically set to 0:
WDS = 0ꢀ BMB0–BMB4 = 0ꢀ RB0 = 0ꢀ RB1 = 0ꢀ AE = 0ꢀ
ABE = 0.
When V
is first applied at a level greater than V
ꢀ
CC
TP
the lithium battery is enabled for backup operation. The
user is required to enable the oscillator (MSB of SEC-
ONDS register) and initialize the required RTC registers
for proper timekeeping operation. A 96 hour initial bat-
tery charge time is recommended for new system
installations.
All other RTC bits are undefined.
Data-Retention Mode
The DS3070W provides full functional capability for V
CC
greater than 3.0V and write-protects by 2.8V. Data is
maintained in the absence of V without additional
CC
Applications Information
support circuitry. The NV SRAM constantly monitors
V
. Should the supply voltage decayꢀ the NV SRAM
CC
Power-Supply Decoupling
automatically write-protects itself. All inputs become
To achieve the best results when using the DS3070Wꢀ
don’t careꢀ and all data outputs become high imped-
assure that all V
and GND balls are connected and
CC
ance. As V
falls below approximately 2.5V (V )ꢀ the
SW
CC
decouple the power supply with a 0.1µF capacitor. Use a
high-qualityꢀ ceramic surface-mount capacitor if possible.
power-switching circuit connects the lithium energy
16
____________________________________________________________________
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
Surface-mount components minimize lead inductanceꢀ
Recommended Reflow Temperature
Profile
which improves performanceꢀ and ceramic capacitors
tend to have adequate high-frequency response for
decoupling applications.
Sn-Pb EUTECTIC
PROFILE FEATURE
ASSEMBLY
Avoiding Data Bus Contention
Care should be taken to avoid simultaneous access of
the SRAM and RTC devices (see Figure 4). Any chip-
Average ramp-up rate
(T to T )
3°C/second max
L
P
enable overlap violates t
and can result in invalid
CCS
Preheat
and unpredictable behavior.
- Temperature min (T
- Temperature max (T
)
100°C
150°C
Smin
Using the Open-Drain IRQ/FT
and RST Outputs
)
Smax
- Time (min to max) (ts)
60 to 120 seconds
The IRQ/FT and RST outputs are open drainꢀ and there-
fore require pullup resistors to realize a high logic out-
put level. Pullup resistor values between 1kΩ and 10kΩ
are typical.
T
to T
Smax
L
- Ramp-up rate
Time maintained above:
Temperature (T )
- Time (t )
L
183°C
60 to 150 seconds
-
L
Battery Charging/Lifetime
The DS3070W charges an ML battery to maximum
capacity in approximately 96 hours of operation when
Peak temperature (T )
P
225 +0/-5°C
V
is greater than V . Once the battery is chargedꢀ
TP
CC
Time within 5°C of actual peak
10 to 30 seconds
its lifetime depends primarily on the V
duty cycle.
CC
temperature (T )
P
The DS3070W can maintain data from a singleꢀ initial
charge for up to 2 years. Once rechargedꢀ this deep-
discharge cycle can be repeated for up to 20 timesꢀ
producing a worst-case service life of 40 years. More
typical duty cycles are of shorter durationꢀ enabling the
DS3070W to be charged hundreds of timesꢀ and
extending the service life well beyond 40 years.
Ramp-down rate
6°C/second max
Time 25°C to peak temperature
6 minutes max
Note: All temperatures refer to topside of the package, mea-
sured on the package body surface.
Recommended Cleaning
Procedures
The DS3070W can be cleaned using aqueous-based
cleaning solutions. No special precautions are needed
when cleaning boards containing a DS3070W module.
Removal of the topside label violates the environmental
integrity of the package and voids the warranty of the
product.
V
V
IH
IH
CE
CS
t
t
CCS
CCS
V
IH
V
IH
Figure 4. SRAM/RTC Data Bus Control
____________________________________________________________________ 17
3.3V Single-Piece 16Mb Nonvolatile SRAM
with Clock
Pin Configuration
1
0
1
1
1
3
1
4
1
5
1
6
1
7
1
8
1
9
1
2
2
0
TOP VIEW
1
2
6
3
4
5
7
9
8
GND
GND
A
B
A
B
A18
A17
A14
A13
A12
A11
A10
A9
IRQ/FT
A15
C
D
E
C
D
E
A16
RST
V
CC
F
F
WE
OE
G
H
G
H
CE
J
J
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
GND
GND
A8
A7
K
L
K
L
DS3070W
A6
M
N
P
M
N
P
A5
A4
A3
R
T
R
T
A2
A1
U
V
U
V
A0
W
Y
W
Y
GND
GND
1
0
1
1
1
1
2
1
4
1
5
1
6
1
8
2
0
3
4
6
7
8
9
1
3
1
7
1
9
2
5
Revision History
Pages changed at Rev1: 1ꢀ 3ꢀ 4ꢀ18
Package Information
For the latest package outline informationꢀ go to
www.maxim-ic.com/DallasPackInfo.
DS3070W BGA modules are recognized by Underwriters Laboratory (UL) under file E99151.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Productsꢀ Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Springer
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