DS3112N+W [MAXIM]
Framer, CMOS, PBGA256, 27 X 27 MM, 2.13 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-256;
| 型号： | DS3112N+W |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Framer, CMOS, PBGA256, 27 X 27 MM, 2.13 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, BGA-256 电信 电信集成电路 |
| 文件： | 总133页 (文件大小：1033K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS3112
TEMPE T3/E3 Multiplexer
3.3V T3/E3 Framer and M13/E13/G.747 Mux
www.maxim-ic.com
FEATURES
FUNCTIONAL DIAGRAM
ꢀ Operates as M13 or E13 Multiplexer or as
Stand-Alone T3 or E3 Framer
T1/E1
T1/E1
T1/E1
T1/E1
ꢀ Flexible Multiplexer can be Programmed for
T2/E2
Multiple Configurations Including:
M13 Multiplexing (28 T1 Lines into a T3
Data Stream)
E13 Multiplexing (16 E1 Lines into an E3
Data Stream)
T3/E3
E1 to T3 Multiplexing (21 E1 Lines into a T3
Data Stream)
ꢀ Two T1/E1 Drop and Insert Ports
T1/E1
T1/E1
T1/E1
T1/E1
T2/E2
DS3112
ꢀ Supports T3 C-Bit Parity Mode
ꢀ B3ZS/HDB3 Encoder and Decoder
ꢀ Generates and Detects T3/E3 Alarms
ꢀ Generates and Detects T2/E2 Alarms
APPLICATIONS
ꢀ Integrated HDLC Controller Handles LAPD
Wide Area Network Access Equipment
PBXs
Access Concentrators
Digital Cross-Connect Systems
Switches
Routers
Optical Multiplexers
ADMs
Messages Without Host Intervention
ꢀ Integrated FEAC Controller
ꢀ Integrated BERT Supports Performance
Monitoring
ꢀ T3/E3 and T1/E1 Diagnostic (Tx to Rx), Line
(Rx to Tx), and Payload Loopback
Supported
Test Equipment
ꢀ Nonmultiplexed or Multiplexed 16-Bit
Control Port (with Optional 8-Bit Mode)
ORDERING INFORMATION
ꢀ 3.3V Supply with 5V Tolerant I/O
ꢀ Available in 256-Pin 1.27mm Pitch PBGA
PART
TEMP RANGE PIN-PACKAGE
Package
DS3112
256 PBGA
256 PBGA
256 PBGA
256 PBGA
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
ꢀ IEEE 1149.1 JTAG Support
DS3112+
DS3112N
DS3112N+
+Denotes lead-free/RoHS-compliant package.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 092706
DS3112
TABLE OF CONTENTS
1
DETAILED DESCRIPTION
7
1.1
1.2
APPLICABLE STANDARDS ..............................................................................................................8
MAIN DS3112 TEMPE FEATURES................................................................................................9
1.2.1 General Features ................................................................................................................................... 9
1.2.2 T3/E3 Framer......................................................................................................................................... 9
1.2.3 T2/E2 Framer......................................................................................................................................... 9
1.2.4 HDLC Controller..................................................................................................................................... 9
1.2.5 FEAC Controller..................................................................................................................................... 9
1.2.6 BERT.................................................................................................................................................... 10
1.2.7 Diagnostics........................................................................................................................................... 10
1.2.8 Control Port.......................................................................................................................................... 10
1.2.9 Packaging and Power .......................................................................................................................... 10
2
PIN DESCRIPTION
14
2.2
CPU BUS SIGNAL DESCRIPTION .................................................................................................19
T3/E3 RECEIVE FRAMER SIGNAL DESCRIPTION...........................................................................21
T3/E3 TRANSMIT FORMATTER SIGNAL DESCRIPTION...................................................................23
LOW-SPEED (T1 OR E1) RECEIVE PORT SIGNAL DESCRIPTION....................................................25
LOW-SPEED (T1 OR E1) TRANSMIT PORT SIGNAL DESCRIPTION..................................................26
HIGH-SPEED (T3 OR E3) RECEIVE PORT SIGNAL DESCRIPTION ...................................................28
HIGH-SPEED (T3 OR E3) TRANSMIT PORT SIGNAL DESCRIPTION .................................................28
JTAG SIGNAL DESCRIPTION .......................................................................................................29
SUPPLY, TEST, RESET, AND MODE SIGNAL DESCRIPTION............................................................29
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
3
4
MEMORY MAP
MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT
31
33
4.1
4.2
4.3
MASTER RESET AND ID REGISTER DESCRIPTION.........................................................................33
MASTER CONFIGURATION REGISTERS DESCRIPTION ...................................................................34
MASTER STATUS AND INTERRUPT REGISTER DESCRIPTION..........................................................38
4.3.1 Status Registers................................................................................................................................... 38
4.3.2 MSR ..................................................................................................................................................... 39
4.4
TEST REGISTER DESCRIPTION ....................................................................................................47
5
T3/E3 FRAMER
48
5.1
5.2
5.3
5.4
5.5
5.6
T3/E3 LINE LOOPBACK ...............................................................................................................48
T3/E3 DIAGNOSTIC LOOPBACK ...................................................................................................48
T3/E3 PAYLOAD LOOPBACK........................................................................................................48
T3/E3 FRAMER CONTROL REGISTER DESCRIPTION .....................................................................49
T3/E3 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION ...............................................53
T3/E3 PERFORMANCE ERROR COUNTERS ..................................................................................59
6
7
M13/E13/G.747 MULTIPLEXER AND T2/E2/G.747 FRAME
62
6.1
6.2
6.3
6.4
T1/E1 AIS GENERATION.............................................................................................................62
T2/E2/G.747 FRAMER CONTROL REGISTER DESCRIPTION ..........................................................62
T2/E2/G.747 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION ....................................64
T1/E1 AIS GENERATION CONTROL REGISTER DESCRIPTION .......................................................68
T1/E1 LOOPBACK AND DROP AND INSERT FUNCTIONALITY
70
7.1
7.2
7.3
7.4
7.5
T1/E1 LINE LOOPBACK ...............................................................................................................70
T1/E1 DIAGNOSTIC LOOPBACK ...................................................................................................70
T1 LINE LOOPBACK COMMAND....................................................................................................70
T1/E1 DROP AND INSERT............................................................................................................70
T1/E1 LOOPBACK CONTROL REGISTER DESCRIPTION .................................................................71
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DS3112
7.6
7.7
T1 LINE LOOPBACK COMMAND STATUS REGISTER DESCRIPTION .................................................75
T1/E1 DROP AND INSERT CONTROL REGISTER DESCRIPTION ......................................................76
8
9
BERT
78
8.1
BERT REGISTER DESCRIPTION ..................................................................................................78
HDLC CONTROLLER
87
9.1
9.2
9.2
9.3
RECEIVE OPERATION..................................................................................................................87
TRANSMIT OPERATION................................................................................................................87
HDLC CONTROL AND FIFO REGISTER DESCRIPTION ..................................................................88
HDLC STATUS AND INTERRUPT REGISTER DESCRIPTION.............................................................91
10 FEAC CONTROLLER
96
10.1
10.2
FEAC CONTROL REGISTER DESCRIPTION...................................................................................96
FEAC STATUS REGISTER DESCRIPTION......................................................................................98
11 JTAG
99
11.1
TAP CONTROLLER STATE MACHINE DESCRIPTION ....................................................................100
Test-Logic-Reset ........................................................................................................................... 101
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
11.1.7
11.1.8
11.1.9
Run-Test-Idle................................................................................................................................. 101
Select-DR-Scan............................................................................................................................. 101
Capture-DR.................................................................................................................................... 101
Shift-DR ......................................................................................................................................... 101
Exit1-DR......................................................................................................................................... 101
Pause-DR ...................................................................................................................................... 101
Exit2-DR......................................................................................................................................... 101
Update-DR..................................................................................................................................... 101
11.1.10 Select-IR-Scan............................................................................................................................... 101
11.1.11 Capture-IR ..................................................................................................................................... 102
11.1.12 Shift-IR........................................................................................................................................... 102
11.1.13 Exit1-IR .......................................................................................................................................... 102
11.1.14 Pause-IR........................................................................................................................................ 102
11.1.15 Exit2-IR .......................................................................................................................................... 102
11.1.16 Update-IR....................................................................................................................................... 102
11.2
INSTRUCTION REGISTER AND INSTRUCTIONS .............................................................................103
11.2.1
SAMPLE/PRELOAD...................................................................................................................... 103
EXTEST......................................................................................................................................... 103
BYPASS......................................................................................................................................... 103
IDCODE......................................................................................................................................... 103
HIGHZ............................................................................................................................................ 103
CLAMP........................................................................................................................................... 104
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.3
11.3.1
11.3.2
11.3.3
TEST REGISTERS......................................................................................................................104
Bypass Register............................................................................................................................. 104
Identification Register .................................................................................................................... 104
Boundary Scan Register................................................................................................................ 104
12 DC ELECTRICAL CHARACTERISTICS
13 AC ELECTRICAL CHARACTERISTICS
14 APPLICATIONS AND STANDARDS OVERVIEW
109
110
121
14.1
14.2
14.3
14.4
14.5
14.6
14.7
APPLICATION EXAMPLES...........................................................................................................121
M13 BASICS.............................................................................................................................122
T2 FRAMING STRUCTURE .........................................................................................................123
M12 MULTIPLEXING..................................................................................................................123
T3 FRAMING STRUCTURE .........................................................................................................125
M23 MULTIPLEXING..................................................................................................................125
C-BIT PARITY MODE .................................................................................................................126
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DS3112
14.8
14.9
14.10
14.11
14.12
E13 BASICS .............................................................................................................................128
E2 FRAMING STRUCTURE AND E12 MULTIPLEXING....................................................................129
E3 FRAMING STRUCTURE AND E23 MULTIPLEXING................................................................129
G.747 BASICS......................................................................................................................131
G.747 FRAMING STRUCTURE AND E12 MULTIPLEXING...........................................................132
15 PACKAGE INFORMATION
133
15.1
256-BALL PBGA (56-G6002-001)............................................................................................133
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DS3112
LIST OF FIGURES
Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode)................................................................... 11
Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode)................................................................... 12
Figure 1-3. DS3112 Framer and Multiplexer Block Diagram (G.747 Mode) ............................................................. 13
Figure 2-1. T3/E3 Receive Framer Timing ................................................................................................................ 22
Figure 2-2. T3/E3 Transmit Formatter Timing ........................................................................................................... 24
Figure 4-1. Event Status Bit....................................................................................................................................... 38
Figure 4-2. Alarm Status Bit....................................................................................................................................... 38
Figure 4-3. Real-Time Status Bit ............................................................................................................................... 39
Figure 4-4. BERT Status Bit Flow.............................................................................................................................. 41
Figure 4-5. HDLC Status Bit Flow.............................................................................................................................. 42
Figure 4-6. T2E2SR1 Status Bit Flow........................................................................................................................ 43
Figure 4-7. T2E2SR2 Status Bit Flow........................................................................................................................ 44
Figure 4-8. T1LB Status Bit Flow............................................................................................................................... 44
Figure 4-9. T3E3SR Status Bit Flow.......................................................................................................................... 45
Figure 5-1. T3E3SR Status Bit Flow.......................................................................................................................... 54
Figure 6-1. T2E2SR1 Status Bit Flow........................................................................................................................ 65
Figure 6-2. T2E2SR2 Status Bit Flow........................................................................................................................ 66
Figure 7-1. T1LBSR1 and T1LBSR2 Status Bit Flow................................................................................................ 76
Figure 8-1. BERT Status Bit Flow.............................................................................................................................. 86
Figure 9-1. HSR Status Bit Flow................................................................................................................................ 94
Figure 11-1. JTAG Block Diagram............................................................................................................................. 99
Figure 11-2. TAP Controller State Machine............................................................................................................. 100
Figure 13-1. Low-Speed (T1 and E1) Port AC Timing Diagram.............................................................................. 111
Figure 13-2. High-Speed (T3 and E3) Port AC Timing Diagram............................................................................. 112
Figure 13-3. Framer (T3 and E3) Port AC Timing Diagram..................................................................................... 113
Figure 13-4. Intel Read Cycle (Nonmultiplexed)...................................................................................................... 115
Figure 13-5. Intel Write Cycle (Nonmultiplexed)...................................................................................................... 115
Figure 13-6. Motorola Read Cycle (Nonmultiplexed) .............................................................................................. 116
Figure 13-7. Motorola Write Cycle (Nonmultiplexed)............................................................................................... 116
Figure 13-8. Intel Read Cycle (Multiplexed) ............................................................................................................ 117
Figure 13-9. Intel Write Cycle (Multiplexed) ............................................................................................................ 117
Figure 13-10. Motorola Read Cycle (Multiplexed)................................................................................................... 118
Figure 13-11. Motorola Write Cycle (Multiplexed) ................................................................................................... 118
Figure 13-12. JTAG Test Port Interface AC Timing Diagram.................................................................................. 119
Figure 13-13. Reset and Manual Error Counter/Insert AC Timing Diagram............................................................ 120
Figure 14-1. Channelized T3/E3 Application........................................................................................................... 121
Figure 14-2. Unchannelized Dual T3/E3 Application............................................................................................... 122
Figure 14-3. T2 M-Frame Structure......................................................................................................................... 124
Figure 14-4. T2 Stuff Block Structure ...................................................................................................................... 124
Figure 14-5. T3 M-Frame Structure......................................................................................................................... 127
Figure 14-6. T3 Stuff Block Structure ...................................................................................................................... 128
Figure 14-7. E2 Frame Structure............................................................................................................................. 130
Figure 14-8. E3 Frame Structure............................................................................................................................. 130
Figure 14-9. G.747 Frame Structure........................................................................................................................ 132
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DS3112
LIST OF TABLES
Table 2-1. Pin Naming Convention............................................................................................................................ 14
Table 2-2. Pin Description ......................................................................................................................................... 14
Table 2-3. Mode Select Decode ................................................................................................................................ 30
Table 3-1. Memory Map............................................................................................................................................. 31
Table 5-1. T3 Alarm Criteria ...................................................................................................................................... 56
Table 5-2. E3 Alarm Criteria ...................................................................................................................................... 57
Table 6-1. T2 Alarm Criteria ...................................................................................................................................... 67
Table 6-2. E2 Alarm Criteria ...................................................................................................................................... 67
Table 6-3. G.747 Alarm Criteria................................................................................................................................. 67
Table 11-1. Instruction Codes.................................................................................................................................. 103
Table 11-2. Boundary Scan Control Bits ................................................................................................................. 104
Table 12-1. Recommended DC Operating Conditions............................................................................................ 109
Table 12-2. DC Characteristics................................................................................................................................ 109
Table 13-1. AC Characteristics—Low-Speed (T1 and E1) Ports ............................................................................ 110
Table 13-2. AC Characteristics—High-Speed (T3 and E3) Ports ........................................................................... 112
Table 13-3. AC Characteristics–Framer (T3 and E3) Ports .................................................................................... 113
Table 13-4. AC Characteristics—CPU Bus (Multiplexed and Nonmultiplexed) ...................................................... 114
Table 13-5. AC Characteristics—JTAG Test Port Interface.................................................................................... 119
Table 13-6. AC Characteristics—Reset and Manual Error Counter/Insert Signals................................................. 120
Table 14-1. T Carrier Rates..................................................................................................................................... 122
Table 14-2. T2 Overhead Bit Assignments.............................................................................................................. 123
Table 14-3. T3 Overhead Bit Assignments.............................................................................................................. 125
Table 14-4. C-Bit Assignment for C-Bit Parity Mode ............................................................................................... 126
Table 14-5. E Carrier Rates..................................................................................................................................... 128
Table 14-6. G.747 Carrier Rates ............................................................................................................................. 131
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DS3112
1 DETAILED DESCRIPTION
The DS3112 TEMPE (T3 E3 MultiPlexEr) device can be used either as a multiplexer or a T3/E3 framer.
When the device is used as a multiplexer, it can be operated in one of three modes:
M13—Multiplex 28 T1 lines into a T3 data stream
E13—Multiplex 16 E1 lines into an E3 data stream
G.747—Multiplex 21 E1 lines into a T3 data stream
See Figure 1-1, Figure 1-2, and Figure 1-3 for block diagrams of these three modes. In each of the block
diagrams, the receive section is at the bottom and the transmit section is at the top. The receive path is
defined as incoming T3/E3 data and the transmit path is defined as outgoing T3/E3 data. When the device
is operated solely as a T3 or E3 framer, the multiplexer portion of the device is disabled and the raw
T3/E3 payload will be output at the FRD output and input at the FTD input. See Figure 1-1 and
Figure 1-2 for details.
In the receive path, raw T3/E3 data is clocked into the device (either in a bipolar or unipolar fashion) with
the HRCLK at the HRPOS and HRNEG inputs. The data is then framed by the T3/E3 framer and passed
through the two-step demultiplexing process to yield the resultant T1 and E1 data streams, which are
output at the LRCLK and LRDAT outputs. In the transmit path, the reverse occurs. The T1 and E1 data
streams are input to the device at the LTCLK and LTDAT inputs. The device will sample these inputs
and then multiplex the T1 and E1 data streams through a two-step multiplexing process to yield the
resultant T3 or E3 data stream. Then this data stream is passed through the T3/E3 formatter to have the
framing overhead added, and the final data stream to be transmitted is output at the HTPOS and HTNEG
outputs using the HTCLK output.
The DS3112 has been designed to meet all of the latest telecommunications standards. Section 1.1 lists all
of the applicable standards for the device.
The TEMPE device has a number of advanced features such as:
•
•
•
•
The ability to drop and insert up to two T1 or E1 ports
An on-board HDLC controller with 256-byte buffers
An on-board Bit Error Rate Tester (BERT)
Advanced diagnostics to create and detect many different types of errors
See Section 1.2 for a complete list of main features within the device.
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DS3112
1.1 Applicable Standards
1) American National Standard for Telecommunications - ANSI T1.107 – 1995 “Digital Hierarchy -
Formats Specification”
2) American National Standard for Telecommunications - ANSI T1.231 - 199X – Draft “Digital
Hierarchy - Layer 1 In-Service Digital Transmission Performance Monitoring”
3) American National Standard for Telecommunications - ANSI T1.231 – 1993 “Digital Hierarchy -
Layer 1 In-Service Digital Transmission Performance Monitoring”
4) American National Standard for Telecommunications - ANSI T1.404 – 1994 “Network-to-Customer
Installation – DS3 Metallic Interface Specification”
5) American National Standard for Telecommunications - ANSI T1.403 – 1999 “Network and Customer
Installation Interfaces – DS1 Electrical Interface”
6) American National Standard for Telecommunications - ANSI T1.102 – 1993 “Digital Hierarchy –
Electrical Interfaces”
7) Bell Communications Research - TR-TSY-000009, Issue 1, May 1986 “Asynchronous Digital
Multiplexes Requirements and Objectives”
8) Bell Communications Research - TR-TSY-000191, Issue 1, May 1986 “Alarm Indication Signal
Requirements and Objectives”
9) Bellcore - GR-499-CORE, Issue 1, December 1995 “Transport Systems Generic Requirements
(TSGR): Common Requirements”
10) Bellcore - GR-820-CORE, Issue 1, November 1994 “Generic Digital Transmission Surveillance”
11) Network Working Group Request for Comments - RFC1407, January, 1993 “Definition of Managed
Objects for the DS3/E3 Interface Type”
12) International Telecommunication Union (ITU) G.703, 1991 “Physical/Electrical Characteristics of
Hierarchical Digital Interfaces
13) International Telecommunication Union (ITU) G.823, March 1993 “The Control of Jitter and Wander
Within Digital Networks Which are Based on the 2048kbps Hierarchy”
14) International Telecommunication Union (ITU) G.742, 1993 “Second Order Digital Multiplex
Equipment Operating at 8448 kbps and Using Positive Justification”
15) International Telecommunication Union (ITU) G.747, 1993 “Second Order Digital Multiplex
Equipment Operating at 6312 kbps and Multiplexing Three Tributaries at 2048kbps”
16) International Telecommunication Union (ITU) G.751, 1993 “Digital Multiplex Equipments Operating
at the Third Order Bit Rate of 34368kbps and Using Positive Justification”
17) International Telecommunication Union (ITU) G.775, November 1994 “Loss Of Signal (LOS) and
Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria”
18) International Telecommunication Union (ITU) O.151, October 1992 “Error Performance Measuring
Equipment Operating at the Primary Rate And Above”
19) International Telecommunication Union (ITU) O.153, October 1992 “Basic Parameters for the
Measurement of Error Performance at Bit Rates Below the Primary Rate”
20) International Telecommunication Union (ITU) O.161, 1984 “In-Service Code Violation Monitors for
Digital Systems”
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DS3112
1.2 Main DS3112 TEMPE Features
1.2.1 General Features
ꢀ Can be operated as a standalone T3 or E3 framer without any M13 or E13 multiplexing
ꢀ T1/E1 FIFOs in the receive direction provide T1/E1 demultiplexed clocks with very little jitter
ꢀ Two T1/E1 drop and insert ports
ꢀ B3ZS/HDB3 encoder and decoder
ꢀ T3 C-Bit Parity mode
ꢀ All the receive T1/E1 ports can be clocked out on a common clock
ꢀ All the transmit T1/E1 ports can be clocked in on a common clock
ꢀ Generates gapped clocks that can be used as demand clocks in unchannelized T3/E3 applications
ꢀ T1/E1 ports can be configured into a “loop-timed” mode
ꢀ T3/E3 port interfaces can be either bipolar or unipolar
ꢀ The clock, data, and control signals can be inverted to allow a glueless interface to other device
ꢀ Loss of transmit and receive clock detect
1.2.2 T3/E3 Framer
ꢀ Generates T3/E3 Alarm Indication Signal (AIS) and Remote Alarm Indication (RAI) alarms
ꢀ Transmit framer pass through mode
ꢀ Generates T3 idle signal
ꢀ Detects the following T3/E3 alarms and events: Loss Of Signal (LOS), Loss Of Frame (LOF), Alarm
Indication Signal (AIS), Remote Alarm Indication (RAI), T3 idle signal, Change Of Frame Alignment
(COFA), B3ZS and HDB3 codewords being received, Severely Errored Framing Event (SEFE), and
T3 Application ID status indication
1.2.3 T2/E2 Framer
ꢀ Generates T2/E2 Alarm Indication Signal (AIS) and Remote Alarm Indication (RAI) alarms
ꢀ Generates Alarm Indication Signal (AIS) for T1/E1 data streams in both the transmit and receive
directions
ꢀ Detects the following T2/E2 alarms and events: Loss Of Frame (LOF), Alarm Indication Signal
(AIS), and Remote Alarm Indication (RAI)
ꢀ Detects T1 line loopback commands (C3 bit is the inverse of C1 and C2)
ꢀ Generates T1 line loopback commands
1.2.4 HDLC Controller
ꢀ Designed to handle multiple LAPD messages without Host intervention
ꢀ 256 byte receive and transmit buffers are large enough to handle the three T3 messages (Path ID, Idle
Signal ID, and Test Signal ID) that are sent and received once a second which means the Host only
needs to access the HDLC Controller once a second
ꢀ Handles all of the normal Layer 2 tasks such as zero stuffing/destuffing, CRC generation/checking,
abort generation/checking, flag generation/detection, and byte alignment
ꢀ Programmable high and low watermarks for the FIFO
ꢀ HDLC Controller can be used in either the T3 C-Bit Parity Mode or in the Sn Bits in the E3 Mode
1.2.5 FEAC Controller
ꢀ Designed to handle multiple FEAC codewords without Host intervention
ꢀ Receive FEAC automatically validates incoming codewords and stores them in a 4-byte FIFO
ꢀ Transmit FEAC can be configured to send either one codeword, or constant codewords, or two
different codewords back-to-back to create T3 Line Loopback commands
ꢀ FEAC Controller can be used in either the T3 C-Bit Parity Mode or in the Sn Bits in the E3 Mode
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DS3112
1.2.6 BERT
ꢀ Can generate and detect the pseudorandom patterns of 27 - 1, 211 - 1, 215 - 1 and QRSS as well as
repetitive patterns from 1 to 32 bits in length
ꢀ BERT is a global chip resource that can be used either in the T3/E3 data path or in any one of the T1
or E1 data paths
ꢀ Large error counter (24 bits) allows testing to proceed for long periods without Host intervention
ꢀ Errors can be inserted into the generated BERT patterns for diagnostic purposes
1.2.7 Diagnostics
ꢀ T3/E3 and T1/E1 diagnostic loopbacks (transmit to receive)
ꢀ T3/E3 and T1/E1 line loopbacks (receive to transmit)
ꢀ T3/E3 payload loopback
ꢀ T3/E3 errors counters for: BiPolar Violations (BPV), Code Violations (CV), Loss Of Frame (LOF),
framing bit errors (F, M or FAS), EXcessive Zeros (EXZ), T3 Parity bits, T3 C-Bit Parity, and Far
End Block Errors (FEBE)
ꢀ Error counters can be either updated automatically on one second boundaries as timed by the DS3112
or via software control or via an external hardware pulse
ꢀ Can insert the following T3/E3 errors: BiPolar Violations (BPV), EXcessive Zeros (EXZ), T3 Parity
bits, T3 C-Bit Parity, framing bit errors (F, M, or FAS)
ꢀ Inserted errors can be either controlled via software or via an external hardware pulse
ꢀ Generates T2/E2 Loss Of Frame (LOF)
1.2.8 Control Port
ꢀ Nonmultiplexed or multiplexed 16-bit control port (with an optional 8-bit mode)
ꢀ Intel and Motorola Bus compatible
1.2.9 Packaging and Power
ꢀ 3.3V low-power CMOS with 5V tolerant inputs and outputs
ꢀ 256-pin plastic BGA package (27mm x 27mm)
ꢀ IEEE 1149.1 JTAG test port
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DS3112
Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode)
FTMEI
FTDEN
FTD
FTCLK
FTSOF
Signal
Inversion
Control
HRCLK
Loss Of Transmit Clock
7 to 1
Mux
4 to 1
Mux
T3
Formatter
Sync
Control
T2
For-
LTDAT
LTCLK
1
2
matter
LTDAT
LTCLK
LTDAT
LTCLK
BERT Mux
LTDAT
LTCLK
7
Transmit
BERT
1 of 7
LTDATA
LTCLKA
LTDATB
LTCLKB
1 of 28
HDLC Controller
with 256 Byte
Transmit
Receive
LTCCLK
Buffer
from
other
ports
FEAC Controller
LRDATA
LRCLKA
from
other
ports
Receive
BERT
LRDATB
LRCLKB
T3
Framer
1 to 7
Demux
1 to 4
Demux
BERT Mux
1
2
LRDAT
LRCLK
T2
Framer
LRDAT
LRCLK
LRDAT
LRCLK
7
LRDAT
LRCLK
1 of 7
LRCCLK
FRSOF
FRCLK
FRD
Error
Counters
Signal
Inversion
Control
FRDEN
FRLOS
FRLOF
JTDI
JTRST*
JTCLK
JTMS
JTAG
Test
Block
CPU Interface & Global Configuration
(Routed to All Blocks)
JTDO
CA0 to CD0 to CWR* CRD* CCS* CALE CIM CINT* CMS TEST RST*
FRMECU
T3E3MS G747E
CA7
CD15 (CR/W*) (CDS*)
(tied low) (tied low)
11 of 133
DS3112
Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode)
FTMEI
FTDEN
FTD
FTCLK
FTSOF
Signal
Inversion
Control
HRCLK
Loss Of Transmit Clock
4 to 1
Mux
4 to 1
Mux
E3
Formatter
Sync
Control
E2
For-
matter
LTDAT
LTCLK
1
LTDAT
LTCLK
2
3
LTDAT
LTCLK
BERT Mux
LTDAT
LTCLK
4
Transmit
BERT
1 of 4
LTDATA
LTCLKA
LTDATB
LTCLKB
1 of 16
HDLC Controller
with 256 Byte
Transmit
Receive
LTCCLK
Buffer
from
other
ports
FEAC Controller
LRDATA
LRCLKA
from
other
ports
Receive
BERT
LRDATB
LRCLKB
E3
Framer
1 to 4
Demux
1 to 4
Demux
BERT Mux
1
2
LRDAT
LRCLK
E2
Framer
LRDAT
LRCLK
3
LRDAT
LRCLK
4
LRDAT
LRCLK
1 of 4
LRCCLK
FRSOF
FRCLK
FRD
Error
Counters
Signal
Inversion
Control
FRDEN
FRLOS
FRLOF
JTDI
JTRST*
JTCLK
JTMS
JTAG
Test
Block
CPU Interface & Global Configuration
(Routed to All Blocks)
JTDO
CA0 to CD0 to CWR* CRD* CCS* CALE CIM CINT* CMS TEST RST*
FRMECU
T3E3MS G747E
(tied high) (tied low)
CA7
CD15 (CR/W*) (CDS*)
12 of 133
DS3112
Figure 1-3. DS3112 Framer and Multiplexer Block Diagram (G.747 Mode)
FTMEI
FTDEN
FTD
FTCLK
FTSOF
Signal
Inversion
Control
HRCLK
Loss Of Transmit Clock
7 to 1
Mux
3 to 1
Mux
T3
Formatter
Sync
Control
G747
For-
1
2
matter
LTDAT
LTCLK
LTDAT
LTCLK
BERT Mux
LTDAT
LTCLK
7
Transmit
BERT
1 of 7
LTDATA
LTCLKA
LTDATB
LTCLKB
1 of 21
HDLC Controller
with 256 Byte
Transmit
Receive
LTCCLK
Buffer
from
other
ports
FEAC Controller
LRDATA
LRCLKA
from
other
ports
Receive
BERT
LRDATB
LRCLKB
T3
Framer
1 to 7
Demux
1 to 3
Demux
BERT Mux
1
2
LRDAT
LRCLK
G747
Framer
LRDAT
LRCLK
LRDAT
LRCLK
7
1 of 7
LRCCLK
FRSOF
FRCLK
FRD
Error
Counters
Signal
Inversion
Control
FRDEN
FRLOS
FRLOF
JTDI
JTRST*
JTCLK
JTMS
JTAG
Test
Block
CPU Interface & Global Configuration
(Routed to All Blocks)
JTDO
FRMECU CA0 to CD0 to CWR* CRD* CCS* CALE CIM CINT* CMS TEST RST* T3E3MS G747E
CA7 CD15 (CR/W*) (CDS*) (tied low) (tied high)
13 of 133
DS3112
2 PIN DESCRIPTION
This section describes the input and output signals on the DS3112. Signal names follow a convention that
is shown in Table 2-1. Table 2-2 lists all the signals, their signal type, description, and pin location.
Table 2-1. Pin Naming Convention
FIRST
LETTERS
SIGNAL CATEGORY
SECTION
C
FR
FT
LR
LT
HR
HT
J
CPU/Host Control Access Port
T3/E3 Receive Framer
T3/E3 Transmit Formatter
Low-Speed (T1 or E1) Receive Port
Low-Speed (T1 or E1) Transmit Port
High-Speed (T3 or E3) Receive Port
High-Speed (T3 or E3) Transmit Port
JTAG Test Port
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Table 2-2. Pin Description
PIN
C7
H3
H2
H1
J4
J3
J2
J1
K2
C4
C2
D2
D3
E4
C1
D1
E3
E2
E1
F3
G4
F2
F1
G3
G2
G1
B3
A2
B2
NAME
CALE
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CCS
CD0
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CIM
CINT
CMS
TYPE
I
FUNCTION
CPU Bus Address Latch Enable
CPU Bus Address Bit 0 (LSB)
CPU Bus Address Bit 1
CPU Bus Address Bit 2
CPU Bus Address Bit 3
CPU Bus Address Bit 4
CPU Bus Address Bit 5
CPU Bus Address Bit 6
CPU Bus Address Bit 7 (MSB)
CPU Bus Chip Select (Active Low)
CPU Bus Data Bit 0 (LSB)
CPU Bus Data Bit 1
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
CPU Bus Data Bit 2
CPU Bus Data Bit 3
CPU Bus Data Bit 4
CPU Bus Data Bit 5
CPU Bus Data Bit 6
CPU Bus Data Bit 7
CPU Bus Data Bit 8
CPU Bus Data Bit 9
CPU Bus Data Bit 10
CPU Bus Data Bit 11
CPU Bus Data Bit 12
CPU Bus Data Bit 13
CPU Bus Data Bit 14
CPU Bus Data Bit 15 (MSB)
CPU Bus Intel/Motorola Bus Select, 0 = Intel, 1 = Motorola
CPU Bus Interrupt
O
I
CPU Bus Mode Select, 0 = 16 Bit, 1 = 8 Bit Mode
14 of 133
DS3112
PIN
D5
NAME
CRD(CDS)
CWR
(CR/W)
FRCLK
FRD
FRDEN
FRLOF
FRLOS
FRMECU
FRSOF
FTCLK
FTD
FTDEN
FTMEI
FTSOF
TYPE
FUNCTION
CPU Bus Read Enable (CPU Bus Data Strobe)
I
A3
I
CPU Bus Write Enable (CPU Bus Read/Write Select)
A9
B9
C9
C8
B8
O
O
O
O
O
I
O
I
I
Receive Framer (T3 or E3) Clock Output
Receive Framer (T3 or E3) Data Output
Receive Framer (T3 or E3) Data Enable Output
Receive Framer (T3 or E3) Loss Of Frame Output
Receive Framer (T3 or E3) Loss Of Signal Output
Receive Framer (T3 or E3) Manual Error Counter Update
Receive Framer (T3 or E3) Start Of Frame Pulse
Transmit Framer (T3 or E3) Clock Input
A7
A8
A10
B10
C10
C11
A11
Transmit Framer (T3 or E3) Data Input
O
I
I/O
Transmit Framer (T3 or E3) Data Enable Output
Transmit Framer (T3 or E3) Manual Error Insert Pulse
Transmit Framer (T3 or E3) Start Of Frame Pulse
G.747 Mode Enable, 0 = Normal T3 Mode, 1 = G.747
Mode
B6
G.747E
I
A13
C12
HRCLK
HRNEG
I
I
High-Speed (T3 or E3) Port Receive Clock Input
High-Speed (T3 or E3) Port Receive Negative Data Input
High-Speed (T3 or E3) Port Receive Positive or NRZ Data
Input
High-Speed (T3 or E3) Port Transmit Clock Output
High-Speed (T3 or E3) Port Transmit Negative Data
Output
B13
B14
A14
HRPOS
HTCLK
HTNEG
I
O
O
High-Speed (T3 or E3) Port Transmit Positive or NRZ Data
Output
C14
HTPOS
O
D7
B5
A4
A5
C6
JTCLK
JTDI
JTDO
JTMS
JTRST
I
I
O
I
I
JTAG IEEE 1149.1 Test Serial Clock
JTAG IEEE 1149.1 Test Serial Data Input
JTAG IEEE 1149.1 Test Serial Data Output
JTAG IEEE 1149.1 Test Mode Select
JTAG IEEE 1149.1 Test Reset (Active Low)
Low-Speed (T1 or E1) Port Common Receive Clock Input
Low-Speed (T1 or E1) Receive Clock from Port 1
Low-Speed (T1 or E1) Receive Clock from Port 2
Low-Speed (T1 or E1) Receive Clock from Port 3
Low-Speed (T1 or E1) Receive Clock from Port 4
Low-Speed (T1 or E1) Receive Clock from Port 5
Low-Speed (T1 or E1) Receive Clock from Port 6
Low-Speed (T1 or E1) Receive Clock from Port 7
Low-Speed (T1 or E1) Receive Clock from Port 8
Low-Speed (T1 or E1) Receive Clock from Port 9
Low-Speed (T1 or E1) Receive Clock from Port 10
Low-Speed (T1 or E1) Receive Clock from Port 11
Low-Speed (T1 or E1) Receive Clock from Port 12
Low-Speed (T1 or E1) Receive Clock from Port 13
Low-Speed (T1 or E1) Receive Clock from Port 14
G20
N2
R1
LRCCLK
LRCLK1
LRCLK2
LRCLK3
LRCLK4
LRCLK5
LRCLK6
LRCLK7
LRCLK8
LRCLK9
LRCLK10
LRCLK11
LRCLK12
LRCLK13
LRCLK14
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
R3
U2
V2
Y2
Y3
Y5
Y6
V8
V9
V10
V11
Y13
15 of 133
DS3112
PIN
W14
Y16
Y17
U16
V18
V19
V20
T20
R20
N18
M18
L18
K18
H20
K1
M1
N1
P2
P4
T3
U3
W3
U5
W5
W6
Y7
NAME
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
FUNCTION
LRCLK15
LRCLK16
LRCLK17
LRCLK18
LRCLK19
LRCLK20
LRCLK21
LRCLK22
LRCLK23
LRCLK24
LRCLK25
LRCLK26
LRCLK27
LRCLK28
LRCLKA
LRCLKB
LRDAT1
LRDAT2
LRDAT3
LRDAT4
LRDAT5
LRDAT6
LRDAT7
LRDAT8
LRDAT9
LRDAT10
LRDAT11
LRDAT12
LRDAT13
LRDAT14
LRDAT15
LRDAT16
LRDAT17
LRDAT18
LRDAT19
LRDAT20
LRDAT21
LRDAT22
LRDAT23
LRDAT24
LRDAT25
LRDAT26
LRDAT27
LRDAT28
LRDATA
LRDATB
Low-Speed (T1 or E1) Receive Clock from Port 15
Low-Speed (T1 or E1) Receive Clock from Port 16
Low-Speed (T1 or E1) Receive Clock from Port 17
Low-Speed (T1 or E1) Receive Clock from Port 18
Low-Speed (T1 or E1) Receive Clock from Port 19
Low-Speed (T1 or E1) Receive Clock from Port 20
Low-Speed (T1 or E1) Receive Clock from Port 21
Low-Speed (T1 or E1) Receive Clock from Port 22
Low-Speed (T1 or E1) Receive Clock from Port 23
Low-Speed (T1 or E1) Receive Clock from Port 24
Low-Speed (T1 or E1) Receive Clock from Port 25
Low-Speed (T1 or E1) Receive Clock from Port 26
Low-Speed (T1 or E1) Receive Clock from Port 27
Low-Speed (T1 or E1) Receive Clock from Port 28
Low-Speed (T1 or E1) Receive Clock from Drop Port A
Low-Speed (T1 or E1) Receive Clock from Drop Port B
Low-Speed (T1 or E1) Receive Data from Port 1
Low-Speed (T1 or E1) Receive Data from Port 2
Low-Speed (T1 or E1) Receive Data from Port 3
Low-Speed (T1 or E1) Receive Data from Port 4
Low-Speed (T1 or E1) Receive Data from Port 5
Low-Speed (T1 or E1) Receive Data from Port 6
Low-Speed (T1 or E1) Receive Data from Port 7
Low-Speed (T1 or E1) Receive Data from Port 8
Low-Speed (T1 or E1) Receive Data from Port 9
Low-Speed (T1 or E1) Receive Data from Port 10
Low-Speed (T1 or E1) Receive Data from Port 11
Low-Speed (T1 or E1) Receive Data from Port 12
Low-Speed (T1 or E1) Receive Data from Port 13
Low-Speed (T1 or E1) Receive Data from Port 14
Low-Speed (T1 or E1) Receive Data from Port 15
Low-Speed (T1 or E1) Receive Data from Port 16
Low-Speed (T1 or E1) Receive Data from Port 17
Low-Speed (T1 or E1) Receive Data from Port 18
Low-Speed (T1 or E1) Receive Data from Port 19
Low-Speed (T1 or E1) Receive Data from Port 20
Low-Speed (T1 or E1) Receive Data from Port 21
Low-Speed (T1 or E1) Receive Data from Port 22
Low-Speed (T1 or E1) Receive Data from Port 23
Low-Speed (T1 or E1) Receive Data from Port 24
Low-Speed (T1 or E1) Receive Data from Port 25
Low-Speed (T1 or E1) Receive Data from Port 26
Low-Speed (T1 or E1) Receive Data from Port 27
Low-Speed (T1 or E1) Receive Data from Port 28
Low-Speed (T1 or E1) Receive Data from Drop Port A
Low-Speed (T1 or E1) Receive Data from Drop Port B
U9
W10
W11
V12
Y14
W15
W16
Y18
Y19
W20
T17
T19
R19
P20
M17
L19
K19
J18
K3
L3
16 of 133
DS3112
PIN
G19
P1
R2
U1
T4
V3
V4
V5
NAME
LTCCLK
LTCLK1
LTCLK2
LTCLK3
LTCLK4
LTCLK5
LTCLK6
LTCLK7
LTCLK8
LTCLK9
LTCLK10
LTCLK11
LTCLK12
LTCLK13
LTCLK14
LTCLK15
LTCLK16
LTCLK17
LTCLK18
LTCLK19
LTCLK20
LTCLK21
LTCLK22
LTCLK23
LTCLK24
LTCLK25
LTCLK26
LTCLK27
LTCLK28
LTCLKA
LTCLKB
LTDAT1
LTDAT2
LTDAT3
LTDAT4
LTDAT5
LTDAT6
LTDAT7
LTDAT8
LTDAT9
LTDAT10
LTDAT11
LTDAT12
LTDAT13
LTDAT14
LTDAT15
TYPE
FUNCTION
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Speed (T1 or E1) Port Common Transmit Clock Input
Low-Speed (T1 or E1) Transmit Clock for Port 1
Low-Speed (T1 or E1) Transmit Clock for Port 2
Low-Speed (T1 or E1) Transmit Clock for Port 3
Low-Speed (T1 or E1) Transmit Clock for Port 4
Low-Speed (T1 or E1) Transmit Clock for Port 5
Low-Speed (T1 or E1) Transmit Clock for Port 6
Low-Speed (T1 or E1) Transmit Clock for Port 7
Low-Speed (T1 or E1) Transmit Clock for Port 8
Low-Speed (T1 or E1) Transmit Clock for Port 9
Low-Speed (T1 or E1) Transmit Clock for Port 10
Low-Speed (T1 or E1) Transmit Clock for Port 11
Low-Speed (T1 or E1) Transmit Clock for Port 12
Low-Speed (T1 or E1) Transmit Clock for Port 13
Low-Speed (T1 or E1) Transmit Clock for Port 14
Low-Speed (T1 or E1) Transmit Clock for Port 15
Low-Speed (T1 or E1) Transmit Clock for Port 16
Low-Speed (T1 or E1) Transmit Clock for Port 17
Low-Speed (T1 or E1) Transmit Clock for Port 18
Low-Speed (T1 or E1) Transmit Clock for Port 19
Low-Speed (T1 or E1) Transmit Clock for Port 20
Low-Speed (T1 or E1) Transmit Clock for Port 21
Low-Speed (T1 or E1) Transmit Clock for Port 22
Low-Speed (T1 or E1) Transmit Clock for Port 23
Low-Speed (T1 or E1) Transmit Clock for Port 24
Low-Speed (T1 or E1) Transmit Clock for Port 25
Low-Speed (T1 or E1) Transmit Clock for Port 26
Low-Speed (T1 or E1) Transmit Clock for Port 27
Low-Speed (T1 or E1) Transmit Clock for Port 28
Low-Speed (T1 or E1) Transmit Clock for Insert Port A
Low-Speed (T1 or E1) Transmit Clock for Insert Port B
Low-Speed (T1 or E1) Transmit Data for Port 1
Low-Speed (T1 or E1) Transmit Data for Port 2
Low-Speed (T1 or E1) Transmit Data for Port 3
Low-Speed (T1 or E1) Transmit Data for Port 4
Low-Speed (T1 or E1) Transmit Data for Port 5
Low-Speed (T1 or E1) Transmit Data for Port 6
Low-Speed (T1 or E1) Transmit Data for Port 7
Low-Speed (T1 or E1) Transmit Data for Port 8
Low-Speed (T1 or E1) Transmit Data for Port 9
Low-Speed (T1 or E1) Transmit Data for Port 10
Low-Speed (T1 or E1) Transmit Data for Port 11
Low-Speed (T1 or E1) Transmit Data for Port 12
Low-Speed (T1 or E1) Transmit Data for Port 13
Low-Speed (T1 or E1) Transmit Data for Port 14
Low-Speed (T1 or E1) Transmit Data for Port 15
U7
W7
Y8
Y9
Y11
W12
V13
V14
V15
W17
W18
Y20
U18
T18
P17
P19
N20
M20
K20
J19
H18
L2
M3
N3
P3
T2
V1
W1
W4
Y4
V6
V7
W8
W9
Y10
Y12
W13
Y15
17 of 133
DS3112
PIN
U14
V16
V17
W19
U19
U20
R18
P18
N19
M19
L20
J20
NAME
TYPE
FUNCTION
LTDAT16
LTDAT17
LTDAT18
LTDAT19
LTDAT20
LTDAT21
LTDAT22
LTDAT23
LTDAT24
LTDAT25
LTDAT26
LTDAT27
LTDAT28
LTDATA
LTDATB
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Speed (T1 or E1) Transmit Data for Port 16
Low-Speed (T1 or E1) Transmit Data for Port 17
Low-Speed (T1 or E1) Transmit Data for Port 18
Low-Speed (T1 or E1) Transmit Data for Port 19
Low-Speed (T1 or E1) Transmit Data for Port 20
Low-Speed (T1 or E1) Transmit Data for Port 21
Low-Speed (T1 or E1) Transmit Data for Port 22
Low-Speed (T1 or E1) Transmit Data for Port 23
Low-Speed (T1 or E1) Transmit Data for Port 24
Low-Speed (T1 or E1) Transmit Data for Port 25
Low-Speed (T1 or E1) Transmit Data for Port 26
Low-Speed (T1 or E1) Transmit Data for Port 27
Low-Speed (T1 or E1) Transmit Data for Port 28
H19
L1
M2
Low-Speed (T1 or E1) Transmit Data for Insert Port A
Low-Speed (T1 or E1) Transmit Data for Insert Port B
A6, A12, A15–
A20, B1, B7,
B11, B12, B15–
B20, C13, C15–
C20, D12, D14,
D16, D18, D19,
D20, E17–E20,
F18, F19, F20,
G17, G18, T1,
W2, Y1
N.C.
—
No Connection. Do not connect any signal to this pin.
C5
B4
C3
RST
T3E3MS
TEST
I
I
I
Active-Low Reset
T3/E3 Mode Select, 0 = T3, 1 = E3
Active-Low Factory Test Input
D6, D10, D11,
D15, F4, F17,
K4, K17, L4,
L17, R4, R17,
U6, U10, U11,
U15
A1, D4, D8,
D9, D13, D17,
H4, H17, J17,
M4, N4, N17,
U4, U8, U12,
U13, U17
VDD
3.3V (±5%) Positive Supply
Ground Reference
VSS
—
18 of 133
DS3112
2.2 CPU Bus Signal Description
Signal Name:
Signal Description: CPU Bus Mode Select
Signal Type: Input
CMS
This signal should be tied low when the device is to be operated as a 16-bit bus. This signal should be tied
high when the device is to be operated as an 8-bit bus.
0 = CPU Bus is in the 16-Bit Mode
1 = CPU Bus is in the 8-Bit Mode
Signal Name:
Signal Description: CPU Bus Intel/Motorola Bus Select
Signal Type: Input
CIM
The signal determines whether the CPU Bus will operate in the Intel Mode (CIM = 0) or the Motorola
Mode (CIM = 1). The signal names in parentheses are operational when the device is in the Motorola
Mode.
0 = CPU Bus is in the Intel Mode
1 = CPU Bus is in the Motorola Mode
Signal Name:
CD0 to CD15
Signal Description: CPU Bus Data Bus
Signal Type:
Input/Output (Tri-State Capable)
The external host will configure the device and obtain real-time status information about the device via
these signals. When reading data from the CPU Bus, these signals will be outputs. When writing data to
the CPU Bus, these signals will become inputs. When the CPU bus is operated in the 8-bit mode
(CMS = 1), CD8 to CD15 are inactive and should be tied low.
Signal Name:
Signal Description: CPU Bus Address Bus
Signal Type: Input
CA0 to CA7
These input signals determine which internal device configuration register that the external host wishes to
access. When the CPU bus is operated in the 16-bit mode (CMS = 0), CA0 is inactive and should be tied
low. When the CPU bus is operated in the 8-bit mode (CMS = 1), CA0 is the least significant address bit.
Signal Name:
Signal Description: CPU Bus Write Enable (CPU Bus Read/Write Select)
Signal Type: Input
CWR (CR/W)
In Intel Mode (CIM = 0), this signal will determine when data is to be written to the device. In Motorola
Mode (CIM = 1), this signal will be used to determine whether a read or write is to occur.
Signal Name:
Signal Description: CPU Bus Read Enable (CPU Bus Data Strobe)
Signal Type: Input
CRD (CDS)
In Intel Mode (CIM = 0) this signal will determine when data is to be read from the device. In Motorola
Mode (CIM = 1), a rising edge will be used to write data into the device.
19 of 133
DS3112
Signal Name:
Signal Description: CPU Bus Interrupt
Signal Type: Output (Open Drain)
CINT
This signal is an open-drain output that will be forced low if one or more unmasked interrupt sources
within the device is active. The signal will remain low until either the interrupt is serviced or masked.
Signal Name:
Signal Description: CPU Bus Chip Select
Signal Type: Input
CCS
This active low signal must be asserted for the device to accept a read or write command from an external
host.
Signal Name:
Signal Description: CPU Bus Address Latch Enable
Signal Type: Input
CALE
This input signal controls a latch that exists on the CA0 to CA7 inputs. When CALE is high, the latch is
transparent. The falling edge of CALE causes the latch to sample and hold the CA0 to CA7 inputs. In
nonmultiplexed bus applications, CALE should be tied high. In multiplexed bus applications, CA[7:0]
should be tied to CD[7:0] and the falling edge of CALE will latch the address.
20 of 133
DS3112
2.3 T3/E3 Receive Framer Signal Description
Signal Name:
Signal Description: T3/E3 Receive Framer Start Of Frame Sync Signal
Signal Type: Output
FRSOF
This signal pulses for one FRCLK period to indicate the T3 or E3 frame boundary (Figure 2-1). This
signal can be configured via the FRSOFI control bit in Master Control Register 3 (Section 4.2) to be
either active high (normal mode) or active low (inverted mode).
Signal Name:
Signal Description: T3/E3 Receive Framer Clock
Signal Type: Output
FRCLK
This signal outputs the clock that is used to pass data through the receive T3/E3 framer. It can be sourced
from either the HRCLK or FTCLK inputs (Figure 1-1 and Figure 1-2). This signal is used to clock the
receive data out of the device at the FRD output. Data can be either updated on a rising edge (normal
mode) or a falling edge (inverted mode). This option is controlled via the FRCLKI control bit in Master
Control Register 3 (Section 4.3).
Signal Name:
Signal Description: T3/E3 Receive Framer Serial Data
Signal Type: Output
FRD
This signal outputs data from the receive T3/E3 framer. This signal is updated either on the rising edge of
FRCLK (normal mode) or the falling edge of FRCLK (inverted mode). This option is controlled via the
FRCLKI control bit in Master Control Register 3 (Section 4.3). Also, this signal can be internally inverted
if enabled via the FRDI control bit in Master Control Register 3 (Section 4.3).
Signal Name:
Signal Description: T3/E3 Receive Framer Serial Data Enable or Gapped Clock Output
Signal Type: Output
FRDEN
Via the DENMS control bit in Master Control Register 1, this signal can be configured to either output a
data enable or a gapped clock. In the data enable mode, this signal will go active when payload data is
available at the FRD output and it will go inactive when overhead data is being output at the FRD output.
In the gapped clock mode, this signal will transition for each bit of payload data and will be suppressed
for each bit of overhead data. In the T3 Mode, overhead data is defined as the M Bits, F Bits, C Bits, X
Bits, and P Bits. In the E3 Mode, overhead data is defined as the FAS word, RAI Bit and Sn Bit (i.e., bits
1 to 12). See Figure 2-1 for an example. This signal can be internally inverted if enabled via the FRDENI
control bit in Master Control Register 3 (Section 4.3).
Signal Name:
Signal Description: T3/E3 Receive Framer Manual Error Counter Update Strobe
Signal Type: Input
FRMECU
Via the AECU control bit in Master Control Register 1 (Section 4.3), the DS3112 can be configured to
use this asynchronous input to initiate an updating of the internal error counters. A zero to one transition
on this input causes the device to begin loading the internal error counters with the latest error counts.
This signal must be returned low before a subsequent updating of the error counters can occur. The host
must wait at least 100ns before reading the error counters to allow the device time to update the error
counters. This signal is logically ORed with the MECU control bit in Master Control Register 1. If this
signal is not used, then it should be tied low.
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Signal Name:
Signal Description: T3/E3 Receive Framer Loss Of Signal
Signal Type: Output
FRLOS
This signal will be forced high when the receive T3/E3 framer is in a Loss Of Signal (LOS) state. It will
remain high as long as the LOS state persists and will return low when the framer exits the LOS state. See
Section 5.3 for details on the set and clear criteria for this signal. LOS status is also available via a
software bit in the T3/E3 Status Register (Section 5.3).
Signal Name:
Signal Description: T3/E3 Receive Framer Loss Of Frame
Signal Type: Output
FRLOF
This signal will be forced high when the receive T3/E3 framer is in a Loss Of Frame (LOF) state. It will
remain high as long as the LOF state persists and will return low when the framer synchronizes. See
Section 5.3 for details on the set and clear criteria for this signal. LOF status is also available via a
software bit in the T3/E3 Status Register (Section 5.3).
Figure 2-1. T3/E3 Receive Framer Timing
FRCLK
Normal Mode
FRCLK
Inverted Mode
Last Bit of
the Frame
T3: X1
E3: Bit 1 of FAS
FRD
(see note)
FRDEN
Data Enable Mode for T3
(see note)
FRDEN
Data Enable Mode for E3
(see note)
FRDEN
Gapped Clock Mode for T3
(see note)
FRDEN
Gapped Clock Mode for E3
(see note)
FRSOF
(see note)
NOTE: FRD, FRDEN, AND FRSOF CAN BE INVERTED VIA MASTER CONTROL REGISTER 3.
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2.4 T3/E3 Transmit Formatter Signal Description
Signal Name:
Signal Description: T3/E3 Transmit Formatter Start Of Frame Sync Signal
Signal Type: Output/Input
FTSOF
This signal can be configured via the FTSOFC control bit in Master Control Register 1 to be either an
output or an input. When this signal is an output, it pulses for one FTCLK period to indicate a T3 or E3
frame boundary (Figure 2-2). When this signal is an input, it is sampled to set the transmit T3 or E3 frame
boundary (Figure 2-2). This signal can be configured via the FTSOFI control bit in Master Control
Register 3 (Section 4.2) to be either active high (normal mode) or active low (inverted mode).
Signal Name:
Signal Description: T3/E3 Transmit Formatter Clock
Signal Type: Input
FTCLK
An accurate T3 (44.736MHz ±20ppm) or E3 (34.368MHz ±20ppm) clock should be applied at this signal.
This signal is used to clock data into the transmit T3/E3 formatter. Transmit data can be clocked into the
device either on a rising edge (normal mode) or a falling edge (inverted mode). This option is controlled
via the FTCLKI control bit in Master Control Register 3 (Section 4.2).
Signal Name:
Signal Description: T3/E3 Transmit Formatter Serial Data
Signal Type: Input
FTD
This signal inputs data into the transmit T3/E3 formatter. This signal can be sampled either on the rising
edge of FTCLK (normal mode) or the falling edge of FTCLK (inverted mode). This option is controlled
via the FTCLKI control bit in Master Control Register 3 (Section 4.2). Also, the data input to this signal
can be internally inverted if enabled via the FTDI control bit in Master Control Register 3 (Section 4.2).
When T3 C-Bit Parity Mode is disabled, C Bits are sampled at this input. This signal is ignored when the
M13/E13 multiplexer is enabled. (See the UNCHEN control bit in Master Control Register 1.) If not
used, this signal should be tied low.
Signal Name:
Signal Description: T3/E3 Transmit Formatter Serial Data Enable or Gapped Clock Output
Signal Type: Output
FTDEN
Via the DENMS control bit in Master Control Register 1, this signal can be configured to either output a
data enable or a gapped clock. In the data enable mode, this signal will go active when payload data
should be made available at the FTD input. In the gapped clock mode, this signal will act as a demand
clock for the FTD input and it will transition for each bit of payload data needed at the FTD input and it
will be suppressed when the transmit formatter inserts overhead data and hence no data is needed at the
FTD input. In the T3 Mode, overhead data is defined as the M Bits, F Bits, C Bits, X Bits, and P Bits. In
the E3 Mode, overhead data is defined as the FAS word, RAI Bit and Sn Bit (i.e., bits 1 to 12). See
Figure 2-2 for an example. This signal can be internally inverted if enabled via the FTDENI control bit in
Master Control Register 3 (Section 4.2). This signal operates in the same manner even when the device is
configured in the Transmit Pass Through mode (see the TPT control bit in the T3/E3 Control Register).
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Signal Name:
Signal Description: T3/E3 Transmit Formatter Manual Error Insert Strobe
Signal Type: Input
FTMEI
Via the EIC control bit in the T3/E3 Error Insert Control Register (Section 5.2), the DS3112 can be
configured to use this asynchronous input to cause errors to be inserted into the transmitted data stream.
A zero to one transition on this input causes the device to begin the process of causing errors to be
inserted. This signal must be returned low before any subsequent errors can be generated. If this signal is
not used, then it should be tied low.
Figure 2-2. T3/E3 Transmit Formatter Timing
FTCLK
Normal Mode
FTCLK
Inverted Mode
Last Bit of
the Frame
T3: X1
E3: Bit 1 of FAS
FTD
(see note)
FTDEN
Data Enable Mode for T3
(see note)
FTDEN
Data Enable Mode for
(see note)
FTDEN
Gapped Clock Mode for T3
(see note)
FTDEN
Gapped Clock Mode for E3
(see note)
FTSOF
Output Mode
(see note)
FTSOF
Input Mode
(see note)
NOTE: FTD, FTDEN, AND FTSOF CAN BE INVERTED VIA MASTER CONTROL REGISTER 3.
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2.5 Low-Speed (T1 or E1) Receive Port Signal Description
Signal Name:
Signal Description: Low-Speed (T1 or E1) Receive Serial Data Outputs
Signal Type: Output
LRDAT1 to LRDAT28
These output signals present the demultiplexed serial data for the 28 T1 data streams or the 16/21 E1 data
streams. Data can be clocked out of the device either on rising edges (normal clock mode) or falling
edges (inverted clock mode) of the associated LRCLK. This option is controlled via the LRCLKI control
bit in Master Control Register 2 (Section 4.2). Also, the data can be internally inverted before being
output if enabled via the LRDATI control bit in Master Control Register 2 (Section 4.2). When the device
is in the E3 Mode, LRDAT17 to LRDAT28 are meaningless and should be ignored. When the device is
in the G.747 Mode, LRDAT4, LRDAT8, LRDAT12, LRDAT16, LRDAT20, LRDAT24, and LRDAT28
are meaningless and should be ignored. When the M13/E13 multiplexer is disabled, then these outputs are
meaningless and should be ignored.
Signal Name:
Signal Description: Low-Speed (T1 or E1) Receive Serial Clock Outputs
Signal Type: Output
LRCLK1 to LRCLK28
These output signals present the demultiplexed serial clocks for the 28 T1 data streams or the 16/21 E1
data streams. The T1 or E1 serial data streams at the associated LRDAT signals can be clocked out of the
device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of LRCLK.
This option is controlled via the LRCLKI control bit in Master Control Register 2 (Section 4.2). When the
device is in the E3 Mode, LRCLK17 to LRCLK28 are meaningless and should be ignored. When the
device is in the G.747 Mode, LRCLK4, LRCLK8, LRCLK12, LRCLK16, LRCLK20, LRCLK24, and
LRCLK28 are meaningless and should be ignored. When the M13/E13 multiplexer is disabled, then these
outputs are meaningless and should be ignored.
Signal Name:
Signal Description: Low-Speed (T1 or E1) Receive Drop Port Serial Data Outputs
Signal Type: Output
LRDATA/LRDATB
These two output signals present the demultiplexed serial data from one of the 28 T1 data streams or from
one of the 16/21 E1 data streams (Section 7.4). Data can be clocked out of the device either on rising
edges (normal clock mode) or falling edges (inverted clock mode) of the associated LRCLK. This option
is controlled via the LRCLKI control bit in Master Control Register 2 (Section 4.2). Also, the data can be
internally inverted before being output if enabled via the LRDATI control bit in Master Control Register
2 (Section 4.2). When the M13/E13 multiplexer is disabled, then these outputs are meaningless and
should be ignored.
Signal Name:
Signal Description: Low-Speed (T1 or E1) Receive Drop Port Serial Clock Outputs
Signal Type: Output
LRCLKA/LRCLKB
These output signals present the demultiplexed serial clocks from one of the 28 T1 data streams or from
one of the 16/21 E1 data streams (Section 7.4). The T1 or E1 serial data streams at the associated LRDAT
signals can be clocked out of the device either on rising edges (normal clock mode) or falling edges
(inverted clock mode) of LRCLK. This option is controlled via the LRCLKI control bit in Master Control
Register 2 (Section 4.2). When the M13/E13 multiplexer is disabled, then these outputs are meaningless
and should be ignored.
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Signal Name:
Signal Description: Low-Speed (T1 or E1) Receive Common Clock Input
Signal Type: Input
LRCCLK
If enabled via the LRCCEN control bit in Master Control Register 1 (Section 4.2), all 28 LRCLK or
16/21 LRCLK can be slaved to this common clock input. In T3 mode, LRCCLK would be a 1.544MHz
clock and in E3 mode, LRCCLK would be 2.048MHz. Use of this configuration is only possible in
applications where it can be guaranteed that all of the multiplexed T1 or E1 signals at the far end are
based on a common clock. If this signal is not used, then it should be tied low. This signal can be
internally inverted. This option is controlled via the LRCLKI control bit in Master Control Register 2
(Section 4.2).
2.6 Low-Speed (T1 or E1) Transmit Port Signal Description
Signal Name:
Signal Description: Low-Speed (T1 or E1) Transmit Serial Data Inputs
Signal Type: Input
LTDAT1 to LTDAT28
These input signals sample the serial data from the 28 T1 data streams or the 16/21 E1 data streams that
will be multiplexed into a single T3 or E3 data stream. Data can be clocked into the device either on
falling edges (normal clock mode) or rising edges (inverted clock mode) of the associated LTCLK. This
option is controlled via the LTCLKI control bit in Master Control Register 2 (Section 4.2). Also, the data
can be internally inverted before being multiplexed if enabled via the LTDATI control bit in Master
Control Register 2 (Section 4.2). When the device is in the E3 Mode, LTDAT17 to LTDAT28 are
ignored and should be tied low. When the device is in the G.747 Mode, LTDAT4, LTDAT8, LTDAT12,
LTDAT16, LTDAT20, LTDAT24, and LTDAT28 are ignored and should be tied low. When the
M13/E13 multiplexer is disabled, then these inputs are ignored and should be tied low.
Signal Name:
Signal Description: Low-Speed (T1 or E1) Transmit Serial Clock Inputs
Signal Type: Input
LTCLK1 to LTCLK28
These input signals clock data in from the 28 T1 data streams or from the 16/21 E1 data streams. The T1
or E1 serial data streams at the associated LTDAT signals can be clocked into the device either on falling
edges (normal clock mode) or rising edges (inverted clock mode) of LTCLK. This option is controlled via
the LTCLKI control bit in Master Control Register 2 (Section 4.2). When the device is in the E3 Mode,
LTCLK17 to LTCLK28 are meaningless and should be tied low. When the device is in the G.747 Mode,
LTCLK4, LTCLK8, LTCLK12, LTCLK16, LTCLK20, LTCLK24, and LTCLK28 are meaningless and
should be tied low. When the M13/E13 multiplexer is disabled, then these inputs are ignored and should
be tied low.
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Signal Name:
Signal Description: Low-Speed (T1 or E1) Transmit Insert Port Serial Data Inputs
Signal Type: Input
LTDATA/LTDATB
These two input signals allow data to be inserted in place of any of the 28 T1 data streams or into any of
the 16/21 E1 data streams (Section 7.4). Data can be clocked into the device either on falling edges
(normal clock mode) or rising edges (inverted clock mode) of the associated LTCLK. This option is
controlled via the LTCLKI control bit in Master Control Register 2 (Section 4.2). Also, the data can be
internally inverted before being multiplexed if enabled via the LTDATI control bit in Master Control
Register 2 (Section 4.2). When the M13/E13 multiplexer is disabled, then these inputs are ignored and
should be tied low.
Signal Name:
Signal Description: Low-Speed (T1 or E1) Transmit Insert Port Serial Clock Inputs
Signal Type: Input
LTCLKA/LTCLKB
These two input signals are used to clock data into the device that will be inserted into one of the 28 T1
data streams or into one of the 16/21 E1 data streams (Section 7.4). The T1 or E1 serial data streams at
the associated LTDAT signals can be clocked into the device either on falling edges (normal clock mode)
or rising edges (inverted clock mode) of LTCLKA/LTCLKB. This option is controlled via the LTCLKI
control bit in Master Control Register 2 (Section 4.2). When the M13/E13 multiplexer is disabled, then
these inputs are ignored and should be tied low.
Signal Name:
Signal Description: Low-Speed (T1 or E1) Transmit Common Clock Input
Signal Type: Input
LTCCLK
If enabled via the LTCCEN in Master Control Register 1 (Section 4.2), all 28 LTCLK or 16 LTCLK
signals are disabled and all the data at the 28 LTDAT or 16 LTDAT inputs (as well as the LTDATA and
LTDATB inputs) will be clocked into the device using the LTCCLK signal. In T3 mode, LTCCLK would
be a 1.544MHz clock and in E3 mode, LTCCLK would be 2.048MHz. If not used, this signal should be
tied low. If this signal is used, then all of the LTCLK signals should be tied low. This signal can be
internally inverted. This option is controlled via the LTCLKI control bit in Master Control Register 2
(Section 4.2).
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2.7 High-Speed (T3 or E3) Receive Port Signal Description
Signal Name:
Signal Description: High-Speed (T3 or E3) Receive Serial Data Inputs
Signal Type: Input
HRPOS/HRNEG
These input signals sample the serial data from the incoming T3 data streams or E3 data streams. Data
can be clocked into the device either on rising edges (normal clock mode) or falling edges (inverted clock
mode) of the associated HRCLK. This option is controlled via the HRCLKI control bit in Master Control
Register 2 (Section 4.2).
Signal Name:
Signal Description: High-Speed (T3 or E3) Receive Serial Clock Input
Signal Type: Input
HRCLK
This signal is used to clock data in from the incoming T3 or E3 data streams. The T3 or E3 serial data
streams at the HRPOS and HRNEG signals can be clocked into the device either on rising edges (normal
clock mode) or falling edges (inverted clock mode) of HRCLK. This option is controlled via the HRCLKI
control bit in Master Control Register 2 (Section 4.2).
Note: The HRCLK must be present for the host to be able to obtain status information (except the LOTC
and LORC status bits, see Section 4.3) from the device.
2.8 High-Speed (T3 or E3) Transmit Port Signal Description
Signal Name:
Signal Description: High-Speed (T3 or E3) Transmit Serial Data Outputs
Signal Type: Output
HTPOS/HTNEG
These output signals present the outgoing T3 data streams or E3 data streams. Data can be clocked out of
the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of HTCLK.
This option is controlled via the HTCLKI control bit in Master Control Register 2 (Section 4.2). Also,
these outputs can be forced high or low via the HTDATH and HTDATL control bits respectively in
Master Control Register 2 (Section 4.2).
Signal Name:
Signal Description: High-Speed (T3 or E3) Transmit Serial Clock Output
Signal Type: Output
HTCLK
This output signal is used to clock T3 or E3 data out of the device. The T3 or E3 serial data streams at the
HTPOS and HTNEG signals can be clocked out of the device either on rising edges (normal clock mode)
or falling edges (inverted clock mode) of HTCLK. This option is controlled via the HTCLKI control bit
in Master Control Register 2 (Section 4.2).
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2.9 JTAG Signal Description
Signal Name:
Signal Description: JTAG IEEE 1149.1 Test Serial Clock
Signal Type: Input
JTCLK
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not
used, this signal should be pulled high.
Signal Name:
Signal Description: JTAG IEEE 1149.1 Test Serial Data Input
Signal Type: Input (with internal 10kΩ pullup)
JTDI
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this signal
should be pulled high. This signal has an internal pullup.
Signal Name:
Signal Description: JTAG IEEE 1149.1 Test Serial Data Output
Signal Type: Output
JTDO
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this signal
should be left open circuited.
Signal Name:
Signal Description: JTAG IEEE 1149.1 Test Reset
Signal Type: Input (with internal 10kΩ pullup)
JTRST
This signal is used to asynchronously reset the test access port controller. At power-up, JTRST must be
set low and then high. This action will set the device into the boundary scan bypass mode allowing
normal device operation. If boundary scan is not used, this signal should be held low. This signal has an
internal pullup.
Signal Name:
Signal Description: JTAG IEEE 1149.1 Test Mode Select
Signal Type: Input (with internal 10kΩ pullup)
JTMS
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various
defined IEEE 1149.1 states. If not used, this signal should be pulled high. This signal has an internal
pullup.
2.10 Supply, Test, Reset, and Mode Signal Description
Signal Name:
RST*
Signal Description: Global Hardware Reset
Signal Type:
Input (with internal 10kΩ pullup)
This active low asynchronous signal causes the device to be reset. When this signal is forced low, it
causes all of the internal registers to be forced to 00h and the high-speed T3/E3 ports as well as the low-
speed T1/E1 ports to source an unframed all ones data pattern. The device will be held in a reset state as
long as this signal is low. This signal should be activated after the hardware configuration signals (LIEN
and T3E3MS) and the clocks (FTCLK, LTCLK, HRCLK, and LITCLK) are stable and must be returned
high before the device can be configured for operation.
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Signal Name:
Signal Description: T3/E3 Mode Select Input
Signal Type: Input
T3E3MS
This signal determines whether the DS3112 will operate in either the T3 mode or the E3 mode. It acts as a
global control bit for the entire DS3112. This signal should be set into the proper state before a hardware
reset is issued via the RST signal. This input is coupled with the G.747E input to create a special test
mode whereby all the outputs are tri-stated (Table 2-3).
0 = T3 Mode
1 = E3 Mode
Signal Name:
Signal Description: G.747 Mode Enable Input
Signal Type: Input
G.747E
This signal determines whether the DS3112 will operate in either the T3 mode or the G.747 mode. It acts
as a global control bit for the entire DS3112. This signal should be set into the proper state before a
hardware reset is issued via the RST signal. This input is coupled with the T3E3MS input to create a
special test mode whereby all the outputs are tri-stated (Table 2-3).
0 = T3 Mode
1 = G.747 Mode
Table 2-3. Mode Select Decode
T3E3MS
G.747E
MODE SELECTED
0
0
1
0
1
0
T3 or M13 Operation
G.747 Operation
E3 or E13 Operation
Special Test Mode that tri-states all outputs. JTRST must be driven
low for tri-state operation without power-up. Refer to note for
JTRST signal.
1
1
Signal Name:
TEST
Signal Description: Factory Test Input
Signal Type:
Input (with internal 10kΩ pullup)
This input should be left open circuited by the user.
Signal Name:
Signal Description: Digital Ground Reference
Signal Type: N/A
All VSS signals should be tied together.
VSS
Signal Name:
Signal Description: Digital Positive Supply
Signal Type: N/A
3.3V (±5%). All VDD signals should be tied together.
VDD
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3 MEMORY MAP
Table 3-1. Memory Map
ADDRESS ACRONYM R/W
REGISTER NAME
SECTION
00
02
04
06
08
0A
0C
10
12
14
16
18
20
22
24
26
28
2A
30
32
34
36
40
42
44
46
50
52
54
56
58
5A
5C
5E
60
62
6E
70
72
74
76
78
7A
7C
7E
80
MRID
MC1
MC2
MC3
MSR
R/W Master Reset and ID Register
4.1
4.2
4.2
4.2
4.3
4.3
4.4
5.2
5.3
5.3
5.3
5.3
5.4
5.4
5.4
5.4
5.4
5.4
6.2
6.2
6.4
6.4
6.4
6.4
6.4
6.4
7.1
7.1
7.2
7.2
7.3
7.3
7.6
7.6
7.4
7.4
8.1
8.1
8.1
8.1
8.1
8.1
8.1
8.1
8.1
9.1
R/W Master Configuration Register 1
R/W Master Configuration Register 2
R/W Master Configuration Register 3
R
Master Status Register
IMSR
TEST
R/W Interrupt Mask Register for MSR
R/W Test Register
R/W T3/E3 Control Register
T3E3CR
T3E3SR
IT3E3SR
T3E3INFO
T3E3EIC
BPVCR
EXZCR
FECR
PCR
CPCR
R
T3/E3 Status Register
R/W Interrupt Mask for T3E3SR
T3/E3 Information Register
R/W T3/E3 Error Insert Control Register
R
R
R
R
R
R
R
T3/E3 Bipolar Violation (BPV) Count Register
T3/E3 Excessive Zero (EXZ) Count Register
T3/E3 Frame Error Count Register
T3 Parity Bit Error Count Register
T3 C-Bit Parity Error Count Register
FEBECR
T2E2CR1
T2E2CR2
T2E2SR1
T2E2SR2
T1E1RAIS1
T1E1RAIS2
T1E1TAIS1
T1E1TAIS2
T1E1LLB1
T1E1LLB2
T1E1DLB1
T1E1DLB2
T1LBCR1
T1LBCR2
T1LBSR1
T1LBSR2
T1E1SDP
T1E1SIP
BERTMC
BERTC0
BERTC1
BERTRP0
BERTRP1
BERTBC0
BERTBC1
BERTEC0
BERTEC1
HCR
T3 Far End Block Error or E3 RAI Count Register
R/W T2/E2 Control Register 1
R/W T2/E2 Control Register 2
R/W T2/E2 Status Register 1
R/W T2/E2 Status Register 2
R/W T1/E1 Receive Path AIS Generation Control Register 1
R/W T1/E1 Receive Path AIS Generation Control Register 2
R/W T1/E1 Transmit Path AIS Generation Control Register 1
R/W T1/E1 Transmit Path AIS Generation Control Register 2
R/W T1/E1 Line Loopback Control Register 1
R/W T1/E1 Line Loopback Control Register 2
R/W T1/E1 Diagnostic Loopback Control Register 1
R/W T1/E1 Diagnostic Loopback Control Register 2
R/W T1 Line Loopback Command Register 1
R/W T1 Line Loopback Command Register 2
R
R
T1 Line Loopback Status Register 1
T1 Line Loopback Status Register 2
R/W T1/E1 Select Register for Receive Drop Ports A and B
R/W T1/E1 Select Register for Transmit Drop Ports A and B
R/W BERT Mux Control Register
R/W BERT Control 0
R/W BERT Control 1
R/W BERT Repetitive Pattern Set 0 (lower word)
R/W BERT Repetitive Pattern Set 1 (upper word)
R
R
R
R
BERT Bit Counter 0 (lower word)
BERT Bit Counter 1 (upper word)
BERT Error Counter 0 (lower word)
BERT Error Counter 1 (upper word)
R/W HDLC Control Register
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SECTION
ADDRESS ACRONYM R/W
REGISTER NAME
Receive HDLC FIFO Register
Transmit HDLC FIFO Register
HDLC Status Register
82
84
RHDLC
THDLC
HSR
R
W
R
9.2
9.2
9.3
86
88
90
92
IHSR
FCR
FSR
R/W Interrupt Mask Register for HSR
R/W FEAC Control Register
9.3
10.1
10.2
R
FEAC Status Register
38, 48, 64,
66, 68, 94,
96, 98, 0E,
1A, 1C, 1E,
2C, 2E, 3A,
3C, 3E, 4A,
4C, 4E, 6A,
6C, 8A, 8C,
8E, 9A, 9C,
9E
—
—
Not Assigned
*
*Addresses A0 to FF are not assigned.
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4 MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT
4.1 Master Reset and ID Register Description
The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set
to one, all of the internal registers will be placed into their default state, which is 0000h. A reset can also
be invoked by the RST hardware signal.
The upper byte of the MRID register is read-only and it can be read by the host to determine the chip
revision. Contact the factory for specifics on the meaning of the value read from the ID0 to ID7 bits.
Register Name:
MRID
Register Description:
Register Address:
Master Reset and ID Register
00h
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
T3E3RSY
0
2
T2E2RSY
0
1
RFIFOR
0
0
RST
0
Bit #
Name
Default
15
ID7
X
14
ID6
X
13
ID5
X
12
ID4
X
11
ID3
X
10
ID2
X
9
ID1
X
8
ID0
X
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Master Software Reset (RST). When this bit is set to a one by the host, it will force all of the internal
registers to their default state, which is 0000h and forces the T3/E3 and T1/E1 outputs to send an all ones pattern.
This bit must be set high for a minimum of 100ns. This software bit is logically ORed with the hardware signal
RST.
0 = normal operation
1 = force all internal registers to their default value of 0000h
Bit 1: Low-Speed (T1/E1) Receive FIFO Reset (RFIFOR). A zero to one transition on this bit will cause the
receive T1/E1 demux FIFOs to be reset, which will cause them to be flushed. See the DS3112 Block Diagrams in
Figure 1-1 and Figure 1-2 for details on the placement of the FIFOs within the chip. This bit must be cleared and
set again for a subsequent reset to occur.
Bit 2: T2/E2/G.747 Force Receive Framer Resynchronization (T2E2RSY). A zero to one transition on this bit
will cause all seven of the T2 receive framers or all four of the E2 receive framers or all seven of the G.747 framers
to resynchronize. This bit must be cleared and set again for a subsequent resynchronization to occur.
Bit 3: T3/E3 Force Receive Framer Resynchronization (T3E3RSY). A zero to one transition on this bit will
cause the T3 receive framer or the E3 receive framer to resynchronize. This bit must be cleared and set again for a
subsequent resynchronization to occur.
Bits 8 to 15: Chip Revision ID Bit 0 to 7 (ID0 to ID7). Read-only. Contact the factory for details on the meaning
of the ID bits.
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DS3112
4.2 Master Configuration Registers Description
Register Name:
MC1
Register Description:
Register Address:
Master Configuration Register 1
02h
Bit #
Name
Default
7
FTSOFC
0
6
LOTCMC
0
5
UNI
0
4
MECU
0
3
AECU
0
2
CBEN
0
1
UNCHEN
0
0
ZCSD
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
LLTM
0
10
DENMS
0
9
LRCCEN
0
8
LTCCEN
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Zero Code Suppression Disable (ZCSD).
0 = enable the B3ZS and HDB3 encoders/decoders
1 = disable the B3ZS and HDB3 encoders/decoders
Bit 1: T3/E3 Unchannelized Mode Enable (UNCHEN). When this bit is set low, the M13/E13/G.747 multiplexer
is enabled and data at the FTD input is ignored. When this bit is set high, the M13/E13/G.747 multiplexer is
disabled and the LTDAT inputs are ignored. The table below displays which bits are not sampled at the FTD input
when UNCHEN = 1.
0 = enable the M13/E13/G.747 multiplexers and disable the FTD Input
1 = disable the M13/E13/G.747 multiplexers and enable the FTD Input
BITS POSITIONS NOT
DS3112 MODE
SAMPLED AT FTD
T3 M23 (C-Bit Parity
F/P/M/C/X
Disabled)
T3 C-Bit Parity
E3
F/P/M/X
FAS/Sn/RAI
Bit 2: T3 C-Bit Parity Mode Enable (CBEN). This bit is only active when the device is T3 mode. When this bit
is set low, C-Bit Parity is defeated and the C Bits are sourced from the M23 Multiplexer Block (Figure 1-1). This
bit should not be set low in the T3 unchannelized mode (UNCHEN = 1). When this bit is set high, C-Bit Parity
mode is enabled and the C bits are sourced from the T3 framer block (Figure 1-1 and Figure 1-3).
0 = disable C-Bit Parity mode (also known as the M23 Mode)
1 = enable C-Bit Parity mode
Bit 3: Automatic One-Second Error Counters Update Defeat (AECU). When this bit is set low, the device will
automatically update the T3/E3 performance error counters on an internally created one-second boundary. The host
will be notified of the update via the setting of the OST status bit in the Master Status Register. In this mode, the
host has a full one second period to retrieve the error information before if will be overwritten with the next update.
When this bit is set high, the device will defeat the automatic one-second update and enable a manual update mode.
In the manual update mode, the device relies on either the Framer Manual Error Counter Update (FRMECU)
hardware input signal or the MECU control bit to update the error counters. The FRMECU hardware input signal
and MECU control bit are logically ORed and hence a zero to one transition on either will initiate an error counter
update to occur. After either the FRMECU signal or MECU bit has toggled, the host must wait at least 100ns
before reading the error counters to allow the device time to complete the update.
0 = enable the automatic update mode and disable the manual update mode
1 = disable the automatic update mode and enable the manual update mode
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Bit 4: Manual Error Counter Update (MECU). A zero to one transition on this bit will cause the device to
update the performance error counters. This bit is ignored if the AECU control bit is set low. This bit must be
cleared and set again for a subsequent update. This bit is logically ORed with the external FRMECU hardware
input signal. After this bit has toggled, the host must wait at least 100ns before reading the error counters to allow
the device time to complete the update.
Bit 5: High-Speed (T3/E3) Port Unipolar Enable (UNI). When this bit is set low, the device will output a bipolar
coded signal at HTPOS and HTNEG and expect a bipolar coded signal at HRPOS and HRNEG. When this bit is
set high, the device will output a NRZ coded signal at HTPOS and expect a NRZ coded signal at HRPOS. In the
unipolar mode, the device will force the HTNEG output low and the HRNEG input is ignored and should be tied
low. In the unipolar mode, the B3ZS and HDB3 coder/decoders should be disabled by setting the ZCSD bit to one
(ZCSD = 1).
0 = bipolar mode
1 = unipolar mode
Bit 6: Loss Of Transmit Clock Mux Control (LOTCMC). The DS3112 can detect if the FTCLK fails to
transition. If this bit is set low, the device will take no action (other than setting the LOTC status bit) when the
FTCLK fails to transition. When this bit is set high, the device will automatically switch to the input receive clock
(HRCLK) when the FTCLK fails and transmit AIS.
0 = do not switch to the HRCLK signal if FTCLK fails to transition
1 = automatically switch to the HRCLK signal if the FTCLK fails to transition and send AIS
Bit 7: T3/E3 Transmit Frame Sync I/O Control (FTSOFC). When this bit is set low, the FTSOF signal will be
an output and will pulse for one FTCLK cycle at the beginning of each frame. When this bit is high, the FTSOF
signal is an input and the device uses it to determine the frame boundaries.
0 = FTSOF is an output
1 = FTSOF is an input
Bit 8: Low-Speed (T1/E1) Transmit Port Common Clock Enable (LTCCEN). When this bit is set high, the
LTCLK1 to LTCLK28 and LTCLKA and LTCLKB inputs are ignored and a common clock sourced via the
LTCCLK input is used in their place.
0 = disable LTCCLK
1 = enable LTCCLK
Bit 9: Low-Speed (T1/E1) Receive Port Common Clock Enable (LRCCEN). When this bit is set high, the
LRCLK1 to LRCLK28 and LRCLKA and LRCLKB outputs will all be sourced from the LRCCLK input. This
configuration can only be used in applications where it can be insured that all of the T1 or E1 channels from the far
end are being sourced from a common clock.
0 = disable LRCCLK
1 = enable LRCCLK
Bit 10: High-Speed (T3/E3) Data Enable Mode Select (DENMS). When this bit is set low, the FRDEN and
FTDEN outputs will be asserted during payload data and deasserted during overhead data. When this bit is high,
FRDEN and FTDEN are gapped clocks that pulse during payload data and are suppressed during overhead data.
0 = FRDEN and FTDEN are data enables
1 = FRDEN and FTDEN are gapped clocks
Bit 11: Low-Speed (T1/E1) Port Loop Timed Mode (LLTM). When this bit is set low, the low-speed T1 and E1
receive clocks (LRCLK) are not routed to the transmit side. When this bit is high, the LRCLKs are routed to the
transmit side to be used as the transmit T1 and E1 clocks. When enabled, all the low-speed ports are looped timed.
This control bit affects all the low-speed ports. The device is not capable of setting individual low-speed ports into
and out of looped timed mode. See the block diagram in Figure 1-1 and Figure 1-2 for more details.
0 = disable loop timed mode (LRCLK is not used to replace the associated LTCLK)
1 = enable loop timed mode (LRCLK replaces the associated LTCLK)
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Register Name:
MC2
Register Description:
Register Address:
Master Configuration Register 2
04h
Bit #
Name
Default
7
—
—
6
—
—
5
HTDATL
0
4
HTDATH
0
3
2
1
0
HTCLKI
HRDATI HRCLKI HTDATI
0
0
0
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
LRDATI
0
10
LRCLKI
0
9
LTDATI
0
8
LTCLKI
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: HTCLK Invert Enable (HTCLKI).
0 = do not invert the HTCLK signal (normal mode)
1 = invert the HTCLK signal (inverted mode)
Bit 1: HTPOS/HTNEG Invert Enable (HTDATI).
0 = do not invert the HTPOS and HTNEG signals (normal mode)
1 = invert the HTPOS and HTNEG signals (inverted mode)
Bit 2: HRCLK Invert Enable (HRCLKI).
0 = do not invert the HRCLK signal (normal mode)
1 = invert the HRCLK signal (inverted mode)
Bit 3: HRPOS/HRNEG Invert Enable (HTDATI).
0 = do not invert the HRPOS and HRNEG signals (normal mode)
1 = invert the HRPOS and HRNEG signals (inverted mode)
Bit 4: HTPOS/HTNEG Force High Disable (HTDATH). Note that this bit must be set by the host in order for
T3/E3 traffic to be output from the device.
0 = force the HTPOS and HTNEG signals high (force high mode)
1 = allow normal transmit data to appear at the HTPOS and HTNEG signals (normal mode)
Bit 5: HTPOS/HTNEG Force Low Enable (HTDATL).
0 = allow normal transmit data to appear at the HTPOS and HTNEG signals (normal mode)
1 = force the HTPOS and HTNEG signals low (force low mode)
Bit 8: LTCLK Invert Enable (LTCLKI).
0 = do not invert the LTCLK[n], LTCLKA, LTCLKB, and LTCCLK signals (normal mode)
1 = invert the LTCLK[n], LTCLKA, LTCLKB, and LTCCLK signals (inverted mode)
Bit 9: LTDAT Invert Enable (LTDATI).
0 = do not invert the LTDAT[n], LTDATA and LTDATB signals (normal mode)
1 = invert the LTDAT[n], LTDATA and LTDATB signals (inverted mode)
Bit 10: LRCLK Invert Enable (LRCLKI).
0 = do not invert the LRCLK[n], LRCLKA, LRCLKB, and LRCCLK signals (normal mode)
1 = invert the LRCLK[n], LRCLKA, LRCLKB, and LRCCLK signals (inverted mode)
Bit 11: LRDAT Invert Enable (LRDATI).
0 = do not invert the LRDAT[n], LRDATA and LRDATB signals (normal mode)
1 = invert the LRDAT[n], LRDATA and LRDATB signals (inverted mode)
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DS3112
Register Name:
MC3
Register Description:
Register Address:
Master Configuration Register 3
06h
Bit #
Name
Default
7
FRSOFI
0
6
FRCLKI
0
5
FRDI
0
4
FRDENI
0
3
FTSOFI
0
2
FTCLKI
0
1
FTDI
0
0
FTDENI
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
—
—
10
—
—
9
—
—
8
—
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: FTDEN Invert Enable (FTDENI).
0 = do not invert the FTDEN signal (normal mode)
1 = invert the FTDEN signal (inverted mode)
Bit 1: FTD Invert Enable (FTDI).
0 = do not invert the FTD signal (normal mode)
1 = invert the FTD signal (inverted mode)
Bit 2: FTCLK Invert Enable (FTCLKI).
0 = do not invert the FTCLK signal (normal mode)
1 = invert the FTCLK signal (inverted mode)
Bit 3: FTSOF Invert Enable (FTSOFI).
0 = do not invert the FTSOF signal (normal mode)
1 = invert the FTSOF signal (inverted mode)
Bit 4: FRDEN Invert Enable (FRDENI).
0 = do not invert the FRDEN signal (normal mode)
1 = invert the FRDEN signal (inverted mode)
Bit 5: FRD Invert Enable (FRDI).
0 = do not invert the FRD signal (normal mode)
1 = invert the FRD signal (inverted mode)
Bit 6: FRCLK Invert Enable (FRCLKI).
0 = do not invert the FRCLK signal (normal mode)
1 = invert the FRCLK signal (inverted mode)
Bit 7: FRSOF Invert Enable (FRSOFI).
0 = do not invert the FRSOF signal (normal mode)
1 = invert the FRSOF signal (inverted mode)
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DS3112
4.3 Master Status and Interrupt Register Description
4.3.1 Status Registers
The status registers in the DS3112 allow the host to monitor the real-time condition of the device. Most of
the status bits in the device can cause a hardware interrupt to occur. Also, most of the status bits within
the device are latched to ensure that the host can detect changes in state and the true status of the device.
There are three types of status bits in the DS3112. The first type is called an event status bit and is
derived from a momentary condition or state that occurs within the device. The event status bits are
always cleared when read and can generate an interrupt when they are asserted. An example of an event
status bit is the one-second timer boundary occurrence (OST).
The second type of status bit is called an alarm status bit, which is derived from conditions that can occur
for longer than an instance. The alarm status bits will be cleared when read unless the alarm is still
present. The alarm status bits generate interrupts on a change in state in the alarm (i.e., when it is asserted
or deasserted). An example of an alarm status bit is the loss of frame (LOF).
The third type of status bit is called a real-time status bit. The real-time status bit remains active as long
as the condition exists and will generate an interrupt as long as the condition exists. An example of a real-
time status bit is the loss of transmit clock (LOTC).
Figure 4-1. Event Status Bit
Internal Signal
Status Bit
Interrupt
Read
Figure 4-2. Alarm Status Bit
Internal Signal
Status Bit
Interrupt
Read
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Figure 4-3. Real-Time Status Bit
Internal Signal
Status Bit
Interrupt
Read
4.3.2 MSR
The Master Status Register (MSR) is a special status register that can be used to help the host quickly
locate changes in device status. There is a status bit in the MSR for each of the major blocks within the
DS3112. When an alarm or event occurs in one of these blocks, the device can be configured to set a bit
in the MSR. Status bits in the MSR can also cause a hardware interrupt to occur. In either polled or
interrupt driven software routines, the host can first read the MSR to locate which status registers need to
be serviced.
Register Name:
MSR
Register Description:
Register Address:
Master Status Register
08h
Bit #
7
6
5
4
3
2
1
0
Name
Default
—
—
T2E2SR2 T2E2SR1
FEAC
—
HDLC
—
BERT
—
COVF
—
OST
—
—
—
Bit #
Name
Default
15
—
—
14
—
—
13
G.747
—
12
T3E3MS
—
11
LORC
—
10
LOTC
—
9
T3E3SR
—
8
T1LB
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: One-Second Timer Boundary Occurrence (OST). This latched read-only event-status bit will be set to a
one on each one-second boundary as timed by the DS3112. The device chooses an arbitrary one-second boundary
that is timed from the HRCLK signal. This bit will be cleared when read and will not be set again until another
one-second boundary has occurred. The setting of this status bit can cause a hardware interrupt to occur if the OST
bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this
bit is read.
Bit 1: Counter Overflow Event (COVF). This latched read-only event-status bit will be set to a one if any of the
error counters saturates (the error counters saturate when full). This bit will be cleared when read even if one or
more of the error counters is still saturated. The setting of this status bit can cause a hardware interrupt to occur if
the COVF bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear
when this bit is read.
Bit 2: Change in BERT Status (BERT). This read-only real-time status bit will be set to a one if there is a major
change of status in the BERT receiver and the associated interrupt enable bit is set in the BERTCO register. A
major change of status is defined as either a change in the receive synchronization (i.e., the BERT has gone into or
out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the Bit Counter
or the Error Counter. The host must read the status bits of the BERT in the BERT Status Register (BERTEC0) to
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DS3112
determine the change of state. This bit will be cleared when the BERTEC0 is read and will not be set again until
the BERT has experienced another change of state. The setting of this status bit can cause a hardware interrupt to
occur if the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed
to clear when the BERTEC0 register is read (Figure 4-4).
Bit 3: Change in HDLC Status (HDLC). This read-only real-time status bit will be set to a one if there is a
change of status in the HDLC controller and the associated interrupt enable bit is set in the IHSR register. The host
must read the status bits of the HDLC in the HDLC Status Register (HSR) to determine the change of state. This bit
will be cleared when the HSR is read and will not be set again until the HDLC has experienced another change of
state. The setting of this status bit can cause a hardware interrupt to occur if the HDLC bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the HSR register is read
(see Figure 4-5).
Bit 4: Change in FEAC Status (FEAC). This read-only real-time status bit will be set to a one when the FEAC
controller has detected and verified a new Far End Alarm and Control (FEAC) 16-bit codeword. This bit will be
cleared when the FEAC Status Register (FSR) is read and will not be set again until the FEAC controller has
detected and verified another new codeword. The setting of this status bit can cause a hardware interrupt to occur if
the FEAC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear
when the FSR register is read.
Bit 5: Change in T2/E2 LOF or AIS Status (T2E2SR1). This read-only real-time status bit will be set to a one
when one or more of the T2/E2/G.747 framers have detected a change in either Loss Of Frame (LOF) or Alarm
Indication Signal (AIS) and the associated interrupt enable bit is set in the T2E2SR1 register. See the T2E2SR1
register description in Section 6.3 for more details. This bit will be cleared when the T2E2SR1 register is read. The
setting of this status bit can cause a hardware interrupt to occur if the T2E2SR1 bit in the Interrupt Mask for MSR
(IMSR) register is set to a one. The interrupt will be allowed to clear when the T2E2SR1 register is read (see
Figure 4-6).
Bit 6: Change in T2/E2 RAI Status (T2E2SR2). This read-only real-time status bit will be set to a one when one
or more of the T2/E2/G.747 framers have detected a change in the detection of the Remote Alarm Indication (RAI)
signal and the interrupt enable (bit 7) is set in the T2E2SR2 register. See the T2E2SR2 register description in
Section 6.3 for more details. This bit will be cleared when the T2E2SR2 register is read. The setting of this status
bit can cause a hardware interrupt to occur if the T2E2SR2 bit in the Interrupt Mask for MSR (IMSR) register is set
to a one. The interrupt will be allowed to clear when the T2E2SR2 register is read (see Figure 4-7).
Bit 8: T1 Loopback Detected (T1LB). This read-only real-time status bit will be set to a one when one or more of
the T2 framers have detects an active T1 loopback command. See the T1LBSR1 and T1LBSR2 register
descriptions in Section 7.3 for more details. This bit will be cleared when the T1 loopback command is no longer
active on any of the lines. The setting of this status bit can cause a hardware interrupt to occur if the T1LB bit in
the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the none of
the T2 framers detects an active T1 loopback command (see Figure 4-8).
Bit 9: Change in T3/E3 Framer Status (T3E3SR). This read-only real-time status bit will be set to a one when
the T3/E3 framer has detected a change in RAI, AIS, LOF, LOS, or T3 Idle signal or has detected the start of a
Transmit or Receive Frame and the associated interrupt enable bit is set in the T3E3SR register. See the T3E3SR
register description in Section 5.3 for more details. This bit will be cleared when the T3E3SR register is read. The
setting of this status bit can cause a hardware interrupt to occur if the T3E3SR bit in the Interrupt Mask for MSR
(IMSR) register is set to a one. The interrupt will be allowed to clear when the T3E3SR register is read (see
Figure 4-9).
Bit 10: Loss Of Transmit Clock Detected (LOTC). This read-only real-time status bit will be set to a one when
the device detects that the FTCLK clock has not toggled for 200ns (±100ns). This bit will be cleared when a clock
is detected at the FTCLK input. The setting of this status bit can cause a hardware interrupt to occur if the LOTC
bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the
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device detects a clock at FTCLK. The HRCLK checks for the presence of the FTCLK. On reset, both the LOTC
and LORC status bits will be set and then immediately cleared if the clock is present.
Bit 11: Loss Of Receive Clock Detected (LORC). This read-only real-time status bit will be set to a one when the
device detects that the HRCLK clock has not toggled for 200ns (±100ns). This bit will be cleared when a clock is
detected at the HRCLK input. The setting of this status bit can cause a hardware interrupt to occur if the LORC bit
in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the
device detects a clock at HRCLK. The FTCLK checks for the presence of the HRCLK. On reset, both the LOTC
and LORC status bits will be set and then immediately cleared if the clock is present.
Bit 12: State of the T3E3MS Input Signal (T3E3MS). This read-only real-time status bit reflects the current state
of the external T3E3MS input signal. This status bit cannot generate an interrupt.
Bit 13: State of the G.747E Input Signal (G.747E). This read-only real-time status bit reflects the current state of
the external G.747E input signal. This status bit cannot generate an interrupt.
Figure 4-4. BERT Status Bit Flow
Internal RLOS
Signal from
BERT
RLOS
(BERTEC0
Bit 4)
Alarm Latch
Change in State Detect
IESYNC (BERTC0 Bit 15)
Event Latch
Mask
BED
(BERTEC0
Bit 3)
Internal Bit
Error Detected
Signal from
BERT
Event Latch
BERT
Mask
Mask
Status Bit
(MSR Bit 2)
OR
IEBED (BERTC0 Bit 14)
INT*
Hardware
Signal
BECO or BBCO
(BERTEC0
Bits 1 & 2)
Internal Counter
Overflow
Signal from
BERT
Mask
Event Latch
BERT
(IMSR Bit 2)
IEOF (BERTC0 Bit 13)
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE BERTEC0 REGISTER IS READ.
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Figure 4-5. HDLC Status Bit Flow
Transmit
TEND
(HSR Bit 0)
Event Latch
Packet End
Signal from
HDLC
Mask
Mask
TEND (IHSR Bit 0)
Internal Transmit
Low Water Mark
Signal from
TLWM
(HSR Bit 2)
HDLC
TLWM (IHSR Bit 2)
Internal Receive
High Water Mark
Signal from
RHWM
(HSR Bit 4)
HDLC
Mask
Mask
RHWM (IHSR Bit 4)
Internal Receive
Packet Start
Signal from
HDLC
RPS
(HSR Bit 5)
Event Latch
Event Latch
Event Latch
Event Latch
RPS (IHSR Bit 5)
HDLC
Status Bit
(MSR Bit 3)
Internal Receive
Packet End
Signal from
HDLC
RPE
(HSR Bit 6)
OR
INT*
Hardware
Signal
Mask
Mask
RPE (IHSR Bit 6)
HDLC
(IMSR Bit 3)
Internal Transmit
FIFO Underrun
Signal from
HDLC
TUDR
(HSR Bit 7)
Mask
Mask
Mask
TUDR (IHSR Bit 3)
Internal Receive
FIFO Overrun
Signal from
HDLC
ROVR
(HSR Bit 13)
ROVR (IHSR Bit 13)
RABT
Internal Receive
Abort Detect
Signal from
HDLC
Event Latch
(HSR Bit 15)
RABT (IHSR Bit 15)
NOTE: ALL EVENT LATCHES ABOVE ARE CLEARED WHEN THE HSR REGISTER IS READ.
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DS3112
Figure 4-6. T2E2SR1 Status Bit Flow
Internal LOF
Signal from
T2/E2 Framer 1
LOF1
(T2E2SR1
Bit 0)
Alarm Latch
Event
Latch
Change in State Detect
Internal LOF
Signal from
T2/E2 Framer 2
LOF2
(T2E2SR1
Bit 1)
Alarm Latch
Event
Latch
Change in State Detect
OR
Mask
IELOF
(T2E2SR1
Bit 7)
Internal LOF
Signal from
T2 Framer 7
LOF7
(T2E2SR1
Bit 6)
Alarm Latch
Event
Latch
Change in State Detect
T2E2SR1
Status Bit
(MSR Bit 5)
OR
INT*
Hardware
Signal
Mask
Internal AIS
AIS1
Signal from
T2/E2 Framer 1
(T2E2SR1
Bit 8)
Alarm Latch
T2E2SR1
(IMSR Bit 5)
Event
Latch
Change in State Detect
Internal AIS
AIS2
(T2E2SR1
Bit 9)
Signal from
T2/E2 Framer 2
Alarm Latch
Event
Latch
Change in State Detect
OR
Mask
IEAIS
(T2E2SR1
Bit 15)
Internal AIS
Signal from
T2 Framer 7
AIS7
(T2E2SR1
Bit 14)
Alarm Latch
Event
Latch
Change in State Detect
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T2E2SR1 REGISTER IS READ.
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Figure 4-7. T2E2SR2 Status Bit Flow
Internal RAI
Signal from
T2/E2 Framer 1
RAI1
(T2E2SR2
Bit 0)
Alarm Latch
Change in State Detect
Event Latch
Event Latch
Internal RAI
Signal from
T2/E2 Framer 2
RAI2
(T2E2SR2
Bit 1)
Alarm Latch
Change in State Detect
T2E2SR2
Status Bit
(MSR Bit 6)
OR
Mask
INT*
Hardware
Signal
Mask
IERAI
(T2E2SR2
Bit 7)
Internal RAI
Signal from
T2 Framer 7
RAI7
(T2E2SR2
Bit 6)
Alarm Latch
T2E2SR2
(IMSR Bit 6)
Change in State Detect
Event Latch
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T2E2SR2 REGISTER IS READ.
Figure 4-8. T1LB Status Bit Flow
LLB1
(T1LBSR1
Bit 0)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
LLB2
(T1LBSR1
Bit 1)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
T1LB
Status Bit
(MSR Bit 8)
OR
INT*
Hardware
Signal
Mask
LLB28
(T1LBSR2
Bit 11)
Internal T1
Loopback Command
Signal from
T1LB
(IMSR Bit 8)
T2/E2 Framer
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Figure 4-9. T3E3SR Status Bit Flow
Receive LOS
Signal from
T3/E3 Framer
LOS
(T3E3SR Bit 0)
Alarm Latch
Change in State Detect
Event Latch
Mask
Mask
Mask
Mask
Mask
Mask
Mask
LOS (IT3E3SR Bit 0)
Receive LOF
Signal from
T3/E3 Framer
LOF
(T3E3SR Bit 1)
Alarm Latch
Change in State Detect
Event Latch
LOF (IT3E3SR Bit 1)
Receive AIS
Signal from
T3/E3 Framer
AIS
Alarm Latch
(T3E3SR Bit 2)
Change in State Detect
Event Latch
AIS (IT3E3SR Bit 2)
Receive RAI
Signal from
T3/E3 Framer
AIS
Alarm Latch
(T3E3SR Bit 3)
T3E3SR
Change in State Detect
Event Latch
Status Bit
(MSR Bit 9)
OR
AIS (IT3E3SR Bit 3)
INT*
Hardware
Signal
Mask
Receive Idle
Signal from
T3/E3 Framer
T3IDLE
(T3E3SR Bit 4)
Alarm Latch
T3E3SR
(IMSR Bit 9)
Change in State Detect
Event Latch
T3IDLE (IT3E3SR Bit 4)
Receive Start
Of Frame
Signal from
RSOF
(T3E3SR Bit 5)
Event Latch
Event Latch
T3/E3 Framer
RSOF (IT3E3SR Bit 5)
Transmit Start
Of Frame
Signal from
T3/E3 Framer
TSOF
(T3E3SR Bit 6)
TSOF (IT3E3SR Bit 6)
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T3E3SR REGISTER IS READ.
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Register Name:
IMSR
Register Description:
Register Address:
Interrupt Mask for Master Status Register
0Ah
Bit #
Name
Default
7
—
—
6
5
4
FEAC
0
3
HDLC
0
2
BERT
0
1
COVF
0
0
OST
0
T2E2SR2 T2E2SR1
0
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
LORC
0
10
LOTC
0
9
T3E3SR
0
8
T1LB
0
Bit 0: One-Second Timer Boundary Occurrence (OST).
0 = interrupt masked
1 = interrupt unmasked
Bit 1: Counter Overflow Event (COVF).
0 = interrupt masked
1 = interrupt unmasked
Bit 2: Change in BERT Status (BERT).
0 = interrupt masked
1 = interrupt unmasked
Bit 3: Change in HDLC Status (HDLC).
0 = interrupt masked
1 = interrupt unmasked
Bit 4: Change in FEAC Status (FEAC).
0 = interrupt masked
1 = interrupt unmasked
Bit 5: Change in T2/E2 LOF or AIS Status (T2E2SR1).
0 = interrupt masked
1 = interrupt unmasked
Bit 6: Change in T2/E2 RAI Status (T2E2SR2).
0 = interrupt masked
1 = interrupt unmasked
Bit 8: T1 Loopback Detected (T1LB).
0 = interrupt masked
1 = interrupt unmasked
Bit 9: Change in T3/E3 Framer Status (T3E3SR).
0 = interrupt masked
1 = interrupt unmasked
Bit 10: Loss Of Transmit Clock (LOTC).
0 = interrupt masked
1 = interrupt unmasked
Bit 11: Loss Of Receive Clock (LORC).
0 = interrupt masked
1 = interrupt unmasked
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4.4 Test Register Description
Register Name:
TEST
Register Description:
Register Address:
Test Register
0Ch
Bit #
Name
Default
7
—
—
6
—
—
5
FT5
0
4
FT4
0
3
FT3
0
2
FT2
0
1
FT1
0
0
FT0
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
—
—
10
—
—
9
—
—
8
—
—
Bits 0 to 5: Factory Test Bits (FT0 to FT5). These bits are used by the factory to place the DS3112 into the test
mode. For normal device operation, these bits should be set to zero whenever this register is written to.
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5 T3/E3 FRAMER
On the receive side, the T3/E3 framer locates the frame boundaries of the incoming T3 or E3 data stream
and monitors the data stream for alarms and errors. Alarms are detected and reported in T3/E3 Status
Register (T3E3SR) and the T3/E3 Information Register (T3E3INFO), which are described in Section 5.3.
Errors are accumulated in a set of error counters (Section 5.4). The host can force the T3/E3 framer to
resynchronize via the T3E3RSY control bit in the MRID register (Section 4.1). On the transmit side, the
device formats the outgoing data stream with the proper framing pattern and overhead and can generate
alarms. It can also inject errors for diagnostic testing purposes (T3E3EIC register). The transmit side of
the framer is called the “formatter.”
The T3/E3 framer and formatter can be used in conjunction with the multiplexer or as a stand-alone
framer. This selection is made in the Master Configuration 1 (MC1) register (Section 4.2).
5.1 T3/E3 Line Loopback
The line loopback loops the incoming T3/E3 data (the HRCLK, HRPOS, and HRNEG inputs) directly
back to the transmit side (the HTCLK, HTPOS, and HTNEG outputs). When this loopback is enabled, the
incoming receive data continues to pass through the device but the data output from the T3/E3 formatter
is replaced with the data being input to the device. See the block diagrams in Section 1 for a visual
description of this loopback.
5.2 T3/E3 Diagnostic Loopback
The diagnostic loopback loops the outgoing T3/E3 data from the T3/E3 formatter back to receive side
framer. When this loopback is enabled, the incoming receive data at HRCLK, HRPOS, and HRNEG is
ignored. See the block diagrams in Section 1 for a visual description of this loopback. Please note that the
device can still generate AIS at the HTCLK, HTPOS, and HTNEG outputs when this loopback is
invoked. This is important to keep the data that is being looped back from disturbing downstream
equipment.
5.3 T3/E3 Payload Loopback
The payload loopback loops the framed T3/E3 data from the receive side framer back to the transmit side
formatter. When this loopback is enabled, the incoming receive data continues to pass through the device
but the data normally being input to the T3/E3 formatter is ignored. See the block diagrams in Section 1
for a visual description of this loopback.
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5.4 T3/E3 Framer Control Register Description
Register Name:
T3E3CR
Register Description:
Register Address:
T3/E3 Control Register
10h
Bit #
Name
Default
7
DLB
0
6
LLB
0
5
T3IDLE
0
4
E3SnC1
0
3
E3SnC0
0
2
TPT
0
1
TRAI
0
0
TAIS
0
Bit #
Name
Default
15
—
—
14
PLB
0
13
TFEBE
0
12
AFEBED
0
11
ECC
0
10
FECC1
0
9
FECC0
0
8
E3CVE
0
Bit 0: T3/E3 Transmit Alarm Indication Signal (TAIS). When this bit is set high in the T3 mode, the transmitter
will generate a properly F-bit and M-bit framed 101010... data pattern with both X bits set to one, all C bits set to
zero, and the proper P bits. This is true regardless of whether the device is in the C-Bit Parity mode or not. When
this bit is set high in the E3 mode, the transmitter will generate an unframed all ones. When this bit it set low,
normal data is transmitted.
0 = do not transmit AIS
1 = transmit AIS
Bit 1: T3/E3 Transmit Remote Alarm Indication (TRAI). When this bit is set high in the T3 mode, both X bits
will be set to a zero. When this bit is set high in the E3 mode, the RAI bit (bit number 11 of each E3 frame) will be
set to a one. When this bit it set low in the T3 mode, both X bits will be set to one. When this bit is set low in the
E3 mode, the RAI bit will be set to a zero.
0 = do not transmit RAI
1 = transmit RAI
Bit 2: T3/E3 Transmit Pass Through Enable (TPT).
0 = enable the framer to insert framing and overhead bits
1 = framer will not insert any framing or overhead bits
Bits 3 and 4: E3 National Bit Control Bits 0 and 1 (E3SnC0 and E3SnC1). These bits determine from where the
E3 national bit is sourced. On the receive side, the Sn bit is always routed to the T3E3INFO Register as well as the
HDLC controller and the FEAC controller. These bits are ignored in the T3 mode.
E3SnC1
E3SnC0
SOURCE OF THE E3 NATIONAL BIT (Sn)
Force the Sn bit to one
Use the HDLC controller to source the Sn bit
Use the FEAC controller to source the Sn bit
Force the Sn bit to zero
0
0
1
1
0
1
0
1
Bit 5: Transmit T3 Idle Signal Enable (T3IDLE). When this bit is set high, the T3 Idle Signal will be transmitted
instead of the normal transmit data. The T3 Idle Signal is defined as a normally T3 framed pattern (i.e., with the
proper F bits and M bits along with the proper P bits) where the information bit fields are completely filled with a
data pattern of ...1100... and the C bits in Subframe 3 are set to zero and both X bits are set to one. This bit is
ignored in the E3 mode.
0 = transmit data normally
1 = transmit T3 Idle Signal
Bit 6: T3/E3 Line Loopback Enable (LLB). See Figure 1-1 and Figure 1-2 for a visual description of this
loopback.
0 = disable loopback
1 = enable loopback
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Bit 7: T3/E3 Diagnostic Loopback Enable (DLB). See Figure 1-1 and Figure 1-2 for a visual description of this
loopback.
0 = disable loopback
1 = enable loopback
Bit 8: E3 Code Violation Enable (E3CVE). This bit is ignored in the T3 mode. This bit is used in the E3 mode to
configure the BiPolar Violation Count Register (BPVCR) to count either BiPolar Violations (BPV) or Code
Violations (CV). A BPV is defined as consecutive pulses (or marks) of the same polarity that are not part of a
HDB3 codeword. A CV is defined in ITU O.161 as consecutive BPVs of the same polarity.
0 = count BPV
1 = count CV
Bits 9 and 10: T3/E3 Frame Error Counting Control Bits 0 and 1 (FECC0 and FECC1).
FECC1
FECC0 FRAME ERROR COUNT REGISTER (FECR) CONFIGURATION
T3 Mode: Count Loss Of Frame (LOF) Occurrences
E3 Mode: Count Loss Of Frame (LOF) Occurrences
0
0
T3 Mode: Count Both F Bit and M Bit Errors
E3 Mode: Count Bit Errors in the FAS Word
T3 Mode: Count Only F Bit Errors
E3 Mode: Count Word Errors in the FAS Word
T3 Mode: Count Only M Bit Errors
E3 Mode: Illegal State
0
1
1
1
0
1
Bit 11: Error Counting Control (ECC). This bit is used to control whether the device will increment the error
counters during Loss Of Frame (LOF) conditions. It only affects the error counters that count errors that are based
on framed information and these include the following:
ꢀ
ꢀ
ꢀ
ꢀ
Frame Error Counter (when it is configured to count frame errors, not LOF occurrences)
T3 Parity Bit Error Counter
T3 C-Bit Parity Error Counter
T3 Far End Block Error or E3 RAI Counter
When this bit is set low, these error counters will not be allowed to increment during LOF conditions. When this bit
is set high, these error counters will be allowed to increment during LOF conditions.
0 = stop the FECR/PCR/CPCR/FEBECR error counters from incrementing during LOF
1 = allow the FECR/PCR/CPCR/FEBECR error counters to increment during LOF
Bit 12: Automatic FEBE Defeat (AFEBED). This bit is ignored in the E3 mode and in the T3 mode when the
device is not configured in the C-Bit Parity Mode. When this bit is low, the device will automatically insert the
FEBE codes into the transmitted data stream by setting all three C bits in Subframe 4 to zero.
0 = automatically insert FEBE codes in the transmit data stream based on detected errors
1 = use the TFEBE control to determine the state of the FEBE codes
Bit 13: Transmit FEBE Setting (TFEBE). This bit is only active when AFEBED is active (i.e., AFEBED = 1).
When this bit is low, the device will force the FEBE code to 111 continuously. When this bit is set high, the device
will force the FEBE code to 000 continuously.
0 = force FEBE to 111 (null state)
1 = force FEBE to 000 (active state)
Bit 14: T3/E3 Payload Loopback Enable (PLB). See Figure 1-1 and Figure 1-2 for a visual description of this
loopback.
0 = disable loopback
1 = enable loopback
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Register Name:
T3E3EIC
Register Description:
Register Address:
T3/E3 Error Insert Control Register
18h
Bit #
Name
Default
7
MEIMS
0
6
FBEIC1
0
5
FBEIC0
0
4
FBEI
0
3
T3CPBEI
0
2
T3PBEI
0
1
EXZI
0
0
BPVI
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
—
—
10
—
—
9
—
—
8
—
—
Bit 0: BiPolar Violation Insert (BPVI). A zero to one transition on this bit will cause a single BPV to be inserted
into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next
occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent
error to be inserted. Toggling this bit has no affect when the T3/E3 interface is in the Unipolar Mode (Section 4.2
for details about the Unipolar Mode). In the manual error insert mode (MEIMS = 1), errors will be inserted on each
toggle of the FTMEI input signal as long as this bit is set high. When this bit is set low, no errors will be inserted.
Bit 1: Excessive Zero Insert (EXZI). A zero to one transition on this bit will cause a single EXZ event to be
inserted into the transmit data stream. An EXZ event is defined as three or more consecutive zeros in the T3 mode
and four or more consecutive zeros in the E3 mode. Once this bit has been toggled from a zero to a one, the device
waits for the next possible B3ZS/HDB3 codeword insertion and it suppresses that codeword from being inserted
and hence this creates the EXZ event. This bit must be cleared and set again for a subsequent error to be inserted.
Toggling this bit has no affect when the T3/E3 interface is in the Unipolar Mode (Section 4.2 for details about the
Unipolar Mode). In the Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle of the
FTMEI input signal as long as this bit is set high. When this bit is set low, no errors will be inserted.
Bit 2: T3 Parity Bit Error Insert (T3PBEI). A zero to one transition on this bit will cause a single T3 parity error
event to be inserted into the transmit data stream. A T3 parity event is defined as flipping the proper polarity of
both the P bits in a T3 Frame. (See Section 14.5 for details about the P bits.) Once this bit has been toggled from a
zero to a one, the device waits for the next T3 frame to flip both P bits. This bit must be cleared and set again for a
subsequent error to be inserted. Toggling this bit has no affect when the device is operated in the E3 mode. In the
Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long
as this bit is set high. When this bit is set low, no errors will be inserted.
Bit 3: T3 C-Bit Parity Error Insert (T3CPBEI). A zero to one transition on this bit will cause a single T3 C-Bit
parity error event to be inserted into the transmit data stream. A T3 parity event is defined as flipping the proper
polarity of all three CP bits in a T3 Frame. (See Section 14.7 for details about the CP bits.) Once this bit has been
toggled from a zero to a one, the device waits for the next T3 frame to flip the three CP bits. This bit must be
cleared and set again for a subsequent error to be inserted. Toggling this bit has no affect when the T3 framer is not
operated in the C-Bit parity mode (See Section 14.7 for details about the C-Bit Parity mode.) or when the device is
operated in the E3 mode. In the Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle of
the FTMEI input signal as long as this bit is set high. When this bit is set low, no errors will be inserted.
Bit 4: Frame Bit Error Insert (FBEI). A zero to one transition on this bit will cause the transmit framer to
generate framing bit errors. The type of framing bit errors inserted is controlled by the FBEIC0 and FBEIC1 bits
(see discussion below). Once this bit has been toggled from a 0 to a 1, the device waits for the next possible
framing bit to insert the errors. This bit must be cleared and set again for a subsequent error to be inserted. In the
Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long
as this bit is set high. When this bit is set low, no errors will be inserted.
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Bits 5 and 6: Frame Bit Error Insert Control Bits 0 and 1 (FBEIC0 and FBEIC1).
FBEIC1
FBEIC0
TYPE OF FRAMING BIT ERROR INSERTED
T3 Mode: A single F-bit error
0
0
E3 Mode: A single FAS word of 1111000000 is generated instead of the normal FAS
word, which is 1111010000 (i.e., only 1 bit inverted)
T3 Mode: A single M-bit error
0
1
1
0
E3 Mode: A single FAS word of 0000101111 is generated instead of the normal FAS
word, which is 1111010000 (i.e., all FAS bits are inverted)
T3 Mode: Four consecutive F-bit errors (causes the far end to lose synchronization)
E3 Mode: Four consecutive FAS words of 1111000000 are generated instead of the
normal FAS word, which is 1111010000 (i.e., only 1 bit inverted; causes the far end
to lose synchronization)
T3 Mode: Three consecutive M-bit errors (causes the far end to lose synchronization)
E3 Mode: Four consecutive FAS words of 0000101111 are generated instead of the
normal FAS word, which is 1111010000 (i.e., all FAS bits are inverted; causes the far
end to lose synchronization)
1
1
Bit 7: Manual Error Insert Mode Select (MEIMS). When this bit is set low, the device will insert errors on each
0 to 1 transition of the BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bits. When this bit is set high, the device
will insert errors on each 0 to 1 transition of the FTMEI input signal. The appropriate BPVI, EXZI, T3PBEI,
T3CPBEI, or FBEI control bit must be set to one for this to occur. If all of the BPVI, EXZI, T3PBEI, T3CPBEI,
and FBEI control bits are set to zero, no errors are inserted.
0 = use zero to one transition on the BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bits to insert errors
1 = use zero to one transition on the FTMEI input signal to insert errors
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5.5 T3/E3 Framer Status and Interrupt Register Description
Register Name:
T3E3SR
Register Description:
Register Address:
T3/E3 Status Register
12h
Bit #
Name
Default
7
—
—
6
5
4
3
RAI
—
2
AIS
—
1
LOF
—
0
LOS
—
RSOF
—
TSOF
—
T3IDLE
—
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
—
—
10
—
—
9
—
—
8
—
—
Note: See Figure 5-1 for details on the signal flow for the status bits in the T3E3SR register. Bits that are underlined are read-only. All
others are read-write.
Bit 0: Loss Of Signal Occurrence (LOS). This latched read-only alarm-status bit will be set to a one when the T3
or E3 framer detects a loss of signal. This bit will be cleared when read unless a LOS condition still exists. A
change in state of the LOS can cause a hardware interrupt to occur if the LOS bit in the Interrupt Mask for T3E3SR
(IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when this bit is read. The LOS alarm criteria are described in Table 5-1
and Table 5-2.
Bit 1: Loss Of Frame Occurrence (LOF). This latched read-only alarm status bit will be set to a one when the T3
or E3 framer detects a loss of frame. This bit will be cleared when read unless a LOF condition still exists. A
change in state of the LOF can cause a hardware interrupt to occur if the LOF bit in the Interrupt Mask for T3E3SR
(IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when this bit is read. The LOF alarm criteria are described in Table 5-1
and Table 5-2.
Bit 2: Alarm Indication Signal Detected (AIS). This latched read-only alarm-status bit will be set to a one when
the T3 or E3 framer detects an incoming Alarm Indication Signal. This bit will be cleared when read unless an AIS
signal is still present. A change in state of the AIS detection can cause a hardware interrupt to occur if the AIS bit
in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read. The AIS alarm
detection criteria is described in Table 5-1 and Table 5-2.
Bit 3: Remote Alarm Indication Detected (RAI). This latched read-only alarm status bit will be set to a one when
the T3 or E3 framer detects an incoming Remote Alarm Indication (RAI) signal. This bit will be cleared when read
unless an RAI signal is still present. A change in state of the RAI detection can cause a hardware interrupt to occur
if the RAI bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
The RAI alarm detection criteria are described in Table 5-1 and Table 5-2. RAI can also be indicated via the FEAC
codes when the device is operated in the C-Bit Parity Mode.
Bit 4: T3 Idle Signal Detected (T3IDLE). This latched read-only alarm status bit will be set to a one when the T3
framer detects an incoming idle signal. This bit will be cleared when read unless the idle signal is still present. A
change in state of idle detection can cause a hardware interrupt to occur if the IDLE bit in the Interrupt Mask for
T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is
set to a one. The IDLE detection criteria are described in Table 5-1. The interrupt will be allowed to clear when this
bit is read. When the DS3112 is operated in the E3 mode, this status bit should be ignored.
Bit 5: Transmit T3/E3 Start Of Frame (TSOF). This latched read-only event-status bit will be set to a one on
each T3/E3 transmit frame boundary. This bit is a software version of the FTSOF hardware signal and it will be
cleared when read. The setting of this bit can cause a hardware interrupt to occur if the TSOF bit in the Interrupt
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Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR)
register is set to a one.
Bit 6: Receive T3/E3 Start Of Frame (RSOF). This latched read-only event status bit will be set to a one on each
T3/E3 receive frame boundary. This bit is a software version of the FRSOF hardware signal and it will be cleared
when read. The setting of this bit can cause a hardware interrupt to occur if the RSOF bit in the Interrupt Mask for
T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is
set to a one.
Figure 5-1. T3E3SR Status Bit Flow
Receive LOS
Signal from
T3/E3 Framer
LOS
(T3E3SR Bit 0)
Alarm Latch
Change in State Detect
Event Latch
Mask
Mask
Mask
Mask
Mask
Mask
Mask
LOS (IT3E3SR Bit 0)
Receive LOF
Signal from
T3/E3 Framer
LOF
(T3E3SR Bit 1)
Alarm Latch
Change in State Detect
Event Latch
LOF (IT3E3SR Bit 1)
Receive AIS
Signal from
T3/E3 Framer
AIS
Alarm Latch
(T3E3SR Bit 2)
Change in State Detect
Event Latch
AIS (IT3E3SR Bit 2)
Receive RAI
Signal from
T3/E3 Framer
RAI
Alarm Latch
(T3E3SR Bit 3)
T3E3SR
Change in State Detect
Event Latch
Status Bit
(MSR Bit 9)
OR
RAI (IT3E3SR Bit 3)
INT*
Hardware
Signal
Mask
Receive Idle
Signal from
T3/E3 Framer
T3IDLE
(T3E3SR Bit 4)
Alarm Latch
T3E3SR
(IMSR Bit 9)
Change in State Detect
Event Latch
T3IDLE (IT3E3SR Bit 4)
Receive Start
Of Frame
Signal from
TSOF
(T3E3SR Bit 5)
Event Latch
Event Latch
T3/E3 Framer
TSOF (IT3E3SR Bit 5)
Transmit Start
Of Frame
Signal from
T3/E3 Framer
RSOF
(T3E3SR Bit 6)
RSOF (IT3E3SR Bit 6)
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T3E3SR REGISTER IS READ.
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DS3112
Register Name:
IT3E3SR
Register Description:
Register Address:
Interrupt Mask for T3/E3 Status Register
14h
Bit #
Name
Default
7
—
—
6
RSOF
0
5
TSOF
0
4
T3IDLE
0
3
RAI
0
2
AIS
0
1
LOF
0
0
LOS
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
—
—
10
—
—
9
—
—
8
—
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Loss Of Signal Occurrence (LOS).
0 = interrupt masked
1 = interrupt unmasked
Bit 1: Loss Of Frame Occurrence (LOF).
0 = interrupt masked
1 = interrupt unmasked
Bit 2: Alarm Indication Signal Detected (AIS).
0 = interrupt masked
1 = interrupt unmasked
Bit 3: Remote Alarm Indication Detected (RAI).
0 = interrupt masked
1 = interrupt unmasked
Bit 4: T3 Idle Signal Detected (T3IDLE).
0 = interrupt masked
1 = interrupt unmasked
Bit 5: Transmit T3/E3 Start Of Frame (TSOF).
0 = interrupt masked
1 = interrupt unmasked
Bit 6: Receive T3/E3 Start Of Frame (RSOF).
0 = interrupt masked
1 = interrupt unmasked
55 of 133
DS3112
Table 5-1. T3 Alarm Criteria
ALARM/
DEFINITION
CONDITION
SET CRITERIA
CLEAR CRITERIA
AIS
Alarm Indication Signal
Properly framed 1010...
pattern, which is aligned
with the 1 just after each
overhead bit and all C bits
are set to zero
In each 84-bit information
field, the properly aligned
10... pattern is detected with
less than 4-bit errors (out of
84 possible) for 1024
consecutive information bit
fields (1.95ms) and all C bits
are majority decoded to be
zero during this time
In each 84 bit information
field, the properly aligned
10... pattern is detected with
4 or more bit errors (out of 84
possible) for 1024
consecutive information bit
fields (1.95ms)
LOS
LOF
Loss Of Signal
(Note 2)
192 consecutive zeros
No EXZ events over a 192-
bit window that starts with
the first one received
Loss Of Frame
Three or more F bits in error
Synchronization occurs
Too many F bits or M bits in out of 16 consecutive, or 2 or
error
more M bits in error out of
four consecutive
RAI
(Note 1)
Remote Alarm Indication
(This is also referred to as
SEF/AIS in Bellcore GR-
820)
X1 and X2 = 0 for four
consecutive M frames (426µs) consecutive M frames
(426µs)
X1 and X2 = 1 for four
Inactive: X1 = X2 = 1
Active: X1 = X2 = 0
Idle Signal
Properly framed 1100...
pattern, which is aligned
with the 11 just after each
overhead bit and the C bits
in Subframe 3 are zero.
In each 84-bit information
field, the properly aligned
1100... pattern is detected with 1100... pattern is detected
less than 4-bit errors (out of
84 possible) for 1024
consecutive information bit
fields (1.95ms) and the C bits
in Subframe 3 are majority
decoded to be zero during this
time.
In each 84-bit information
field, the properly aligned
with four or more bit errors
(out of 84 possible) for 1024
consecutive information bit
fields (1.95ms)
Note 1: RAI can also be indicated via FEAC codes in the C-Bit Parity Mode
Note 2: LOS is not defined for unipolar (binary) operation.
56 of 133
DS3112
Table 5-2. E3 Alarm Criteria
ALARM/
DEFINITION
CONDITION
SET CRITERIA
CLEAR CRITERIA
AIS
Alarm Indication Signal
Unframed all ones
Four or fewer zeros in
two consecutive 1536-
bit frames
Five or more zeros in two
consecutive 1536-bit frames
LOS
Loss Of Signal
(See note)
192 consecutive zeros
No EXZ events over a 192-bit
window that starts with the
first one received
LOF
RAI
Loss Of Frame
Too many FAS errors
Remote Alarm Indication
Inactive: Bit 11 of the frame = 0
Active: Bit 11 of the frame = 1
Four consecutive bad
FAS
Bit 11 = 1 for 4
consecutive frames
(6144 bits/179µs)
Three consecutive good FAS
Bit 11 = 0 for 4 consecutive
frames (6144 bits/179µs)
Note: LOS is not defined for unipolar (binary) operation.
Register Name:
T3E3INFO
Register Description:
Register Address:
T3/E3 Information Register
16h
Bit #
7
6
5
4
3
2
1
0
Name
Default
—
—
—
—
SEFE
—
EXZ
—
MBE
—
FBE
—
ZSCD
—
COFA
—
Bit #
Name
Default
15
—
—
14
—
—
13
RAIC
—
12
AISC
—
11
LOFC
—
10
LOSC
—
9
T3AIC
—
8
E3Sn
—
Note: Bits that are underlined are read-only; all other bits are read-write. The status bits in the T3E3INFO cannot cause a hardware
interrupt to occur.
Bit 0: Change Of Frame Alignment Detected (COFA). This latched read-only event-status bit will be set to a
one when the T3/E3 framer has experienced a change of frame alignment (COFA). A COFA occurs when the
device achieves synchronization in a different alignment than it had previously. If the device has never acquired
synchronization before, then this status bit is meaningless. This bit will be cleared when read and will not be set
again until the framer has lost synchronization and reacquired synchronization in a different alignment.
Bit 1: Zero Suppression Codeword Detected (ZSCD). This latched read-only event-status bit will be set to a one
when the T3/E3 framer has detected a B3ZS/HDB3 codeword. This bit will be cleared when read and will not be
set again until the framer has detected another B3ZS/HDB3 codeword.
Bit 2: F-Bit or FAS Error Detected (FBE). This latched read-only status bit will be set to a one when the DS3112
has detected an error in either the F bits (T3 mode) or the FAS word (E3 mode). This bit will be cleared when read
and will not be set again until the device detects another error.
Bit 3: M-Bit Error Detected (MBE). This latched read-only event status bit will be set to a one when the DS3112
has detected an error in the M bits. This bit will be cleared when read and will not be set again until the device
detects another error in one of the M bits. This status bit has no meaning in the E3 mode and should be ignored.
Bit 4: Excessive Zeros Detected (EXZ). This latched read-only event status bit will be set to a one each time the
DS3112 has detected a consecutive string of either three or more zeros (T3 mode) or four or more zeros (E3 mode).
This bit will be cleared when read and will not be set again until the device detects another EXcessive Zero event.
57 of 133
DS3112
Bit 5: Severely Errored Framing Event Detected (SEFE). This latched read-only event-status bit will be set to a
one each time the DS3112 has detected either three or more F bits in error out of 16 consecutive F bits (T3 mode)
or four bad FAS words in a row (E3 mode). This bit will be cleared when read and will not be set again until the
device detects another SEFE event.
Bit 8: E3 National Bit (E3Sn). This read-only real-time status bit reports the incoming E3 National Bit (Sn). It is
loaded at the start of each E3 frame as the Sn bit is decoded. The host can use the RSOF status bit in the T3/E3
Status Register (T3E3SR) to determine when to read this bit.
Bit 9: T3 Application ID Channel Status (T3AIC). This read-only real-time status bit can be used to help
determine whether an incoming T3 data stream is in C-Bit Parity mode or M23 mode. In C-Bit Parity mode, it is
recommended that the first C bit in each M frame be set to one. In M23 mode, the first C bit in each M frame
should be toggling between zero and one to indicate that the bits need to be stuffed or not. This bit will be set to a
one when the device detects that the first C bit in the M frame is set to one for 1020 times or more out of 1024
consecutive M frames (109ms). It will be allowed to be cleared when the device detects that the first C bit is set to
one less than 1020 times out of 1024 consecutive M frames (109ms). This status bit has no meaning in the E3 mode
and should be ignored.
Bit 10: Loss Of Signal Clear Detected (LOSC). This latched read-only event-status bit will be set to a one each
time the T3/E3 framer exits a Loss Of Signal (LOS) state. This bit will be cleared when read and will not be set
again until the device once again exits the LOS state. The LOS alarm criteria are described in Table 5-1 and
Table 5-2. This status bit is useful in helping the host determine if the LOS persists as defined in ANSI T1.231.
Bit 11: Loss Of Frame Clear Detected (LOFC). This latched read-only event-status bit will be set to a one each
time the T3/E3 framer exits a Loss Of Frame (LOF) state. This bit will be cleared when read and will not be set
again until the device once again exits the LOF state. The LOF alarm criteria are described in Table 5-1 and
Table 5-2. This status bit is useful in helping the host determine if the LOF persists as defined in ANSI T1.231.
Bit 12: Alarm Indication Signal Clear Detected (AISC). This latched read-only event status bit will be set to a
one each time the T3/E3 framer no longer detects the AIS alarm state. This bit will be cleared when read and will
not be set again until the device once again exits the AIS alarm state. The AIS alarm criteria is described in
Table 5-1 and Table 5-2. This status bit is useful in helping the host determine if the AIS persists as defined in
ANSI T1.231.
Bit 13: Remote Alarm Indication Clear Detected (RAIC). This latched read-only event-status bit will be set to a
one each time the T3/E3 framer no longer detects the RAI alarm state. This bit will be cleared when read and will
not be set again until the device once again exits the RAI alarm state. The RAI alarm criteria are described in
Table 5-1 and Table 5-2. This status bit is useful in helping the host determine if the RAI persists as defined in
ANSI T1.231.
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DS3112
5.6 T3/E3 Performance Error Counters
There are six error counters in the DS3112. All of the errors counters are 16 bits in length. The host has
three options as to how these errors counters are updated. The device can be configured to automatically
update the counters once a second or manually via either an internal software bit (MECU) or an external
signal (FRMECU). See Section 4.2 for details. All the error counters saturate when full and will not
rollover.
Register Name:
BPVCR
Register Description:
Register Address:
BiPolar Violation Count Register
20h
Bit #
7
6
5
4
3
2
1
0
Name
Default
BPV7
—
BPV6
—
BPV5
—
BPV4
—
BPV3
—
BPV2
—
BPV1
—
BPV0
—
Bit #
Name
Default
15
BPV15
—
14
BPV14
—
13
BPV13
—
12
BPV12
—
11
BPV11
—
10
BPV10
—
9
8
BPV9
—
BPV8
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit BiPolar Violation Counter (BPV0 to BPV15). These bits report the number of BiPolar
Violations (BPV). In the E3 Mode, this counter can also be configured via the E3CVE bit in the T3E3 Control
Register (Section 5.2) to count Code Violations (CV). A BPV is defined as consecutive pulses (or marks) of the
same polarity that are not part of a B3ZS/HDB3 codeword. A CV is defined in ITU O.161 as consecutive BPVs of
the same polarity.
Register Name:
EXZCR
Register Description:
Register Address:
EXcessive Zero Count Register
22h
Bit #
7
6
5
4
3
2
1
0
Name
Default
EXZ7
—
EXZ6
—
EXZ5
—
EXZ4
—
EXZ3
—
EXZ2
—
EXZ1
—
EXZ0
—
Bit #
Name
Default
15
EXZ15
—
14
EXZ14
—
13
EXZ13
—
12
EXZ12
—
11
EXZ11
—
10
EXZ10
—
9
8
EXZ9
—
EXZ8
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit EXcessive Zero Counter (EXZ0 to EXZ15). These bits report the number of EXcessive Zero
occurrences (EXZ). An EXZ occurrence is defined as three or more consecutive zeros in the T3 mode and four or
more consecutive zeros in the E3 mode. As an example, a string of eight consecutive zeros would only increment
this counter once.
59 of 133
DS3112
Register Name:
FECR
Register Description:
Register Address:
Frame Error Count Register
24h
Bit #
Name
Default
7
FE7
—
6
FE6
—
5
FE5
—
4
FE4
—
3
FE3
—
2
FE2
—
1
FE1
—
0
FE0
—
Bit #
Name
Default
15
FE15
—
14
FE14
—
13
FE13
—
12
FE12
—
11
FE11
—
10
FE10
—
9
FE9
—
8
FE8
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit Framing Bit Error Counter (FE0 to FE15). These bits report either the number of Loss Of
Frame (LOF) occurrences or the number of framing bit errors received. The FECR is configured via the host by the
Frame Error Counting Control Bits (FECC0 and FECC1) in the T3E3 Control Register (Section 5.2). The possible
configurations are shown below.
FRAME ERROR COUNT REGISTER (FECR)
FECC1
FECC0
CONFIGURATION
T3 Mode: Count Loss Of Frame (LOF) Occurrences
E3 Mode: Count Loss Of Frame (LOF) Occurrences
T3 Mode: Count both F Bit and M Bit Errors
E3 Mode: Count Bit Errors in the FAS Word
T3 Mode: Count Only F Bit Errors
E3 Mode: Count Word Errors in the FAS Word
T3 Mode: Count only M Bit Errors
E3 Mode: Illegal State
0
0
1
1
0
1
0
1
When the FECR is configured to count LOF occurrences, the FECR increments by one each time the device loses
receive synchronization. When the FECR is configured to count framing bit errors, it can be configured via the
ECC control bit in the T3/E3 Control Register (Section 5.2) to either continue counting frame bit errors during a
LOF or not.
Register Name:
PCR
Register Description:
Register Address:
T3 Parity Bit Error Count Register
26h
Bit #
7
6
5
4
3
2
1
0
Name
Default
PE7
—
PE6
—
PE5
—
PE4
—
PE3
—
PE2
—
PE1
—
PE0
—
Bit #
Name
Default
15
PE15
—
14
PE14
—
13
PE13
—
12
PE12
—
11
PE11
—
10
PE10
—
9
PE9
—
8
PE8
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15:16-Bit T3 Parity Bit Error Counter (PE0 to PE15). These bits report the number of T3 parity bit
errors. In the E3 mode, this counter is meaningless and should be ignored. A parity bit error is defined as an
occurrence when the two parity bits do not match one another or when the two Parity Bits do not match the parity
calculation made on the information bits. Via the ECC control bit in the T3/E3 Control Register (Section 5.2), the
PCR can be configured to either continue counting parity bit errors during a LOF or not.
60 of 133
DS3112
Register Name:
CPCR
Register Description:
Register Address:
T3 C-Bit Parity Bit Error Count Register
28h
Bit #
Name
Default
7
6
5
4
3
2
1
0
CPE0
—
CPE7
—
CPE6
—
CPE5
—
CPE4
—
CPE3
—
CPE2
—
CPE1
—
Bit #
Name
Default
15
CPE15
—
14
CPE14
—
13
CPE13
—
12
CPE12
—
11
CPE11
—
10
CPE10
—
9
8
CPE9
—
CPE8
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit T3 C-Bit Parity Bit Error Counter (CPE0 to CPE15). These bits report the number of T3
C-bit parity bit errors. When the device is not in the C-bit parity mode or when the device is in the E3 mode, this
counter is meaningless and should be ignored. A C-bit parity bit error is defined as an occurrence when the
majority decoded three CP parity bits do not match the parity calculation made on the information bits. Via the
ECC control bit in the T3/E3 control register (Section 5.2), the CPCR can be configured to either continue counting
C-bit parity bit errors during a LOF or not.
Register Name:
FEBECR
Register Description:
Register Address:
T3 Far End Block Error or E3 RAI Count Register
2Ah
Bit #
Name
Default
7
FEBE7
—
6
FEBE6
—
5
FEBE5
—
4
FEBE4
—
3
FEBE3
—
2
FEBE2
—
1
FEBE1
—
0
FEBE0
—
Bit #
Name
Default
15
FEBE15
—
14
FEBE14
—
13
FEBE13
—
12
FEBE12
—
11
FEBE11
—
10
FEBE10
—
9
FEBE9
—
8
FEBE8
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit T3 Far End Block Error or E3 RAI Counter (FEBE0 to FEBE15). In the T3 C-bit parity
mode, these bits report the number of T3 Far End Block Errors (FEBE). This counter increments each time the
three FEBE bits do not equal 111. In the E3 Mode, these bits report the number of times the RAI bit is received in
the “disturbed state” (i.e., the number of times that it is set to a one). In the T3 mode, when the device is not in the
C-bit parity mode, this counter is meaningless and should be ignored. Via the ECC control bit in the T3/E3 control
register (Section 5.2), the FEBECR can be configured to either continue counting FEBEs or active RAI bits during
a LOF or not.
61 of 133
DS3112
6 M13/E13/G.747 MULTIPLEXER AND T2/E2/G.747 FRAME
Note that if the DS3112 is used as a stand-alone T3/E3 framer and the multiplexer functionality is
disabled, then the registers and functionality described in this section are not applicable and should be
ignored by the host.
On the receive side, the T2/E2/G.747 framer locates the frame boundaries of the incoming T2/E2/G.747
data stream and monitors the data stream for alarms and errors. Alarms are detected and reported in
T2/E2 Status Registers (T2E2SR1 and T2E2SR2), which are described in Section 6.3. The host can force
the T2/E2/G.747 framer to resynchronize via the T2E2RSY control bit in the MRID register (Section
4.1). On the transmit side, the device formats the outgoing data stream with the proper framing pattern
and overhead and can generate alarms. It can also inject errors for diagnostic testing purposes. The
transmit side of the framer is called the “formatter.”
6.1 T1/E1 AIS Generation
The DS3112 can generate an Alarm Indication Signal (AIS) for the T1 and E1 data streams in both the
transmit and receive directions. AIS for T1 and E1 signals is defined as an unframed all ones pattern. On
reset, the DS3112 will force AIS in both the transmit and receive directions on all 28 T1 and 16/21 E1
data streams. It is the host’s task to configure the device to pass normal traffic via the T1E1RAIS1,
T1E1RAIS2, T1E1TAIS1, and T1E1TAIS2 registers (Section 6.4).
6.2 T2/E2/G.747 Framer Control Register Description
Register Name:
T2E2CR1
Register Description:
Register Address:
T2/E2 Control Register 1
30h
Bit #
Name
Default
7
—
—
6
TRAI7
0
5
TRAI6
0
4
TRAI5
0
3
TRAI4
0
2
TRAI3
0
1
TRAI2
0
0
TRAI1
0
Bit #
Name
Default
15
—
—
14
TAIS7
0
13
TAIS6
0
12
TAIS5
0
11
TAIS4
0
10
TAIS3
0
9
TAIS2
0
8
TAIS1
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 6: T2/E2/G.747 Transmit Remote Alarm Indication (TRAIn where n = 1 to 7). When this bit is set
high in the T3 mode, the X bit will be set to zero. When this bit is set high in the E3 mode, the RAI bit (bit number
11 of each E2 frame) will be set to a one. In the E3 mode, TRAI5 to TRAI7 (bits 4 to 6) are disabled and should be
set low by the host. When this bit is set high in the G.747 mode, the RAI bit (bit number 1 of Set 2 in each G.747
frame) will be set to a one. When this bit it set low in the T3 mode, the X bit will be set to a one. When this bit is
set low in the E3 and G.747 modes, the RAI bit will be set to zero.
0 = do not transmit RAI
1 = transmit RAI
Bits 8 to 14:T2/E2/G.747 Transmit Alarm Indication Signal (TAISn where n = 1 to 7). When this bit is set
high, the transmit formatter will generate an unframed all ones pattern. When this bit it set low, normal data is
transmitted. In the E3 mode, TAIS5 to TAIS7 (bits 4 to 6) are disabled and should be set low by the host.
0 = do not transmit AIS
1 = transmit AIS
62 of 133
DS3112
Register Name:
T2E2CR2
Register Description:
Register Address:
T2/E2 Control Register 2
32h
Bit #
Name
Default
7
—
—
6
LOFG7
0
5
LOFG6
0
4
LOFG5
0
3
LOFG4
0
2
LOFG3
0
1
LOFG2
0
0
LOFG1
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
E2Sn4
—
10
E2Sn3
—
9
8
E2Sn2
—
E2Sn1
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 6: T2/E2/G.747 Transmit Loss Of Frame Generation (LOFGn where n = 1 to 7). A zero to one
transition on this bit will cause the T2/E2/G.747 transmit formatter to generate enough framing bit errors to cause
the far end to lose frame synchronization. This bit must be cleared and set again for a subsequent set of errors to be
generated.
MODE
FRAMING ERRORS GENERATED
T3 Mode
Four consecutive F bit errors
Four consecutive FAS words of 0000101111 generated instead of the normal FAS word,
which is 1111010000 (i.e., all FAS bits are inverted)
E3 Mode
Four consecutive FAS words of 000101111 generated instead of the normal FAS word,
which is 111010000 (i.e., all FAS bits are inverted)
G.747 Mode
Bits 8 to 11: E2 Transmit National Bit Setting (E2Snn where n = 1 to 4). These bits are ignored in the T3 and
G.747 modes. The received Sn can be read from the T2E2 Status Register 2.
0 = force the Sn bit to zero
1 = force the Sn bit to one
63 of 133
DS3112
6.3 T2/E2/G.747 Framer Status and Interrupt Register Description
Register Name:
T2E2SR1
Register Description:
Register Address:
T2/E2 Status Register 1
34h
Bit #
Name
Default
7
IELOF
0
6
LOF7
-
5
LOF6
-
4
LOF5
-
3
LOF4
-
2
LOF3
-
1
LOF2
-
0
LOF1
-
Bit #
Name
Default
15
IEAIS
0
14
AIS7
-
13
AIS6
-
12
AIS5
-
11
AIS4
-
10
AIS3
-
9
AIS2
-
8
AIS1
-
Note: See Figure 6-1 for details on the signal flow for the status bits in the T2E2SR1 register. Bits that are underlined are read-only; all
other bits are read-write.
Bits 0 to 6: Loss Of Frame Occurrence (LOFn when n = 1 to 7). This latched read-only alarm-status bit will be
set to a one each time the corresponding T2/E2/G.747 framer detects a Loss Of Frame (LOF). This bit will be
cleared when read unless a LOF condition still exists in that T2/E2/G.747 framer. A change in state of the LOF in
one or more of the T2/E2/G.747 framers can cause the T2E2SR1 status bit (in the MSR register) to be set and a
hardware interrupt to occur if the IELOF bit is set to a one and the T2E2SR1 bit in the Interrupt Mask for MSR
(IMSR) register is set to a one (Figure 6-1). The interrupt will be allowed to clear when this bit is read. The LOF
alarm criteria are described in Table 6-1, Table 6-2, and Table 6-3. In the E3 mode, LOF5 to LOF7 (bits 4 to 6) are
meaningless and should be ignored.
Bit 7: Interrupt Enable for Loss of Frame Occurrence (IELOF). This bit should be set to one if the host wishes
to have T2/E2/G.747 LOF occurrences cause a hardware interrupt or the setting of the T2E2SR1 status bit in the
MSR register (Figure 6-1). The T2E2SR1 bit in the Interrupt Mask for the Master Status Register (IMSR) must
also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
Bits 8 to 14: Alarm Indication Signal Detected (AISn when n = 1 to 7). This latched read-only alarm-status bit
will be set to a one each time the corresponding T2/E2/G.747 framer detects an incoming AIS alarm. This bit will
be cleared when read unless the AIS alarm still exists in that T2/E2/G.747 framer. A change in state of the AIS
detector in one or more of the T2/E2/G.747 framers can cause the T2E2SR1 status bit (in the MSR register) to be
set and a hardware interrupt to occur if the IEAIS bit is set to a one and the T2E2SR1 bit in the Interrupt Mask for
MSR (IMSR) register is set to a one (Figure 6-1). The interrupt will be allowed to clear when this bit is read. The
AIS alarm criteria is described in Table 6-1, Table 6-2, and Table 6-3. In the E3 mode, AIS5 to AIS7 (bits 4 to 6)
are meaningless and should be ignored.
Bit 15: Interrupt Enable for Alarm Indication Signal (IEAIS). This bit should be set to one if the host wishes to
have T2/E2/G.747 AIS detection occurrences cause a hardware interrupt or the setting of the T2E2SR1 status bit in
the MSR register (Figure 6-1). The T2E2SR1 bit in the Interrupt Mask for the Master Status Register (IMSR) must
also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
64 of 133
DS3112
Figure 6-1. T2E2SR1 Status Bit Flow
Internal LOF
Signal from
T2/E2 Framer 1
LOF1
(T2E2SR1
Bit 0)
Alarm Latch
Event
Latch
Change in State Detect
Internal LOF
Signal from
T2/E2 Framer 2
LOF2
(T2E2SR1
Bit 1)
Alarm Latch
Event
Latch
Change in State Detect
OR
Mask
IELOF
(T2E2SR1
Bit 7)
Internal LOF
Signal from
T2 Framer 7
LOF7
(T2E2SR1
Bit 6)
Alarm Latch
Event
Latch
Change in State Detect
T2E2SR1
Status Bit
(MSR Bit 5)
OR
INT*
Hardware
Signal
Mask
Internal AIS
AIS1
Signal from
T2/E2 Framer 1
(T2E2SR1
Bit 8)
Alarm Latch
T2E2SR1
(IMSR Bit 5)
Event
Latch
Change in State Detect
Internal AIS
AIS2
(T2E2SR1
Bit 9)
Signal from
T2/E2 Framer 2
Alarm Latch
Event
Latch
Change in State Detect
OR
Mask
IEAIS
(T2E2SR1
Bit 15)
Internal AIS
Signal from
T2 Framer 7
AIS7
(T2E2SR1
Bit 14)
Alarm Latch
Event
Latch
Change in State Detect
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T2E2SR1 REGISTER IS READ.
65 of 133
DS3112
Register Name:
T2E2SR2
Register Description:
Register Address:
T2/E2 Status Register 2
36h
Bit #
Name
Default
7
IERAI
0
6
5
4
3
2
1
0
RAI1
—
RAI7
—
RAI6
—
RAI5
—
RAI4
—
RAI3
—
RAI2
—
Bit #
Name
Default
15
E2SOF4
—
14
E2SOF3
—
13
E2SOF2
—
12
E2SOF1
—
11
E2Sn4
—
10
E2Sn3
—
9
8
E2Sn2
—
E2Sn1
—
Note: See Figure 6-2 for details on the signal flow for the status bits in the T2E2SR2 register. Bits that are underlined are read-only; all
other bits are read-write.
Bits 0 to 6: Remote Alarm Indication Signal Detected (RAIn when n = 1 to 7). This latched read-only alarm-
status bit will be set to a one each time the corresponding T2/E2/G.747 framer detects an incoming RAI alarm.
This bit will be cleared when read unless the RAI alarm still exists in that T2/E2/G.747 framer. A change in state of
the RAI in one or more of the T2/E2/G.747 framers can cause the T2E2SR2 status bit (in the MSR register) to be
set and a hardware interrupt to occur if the IERAI bit is set to a one and the T2E2SR2 bit in the Interrupt Mask for
MSR (IMSR) register is set to a one (Figure 6-2). The interrupt will be allowed to clear when this bit is read. The
RAI alarm criteria are described in Table 6-1, Table 6-2, and Table 6-3. In the E3 mode, RAI5 to RAI7 (bits 4 to 6)
are meaningless and should be ignored.
Bit 7: Interrupt Enable for Remote Alarm Indication Signal (IERAI). This bit should be set to one if the host
wishes to have RAI detection occurrences cause a hardware interrupt or the setting of the T2E2SR2 status bit in the
MSR register (Figure 6-2). The T2E2SR2 bit in the Interrupt Mask for the Master Status Register (IMSR) must
also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
Bits 8 to 11: E2 Receive National Bit (E2Snn when n = 1 to 4). This read-only real-time status bit reports the
incoming E2 National Bit (Sn). It is loaded at the start of each E2 frame as the Sn bit is decoded. The host can use
the E2SOF status bit to determine when to read this bit. In the T3 and G.747 modes, this bit is meaningless and
should be ignored. This bit cannot cause an interrupt to occur.
Bits 12 to 15: E2 Receive Start Of Frame (E2SOFn where n = 1 to 4). This latched read-only event-status bit
will be set to a one on each E2 receive frame boundary. This bit will be cleared when read. The setting of this
status bit cannot cause an interrupt to occur.
Figure 6-2. T2E2SR2 Status Bit Flow
Internal RAI
Signal from
T2/E2 Framer 1
RAI1
(T2E2SR2
Bit 0)
Alarm Latch
Change in State Detect
Event Latch
Internal RAI
Signal from
T2/E2 Framer 2
RAI2
(T2E2SR2
Bit 1)
Alarm Latch
Change in State Detect
Event Latch
T2E2SR2
Status Bit
(MSR Bit 6)
OR
Mask
INT*
Hardware
Signal
Mask
IERAI
(T2E2SR2
Bit 7)
Internal RAI
Signal from
T2 Framer 7
RAI7
(T2E2SR2
Bit 6)
Alarm Latch
T2E2SR2
(IMSR Bit 6)
Change in State Detect
Event Latch
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T2E2SR2 REGISTER IS READ.
66 of 133
DS3112
Table 6-1. T2 Alarm Criteria
ALARM/
DEFINITION
CONDITION
SET CRITERIA
CLEAR CRITERIA
Alarm Indication Signal
Unframed all ones
Eight or fewer zeros in four
consecutive M frames (4704
bits)
Two or more F bits in error
out of five, or two or more M
bits in error out of four
Nine or more zeros in four
consecutive M frames
(4704 bits)
AIS
LOF
RAI
Loss Of Frame
Too many F bits or M bits in
error
Remote Alarm Indication
Inactive: X = 1
Synchronization occurs
X = 0 for four consecutive M X = 1 for four consecutive
frames (4704 bits)
M frames (4704 bits)
Active: X = 0
Table 6-2. E2 Alarm Criteria
ALARM/
DEFINITION
CONDITION
SET CRITERIA
CLEAR CRITERIA
Alarm Indication Signal
Four or fewer zeros in each of Five or more zeros in each
AIS
LOF
RAI
Unframed all ones
two consecutive 848-bit
frames
Four consecutive bad FAS
of two consecutive 848-bit
frames
Three consecutive good
FAS
Loss Of Frame
Too many FAS errors
Remote Alarm Indication
Inactive: Bit 11 of the frame = 0 frames (3392 bits)
Active: Bit 11 of the frame = 1
Bit 11 = 1 for four consecutive Bit 11 = 0 for four
consecutive frames (3392
bits)
Table 6-3. G.747 Alarm Criteria
ALARM/
DEFINITION
CONDITION
SET CRITERIA
CLEAR CRITERIA
Alarm Indication Signal
Four or fewer zeros in each of Five or more zeros in each
AIS
LOF
RAI
Unframed all ones
two consecutive 840-bit
frames
Four consecutive bad FAS
of two consecutive 840-bit
frames
Three consecutive good
FAS
Bit 1 of Set 2 = 0 for four
consecutive frames (3360
bits)
Loss Of Frame
Too many FAS errors
Remote Alarm Indication
Inactive: Bit 1 of Set 2 = 0
Active: Bit 1 of Set 2 = 1
Bit 1 of Set 2 = 1 for four
consecutive frames (3360
bits)
67 of 133
DS3112
6.4 T1/E1 AIS Generation Control Register Description
Via the T1/E1 Alarm Indication Signal (AIS) Control Registers, the host can configure the DS3112 to
generate an unframed all ones signal in either the transmit or receive paths on the 28 T1 ports or the 16/21
E1 ports. On reset, the device will force AIS in both the transmit and receive paths and it is up to the host
to modify the T1/E1 AIS Generation Control Registers to allow normal T1/E1 traffic to traverse the
DS3112. See the block diagrams in Section 1 for details on where the AIS signal is injected into the data
flow. When the M13/E13 multiplexer function is disabled in the DS3112 (see the UNCHEN control bit in
the Master Control Register 1 in Section 4.2 for details), the T1/E1 AIS Generation Control Registers are
meaningless and can be set to any value.
Register Name:
T1E1RAIS1
Register Description:
Register Address:
T1/E1 Receive Path AIS Generation Control Register 1
40h
Bit #
Name
Default
7
AIS8
0
6
AIS7
0
5
AIS6
0
4
AIS5
0
3
AIS4
0
2
AIS3
0
1
AIS2
0
0
AIS1
0
Bit #
Name
Default
15
AIS16
0
14
AIS15
0
13
AIS14
0
12
AIS13
0
11
AIS12
0
10
AIS11
0
9
AIS10
0
8
AIS9
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: Receive AIS Generation Control for T1/E1 Ports 1 to 16 (AIS1 to AIS2). These bits determine
whether the device will replace the demultiplexed T1/E1 data stream with an unframed all ones AIS signal. AIS1
controls the data at LRDAT1, AIS2 controls the data at LRDAT2, and so on. Since ports 4, 8, 12, 16, 20, 24, and
28 are not active in the G.747 mode, the AIS4, AIS8, AIS12, and AIS16 bits have no affect in the G.747 mode.
0 = send AIS to the LRDAT output
1 = send normal data to the LRDAT output
Register Name:
T1E1RAIS2
Register Description:
Register Address:
T1/E1 Receive Path AIS Generation Control Register 2
42h
Bit #
Name
Default
7
AIS24
0
6
AIS23
0
5
AIS22
0
4
AIS21
0
3
AIS20
0
2
AIS19
0
1
AIS18
0
0
AIS17
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
AIS28
0
10
AIS27
0
9
AIS26
0
8
AIS25
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 11:Receive AIS Generation Control for T1 Ports 17 to 28 (AIS17 to AIS28). These bits determine
whether the device will replace the demultiplexed T1/E1 data stream with an unframed all ones AIS signal. AIS17
controls the data at LRDAT17, AIS18 controls the data at LRDAT18, and so on. Since ports 17 to 28 are not active
in the E3 mode, these bits have no effect in the E3 mode. Since ports 4, 8, 12, 16, 20, 24, and 28 are not active in
the G.747 mode, the AIS20, AIS24 and AIS28 bits have no affect in the G.747 Mode.
0 = send AIS to the LRDAT output
1 = send normal data to the LRDAT output
68 of 133
DS3112
Register Name:
T1E1TAIS1
Register Description:
Register Address:
T1/E1 Transmit Path AIS Generation Control Register 1
44h
Bit #
Name
Default
7
AIS8
0
6
AIS7
0
5
AIS6
0
4
AIS5
0
3
AIS4
0
2
AIS3
0
1
AIS2
0
0
AIS1
0
Bit #
Name
Default
15
AIS16
0
14
AIS15
0
13
AIS14
0
12
AIS13
0
11
AIS12
0
10
AIS11
0
9
AIS10
0
8
AIS9
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: Transmit AIS Generation Control for T1/E1 Ports 1 to 16 (AIS1 to AIS2). These bits determine
whether the device will replace the data input from the 28 T1 data streams or 16/21 E1 data streams with an
unframed all ones AIS signal. AIS1 controls the data from LTDAT1, AIS2 controls the data from LTDAT2, and so
on. Since ports 4, 8, 12, 16, 20, 24, and 28 are not active in the G.747 Mode, the AIS4, AIS8, AIS12, and AIS16
bits have no affect in the G.747 mode.
0 = replace data from LTDAT with AIS
1 = allow normal data from LTDAT to flow through to the multiplexer
Register Name:
T1E1TAIS2
Register Description:
Register Address:
T1/E1 Transmit Path AIS Generation Control Register 2
46h
Bit #
Name
Default
7
AIS24
0
6
AIS23
0
5
AIS22
0
4
AIS21
0
3
AIS20
0
2
AIS19
0
1
AIS18
0
0
AIS17
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
AIS28
0
10
AIS27
0
9
AIS26
0
8
AIS25
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 11: Transmit AIS Generation Control for T1 Ports 17 to 28 (AIS17 to AIS28). These bits determine
whether the device will replace the data input from the 28 T1 data streams or 16/21 E1 data streams with an
unframed all ones AIS signal. AIS17 controls the data from LTDAT17, AIS18 controls the data from LTDAT18,
and so on. Since ports 17 to 28 are not active in the E3 mode, these bits have no affect in the E3 mode. Since ports
22 to 28 are not active in the G.747 mode, these bits have no affect in the G.747 mode. Since ports 4, 8, 12, 16, 20,
24, and 28 are not active in the G.747 mode, the AIS20, AIS24, and AIS28 bits have no effect in the G.747 mode.
0 = replace data from LTDAT with AIS
1 = allow normal data from LTDAT to flow through to the multiplexer
69 of 133
DS3112
7 T1/E1 LOOPBACK AND DROP AND INSERT FUNCTIONALITY
On the T1 and E1 ports, the DS3112 has loopback capability in both directions. There is a per-port line
loopback that loops the receive side back to the transmit side and a per-port diagnostic loopback that
loops the transmit side back to the receive side. In addition, the device can detect the T1 line loopback
command as well as generate it. Also, the DS3112 has two drop and insert ports that allow any two of the
28 T1 or 16/21 E1 data streams to be dropped or inserted from two auxiliary ports. All these functions are
described below.
7.1 T1/E1 Line Loopback
Each of the 28 T1 or 16/21 E1 receive demultiplexed ports can be looped back to the transmit side. This
loopback is called a line loopback and is shown in the block diagrams in Section 1. When the line
loopback is invoked, the normal transmit data input at the LTCLK and LTDAT inputs is ignored and
replaced with the data from the associated receive port. The host invokes the line loopback via the
T1E1LLB1 and T1E1LLB2 control registers (Section 7.5).
7.2 T1/E1 Diagnostic Loopback
Each of the 28 T1 or 16/21 E1 transmit multiplexed ports can be looped back to the receive side. This
loopback is called a diagnostic loopback and is shown in the block diagrams in Section 1. When the
diagnostic loopback is invoked, the normal receive data output at the LRCLK and LRDAT outputs is
replaced with the data from the associated transmit port. The host invokes the diagnostic loopback via the
T1E1DLB1 and T1E1DLB2 control registers (Section 7.5).
7.3 T1 Line Loopback Command
M13 systems have the ability to request that a T1 line be looped back, which is achieved by inverting the
C3 bit. See Section 14.2 for details on M13 formats and operation. The DS3112 will detect when the C3
bit has been inverted and will indicate which T1 line is being requested to be placed into line loopback
via the T1LBSR1 and T1LBSR2 registers (Section 7.6). When the host detects that a T1 line is being
requested to be placed into loopback, it should set the appropriate control bit in either the T1E1LLB1 or
T1E1LLB2 register. The DS3112 can also generate a T1 line loopback command by inverting the C3 bit,
which is accomplished via the T1LBCR1 and L1LBCR2 registers (Section 7.5). Note that when E3 or
G.747 mode is enabled, the T1 line loopback command functionality is not applicable.
7.4 T1/E1 Drop and Insert
The DS3112 has the ability to drop any of the 28 T1 or 16/21 E1 receive channels to either one of two
drop ports. Drop Port A and Drop Port B consist of the outputs LRCLKA/LRDATA and
LRCLKB/LRDATB, respectively. See the block diagrams in Section 1 for more details. The host can
determine which T1/E1 port should be dropped via the T1E1SDP control register (Section 7.7). When a
T1/E1 channel is dropped to either Drop Port A or B, the demultiplexed data is still output at the normal
LRCLK and LRDAT outputs. On the transmit side, there are a complimentary pair of Insert Ports that are
controlled via the T1E1SIP control register (Section 7.7). When enabled, the inserted port data and clock
(LTDATA/LTDATB and LTCLKA/LTCLKB, respectively) replace the data that would normally be
multiplexed in at LTDAT and LTCLK inputs.
70 of 133
DS3112
7.5 T1/E1 Loopback Control Register Description
Register Name:
T1E1LLB1
Register Description:
Register Address:
T1/E1 Line Loopback Control Register 1
50h
Bit #
Name
Default
7
LLB8
0
6
LLB7
0
5
LLB6
0
4
LLB5
0
3
LLB4
0
2
LLB3
0
1
LLB2
0
0
LLB1
0
Bit #
Name
Default
15
LLB16
0
14
LLB15
0
13
LLB14
0
12
LLB13
0
11
LLB12
0
10
LLB11
0
9
LLB10
0
8
LLB9
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: T1/E1 Line Loopback Enable for Ports 1 to 16 (LLB1 to LLB16). These bits enable or disable the
T1/E1 Line Loopback (LLB). See the Block Diagrams in Section 1 for a visual description of this loopback. LLB1
corresponds to T1/E1 Port 1, LLB2 corresponds to T1/E1 Port 2, and so on. Since ports 4, 8, 12, 16, 20, 24, and 28
are not active in the G.747 mode, the LLB4, LLB8, LLB12, and LLB16 bits have no effect in the G.747 mode.
0 = disable loopback
1 = enable loopback
Register Name:
T1E1LLB2
Register Description:
Register Address:
T1/E1 Line Loopback Control Register 2
52h
Bit #
Name
Default
7
LLB24
0
6
LLB23
0
5
LLB22
0
4
LLB21
0
3
LLB20
0
2
LLB19
0
1
LLB18
0
0
LLB17
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
LLB28
0
10
LLB27
0
9
LLB26
0
8
LLB25
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 11: T1 Line Loopback Enable for Ports 17 to 28 (LLB17 to LLB28). These bits enable or disable the
T1 Line Loopback (LLB). See the block diagrams in Section 1 for a visual description of this loopback. LLB1
corresponds to T17 Port 17, LLB18 corresponds to T1 Port 18, and so on. Since ports 17 to 28 are not active in the
E3 mode, these bits have no effect in the E3 mode. Since ports 4, 8, 12, 16, 20, 24, and 28 are not active in the
G.747 mode, the LLB20, LLB24, and LLB28 bits have no effect in the G.747 mode.
0 = disable loopback
1 = enable loopback
71 of 133
DS3112
Register Name:
T1E1DLB1
Register Description:
Register Address:
T1/E1 Diagnostic Loopback Control Register 1
54h
Bit #
Name
Default
7
DLB8
0
6
DLB7
0
5
DLB6
0
4
DLB5
0
3
DLB4
0
2
DLB3
0
1
DLB2
0
0
DLB1
0
Bit #
Name
Default
15
DLB16
0
14
DLB15
0
13
DLB14
0
12
DLB13
0
11
DLB12
0
10
DLB11
0
9
DLB10
0
8
DLB9
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: T1/E1 Diagnostic Loopback Enable for Ports 1 to 16 (DLB1 to DLB16). These bits enable or
disable the T1/E1 Diagnostic Loopback (DLB). See the block diagrams in Section 1 for a visual description of this
loopback. DLB1 corresponds to T1/E1 Port 1, DLB2 corresponds to T1/E1 Port 2, and so on. If the device is
configured in Low-Speed T1/E1 Port Loop Timed mode (if LLTM bit in the MC1 register is set to a one) then only
data will be looped back—the clock will not be looped back. Since ports 4, 8, 12, 16, 20, 24, and 28 are not active
in the G.747 mode, the DLB4, DLB8, DLB12, and DLB16 bits have no effect in the G.747 mode.
0 = disable loopback
1 = enable loopback
Register Name:
T1E1DLB2
Register Description:
Register Address:
T1/E1 Diagnostic Loopback Control Register 2
56h
Bit #
Name
Default
7
DLB24
0
6
DLB23
0
5
DLB22
0
4
DLB21
0
3
DLB20
0
2
DLB19
0
1
DLB18
0
0
DLB17
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
DLB28
0
10
DLB27
0
9
DLB26
0
8
DLB25
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 17 to 28: T1 Diagnostic Loopback Enable for Ports 17 to 28 (DLB17 to DLB28). These bits enable or
disable the T1 Diagnostic Loopback (DLB). See the block diagrams in Section 1 for a visual description of this
loopback. DLB1 corresponds to T17 Port 17, DLB18 corresponds to T1 Port 18, and so on. Since ports 17 to 28 are
not active in the E3 mode, these bits have no effect in the E3 mode. Since ports 4, 8, 12, 16, 20, 24, and 28 are not
active in the G.747 Mode, the DLB20, DLB24 and DLB28 bits have no affect in the G.747 mode. If the device is
configured in Low-Speed T1/E1 Port Loop Timed mode (if LLTM bit in the MC1 register is set to a one), then
only data will be looped back, the clock will not be looped back.
0 = disable loopback
1 = enable loopback
72 of 133
DS3112
Register Name:
T1LBCR1
Register Description:
Register Address:
T1 Line Loopback Command Register 1
58h
Bit #
Name
Default
7
LB8
0
6
LB7
0
5
LB6
0
4
LB5
0
3
LB4
0
2
LB3
0
1
LB2
0
0
LB1
0
Bit #
Name
Default
15
LB16
0
14
LB15
0
13
LB14
0
12
LB13
0
11
LB12
0
10
LB11
0
9
LB10
0
8
LB9
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: T1 Line Loopback Far End Activate Command for Ports 1 to 16 (LB1 to LB16). These bits cause
the appropriate T2 transmit formatter to generate a Line Loopback command for the far end. When this bit is set
high, the T2 transmit formatter will force the C3 bit to be the inverse of the C1 and C2 bits. The T2 transmit
formatter will continue to force the C3 bit to be the inverse of the C1 and C2 bits as long as this bit is held high.
When this bit is set low, C3 will match the C1 and C2 bits. LB1 corresponds to T1/E1 Port 1, LB2 corresponds to
T1/E1 Port 2, and so on. These bits are meaningless in the E3 and G.747 modes and should be set to 0.
0 = do not generate the line loopback command by inverting the C3 bit
1 = generate the line loopback command by inverting the C3 bit
73 of 133
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Register Name:
T1LBCR2
Register Description:
Register Address:
T1 Line Loopback Command Register 2
5Ah
Bit #
Name
Default
7
LB24
0
6
LB23
0
5
LB22
0
4
LB21
0
3
LB20
0
2
LB19
0
1
LB18
0
0
LB17
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
LB28
0
10
LB27
0
9
LB26
0
8
LB25
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 17 to 28: T1 Line Loopback Far End Activate Command for Ports 17 to 28 (LB17 to LB28). These bits
cause the appropriate T2 transmit formatter to generate a Line Loopback command for the far end. When this bit is
set high, the T2 transmit formatter will force the C3 bit to be the inverse of the C1 and C2 bits. The T2 transmit
formatter will continue to force the C3 bit to be the inverse of the C1 and C2 bits as long as this bit is held high.
When this bit is set low, C3 will match the C1 and C2 bits. LB17 corresponds to T1/E1 Port 17, L18 corresponds to
T1/E1 Port 18, and so on. These bits are meaningless in the E3 and G.747 modes and should be set to 0.
0 = do not generate the line loopback command by inverting the C3 bit
1 = generate the line loopback command by inverting the C3 bit
74 of 133
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7.6 T1 Line Loopback Command Status Register Description
Register Name:
T1LBSR1
Register Description:
Register Address:
T1 Line Loopback Command Status Register 1
5Ch
Bit #
Name
Default
7
6
5
4
3
2
1
0
LLB1
—
LLB8
—
LLB7
—
LLB6
—
LLB5
—
LLB4
—
LLB3
—
LLB2
—
Bit #
Name
Default
15
LLB16
—
14
LLB15
—
13
LLB14
—
12
LLB13
—
11
LLB12
—
10
LLB11
—
9
LLB10
—
8
LLB9
—
Note: See Figure 7-1 for details on the signal flow for the status bits in the T1LBSR1 and T1LBSR2 registers. Bits that are underlined are
read-only; all other bits are read-write.
Bits 0 to 15: T1 Line Loopback Command Status for Ports 1 to 16 (LLB1 to LLB16). These read-only real-
time status bits will be set to a one when the corresponding T2 framer detects that the C3 bit is the inverse of the
C1 and C2 bits for 5 consecutive frames. These bits will be allowed to clear when the C3 bit is not the inverse of
the C1 and C2 bits for five consecutive frames. LLB1 corresponds to T1/E1 Port 1, LLB2 corresponds to T1/E1
Port 2, and so on. The setting of any of the bits in T1LBSR1 or T1LBSR2 can cause a hardware interrupt to occur
if the T1LB bit in the Interrupt Mask for MSR (IMSR) is set to a one. In the E3 and G.747 modes, these bits are
meaningless and should be ignored.
Register Name:
T1LBSR2
Register Description:
Register Address:
T1 Line Loopback Command Status Register 2
5Eh
Bit #
Name
Default
7
LLB24
—
6
LLB23
—
5
LLB22
—
4
LLB21
—
3
LLB20
—
2
LLB19
—
1
LLB18
—
0
LLB17
—
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
LLB28
—
10
LLB27
—
9
LLB26
—
8
LLB25
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 11: T1 Line Loopback Command Status for Ports 17 to 28 (LLB17 to LLB28). These read-only real-
time status bits will be set to a one when the corresponding T2 framer detects that the C3 bit is the inverse of the
C1 and C2 bits for 5 consecutive frames. These bits will be allowed to clear when the C3 bit is not the inverse of
the C1 and C2 bits for five consecutive frames. LLB17 corresponds to T1/E1 Port 17, LLB18 corresponds to T1/E1
Port 18, and so on. The setting of any of the bits in T1LBSR1 or T1LBSR2 can cause a hardware interrupt to occur
if the T1LB bit in the Interrupt Mask for MSR (IMSR) is set to a one. In the E3 and G.747 Modes, these bits are
meaningless and should be ignored.
75 of 133
DS3112
Figure 7-1. T1LBSR1 and T1LBSR2 Status Bit Flow
LLB1
(T1LBSR1
Bit 0)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
LLB2
(T1LBSR1
Bit 1)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
T1LB
Status Bit
(MSR Bit 8)
OR
INT*
Hardware
Signal
Mask
LLB28
(T1LBSR2
Bit 11)
Internal T1
Loopback Command
Signal from
T1LB
(IMSR Bit 8)
T2/E2 Framer
7.7 T1/E1 Drop and Insert Control Register Description
Register Name:
T1E1SDP
Register Description:
Register Address:
T1/E1 Select Register for Receive Drop Ports A and B
60h
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
DPAS4
0
3
DPAS3
0
2
DPAS2
0
1
0
DPAS0
DPAS1
0
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
DPBS4
0
11
DPBS3
0
10
DPBS2
0
9
DPBS1
0
8
DPBS0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 4: T1/E1 Drop Port A Select Bits (DPAS0 to DPAS4).
Bits 8 to 12: T1/E1 Drop Port B Select Bits (DPBS0 to DPBS4).
These bits select which of the 28 T1 ports or 16 E1 ports (if any) should be output at either Drop Port A or Drop
Port B. If no port is selected, the LRDATA, LRCLKA, LRDATB, and LRCLKB output pins will be forced low.
DPxS4:0
00000 No Port
00001 Port 1
00010 Port 2
00011 Port 3
00100 Port 4
00101 Port 5
00110 Port 6
00111 Port 7
01000 Port 8
01001 Port 9
01010 Port 10
01011 Port 11
01100 Port 12
01101 Port 13
01110 Port 14
01111 Port 15
10000 Port 16
10001 Port 17
10010 Port 18
10011 Port 19
10100 Port 20
10101 Port 21
10110 Port 22
10111 Port 23
11000 Port 24
11001 Port 25
11010 Port 26
11011 Port 27
11100 Port 28
11101 No Port
11110 No Port
11111 No Port
76 of 133
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Register Name:
T1E1SIP
Register Description:
Register Address:
T1/E1 Select Register for Transmit Insert Ports A and B
62h
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
IPAS4
0
3
IPAS3
0
2
IPAS2
0
1
IPAS1
0
0
IPAS0
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
IPBS4
0
11
IPBS3
0
10
IPBS2
0
9
IPBS1
0
8
IPBS0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 4: T1/E1 Insert Port A Select Bits (IPAS0 to IPAS4).
Bits 8 to 12: T1/E1 Insert Port B Select Bits (IPBS0 to IPBS4).
These bits select if clock and data from either of the two insert ports (Insert Port A or Insert Port B) should replace
the clock and data presented at one of the 28 T1 ports or 16/21 E1 ports. If no port is selected, the clock and data
presented at the LTDATA, LTCLKA, LTDATB, and LTCLKB input pins is ignored. The same port should not be
selected for both Insert Port A and Insert Port B.
IPxS4:0
00000 No Port
00001 Port 1
00010 Port 2
00011 Port 3
00100 Port 4
00101 Port 5
00110 Port 6
00111 Port 7
01000 Port 8
01001 Port 9
01010 Port 10
01011 Port 11
01100 Port 12
01101 Port 13
01110 Port 14
01111 Port 15
10000 Port 16
10001 Port 17
10010 Port 18
10011 Port 19
10100 Port 20
10101 Port 21
10110 Port 22
10111 Port 23
11000 Port 24
11001 Port 25
11010 Port 26
11011 Port 27
11100 Port 28
11101 No Port
11110 No Port
11111 No Port
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8 BERT
The BERT block can generate and detect the following patterns:
•
•
•
Pseudorandom patterns 27 - 1, 211 - 1, 215 - 1, and QRSS
A repetitive pattern from 1 to 32 bits in length
Alternating (16-bit) words that flip every 1 to 256 words
The BERT receiver has a 32-bit bit counter and a 24-bit error counter. It can generate interrupts on
detecting a bit error, a change in synchronization, or if an overflow occurs in the bit and error counters.
See Section 8.1 for details on status bits and interrupts from the BERT block. To activate the BERT
block, the host must configure the BERT mux via the BERT mux control register (Section 8.1). Data can
be routed to the receive side of the BERT from either the T3/E3 framer or from one of the 28 T1 or 16/21
E1 receive ports. Data from the transmit side of the BERT can be inserted either into the T3/E3 framer or
into one of the 28 T1 or 16/21 E1 transmit ports. See Figure 1-1 and Figure 1-2 for a visual description of
where data to and from the BERT can be placed.
8.1 BERT Register Description
Register Name:
BERTMC
Register Description:
Register Address:
BERT Mux Control Register
0x6Eh
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
RBPS4
0
3
RBPS3
0
2
RBPS2
0
1
RBPS1
0
0
RBPS0
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
TBPS4
0
11
TBPS3
0
10
TBPS2
0
9
TBPS1
0
8
TBPS0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 4: Receive BERT Port Select Bits 0 to 4 (RBPS0 to RBPS4). These bits determine if data from any of
the 28 T1 or 16/21 E1 receive ports or the T3/E3 receive framer (with or without the overhead bits) will be routed
to the receive side of the BERT. If these bits are set to 11101, only the T3/E3 payload data will be routed to the
receive BERT. If these bits are set to 11110, all T3/E3 data (payload and the overhead bits) will be routed to the
receive BERT.
RBPS4:0
00000 No Data
00001 Port 1
00010 Port 2
00011 Port 3
00100 Port 4
00101 Port 5
00110 Port 6
00111 Port 7
10000 Port 16
10001 Port 17
10010 Port 18
10011 Port 19
10100 Port 20
10101 Port 21
10110 Port 22
10111 Port 23
01000 Port 8
01001 Port 9
01010 Port 10
01011 Port 11
01100 Port 12
01101 Port 13
01110 Port 14
01111 Port 15
11000 Port 24
11001 Port 25
11010 Port 26
11011 Port 27
11100 Port 28
11101 T3/E3 Framer (payload bits only)
11110 T3/E3 Framer (payload + overhead bits)
11111 Illegal State
78 of 133
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Bits 8 to 12: Transmit BERT Port Select Bits 0 to 4 (TBPS0 to TBPS4). These bits determine if the transmit
BERT will be used to replace the normal transmit data on any of the 28 T1 or 16/21 E1 transmit ports or at the
T3/E3 transmit formatter. If these bits are set to 11101, data from the transmit BERT is only placed in the payload
bit positions of the T3/E3 data stream. If these bits are set to 11110, then data from the transmit BERT is placed
into all bit positions of the T3/E3 data stream (payload and the overhead bits).
TBPS4:0
00000 No Data
00001 Port 1
00010 Port 2
00011 Port 3
00100 Port 4
00101 Port 5
00110 Port 6
00111 Port 7
10000 Port 16
10001 Port 17
10010 Port 18
10011 Port 19
10100 Port 20
10101 Port 21
10110 Port 22
10111 Port 23
01000 Port 8
01001 Port 9
01010 Port 10
01011 Port 11
01100 Port 12
01101 Port 13
01110 Port 14
01111 Port 15
11000 Port 24
11001 Port 25
11010 Port 26
11011 Port 27
11100 Port 28
11101 T3/E3 Framer (payload bits only)
11110 T3/E3 Framer (payload + overhead bits)
11111 Illegal State
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Register Name:
BERTC0
Register Description:
Register Address:
BERT Control Register 0
70h
Bit #
Name
Default
7
PBS
0
6
TINV
0
5
RINV
0
4
PS2
0
3
PS1
0
2
PS0
0
1
LC
0
0
RESYNC
0
Bit #
Name
Default
15
IESYNC
0
14
IEBED
0
13
IEOF
0
12
n/a
-
11
RPL3
0
10
RPL2
0
9
RPL1
0
8
RPL0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Force Resynchronization (RESYNC). A low to high transition will force the receive BERT synchronizer
to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host
wishes to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent
resynchronization.
Bit 1: Load Bit and Error Counters (LC). A low to high transition latches the current bit and error counts into
the host accessible registers BERTBC and BERTEC and clears the internal count. This bit should be toggled from
low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for a
subsequent loads.
Bits 2 to 4: Pattern Select Bits 0 (PS0 to PS2).
If PBS = 0:
000 = Pseudorandom Pattern 27 - 1 (ANSI T1.403-1999 Annex B)
001 = Pseudorandom Pattern 211 - 1 (ITU O.153)
010 = Pseudorandom Pattern 215 - 1 (ITU O.151)
011 = Pseudorandom Pattern QRSS (2E20 - 1 with a one forced if the next 14 positions are zero)
100 = Repetitive Pattern
101 = Alternating Word Pattern
110 = Illegal State
111 = Illegal State
If PBS = 1:
000 = Psuedorandom Pattern 29 - 1
001 = Pseudorandom Pattern 220 - 1 (non-QRSS)
010 = Pseudorandom Pattern 223 - 1 (ITU O.151)
011 = Illegal State
10X = Illegal State (X = 0 or 1)
11X = lllegal State (X = 0 or 1)
Bit 5: Receive Invert Data Enable (RINV).
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bit 6: Transmit Invert Data Enable (TINV).
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
Bit 7: Pattern Bank Select (PBS)
0 = PS[2:0] select a pattern from Pattern Bank 0
1 = PS[2:0] select a pattern from Pattern Bank 1
80 of 133
DS3112
Bits 8 to 11: Repetitive Pattern Length Bits 5 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is the MSB of a
nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are
ignored if the receive BERT is programmed for a pseudorandom pattern. To create repetitive patterns less than 17
bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32.
For example, to create a 6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101).
Repetitive Pattern Length Map
Length
17 Bits
21 Bits
25 Bits
29 Bits
Code
0000
0100
1000
1100
Length Code
Length Code
Length Code
18 Bits
22 Bits
26 Bits
30 Bits
0001
0101
1001
1101
19 Bits
23 Bits
27 Bits
31 Bits
0010
0110
1010
1101
20 Bits
24 Bits
28 Bits
32 Bits
0011
0111
1011
1111
Bit 13: Interrupt Enable for Counter Overflow (IEOF). Allows the receive BERT to cause an interrupt if either
the Bit Counter or the Error Counter overflows (Figure 8-1).
0 = interrupt masked
1 = interrupt enabled
Bit 14: Interrupt Enable for Bit Error Detected (IEBED). Allows the receive BERT to cause an interrupt if a bit
error is detected (Figure 8-1).
0 = interrupt masked
1 = interrupt enabled
Bit 15: Interrupt Enable for Change of Synchronization Status (IESYNC). Allows the receive BERT to cause
an interrupt if there is a change of state in the synchronization status (i.e., the receive BERT either goes into or out
of synchronization) (Figure 8-1).
0 = interrupt masked
1 = interrupt enabled
81 of 133
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Register Name:
BERTC1
Register Description:
Register Address:
BERT Control Register 1
72h
Bit #
Name
Default
7
6
EIB1
0
5
EIB0
0
4
SBE
0
3
—
0
2
—
0
1
—
0
0
TC
0
EIB2
—
Bit #
Name
Default
15
AWC7
0
14
AWC6
0
13
AWC5
0
12
AWC4
0
11
AWC3
0
10
AWC2
0
9
AWC1
0
8
AWC0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Transmit Pattern Load (TC). A low to high transition loads the pattern generator with Repetitive or
Pseudorandom pattern that is to be generated. This bit should be toggled from low to high whenever the host
wishes to load a new pattern. Must be cleared and set again for a subsequent loads.
Bit 4: Single Bit Error Insert (SBE). A low to high transition will create a single bit error. Must be cleared and
set again for a subsequent bit error to be inserted.
Bits 5 to 7: Error Insert Bits (EIB0 to EIB2). Will automatically insert bit errors at the prescribed rate into the
generated data pattern. Useful for verifying error detection operation.
EIB2
EIB1
EIB0
ERROR RATE INSERTED
No errors automatically inserted
10-1 (1 error per 10 bits)
10-2 (1 error per 100 bits)
10-3 (1 error per 1kbits)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10-4 (1 error per 10kbits)
10-5 (1 error per 100kbits)
10-6 (1 error per 1Mbits)
10-7 (1 error per 10Mbits)
Bits 8 to 15: Alternating Word Count Rate (AWC0 to AWC7). When the BERT is programmed in the
alternating word mode, the word in BERTRP0 will be transmitted for the count loaded into this register plus one,
then flip to the other word loaded in BERTRP1 and again repeat for the same number of times. The valid count
range is from 00h to FFh.
AWC VALUE
ALTERNATING COUNT ACTION
00h
01h
02h
06h
07h
FFh
Send the word in BERTRP0 1 time followed by the word in BERTRP1 1 time…
Send the word in BERTRP0 2 times followed by the word in BERTRP1 2 times…
Send the word in BERTRP0 3 times followed by the word in BERTRP1 3 times…
Send the word in BERTRP0 7 times followed by the word in BERTRP1 7 times…
Send the word in BERTRP0 8 times followed by the word in BERTRP1 8 times…
Send the word in BERTRP0 256 times followed by the word in BERTRP1 256 times…
82 of 133
DS3112
Register Name:
BERTRP0
Register Description:
Register Address:
BERT Repetitive Pattern 0 (lower word)
74h
Bit #
Name
Default
7
RP7
0
6
RP6
0
5
RP5
0
4
RP4
0
3
RP3
0
2
RP2
0
1
RP1
0
0
RP0
0
Bit #
Name
Default
15
RP15
0
14
RP14
0
13
RP13
0
12
RP12
0
11
RP11
0
10
RP10
0
9
RP9
0
8
RP8
0
Register Name:
BERTRP1
Register Description:
Register Address:
BERT Repetitive Pattern 1 (upper word)
76h
Bit #
Name
Default
7
RP23
0
6
RP22
0
5
RP21
0
4
RP20
0
3
RP19
0
2
RP18
0
1
RP17
0
0
RP16
0
Bit #
Name
Default
15
RP31
0
14
RP30
0
13
RP29
0
12
RP28
0
11
RP27
0
10
RP26
0
9
RP25
0
8
RP24
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 31: BERT Repetitive Pattern Set (RP0 to RP31). RP0 is the LSB and RP31 is the MSB. These registers
must be properly loaded for the BERT to properly generate and synchronize to either a repetitive pattern, a
pseudorandom pattern, or a alternating word pattern. For a repetitive pattern that is less than 17 bits, then the
pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern was the
repeating 5-bit pattern …01101… (where rightmost bit is one sent first and received first) then BERTRP0 should
be loaded with xB5AD and BERTRP1 should be loaded with x5AD6. For a pseudorandom pattern, both registers
should be loaded with all ones (i.e., xFFFF). For an alternating word pattern, one word should be placed into
BERTRP0 and the other word should be placed into BERTRP1. For example, if the DDS stress pattern “7E” is to
be described, the user would place x0000 in BERTRP0 and x7E7E in BERTRP1 and the alternating word counter
would be set to 50 (decimal) to allow 100 bytes of 00h followed by 100 bytes of 7Eh to be sent and received.
83 of 133
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Register Name:
BERTBC0
Register Description:
Register Address:
BERT 32-Bit Bit Counter (lower word)
78h
Bit #
Name
Default
7
BBC7
0
6
BBC6
0
5
BBC5
0
4
BBC4
0
3
BBC3
0
2
BBC2
0
1
BBC1
0
0
BBC0
0
Bit #
Name
Default
15
BBC15
0
14
BBC14
0
13
BBC13
0
12
BBC12
0
11
BBC11
0
10
BBC10
0
9
BBC9
0
8
BBC8
0
Register Name:
BERTBC1
Register Description:
Register Address:
BERT 32-Bit Bit Counter (upper word)
7Ah
Bit #
Name
Default
7
BBC23
0
6
BBC22
0
5
BBC21
0
4
BBC20
0
3
BBC19
0
2
BBC18
0
1
BBC17
0
0
BBC16
0
Bit #
Name
Default
15
BBC31
0
14
BBC30
0
13
BBC29
0
12
BBC28
0
11
BBC27
0
10
BBC26
0
9
BBC25
0
8
BBC24
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 31: BERT 32-Bit Bit Counter (BBC0 to BBC31). This 32-bit counter will increment for each data bit
(i.e., clock received). This counter is not disabled when the receive BERT loses synchronization. This counter can
be cleared by toggling the LC control bit in BERTC0. This counter saturates and will not rollover. Upon saturation,
the BBCO status bit in the BERTEC0 register will be set. This error counter starts counting when the BERT goes
into receive synchronization (RLOS = 0 or SYNC = 1) and it will not stop counting when the BERT loses
synchronization. It is recommended that the host toggle the LC bit in BERTC0 register once the BERT has
synchronized and then toggle the LC bit again when the error-checking period is complete. If the device loses
synchronization during this period, then the counting results are suspect.
84 of 133
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Register Name:
BERTEC0
Register Description:
Register Address:
BERT 24-Bit Error Counter (lower) and Status Information
7Ch
Bit #
Name
Default
7
—
—
6
RA1
—
5
RA0
—
4
3
2
1
0
SYNC
—
RLOS
—
BED
—
BBCO
—
BECO
—
Bit #
Name
Default
15
BEC7
0
14
BEC6
0
13
BEC5
0
12
BEC4
0
11
BEC3
0
10
BEC2
0
9
BEC1
0
8
BEC0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Real-Time Synchronization Status (SYNC). Read-only real-time status of the synchronizer (this bit is not
latched). Will be set when the incoming pattern matches for 32 consecutive bit positions. Will be cleared when six
or more bits out of 64 are received in error.
Bit 1: BERT Error Counter Overflow (BECO). A latched read-only event-status bit that is set when the 24-bit
BERT Error Counter (BEC) saturates. Cleared when read and will not be set again until another overflow occurs
(i.e., the BEC counter must be cleared and allowed to overflow again). The setting of this status bit can cause a
hardware interrupt to occur if the IEOF bit in BERT Control Register 0 is set to a one and the BERT bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read
(Figure 8-1).
Bit 2: BERT Bit Counter Overflow (BBCO). A latched read-only event-status bit that is set when the 32-bit
BERT Bit Counter (BBC) saturates. Cleared when read and will not be set again until another overflow occurs (i.e.,
the BBC counter must be cleared and allowed to overflow again). The setting of this status bit can cause a
hardware interrupt to occur if the IEOF bit in BERT Control Register 0 is set to a one and the BERT bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read
(Figure 8-1).
Bit 3: Bit Error Detected (BED). A latched read-only event status bit that is set when a bit error is detected. The
receive BERT must be in synchronization for it to detect bit errors. This bit will be cleared when read. The setting
of this status bit can cause a hardware interrupt to occur if the IEBED bit in BERT Control Register 0 is set to a one
and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to
clear when this bit is read (Figure 8-1).
Bit 4: Receive Loss Of Synchronization (RLOS). A latched read-only alarm-status bit that is set whenever the
receive BERT begins searching for a pattern. Once synchronization is achieved, this bit will remain set until read.
A change in this status bit (i.e., the synchronizer goes into or out of synchronization) can cause a hardware interrupt
to occur if the IESYNC bit in BERT Control Register 0 is set to a one and the BERT bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read (Figure 8-1).
Bit 5: Receive All Zeros (RA0). A latched read-only alarm-status bit that is set when 31 consecutive zeros are
received. Allowed to be cleared once a one is received.
Bit 6: Receive All Ones (RA1). A latched read-only alarm-status bit that is set when 31 consecutive ones are
received. Allowed to be cleared once a zero is received.
Bits 8 to 15: BERT 24-Bit Error Counter (BEC0 to BEC7). Lower byte of the 24-bit counter. See the
BERTEC1 register description for details.
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Figure 8-1. BERT Status Bit Flow
Internal RLOS
Signal from
BERT
RLOS
(BERTEC0
Bit 4)
Alarm Latch
Change in State Detect
IESYNC (BERTC0 Bit 15)
Event Latch
Mask
BED
(BERTEC0
Bit 3)
Internal Bit
Error Detected
Signal from
BERT
Event Latch
BERT
Mask
Mask
Status Bit
(MSR Bit 2)
OR
IEBED (BERTC0 Bit 14)
INT*
Hardware
Signal
BECO or BBCO
(BERTEC0
Bits 1 & 2)
Internal Counter
Overflow
Signal from
BERT
Mask
Event Latch
BERT
(IMSR Bit 2)
IEOF (BERTC0 Bit 13)
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE BERTEC0 REGISTER IS READ.
Register Name:
BERTEC1
Register Description:
Register Address:
BERT 24-Bit Error Counter (upper)
7Eh
Bit #
Name
Default
7
BEC15
0
6
BEC14
0
5
BEC13
0
4
BEC12
0
3
BEC11
0
2
BEC10
0
1
0
BEC8
BEC9
0
0
Bit #
Name
Default
15
BEC23
0
14
BEC22
0
13
BEC21
0
12
BEC20
0
11
BEC19
0
10
BEC18
0
9
BEC17
0
8
BEC16
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: BERT 24-Bit Error Counter (BEC8 to BEC23). Upper two bytes of the 24-bit counter. This 24-bit
counter will increment for each data bit received in error. This counter is not disabled when the receive BERT loses
synchronization. This counter can be cleared by toggling the LC control bit in BERTBC0. This counter saturates
and will not rollover. Upon saturation, the BECO status bit in the BERTEC0 register will be set. This error counter
starts counting when the BERT goes into receive synchronization (RLOS = 0 or SYNC = 1) and it will not stop
counting when the BERT loses synchronization. It is recommended that the host toggle the LC bit in BERTC0
register once the BERT has synchronized and then toggle the LC bit again when the error checking period is
complete. If the device loses synchronization during this period, then the counting results are suspect.
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9 HDLC CONTROLLER
The DS3112 contains an on-board HDLC controller with 256-byte buffers in both the transmit and
receive paths. When the device is operated in the T3 mode, the HDLC controller is only active in the C-
Bit Parity mode. When the device is operated in the E3 mode, the user has the option to connect the
HDLC controller to the Sn bit position. On the receive side, the HDLC controller is always connected to
the receive E3 framer. If the host does not wish to use the HDLC controller for the Sn bit, then the status
updates provided by the HDLC controller are ignored. On the transmit side, the host selects the source of
the Sn via the E3SnC0 and E3SnC1 controls bits in the T3/E3 Control Register (Section 5.2).
9.1 Receive Operation
On reset, the receive HDLC controller will flush the receive FIFO and begin searching for a new
incoming HDLC packet. The receive HDLC controller performs a bit by bit search for a HDLC packet
and when one is detected, it will zero destuff the incoming data stream and automatically byte align to it
and place the incoming bytes as they are received into the receive FIFO. The first byte of each packet is
marked in the receive FIFO by setting the Opening Byte (OBYTE) bit. Upon detecting a closing flag, the
device will check the 16-bit CRC to see if the packet is valid or not and then mark the last byte of the
packet in the receive FIFO by setting the Closing Byte (CBYTE) bit. The CRC is not passed to the
receive FIFO. When the CBYTE bit is set, the host can obtain the status of the incoming packet via the
Packet Status bits (PS0 and PS1). Incoming packets can be separated by a single flag or even by two flags
that share a common zero. If the receive FIFO ever fills beyond capacity, the new incoming packet data
will be discarded and the Receive FIFO Overrun (ROVR) status bit will be set. If such a scenario occurs,
then the last packet in the FIFO is suspect and should be discarded. When an overflow occurs, the receive
HDLC will stop accepting packets until either the FIFO is completely emptied or reset. If the receive
HDLC controller ever detects an incoming abort (seven or more ones in a row), it will set the Receive
Abort Sequence Detected (RABT) status bit. If an abort sequence is detected in the middle of an
incoming packet, then the receive HDLC controller will set the Packet Status bits accordingly.
The receive HDLC has been designed to minimize its real-time host support requirements. The receive
FIFO is 256 bytes, which is deep enough to store the three T3 packets (Path ID, Idle Signal ID, and Test
Signal ID) that can arrive once a second. Hence in T3 applications, the host only needs to access the
receive HDLC once a second to retrieve the three messages. The host will be notified when a new
message has begun (Receive Packet Start status bit) to be received and when a packet has completed
(Receive Packet End status bit). Also, the host can be notified when the FIFO has filled beyond a
programmable level called the high watermark. The host will read the incoming packet data out of the
receive FIFO a byte at a time. When the receive FIFO is empty, the REMPTY bit in the FIFO will be set.
9.2 Transmit Operation
On reset, the transmit HDLC controller will flush the transmit FIFO and transmit an abort followed by
either 7Eh or FFh (depends on the setting of the TFS control bit) continuously. The transmit HDLC then
waits until there are at least two bytes in the transmit FIFO before beginning to send the packet. The
transmit HDLC will automatically add an opening flag of 7Eh to the beginning of the packet and zero
stuff the outgoing data stream. When the transmit HDLC controller detects that the TMEND bit in the
transmit FIFO is set, it will automatically calculate and add in the 16-bit CRC checksum followed by a
closing flag of 7Eh. If the FIFO is empty, then it will begin sending either 7Eh or FFh continuously. If
there is some more data in the FIFO, then the transmit HDLC will automatically add in the opening flag
and begin sending the next packet. Between consecutive packets, there are always at least two flags of
7Eh. If the transmit FIFO ever empties when a packet is being sent (i.e., before the TMEND bit is set),
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then the transmit HDLC controller will send an abort of seven ones in a row (FEh) followed by a
continuous transmission of either 7Eh (flags) or FFh (idle) and the Transmit FIFO Underrun (TUDR)
status bit will be set. When the FIFO underruns, the transmit HDLC controller should be reset by the host.
The transmit HDLC has been designed to minimize its real-time host support requirements. The transmit
FIFO is 256 bytes, which is deep enough to store the three T3 packets (Path ID, Idle Signal ID, and Test
Signal ID) that need to be sent once a second. Hence in T3 applications, the host only needs to access the
transmit HDLC once a second to load up the three messages. Once the host has loaded an outgoing
packet, it can monitor the Transmit Packet End (TEND) status bit to know when the packet has finished
being transmitted. Also, the host can be notified when the FIFO has emptied below a programmable level
called the low watermark. The host must never overfill the FIFO. To keep this from occurring, the host
can obtain the real-time depth of the transmit FIFO via the Transmit FIFO Level bits in the HDLC Status
Register (HSR).
9.2 HDLC Control and FIFO Register Description
Register Name:
HCR
Register Description:
Register Address:
HDLC Control Register
80h
Bit #
Name
Default
7
—
—
6
RHR
0
5
THR
0
4
TFS
0
3
—
—
2
TCRCI
—
1
TZSD
0
0
TCRCD
0
Bit #
Name
Default
15
14
13
12
11
10
9
RID
0
8
TID
0
RHWMS2 RHWMS1 RHWMS0
TLWMS2 TLWMS1 TLWMS0
0
0
0
0
0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Transmit CRC Defeat (TCRCD). When this bit is set low, the HDLC will automatically calculate and
append the 16-bit CRC to the outgoing HDLC message. When this bit is set high, the device will not append the
CRC to the outgoing message.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
Bit 1: Transmit Zero Stuffer Defeat (TZSD). When this bit is set low, the HDLC will automatically enable the
zero stuffer in between the opening and closing flags of the HDLC message. When this bit is set high, the device
will not enable the zero stuffer under any condition.
0 = enable zero stuffer (normal operation)
1 = disable zero stuffer
Bit 2: Transmit CRC Invert (TCRCI). When this bit is set low, the HDLC will allow the CRC to be generated
normally. When this bit is set high, the device will invert all 16 bits of the generated CRC. This bit is ignored when
the CRC generation is disabled (TCRCD = 1). This bit is useful in testing HDLC operation.
0 = do not invert the generated CRC (normal operation)
1 = Invert the generated CRC
Bit 4: Transmit Flag/Idle Select (TFS). This control bit determines whether flags or idle bytes will be transmitted
in between packets.
0 = 7Eh (flags)
1 = FFh (idle)
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Bit 5: Transmit HDLC Reset (THR). A zero to one transition will reset the Transmit HDLC controller. Must be
cleared and set again for a subsequent reset. A reset will flush the current contents of the transmit FIFO and cause
one FEh abort sequence (7 ones is a row) to be sent followed by either 7Eh (flags) or FFh (idle) until a new packet
is initiated by writing new data (at least 2 bytes) into the FIFO.
Bit 6: Receive HDLC Reset (RHR). A zero to one transition will reset the Receive HDLC controller. Must be
cleared and set again for a subsequent reset. A reset will flush the current contents of the receive FIFO and cause
the receive HDLC controller to begin searching for a new incoming HDLC packet.
Bit 8: Transmit Invert Data (TID). The control bit determines whether all of the data from the HDLC controller
(including flags and CRC checksum) will be inverted after processing.
0 = do not invert data (normal operation)
1 = invert all data
Bit 9: Receive Invert Data (RID). The control bit determines whether all of the data into the HDLC controller
(including flags and CRC checksum) will be inverted before processing.
0 = do not invert data (normal operation)
1 = invert all data
Bits 10 to 12: Transmit Low Watermark Select Bits (TLWMS0 to TLWMS2). These control bits determine
when the HDLC controller should set the TLWM status bit in the HDLC Status Register (HSR). When the transmit
FIFO contains less than the number of bytes configured by these bits, the TLWM status bit will be set to a one.
TRANSMIT LOW
WATERMARK (bytes)
TLWMS2 TLWMS1 TLWMS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
48
80
112
144
176
208
240
Bits 13 to 15: Receive High Watermark Select Bits (RHWMS0 to RHWMS2). These control bits determine
when the HDLC controller should set the RHWM status bit in the HDLC Status Register (HSR). When the receive
FIFO contains more than the number of bytes configured by these bits, the RHWM status bit will be set to a one.
RECEIVE HIGH
RHWMS2 RHWMS1
RHWMS0
WATERMARK (bytes)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
48
80
112
144
176
208
240
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Register Name:
RHDLC
Register Description:
Register Address:
Receive HDLC FIFO
82h
Bit #
7
6
5
4
3
2
1
0
Name
Default
D7
—
D6
—
D5
—
D4
—
D3
—
D2
—
D1
—
D0
—
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
PS1
—
10
PS0
—
9
CBYTE
—
8
OBYTE
—
Note 1: When the CPU bus is operated in the 8-bit mode (CMS = 1), the host should always read the lower byte (bits 0 to 7) first followed by
the upper byte (bits 8 to 15). Bits that are underlined are read-only; all other bits are read-write.
Note 2: Packets with three or fewer bytes (including the CRC FCS) in between flags are invalid and the data that appears in the FIFO in
such instances is meaningless. If only one byte is received between flags, then both the CBYTE and OBYTE bits will be set. If two bytes are
received, then OBYTE will be set for the first one received and CBYTE will be set for the second byte received. If three bytes are received,
then OBYTE will be set for the first one received and CBYTE will be set for the third byte received. In all of these cases, the packet status
will be reported as PS0 = 0/PS1 = 1 and the data in the FIFO should be ignored.
Bits 0 to 7: Receive FIFO Data (D0 to D7). Data from the Receive FIFO can be read from these bits. D0 is the
LSB and is received first while D7 is the MSB and is received last.
Bit 8: Opening Byte (OBYTE). This bit will be set to a one when the byte available at the D0 to D7 bits from the
Receive FIFO is the first byte of a HDLC packet.
Bit 9: Closing Byte (CBYTE). This bit will be set to a one when the byte available at the D0 to D7 bits from the
Receive FIFO is the last byte of a HDLC packet whether the packet is valid or not. The host can use the PS0 and
PS1 bits to determine if the packet is valid or not.
Bits 10 and 11: Packet Status Bits 0 and 1 (PS0 and PS1). These bits are only valid when the CBYTE bit is set
to a one. These bits inform the host of the validity of the incoming packet and the cause of the problem if the
packet was received in error.
PACKET
STATUS
Valid
PS1
PS0
REASON FOR INVALID RECEPTION OF THE PACKET
0
0
0
1
—
Invalid
Corrupt CRC
Incoming packet was either too short (three or fewer bytes including the CRC) or
did not contain an integral number of octets
Abort sequence detected
1
1
0
1
Invalid
Invalid
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Register Name:
THDLC
Register Description:
Register Address:
Transmit HDLC FIFO
84h
Bit #
Name
Default
7
D7
0
6
D6
0
5
D5
0
4
D4
0
3
D3
0
2
D2
0
1
D1
0
0
D0
0
Bit #
Name
Default
15
—
—
14
—
—
13
—
—
12
—
—
11
—
—
10
—
—
9
—
—
8
TMEND
0
Note 1: When the CPU bus is operated in the 8-bit mode (CMS = 1), the host should always write to the lower byte (bits 0 to 7) first followed
by the upper byte (bits 8 to 15).
Note 2: The THDLC is a write-only register.
Note 3: The Transmit FIFO can be filled to a maximum capacity of 256 bytes. When the Transmit FIFO is full, it will not accept any
additional data.
Bits 0 to 7: Transmit FIFO Data (D0 to D7). Data for the Transmit FIFO can be written to these bits. D0 is the
LSB and is transmitted first while D7 is the MSB and is transmitted last.
Bit 8: Transmit Message End (TMEND). This bit is used to delineate multiple messages in the Transmit FIFO. It
should be set to a one when the last byte of a packet is written to the Transmit FIFO. The setting of this bit
indicates to the HDLC controller that the message is complete and that it should calculate and add in the CRC
checksum and at least two flags. This bit should be set to zero for all other data written to the FIFO. All HDLC
messages must be at least 2 bytes in length.
9.3 HDLC Status and Interrupt Register Description
Register Name:
HSR
Register Description:
Register Address:
HDLC Status Register
86h
Bit #
Name
Default
7
6
RPE
—
5
RPS
—
4
RHWM
—
3
—
—
2
TLWM
—
1
—
—
0
TUDR
—
TEND
—
Bit #
Name
Default
15
RABT
—
14
REMPTY
—
13
ROVR
—
12
TEMPTY
—
11
TFL3
—
10
TFL2
—
9
8
TFL1
—
TFL0
—
Note: See Figure 9-1 for details on the signal flow for the status bits in the HSR register. Bits that are underlined are read-only; all other
bits are read-write.
Bit 0: Transmit Packet End (TEND). This latched read-only event-status bit will be set to a one each time the
transmit HDLC controller reads a transmit FIFO byte with the corresponding TMEND bit set or if a FIFO underrun
occurs. This bit will be cleared when read and will not be set again until another message end is detected. The
setting of this bit can cause a hardware interrupt to occur if the TEND bit in the Interrupt Mask for HSR (IHSR)
register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read.
Bit 2: Transmit FIFO Low Watermark (TLWM). This read-only real time status bit will be set to a one when
the transmit FIFO contains less than the number of bytes configured by the Transmit Low Watermark Setting
control bits (TLWMS0 to TLWMS2) in the HDLC Control Register (HCR). This bit will be cleared when the FIFO
fills beyond the low watermark. The setting of this bit can cause a hardware interrupt to occur if the TLWM bit in
the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR
(IMSR) register is set to a one.
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Bit 4: Receive FIFO High Watermark (RHWM). This read-only real-time status bit will be set to a one when the
receive FIFO contains more than the number of bytes configured by the Receive High Watermark Setting control
bits (RHWMS0 to RHWMS2) in the HDLC Control Register (HCR). This bit will be cleared when the FIFO
empties below the high watermark. The setting of this bit can cause a hardware interrupt to occur if the RHWM bit
in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR
(IMSR) register is set to a one.
Bit 5: Receive Packet Start (RPS). This latched read-only event-status bit will be set to a one each time the
HDLC controller detects an opening byte of an HDLC packet. This bit will be cleared when read and will not be set
again until another message is detected. The setting of this bit can cause a hardware interrupt to occur if the RPS bit
in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for MSR
(IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bit 6: Receive Packet End (RPE). This latched read-only event-status bit will be set to a one each time the HDLC
controller detects the finish of a message whether the packet is valid (CRC correct) or not (bad CRC, abort
sequence detected, packet too small, not an integral number of octets, or an overrun occurred). This bit will be
cleared when read and will not be set again until another message end is detected. The setting of this bit can cause a
hardware interrupt to occur if the RPE bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the
HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear
when this bit is read.
Bit 7: Transmit FIFO Underrun (TUDR). This latched read-only event-status bit will be set to a one each time
the transmit FIFO underruns and an abort is automatically sent. This bit will be cleared when read and will not be
set again until another underrun occurs (i.e., the FIFO has been written to and then allowed to empty again). The
setting of this bit can cause a hardware interrupt to occur if the TUDR bit in the Interrupt Mask for HSR (IHSR)
register is set to a one and the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read.
Bits 8 to 11: Transmit FIFO Level Bits 0 to 3 (TFL0 to TFL3). These read-only real-time status bits indicate the
current depth of the transmit FIFO with a 16-byte resolution. These status bits cannot cause a hardware interrupt.
TFL3
TFL2
TFL1
TFL0
TRANSMIT FIFO LEVEL
empty to 15 bytes
16 to 31 bytes
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
32 to 47 bytes
48 to 63 bytes
64 to 79 bytes
80 to 95 bytes
96 to 111 bytes
112 to 127 bytes
128 to 143 bytes
144 to 159 bytes
160 to 175 bytes
176 to 191 bytes
192 to 207 bytes
208 to 223 bytes
224 to 239 bytes
240 to 256 bytes
Bit 12: Transmit FIFO Empty (TEMPTY). This read-only real-time status bit will be set to a one when the
transmit FIFO is empty. It will be cleared when the transmit FIFO contains one or more bytes. This status bit
cannot cause a hardware interrupt.
Bit 13: Receive FIFO Overrun (ROVR). This latched read-only event-status bit will be set to a one each time the
receive FIFO overruns. This bit will be cleared when read and will not be set again until another overrun occurs
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(i.e., the FIFO has been read from and then allowed to fill up again). The setting of this bit can cause a hardware
interrupt to occur if the ROVR bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit
in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is
read.
Bit 14: Receive FIFO Empty (REMPTY). This real-time bit will be set to a one when the Receive FIFO is empty
and will be set to a zero when the Receive FIFO is not empty.
Bit 15: Receive Abort Sequence Detected (RABT). This latched read-only event-status bit will be set to a one
each time the receive HDLC controller detects seven or more ones in a row during packet reception. If the receive
HDLC is not currently receiving a packet, then seven or more ones in a row will not trigger this status bit. This bit
will be cleared when read and will not be set again until another abort is detected (at least one valid flag must be
detected before another abort can be detected). The setting of this bit can cause a hardware interrupt to occur if the
RABT bit in the Interrupt Mask for HSR (IHSR) register is set to a one and the HDLC bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
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Figure 9-1. HSR Status Bit Flow
Transmit
TEND
(HSR Bit 0)
Event Latch
Packet End
Signal from
HDLC
Mask
Mask
TEND (IHSR Bit 0)
Internal Transmit
Low Water Mark
Signal from
TLWM
(HSR Bit 2)
HDLC
TLWM (IHSR Bit 2)
Internal Receive
High Water Mark
Signal from
RHWM
(HSR Bit 4)
HDLC
Mask
Mask
RHWM (IHSR Bit 4)
Internal Receive
Packet Start
Signal from
HDLC
RPS
(HSR Bit 5)
Event Latch
Event Latch
Event Latch
Event Latch
RPS (IHSR Bit 5)
HDLC
Status Bit
(MSR Bit 3)
Internal Receive
Packet End
Signal from
HDLC
RPE
(HSR Bit 6)
OR
INT*
Hardware
Signal
Mask
Mask
RPE (IHSR Bit 6)
HDLC
(IMSR Bit 3)
Internal Transmit
FIFO Underrun
Signal from
HDLC
TUDR
(HSR Bit 7)
Mask
Mask
Mask
TUDR (IHSR Bit 7)
Internal Receive
FIFO Overrun
Signal from
HDLC
ROVR
(HSR Bit 13)
ROVR (IHSR Bit 13)
RABT
Internal Receive
Abort Detect
Signal from
HDLC
Event Latch
(HSR Bit 15)
RABT (IHSR Bit 15)
NOTE: ALL EVENT LATCHES ABOVE ARE CLEARED WHEN THE HSR REGISTER IS READ.
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DS3112
Register Name:
IHSR
Register Description:
Register Address:
Interrupt Mask for HDLC Status Register
88h
Bit #
Name
Default
7
TUDR
0
6
RPE
0
5
RPS
0
4
RHWM
0
3
—
—
2
TLWM
0
1
—
—
0
TEND
0
Bit #
Name
Default
15
RABT
0
14
—
—
13
ROVR
0
12
—
—
11
—
—
10
—
—
9
—
—
8
—
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Transmit Packet End (TEND).
0 = interrupt masked
1 = interrupt unmasked
Bit 2: Transmit FIFO Low Watermark (TLWM).
0 = interrupt masked
1 = interrupt unmasked
Bit 4: Receive FIFO High Watermark (RHWM).
0 = interrupt masked
1 = interrupt unmasked
Bit 5: Receive Packet Start (RPS).
0 = interrupt masked
1 = interrupt unmasked
Bit 6: Receive Packet End (RPE).
0 = interrupt masked
1 = interrupt unmasked
Bit 7: Transmit FIFO Underrun (TUDR).
0 = interrupt masked
1 = interrupt unmasked
Bit 13: Receive FIFO Overrun (ROVR).
0 = interrupt masked
1 = interrupt unmasked
Bit 15: Receive Abort Sequence Detected (RABT).
0 = interrupt masked
1 = interrupt unmasked
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DS3112
10 FEAC CONTROLLER
The DS3112 contains an onboard FEAC controller. When the device is operated in the T3 mode, the
FEAC controller is only active in the C-Bit Parity Mode. When the device is operated in the E3 mode, the
user has the option to connect the FEAC controller to the Sn bit position. On the receive side, the FEAC
controller is always connected to the receive E3 framer. If the host does not wish to use the FEAC
controller for the Sn bit, then the status updates provided by the FEAC controller are ignored. On the
transmit side, the host selects the source of the Sn via the E3SnC0 and E3SnC1 controls bits in the T3/E3
Control Register (Section 5.2).
The DS3112 can both detect and generate Far End Alarm Codewords (FEAC). The FEAC codeword is a
repeating 16 bit pattern of the form ...0xxxxxx011111111... where the rightmost bit is transmitted first.
The FEAC codeword must be transmitted at least 10 times. When no FEAC codeword is being
transmitted, the data pattern should be forced to all ones.
The receive FEAC detector does a bit by bit search for a data pattern of the form of a FEAC codeword.
Once found, the receive FEAC detector validates incoming codewords by checking to see that the same
codeword is found in three consecutive opportunities. Once validated, a codeword is considered no longer
present when it is received incorrectly twice in a row. Once a codeword is validated, the Receive FEAC
Codeword Detect (RFCD) status bit is set and the codeword is written into the Receive FEAC FIFO for
the host to read. The host can use the RFCD status to know when to read the Receive FEAC FIFO. The
Receive FEAC FIFO is four codewords deep. If the FIFO is full when the receive FEAC detector
attempts to write a new incoming codeword, the latest incoming codeword(s) will be discarded and the
Receive FEAC FIFO Overflow (RFFO) status bit will be set.
The DS3112 can transmit two different FEAC codewords. This is useful if the host wishes to generate a
Loopback Command which is made up of 10 FEAC codewords that indicate the type of loopback
followed by 10 FEAC codewords that indicate which line is to be looped back.
10.1 FEAC Control Register Description
Register Name:
FCR
Register Description:
Register Address:
FEAC Control Register
90h
Bit #
Name
Default
7
TFS1
0
6
TFS0
0
5
TFCA5
0
4
TFCA4
0
3
TFCA3
0
2
TFCA2
0
1
TFCA1
0
0
TFCA0
0
Bit #
Name
Default
15
RFR
0
14
IERFI
—
13
TFCB5
0
12
TFCB4
0
11
TFCB3
0
10
TFCB2
0
9
TFCB1
0
8
TFCB0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 5: Transmit FEAC Codeword A Data (TFCA0 to TFCA5). The FEAC codeword is of the form
...0xxxxxx011111111... where the rightmost bit is transmitted first. These six bits are the middle six bits of the
second byte of the FEAC codeword (i.e., the six “x” bits). The device can generate two different codewords and
these six bits represent what will be transmitted for codeword A. TFCA0 is the LSB and is transmitted first while
TFCA5 is the MSB and is transmitted last. The TFS0 and TFS1 control bits determine if this codeword is to be
generated. These bits should only be changed when the transmit FEAC controller is in the idle state (TFS0 = 0 and
TFS1 = 0).
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DS3112
Bits 6 and 7: Transmit FEAC Codeword Select Bits 0 and 1 (TFS0 and TFS1). These two bits control what
two available codewords should be generated. Both TFS0 and TFS1 are edge triggered. To change the action, the
host must go back to the null state (TFS0 = TFS1 = 0) before proceeding to the desired action. Wait a minimum of
(10) codewords before changing to out-of-idle state.
TFS1
TFS0
ACTION
0
0
1
1
0
1
0
1
Idle state; do not generate a FEAC codeword (send all ones)
Send 10 of codeword A followed by all ones
Send 10 of codeword A followed by 10 of codeword B followed by all ones
Send codeword A continuously (will be sent for at least 10 times)
Bits 8 to 13: Transmit FEAC Codeword B Data (TFCB0 to TFCB5). The FEAC codeword is of the form
...0xxxxxx011111111... where the rightmost bit is transmitted first. These six bits are the middle six bits of the
second byte of the FEAC codeword (i.e., the six “x” bits). The device can generate two different codewords and
these six bits represent what will be transmitted for codeword B. TFCB0 is the LSB and is transmitted first while
TFCB5 is the MSB and is transmitted last. The TFS0 and TFS1 control bits determine if this codeword is to be
generated. These bits should only be changed when the transmit FEAC controller is in the idle state (TFS0 = 0 and
TFS1 = 0).
Bit 14: Interrupt Enable, Receive FEAC Idle (IERFI). This bit masks or enables interrupts caused by the
Receive FEAC Idle (RFI) bit in the FSR register.
0 = interrupt masked
1 = interrupt unmasked
Bit 15: Receive FEAC Controller Reset (RFR). A zero to one transition will reset the receive FEAC controller
and flush the Receive FEAC FIFO. This bit must be cleared and set again for a subsequent reset.
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DS3112
10.2 FEAC Status Register Description
Register Name:
FSR
Register Description:
Register Address:
FEAC Status Register
92h
Bit #
Name
Default
7
—
—
6
—
—
5
—
—
4
—
—
3
—
—
2
—
—
1
RFI
—
0
RFCD
—
Bit #
Name
Default
15
RFFO
—
14
RFFE
—
13
RFF5
—
12
RFF4
—
11
RFF3
—
10
RFF2
—
9
8
RFF1
—
RFF0
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Receive FEAC Codeword Detected (RFCD). This latched read-only event-status bit will be set to a one
each time the FEAC controller has detected and validated a new FEAC codeword. This bit will be cleared when
read and will not be set again until another new codeword is detected. The setting of this bit can cause a hardware
interrupt to occur if the FEAC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will
be allowed to clear when this bit is read.
Bit 1: Receive FEAC Idle (RFI). This latched read-only event status bit will be set to a one each time the FEAC
controller has detected 16 consecutive ones following a valid codeword. This bit will be cleared when read. The
setting of this bit can cause a hardware interrupt to occur if the IERFI bit in the FEAC Control Register (FCR) is
set to one and the FEAC bit in the Interrupt Mask for MSR (IMSR) is set to one.
Bits 8 to 13: Receive FEAC FIFO Data (RFF0 to RFF5). Data from the Receive FEAC FIFO can be read from
these bits. The FEAC codeword is of the form ...0xxxxxx011111111... where the rightmost bit is received first.
These six bits are the debounced and integrated middle six bits of the second byte of the FEAC codeword (i.e., the
six “x” bits). RFF0 is the LSB and is received first while RFF5 is the MSB and is received last.
Bit 14: Receive FEAC FIFO Empty (RFFE). This read-only real time status bit will be set to a one when the
Receive FEAC FIFO is empty and hence the RFF0 to RFF5 bits contain no valid information.
Bit 15: Receive FEAC FIFO Overflow (RFFO). This latched read-only event-status bit will be set to a one when
the receive FEAC controller has attempted to write to an already full Receive FEAC FIFO and current incoming
FEAC codeword is lost. This bit will be cleared when read and will not be set again until another FIFO overflow
occurs (i.e., the Receive FEAC FIFO has been read and then fills beyond capacity).
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DS3112
11 JTAG
The DS3112 device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, IDCODE (Figure 11-1). The
DS3112 contains the following items that meet the requirements set by the IEEE 1149.1 Standard Test
Access Port and Boundary Scan Architecture:
ꢀ Test Access Port (TAP)
ꢀ TAP Controller
ꢀ Instruction Register
ꢀ Bypass Register
ꢀ Boundary Scan Register
ꢀ Device Identification Register
The Test Access Port has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS.
Details on these pins can be found in Section 2.9. Details on the Boundary Scan Architecture and the Test
Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 11-1. JTAG Block Diagram
Boundary Scan
Register
Identification
Register
Mux
Bypass
Register
Instruction
Register
Select
Test Access Port
Controller
Tri-State
10K
10K
10K
JTDI
JTMS
JTCLK
JTDO
JTRST
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DS3112
11.1 TAP Controller State Machine Description
This section describes the operation of the test access port (TAP) controller state machine (Figure 11-2).
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK.
Figure 11-2. TAP Controller State Machine
Test-Logic-Reset
1
0
1
1
Select
Select
1
Run-Test/Idle
DR-Scan
IR-Scan
0
0
0
1
1
Capture-DR
0
Capture-IR
0
Shift-DR
1
Shift-IR
1
0
1
0
1
Exit1- DR
0
Exit1-IR
0
Pause-DR
1
Pause-IR
1
0
0
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
0
1
0
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DS3112
11.1.1 Test-Logic-Reset
Upon power-up of the DS3112, the TAP controller will be in the Test-Logic-Reset state. The Instruction
register will contain the IDCODE instruction. All system logic on the DS3112 will operate normally.
11.1.2 Run-Test-Idle
Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and Test
register will remain idle.
11.1.3 Select-DR-Scan
All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the controller
into the Capture-DR state and will initiate a scan sequence. JTMS high moves the controller to the Select-
IR-SCAN state.
11.1.4 Capture-DR
Data can be parallel-loaded into the Test Data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the Test
register will remain at its current value. On the rising edge of JTCLK, the controller will go to the Shift-
DR state if JTMS is low or it will go to the Exit1-DR state if JTMS is high.
11.1.5 Shift-DR
The Test Data register selected by the current instruction will be connected between JTDI and JTDO and
will shift data one stage towards its serial output on each rising edge of JTCLK. If a Test register selected
by the current instruction is not placed in the serial path, it will maintain its previous state.
11.1.6 Exit1-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR
state, which terminates the scanning process. A rising edge on JTCLK with JTMS low will put the
controller in the Pause-DR state.
11.1.7 Pause-DR
Shifting of the Test registers is halted while in this state. All Test registers selected by the current
instruction will retain their previous state. The controller will remain in this state while JTMS is low. A
rising edge on JTCLK with JTMS high will put the controller in the Exit2-DR state.
11.1.8 Exit2-DR
While in this state, a rising edge on JTCLK with JTMS high will put the controller in the Update-DR
state and terminate the scanning process. A rising edge on JTCLK with JTMS low will enter the Shift-DR
state.
11.1.9 Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of
the Test registers into the data output latches. This prevents changes at the parallel output due to changes
in the shift register. A rising edge on JTCLK with JTMS low will put the controller in the Run-Test-Idle
state. With JTMS high, the controller will enter the Select-DR-Scan state.
11.1.10
Select-IR-Scan
All Test registers retain their previous state. The Instruction register will remain unchanged during this
state. With JTMS low, a rising edge on JTCLK moves the controller into the Capture-IR state and will
initiate a scan sequence for the Instruction register. JTMS high during a rising edge on JTCLK puts the
controller back into the Test-Logic-Reset state.
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DS3112
11.1.11
Capture-IR
The Capture-IR state is used to load the shift register in the Instruction register with a fixed value. This
value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller
will enter the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller will enter the
Shift-IR state.
11.1.12
Shift-IR
In this state, the shift register in the Instruction register is connected between JTDI and JTDO and shifts
data one stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as
all Test registers remain at their previous states. A rising edge on JTCLK with JTMS high will move the
controller to the Exit1-IR state. A rising edge on JTCLK with JTMS low will keep the controller in the
Shift-IR state while moving data one stage through the Instruction shift register.
11.1.13
Exit1-IR
A rising edge on JTCLK with JTMS low will put the controller in the Pause-IR state. If JTMS is high on
the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning
process.
11.1.14
Pause-IR
Shifting of the Instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK will
put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is low
during a rising edge on JTCLK.
11.1.15
Exit2-IR
A rising edge on JTCLK with JTMS high will put the controller in the Update-IR state. The controller
will loop back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state.
11.1.16
Update-IR
The instruction shifted into the Instruction shift register is latched into the parallel output on the falling
edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current
instruction. A rising edge on JTCLK with JTMS low will put the controller in the Run-Test-Idle state.
With JTMS high, the controller will enter the Select-DR-Scan state.
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DS3112
11.2 Instruction Register and Instructions
The Instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between
JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low will shift data one
stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR
state with JTMS high will move the controller to the Update-IR state. The falling edge of that same
JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions
supported by the DS3112 and their respective operational binary codes are shown in Table 11-1.
Table 11-1. Instruction Codes
INSTRUCTIONS
SAMPLE/PRELOAD
BYPASS
SELECTED REGISTER INSTRUCTION CODES
Boundary Scan
Bypass
010
111
000
011
100
001
EXTEST
CLAMP
HIGH-Z
IDCODE
Boundary Scan
Bypass
Bypass
Device Identification
11.2.1 SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of
the DS3112 can be sampled at the Boundary Scan register without interfering with the normal operation
of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS3112 to shift data
into the Boundary Scan register via JTDI using the Shift-DR state.
11.2.2 EXTEST
EXTEST allows testing of all interconnections to the DS3112. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The Boundary Scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the Boundary Scan register.
11.2.3 BYPASS
When the BYPASS instruction is latched into the parallel Instruction register, JTDI connects to JTDO
through the one-bit Bypass Test register. This allows data to pass from JTDI to JTDO not affecting the
device's normal operation.
11.2.4 IDCODE
When the IDCODE instruction is latched into the parallel Instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register's parallel output. The device ID code will always have a one in the LSB position.
The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed
by 16 bits for the device and 4 bits for the version. The device ID code for the DS3112 is 0000B143h.
11.2.5 HIGHZ
All digital outputs will be placed into a high impedance state. The Bypass Register will be connected
between JTDI and JTDO.
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DS3112
11.2.6 CLAMP
All digital outputs will output data from the boundary scan parallel output while connecting the Bypass
Register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
11.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers, the bypass register and the boundary scan register.
An optional test register, the Identification register, has been included in the DS3112 design. It is used in
conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
11.3.1 Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGH-Z
instructions that provides a short path between JTDI and JTDO.
11.3.2 Identification Register
The Identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
11.3.3 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is 196 bits in length. Table 11-2 shows all the cell bit locations and definitions.
Table 11-2. Boundary Scan Control Bits
I/O OR CONTROL BIT
BIT
SYMBOL
PIN
DESCRIPTION
0 = outputs are active
1 = outputs are tri-state (“z”)
I
0 = CINT is a zero (“0”)
1 = CINT is tri-state (“z”)
0
1
2
OUT_ENB
TEST
Control bit
C3
CINT_ENB_N Control bit
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CINT_OUT
CINT_IN
CMS
A2
A2
B2
B3
C4
D5
A3
B4
C5
B6
C7
A7
C8
B8
A8
C9
B9
A9
C10
O (open drain)
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
CIM
CCS
CRD
CWR
T3E3MS
RST
G.747E
CALE
FRMECU
FRLOF
FRLOS
FRSOF
FRDEN
FRD
FRCLK
FTDEN
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DS3112
I/O OR CONTROL BIT
DESCRIPTION
BIT
SYMBOL
PIN
22
23
FTD
FTCLK
B10
A10
I
I
FTSOF_ENB_
N
1 = FTSOF is an input
0 = FTSOF is an output
24
Control bit
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
FTSOF_OUT
FTSOF_IN
FTMEI
A11
A11
C11
C12
A13
B13
A14
B14
C14
G19
G20
H18
H19
H20
J18
O
I
I
I
I
HRNEG
HRCLK
HRPOS
HTNEG
HTCLK
HTPOS
I
O
O
O
I
I
I
LTCCLK
LRCCLK
LTCLK28
LTDAT28
LRCLK28
LRDAT28
LTCLK27
LTDAT27
LRCLK27
LRDAT27
LTCLK26
LTDAT26
LRCLK26
LRDAT26
LTCLK25
LTDAT25
LRCLK25
LRDAT25
LTCLK24
LTDAT24
LRCLK24
LRDAT24
LTCLK23
LTDAT23
LRCLK23
LRDAT23
LTCLK22
LTDAT22
LRCLK22
LRDAT22
LTCLK21
LTDAT21
LRCLK21
LRDAT21
LTCLK20
LTDAT20
I
O
O
I
J19
J20
I
K18
K19
K20
L20
L18
L19
M20
M19
M18
M17
N20
N19
N18
P20
P19
P18
R20
R19
P17
R18
T20
T19
T18
U20
V20
T17
U18
U19
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
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DS3112
I/O OR CONTROL BIT
DESCRIPTION
BIT
SYMBOL
PIN
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
LRCLK20
LRDAT20
LTCLK19
LTDAT19
LRCLK19
LRDAT19
LTCLK18
LTDAT18
LRCLK18
LRDAT18
LTCLK17
LTDAT17
LRCLK17
LRDAT17
LTCLK16
LTDAT16
LRCLK16
LRDAT16
LTCLK15
LTDAT15
LRCLK15
LRDAT15
LTCLK14
LTDAT14
LRCLK14
LRDAT14
LTCLK13
LTDAT13
LRCLK13
LRDAT13
LTCLK12
LTDAT12
LRCLK12
LRDAT12
LTCLK11
LTDAT11
LRCLK11
LRDAT11
LTCLK10
LTDAT10
LRCLK10
LRDAT10
LTCLK9
V19
W20
Y20
W19
V18
Y19
W18
V17
U16
Y18
W17
V16
Y17
W16
V15
U14
Y16
W15
V14
Y15
W14
Y14
V13
W13
Y13
V12
W12
Y12
V11
W11
Y11
Y10
V10
W10
Y9
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
I
O
O
I
W9
V9
U9
Y8
W8
V8
Y7
W7
V7
Y6
W6
U7
V6
Y5
I
O
O
I
I
O
O
I
LTDAT9
LRCLK9
LRDAT9
LTCLK8
LTDAT8
I
O
O
I
I
O
LRCLK8
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DS3112
I/O OR CONTROL BIT
DESCRIPTION
BIT
SYMBOL
PIN
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
LRDAT8
LTCLK7
LTDAT7
LRCLK7
LRDAT7
LTCLK6
LTDAT6
LRCLK6
LRDAT6
LTCLK5
LTDAT5
LRCLK5
LRDAT5
LTCLK4
LTDAT4
LRCLK4
LRDAT4
LTCLK3
LTDAT3
LRCLK3
LRDAT3
LTCLK2
LTDAT2
LRCLK2
LRDAT2
LTCLK1
LTDAT1
LRCLK1
LRDAT1
LTCLKB
LTDATB
LRCLKB
LRDATB
LTCLKA
LTDATA
LRCLKA
LRDATA
CA7
W5
V5
Y4
Y3
U5
V4
W4
Y2
W3
V3
W1
V2
U3
T4
V1
U2
T3
U1
T2
R3
P4
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
I
O
O
I
R2
P3
R1
P2
I
O
O
I
P1
N3
N2
N1
M3
M2
M1
L3
L2
L1
K1
K3
K2
J1
J2
J3
J4
H1
H2
H3
G1
G1
G2
G2
I
O
O
I
I
O
O
I
I
O
O
I
I
I
I
I
I
I
I
O
I
O
I
CA6
CA5
CA4
CA3
CA2
CA1
CA0
CD15_OUT
CD15_IN
CD14_OUT
CD14_IN
107 of 133
DS3112
I/O OR CONTROL BIT
DESCRIPTION
BIT
SYMBOL
PIN
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
CD13_OUT
CD13_IN
CD12_OUT
CD12_IN
CD11_OUT
CD11_IN
CD10_OUT
CD10_IN
CD9_OUT
CD9_IN
CD8_OUT
CD8_IN
CD7_OUT
CD7_IN
CD6_OUT
CD6_IN
CD5_OUT
CD5_IN
CD4_OUT
CD4_IN
CD3_OUT
CD3_IN
CD2_OUT
CD2_IN
CD1_OUT
CD1_IN
G3
G3
F1
F1
F2
F2
G4
G4
F3
F3
E1
E1
E2
E2
E3
E3
D1
D1
C1
C1
E4
E4
D3
D3
D2
D2
C2
C2
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
CD0_OUT
CD0_IN
1 = CD is an input
0 = CD is an output
196
CD_ENB_N
Control bit
108 of 133
DS3112
12 DC ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin with Respect to VSS (except VDD)……………………………...-0.3V to +5.5V
Supply Voltage (VDD) Range with Respect to VSS……………………………….………..-0.3V to +3.63V
Operating Temperature Range………………………………………………………………..0°C to +70°C
Storage Temperature Range………………………………………………………………-55°C to +125°C
Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification
Note: The typical values listed below are not production tested.
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect
reliability.
Table 12-1. Recommended DC Operating Conditions
(TA = 0°C to +70°C for DS3112, TA = -40°C to +85°C for DS3112N.)
PARAMETER
SYMBOL
MIN
TYP
MAX
5.5
UNITS NOTES
Logic 1
Logic 0
Supply
VIH
2.2
V
V
V
VIL
VDD
-0.3
3.135
0.8
3.465
Table 12-2. DC Characteristics
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.)
PARAMETER
Supply Current at VDD = 3.465V
Pin Capacitance
SYMBOL
MIN
TYP
150
7
MAX
UNITS NOTES
IDD
CIO
IIL
mA
pF
1
Input Leakage
-10
-500
-10
+10
+500
+10
2
2
3
µA
µA
µA
mA
mA
Input Leakage (with Pullups)
Output Leakage
IILP
ILO
IOH
IOL
Output Current (2.4V)
Output Current (0.4V)
-4.0
+4.0
NOTES:
1) FTCLK = HRCLK = 44.736MHz and LTCLK1 to LTCLK28 = 1.544MHz; other inputs at VDD or
grounded; other outputs left open-circuited.
2) 0V < VIN < VDD.
3) Outputs in tri-state.
109 of 133
DS3112
13 AC ELECTRICAL CHARACTERISTICS
Table 13-1. AC Characteristics—Low-Speed (T1 and E1) Ports
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.)
(See Figure 13-1.)
PARAMETER
LRCLK/LRCCLK/LTCLK/LTCCLK
Clock Period
SYMBOL
MIN
TYP
648
488
324
244
MAX
UNITS NOTES
ns
ns
ns
ns
1
2
1
2
t1
294
204
354
284
LRCLK Clock High Time
t2
t2
t3
t3
LTCLK/LTCCLK/LRCCLK Clock
High Time
100
ns
294
204
324
244
354
284
ns
ns
1
2
LRCLK Clock Low Time
LTCLK/LTCCLK/LRCCLK Clock
Low Time
100
ns
LTDAT Setup Time to the Falling
Edge or Rising Edge of
LTCLK/LTCCLK
LTDAT Hold Time from the Falling
Edge or Rising Edge of
LTCLK/LTCCLK
Delay from the Rising Edge or
Falling Edge of LRCLK to Data
Valid on LRDAT
Delay from the Rising Edge or
Falling Edge of LRCCLK to Data
Valid on LRDAT
t4
t5
t6
t6
50
ns
50
ns
ns
ns
50
100
5
NOTES:
1) T3 mode.
2) E3 mode.
3) In normal mode, LTDAT is sampled on the falling edge of LTCLK/LTCCLK and LRDAT is updated on the
rising edge of LRCLK/LRCCLK.
4) In inverted mode, LTDAT is sampled on the rising edge of LTCLK/LTCCLK and LRDAT is updated on the
falling edge of LRCLK/LRCCLK.
5) LRCCLK is enabled. (See Section 4.2 and Figure 1-1, Figure 1-2, and Figure 1-3 for details.)
110 of 133
DS3112
Figure 13-1. Low-Speed (T1 and E1) Port AC Timing Diagram
t1
t2
t3
LRCLK (or LRCCLK) /
LTCLK (or LTCCLK)
Normal Mode
LRCLK (or LRCCLK) /
LTCLK (or LTCCLK)
Inverted Mode
t4
t5
LTDAT
LRDAT
t6
ls_ac
111 of 133
DS3112
Table 13-2. AC Characteristics—High-Speed (T3 and E3) Ports
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.)
(See Figure 13-2.)
PARAMETER
SYMBOL MIN
TYP
22.4
29.1
MAX UNITS
NOTES
ns
ns
ns
ns
1, 3
2, 3
HRCLK/HTCLK Clock Period
t1
HRCLK Clock Low Time
HRCLK Clock High Time
HRPOS/HRNEG Setup Time to the
Rising Edge or Falling Edge of
HRCLK
HRPOS/HRNEG Hold Time from the
Rising Edge or Falling Edge of
HRCLK
t2
t3
9
9
t4
t5
t6
3
3
3
ns
ns
Delay from the Rising Edge or
Falling Edge of HTCLK to Data
Valid on HTPOS/HTNEG
10
ns
NOTES:
1) T3 mode.
2) E3 mode.
3) HTCLK is a buffered version of either FTCLK or HRCLK and, as such, the duty cycle of HTCLK is
determined by the source clock.
4) In normal mode, HRPOS and HRNEG are sampled on the rising edge of HRCLK and HTPOS and HTNEG are
updated on the rising edge of HTCLK.
5) In inverted mode, HRPOS and HRNEG are sampled on the falling edge of HRCLK and HTPOS and HTNEG
are updated on the falling edge of HTCLK.
Figure 13-2. High-Speed (T3 and E3) Port AC Timing Diagram
t1
t2
t3
HRCLK / HTCLK
Normal Mode
HRCLK / HTCLK
Inverted Mode
t4
t5
HRPOS / HRNEG
HTPOS / HTNEG
t6
ls_ac
112 of 133
DS3112
Table 13-3. AC Characteristics–Framer (T3 and E3) Ports
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.)
(See Figure 13-3.)
PARAMETER
SYMBOL
MIN
TYP
22.4
29.1
MAX
UNITS NOTES
ns
ns
ns
ns
1, 3
2, 3
FRCLK/FTCLK Clock Period
t1
FTCLK Clock Low Time
FTCLK Clock High Time
FTD/FTSOF Setup Time to the
Rising Edge or Falling Edge of
FTCLK
FTD/FTSOF Hold Time from the
Rising Edge or Falling Edge of
FTCLK
t2
t3
9
9
t4
t5
3
3
ns
ns
4
4
Delay from the Rising Edge or
Falling Edge of FRCLK/FTCLK to
Data Valid on FRDEN/FRD/
FRSOF/FTDEN/FTSOF
t6
3
10
ns
5
NOTES:
1) T3 mode.
2) E3 mode.
3) FRCLK is a buffered version of either FTCLK or HRCLK and, as such, the duty cycle of FRCLK is
determined by the source clock.
4) FTSOF is configured to be an input.
5) FTSOF is configured to be an output.
6) In normal mode, FTD (and FTSOF if it is configured as an input) is sampled on the rising edge of FTCLK and
FRDEN, FRD, FRSOF, and FTDEN (and FTSOF if it is configured as an output) are updated on the rising
edge of FRCLK or FTCLK.
7) In inverted mode, FTD (and FTSOF if it is configured as an input) is sampled on the falling edge of FTCLK
and FRDEN, FRD, FRSOF, and FTDEN (and FTSOF if it is configured as an output) are updated on the
falling edge of FRCLK or FTCLK.
Figure 13-3. Framer (T3 and E3) Port AC Timing Diagram
t1
t2
t3
FRCLK / FTCLK
Normal Mode
FRCLK / FTCLK
Inverted Mode
t4
t5
FTD / FTSOF
t6
FRD / FRDEN /
FRSOF / FTSOF /
FTDEN
ls_ac
113 of 133
DS3112
Table 13-4. AC Characteristics—CPU Bus (Multiplexed and Nonmultiplexed)
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.)
(See Figure 13-4, Figure 13-5, Figure 13-6, Figure 13-7, Figure 13-8, Figure 13-9, Figure 13-10,
and Figure 13-11.)
PARAMETER
Setup Time for CA[7:0] Valid to CCS
Active
SYMBOL MIN
TYP
MAX
UNITS NOTES
t1
t2
t3
t4
t5
t6
t7
t8
t9
0
0
ns
Setup Time for CCS Active to CRD,
CWR, or CDS Active
Delay Time from CRD or CDS Active
ns
ns
ns
ns
ns
ns
ns
65
20
to CD[15:0] Valid
Hold Time from CRD or CWR or CDS
Inactive to CCS Inactive
Hold Time from CCS or CRD or CDS
0
5
Inactive to CD[15:0] Tri-State
Wait Time from CWR or CDS Active
to Latch CD[15:0]
65
10
2
CD[15:0] Setup Time to CWR or CDS
Inactive
CD[15:0] Hold Time from CWR or
CDS Inactive
CA[7:0] Hold Time from CWR or
CRD or CDS Inactive
CRD, CWR, or CDS Inactive Time
Muxed Address Valid to CALE Falling
Muxed Address Hold Time
5
ns
ns
t10
t11
t12
t13
75
10
10
30
ns
ns
ns
2
2
2
CALE Pulse Width
Setup Time for CALE High or Muxed
Address Valid to CCS Active
t14
0
ns
2
NOTES:
1) In nonmultiplexed bus applications (Figure 13-4), CALE should be tied high.
2) In multiplexed bus applications (Figure 13-5), CA[7:0] should be tied to CD[7:0] and the falling edge of CALE
will latch the address.
114 of 133
DS3112
Figure 13-4. Intel Read Cycle (Nonmultiplexed)
t9
CA[7:0]
Address Valid
Data Valid
CD[15:0]
CWR
t5
t1
CCS
t2
t3
t4
t10
CRD
Figure 13-5. Intel Write Cycle (Nonmultiplexed)
t9
CA[7:0]
Address Valid
CD[15:0]
CRD
t7
t8
t1
CCS
t2
t6
t4
t10
CWR
115 of 133
DS3112
Figure 13-6. Motorola Read Cycle (Nonmultiplexed)
t9
CA[7:0]
Address Valid
Data Valid
CD[15:0]
CR/W
CCS
t5
t1
t2
t3
t4
t10
CDS
Figure 13-7. Motorola Write Cycle (Nonmultiplexed)
t9
CA[7:0]
Address Valid
CD[15:0]
CR/W
CCS
t7 t8
t1
t2
t6
t4
t10
CDS
116 of 133
DS3112
Figure 13-8. Intel Read Cycle (Multiplexed)
t13
t12
CALE
t11
Address
CA[7:0]
Valid
t14
Data Valid
CD[15:0]
t14
t5
CWR
t1
CCS
t2
t3
t4
t10
CRD
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST.
Figure 13-9. Intel Write Cycle (Multiplexed)
t13
t12
CALE
t11
Address
CA[7:0]
Valid
t14
t14
CD[15:0]
t7
t8
CRD
CCS
CWR
t1
t6
t4
t2
t10
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST.
117 of 133
DS3112
Figure 13-10. Motorola Read Cycle (Multiplexed)
t13
t12
CALE
t11
Address
CA[7:0]
Valid
t14
Data Valid
CD[15:0]
CR/W
CCS
t14
t5
t1
t4
t2
t3
t10
CDS
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST.
Figure 13-11. Motorola Write Cycle (Multiplexed)
t13
t12
CALE
t11
Address
CA[7:0]
Valid
t14
t14
CD[15:0]
CR/W
CCS
t7 t8
t1
t6
t2
t4
t10
CDS
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST.
118 of 133
DS3112
Table 13-5. AC Characteristics—JTAG Test Port Interface
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.)
(See Figure 13-12.)
PARAMETER
JTCLK Clock Period
JTCLK Clock Low Time
SYMBOL
MIN
1000
400
TYP
MAX UNITS NOTES
t1
t2
t3
ns
ns
ns
JTCLK Clock High Time
400
JTMS/JTDI Setup Time to the
Rising Edge of JTCLK
JTMS/JTDI Hold Time from the
Rising Edge of JTCLK
Delay Time from the Falling Edge
of JTCLK to Data Valid on JTDO
t4
t5
t6
50
50
2
ns
ns
50
ns
Figure 13-12. JTAG Test Port Interface AC Timing Diagram
t1
t2
t3
JTCLK
t4
t5
JTMS/JTDI
JTDO
t6
119 of 133
DS3112
Table 13-6. AC Characteristics—Reset and Manual Error Counter/Insert
Signals
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.)
(See Figure 13-13 .)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
RST Low Time
t1
1000
ns
FRMECU/FTMEI High Time
FRMECU/FTMEI Low Time
t2
t3
50
ns
ns
1000
Figure 13-13. Reset and Manual Error Counter/Insert AC Timing Diagram
t1
RST
t2
t3
FRMECU/
FTMEI
120 of 133
DS3112
14 APPLICATIONS AND STANDARDS OVERVIEW
14.1Application Examples
Figure 14-1 and Figure 14-2 detail two possible applications of the DS3112. Figure 14-1 shows an
example of a channelized T3/E3 application. It shows the DS3112 being used to multiplex and
demultiplex a T3/E3 data stream into either 28 T1 data streams or 16 E1 data streams. The demultiplexed
T1/E1 data streams are fed into the DS21FF42/44 16-channel T1/E1 framer and the DS21FT42 12-
channel T1 framer devices. The T1/E1 framers locate the frame boundaries and concatenate four T1/E1
data streams into one 8.192MHz data stream, which is feed into the DS3134 HDLC controller.
Figure 14-2 shows an example of a dual unchannelized T3/E3 application. In this application, the
multiplexing capability of the DS3112 is disabled and it is only used as a T3/E3 framer.
Figure 14-1. Channelized T3/E3 Application
8.192MHz
I/F
DS21FF42/
DS21FF44
DS3150
T3/E3
Line
bipolar
I/F
16
Channel
T1/E1
T3/E3
Line
Interface
DS3112
TEMPE
DS3134
CHATEAU
PCI
Bus
Framer
T1/E1
datastreams
T3/E3
Framer &
M13/
- or -
256
Channel
HDLC
8.192MHz
I/F
DS21FT42
E13/
G747
Mux
Controller
OC-3/
OC-12/
OC-48
Mux
Optical
I/F
NRZ
I/F
12
Channel
T1
Framer
121 of 133
DS3112
Figure 14-2. Unchannelized Dual T3/E3 Application
DS3150
T3/E3
Line
bipolar
I/F
DS3112
TEMPE
T3/E3
Line
Interface
T3/E3
Framer &
M13/
E13/
G747
Mux
- or -
Optical
I/F
44.2Mbps (T3) or
34Mbps (E3)
datastream
NRZ
I/F
OC-3/
OC-12/
OC-48
Mux
DS3134
CHATEAU
PCI
Bus
44.2Mbps (T3) or
34Mbps (E3)
datastream
256
Channel
HDLC
DS3150
T3/E3
Line
bipolar
I/F
DS3112
TEMPE
T3/E3
Line
Controller
Interface
T3/E3
Framer &
M13/
E13/
G747
Mux
- or -
Optical
I/F
NRZ
I/F
OC-3/
OC-12/
OC-48
Mux
14.2 M13 Basics
M13 multiplexing is a two-step process of merging 28 T1 lines into a single T3 line. First, four of the T1
lines are merged into a single T2 rate and then seven T2 rates are merged to form the T3. The first step of
this process is called a M12 function since it is merging T1 lines into T2. The second step of this process
is called a M23 function since it is merging T2 lines into a T3. The term M13 implies that both M12 and
M23 are being performed to map 28 T1 lines into the T3. These two steps are independent and will be
discussed separately.
Table 14-1. T Carrier Rates
NOMINAL
T CARRIER
DATA RATE
LEVEL
(Mbps)
T1/DS1
T2/DS2
T3/DS3
1.544
6.312
44.736
122 of 133
DS3112
14.3 T2 Framing Structure
To understand the M12 function users must understand T2 framing. The T2 frame structure is made up of
four subframes called M subframes (Figure 14-3). The four M subframes are transmitted one after
another (...M1/M2/M3/M4/M1/M2...) to make up the complete T2 M frame data structure. Each M
subframe is made up of six blocks and each block is made up of 49 bits. The first bit of each block is
dedicated to overhead and the next 48 bits are the information bits where the T1 data will be placed for
transport. The definitions of the overhead bits are shown in Table 14-2 and the placements of the
overhead bits are shown in Figure 14-3.
Table 14-2. T2 Overhead Bit Assignments
OVERHEAD BIT
M Bits
DESCRIPTION
The M bits provide the frame alignment pattern for the four M subframes. Like all
framing patterns, the M bits are fixed to a certain state (M1 = 0/M2 = 1/M3 = 1).
The F bits provide the frame alignment pattern for the M frame. Like all framing
patterns, the F bits are fixed to a certain state (F1 = 0/F2 = 1).
(M1/M2/M3)
F Bits
(F1/F2)
In the M12 application, the C bits are used to indicate when stuffing occurs. If all three
C Bits within a subframe are set to 1, then stuffing has occurred in the stuff block of
that subframe. If all three C Bits are set to zero, then no stuffing has occurred. When
the three C bits are not equal, a majority vote is used to determine the true state. The
exception to this rule is when the C3 bit is the inverse of C1 and C2. When this occurs,
it indicates that the T1 signal should be looped back.
C Bits
(C1/C2/C3)
The X bit is used as a Remote Alarm Indication (RAI). It will be set to a zero (X = 0)
when the T2 framer cannot synchronize. It will be set to a one (X = 1) otherwise.
X Bit
14.4 M12 Multiplexing
The M12 function multiplexes four T1 lines into a single T2 line. Since there are four M subframes in the
T2 framing structure, it might be concluded that each M subframe supports one T1 line but this is not the
case. The four T1 lines are bit interleaved into the T2 framing structure. A bit from T1 line #1 is placed
immediately after the overhead bit, followed by a bit from T1 line #2, which is followed by a bit from T1
line #3, which is followed by a bit from T1 line #4, and then the process repeats. Since there are 48
information bits in each block, there are 12 bits from each T1 line in a block. The second and fourth T1
lines are logically inverted before the bit interleaving occurs.
The four T1 lines are mapped asynchronously into the T2 data stream. This implies that there is no T1
framing information passed to the T2 level. The four T1 lines can have independent timing sources and
they do not need to be timing locked to the T2 clock. To account for differences in timing, bit stuffing is
used. The last block of each M subframe is the stuff block (Figure 14-3). In each stuff block there is an
associated stuff bit (Figure 14-4) that will be either an information bit (if the three C bits are decoded to
be a zero) or a stuff bit (if the three C bits are decoded to be a one). As shown in Figure 14-4 the position
of the stuff bit varies depending on the M subframe. This is done to allow a stuffing opportunity to occur
on each T1 line in every T2 M frame. For example, if the C bits in M Subframe 2 were all set to one, then
the second bit after the F2 overhead bit in the last block would be a stuff bit instead of an information bit.
123 of 133
DS3112
Figure 14-3. T2 M-Frame Structure
M1 Subframe
Stuff Block
48
48
48
48
48
48
M1
(0)
Info
Bits
C1
C1
C1
C1
Info
Bits
F1
(0)
Info
Bits
C2
C2
C2
C2
Info
Bits
C3
C3
C3
C3
Info
Bits
F2
(1)
Info
Bits
M2 Subframe
Stuff Block
48
Info
Bits
48
Info
Bits
48
Info
Bits
48
Info
Bits
48
Info
Bits
48
Info
Bits
M2
(1)
F1
(0)
F2
(1)
M3 Subframe
Stuff Block
48
Info
Bits
48
Info
Bits
48
Info
Bits
48
Info
Bits
48
Info
Bits
48
Info
Bits
M3
(1)
F1
(0)
F2
(1)
M4 Subframe
Stuff Block
48
Info
Bits
48
Info
Bits
48
Info
Bits
48
Info
Bits
48
Info
Bits
48
Info
Bits
X
F1
(0)
F2
(1)
NOTE: M1 IS TRANSMITTED AND RECEIVED FIRST.
Figure 14-4. T2 Stuff Block Structure
M1
Subframe
F2 Stuff
Bit 1
Info
Bit 2
Info
Bit 3
Info
Bit 4
Info
Bit 5
Info
Bit 6
Info
Bit 7
Info
Bit 8
...... Info
Bit 48
M2
Subframe
F2 Info
Bit 1
Stuff
Bit 2
Info
Bit 3
Info
Bit 4
Info
Bit 5
Info
Bit 6
Info
Bit 7
Info
Bit 8
...... Info
Bit 48
M3
Subframe
F2 Info
Bit 1
Info
Bit 2
Stuff
Bit 3
Info
Bit 4
Info
Bit 5
Info
Bit 6
Info
Bit 7
Info
Bit 8
...... Info
Bit 48
M4
Subframe
F2 Info
Bit 1
Info
Bit 2
Info
Bit 3
Stuff
Bit 4
Info
Bit 5
Info
Bit 6
Info
Bit 7
Info
Bit 8
...... Info
Bit 48
124 of 133
DS3112
14.5 T3 Framing Structure
As with M12, to understand the M23 function requires an understanding of T3 framing. The T3 frame
structure is very similar to the T2 frame structure; however, it is made up of seven M subframes (see
Figure 14-5). The seven M subframes are transmitted one after another (...M1/M2/M3/.../
M6/M7M1/M2...) to make up the complete T3 M frame structure. Each M subframe is made up of eight
blocks and each block is made up of 85 bits. The first bit of each block is dedicated to overhead and the
next 84 bits are the information bits where the T2 data will be placed for transport. Table 14-3 shows the
definitions of the overhead bits, and Figure 14-5 shows the placements of the overhead bits.
Table 14-3. T3 Overhead Bit Assignments
OVERHEAD
DESCRIPTION
BIT
M Bits
(M1/M2/M3)
F Bits
The M bits provide the frame alignment pattern for the seven M subframes. Like all framing
patterns, the M bits are fixed to a certain state (M1 = 0/M2 = 1/M3 = 0).
The F bits provide the frame alignment pattern for the M frame. Like all framing patterns,
the F bits are fixed to a certain state (F1 = 1/F2 = 0/F3 = 0/F4 = 1).
(F1/F2/F3/F4)
In the M23 application, the C bits are used to indicate when stuffing occurs. If all three C
bits within a subframe are set to 1, then stuffing has occurred in the stuff block of that
subframe. If all three C bits are set to zero, then no stuffing has occurred. When the three C
bits are not equal, a majority vote is used to determine the true state.
C Bits
(C1/C2/C3)
In the C-Bit Parity application, the C bits are defined as shown in Table 14-4.
The P bits provide parity information for the preceding M frame (not including the M, F, X,
and C overhead bits). P1 and P2 are always the same value (if they are not the same value,
this implies a parity error).
P Bits
(P1/P2)
The X bit is used as a Remote Alarm Indication (RAI). It will be set to a zero (X1 = X2 = 0)
when the T3 framer cannot synchronize or detects AIS. It will be set to a one (X1 = X2 = 1)
otherwise. The value of the X bits should not change more than once per second. X1 and X2
are always the same value.
X Bits
(X1/X2)
14.6 M23 Multiplexing
The M23 function multiplexes seven T2 data streams into a single T3 data stream. The seven T2 data
streams are bit interleaved into the T3 framing structure. A bit from T2 line #1 is placed immediately
after the overhead bit in the information bit field, followed by a bit from T2 line #2, and so on. Since
there are 84 information bits in each block, there are 12 bits from each T2 line in a block.
The seven T2 lines are mapped asynchronously into the T3 data stream. This implies that there is no T2
framing information passed to the T3 level. The seven T2 lines can have independent timing sources and
they do not need to be timing locked to the T3 clock. To account for differences in timing, bit stuffing is
used. The last block of each M subframe is the stuff block (Figure 14-5). In each stuff block there is an
associated stuff bit (Figure 14-6) that will be either an information bit (if the three C bits are decoded to
be zero) or a stuff bit (if the three C bits are decoded to be a one). As shown in Figure 14-6, the position
of the stuff bit varies depending on the M subframe. This is done to allow a stuffing opportunity to occur
on each T2 line in every T3 frame. For example, if the C bits in M Subframe 5 were all set to one, then
the fifth bit after the F4 overhead bit in the last block would be a stuff bit instead of an information bit.
125 of 133
DS3112
14.7 C-Bit Parity Mode
Unlike the M23 application that uses the C bits for stuffing, the C-Bit Parity mode assumes that a stuff bit
should be placed at every opportunity and, hence, the C bits can be used for other purposes. Table 14-4
lists how the C bits are redefined in the C-Bit Parity mode.
Table 14-4. C-Bit Assignment for C-Bit Parity Mode
M
C-BIT
NUMBER
SUBFRAME
NUMBER
1
FUNCTION
DESCRIPTION
1
Application ID
This bit (which is fixed to a value of 1) identifies the T3
data stream as operating in C-Bit Parity mode.
2
3
Reserved
Must be set to one (1).
Far End Alarm
and Control
(FEAC)
A serial communications channel that contains a repeating
16-bit codeword that indicates the state of the far-end and
can control the near-end by invoking loopbacks both on
the T3 and T1 lines. If no codewords are being sent, the
channel contains all ones.
2
3
4
1
2
3
1
2
3
1
2
3
Unused
Unused
Unused
C-Bit Parity (CP)
C-Bit Parity (CP)
C-Bit Parity (CP)
FEBE
FEBE
FEBE
All unused bits are set to a one (1).
All three CP bits are set to the same value as the two P
bits. If the three CP bits are not equal, a majority vote is
used to decode the true value.
All three Far End Block Error (FEBE) bits shall be set to
one (111) if the local T3 framer did not incur an error in
either the M bits or F bits nor has it detected a CP parity
error. The FEBE bits are set to any value except 111 when
an error is detected in the M bits or F bits or if a CP parity
error is detected. During an LOF event, these bits are set
to 000.
5
1
2
3
Data Link
Data Link
Data Link
These three C bits make up a 28.2kbps HDLC (LAPD)
maintenance data link over which three 76 octet messages
are sent from the local end to the remote end once a
second.
6
7
1
2
3
1
2
3
Unused
Unused
Unused
Unused
Unused
Unused
Must be set to 1.
Must be set to 1.
Must be set to 1.
Must be set to 1.
Must be set to 1.
Must be set to 1.
126 of 133
DS3112
Figure 14-5. T3 M-Frame Structure
M1 Subframe
Stuff Block
84
84
84
84
84
84
84
84
X1 Info F1 Info C1 Info F2 Info C2 Info F3 Info C3 Info F4 Info
Bits (1) Bits
Bits (0) Bits
Bits (0) Bits
Bits (1) Bits
M2 Subframe
Stuff Block
84
84
84
84
84
84
84
84
X2 Info F1 Info C1 Info F2 Info C2 Info F3 Info C3 Info F4 Info
Bits (1) Bits
Bits (0) Bits
Bits (0) Bits
Bits (1) Bits
M3 Subframe
Stuff Block
84
84
84
84
84
84
84
84
P1 Info F1 Info C1 Info F2 Info C2 Info F3 Info C3 Info F4 Info
Bits (1) Bits
Bits (0) Bits
Bits (0) Bits
Bits (1) Bits
M4 Subframe
Stuff Block
84
84
84
84
84
84
84
84
P2 Info F1 Info C1 Info F2 Info C2 Info F3 Info C3 Info F4 Info
Bits (1) Bits
Bits (0) Bits
Bits (0) Bits
Bits (1) Bits
M5 Subframe
Stuff Block
84
84
84
84
84
84
84
84
M1 Info F1 Info C1 Info F2 Info C2 Info F3 Info C3 Info F4 Info
(0) Bits (1) Bits
Bits (0) Bits
Bits (0) Bits
Bits (1) Bits
M6 Subframe
Stuff Block
84
84
84
84
84
84
84
84
M2 Info F1 Info C1 Info F2 Info C2 Info F3 Info C3 Info F4 Info
(1) Bits (1) Bits
Bits (0) Bits
Bits (0) Bits
Bits (1) Bits
M7 Subframe
Stuff Block
84
84
84
84
84
84
84
84
M3 Info F1 Info C1 Info F2 Info C2 Info F3 Info C3 Info F4 Info
(0) Bits (1) Bits
Bits (0) Bits
Bits (0) Bits
Bits (1) Bits
NOTE: X1 IS TRANSMITTED AND RECEIVED FIRST.
127 of 133
DS3112
Figure 14-6. T3 Stuff Block Structure
M1
Subframe
F4 Stuff
Bit 1
Info
Bit 2
Info
Bit 3
Info
Bit 4
Info
Bit 5
Info
Bit 6
Info
Bit 7
Info
Bit 8
...... Info
Bit 84
M2
Subframe
F4 Info
Bit 1
Stuff
Bit 2
Info
Bit 3
Info
Bit 4
Info
Bit 5
Info
Bit 6
Info
Bit 7
Info
Bit 8
...... Info
Bit 84
M3
Subframe
F4 Info
Bit 1
Info
Bit 2
Stuff
Bit 3
Info
Bit 4
Info
Bit 5
Info
Bit 6
Info
Bit 7
Info
Bit 8
...... Info
Bit 84
M4
Subframe
F4 Info
Bit 1
Info
Bit 2
Info
Bit 3
Stuff
Bit 4
Info
Bit 5
Info
Bit 6
Info
Bit 7
Info
Bit 8
...... Info
Bit 84
M5
Subframe
F4 Info
Bit 1
Info
Bit 2
Info
Bit 3
Info
Bit 4
Stuff
Bit 5
Info
Bit 6
Info
Bit 7
Info
Bit 8
...... Info
Bit 84
M6
Subframe
F4 Info
Bit 1
Info
Bit 2
Info
Bit 3
Info
Bit 4
Info
Bit 5
Stuff
Bit 6
Info
Bit 7
Info
Bit 8
...... Info
Bit 84
M7
Subframe
F4 Info
Bit 1
Info
Bit 2
Info
Bit 3
Info
Bit 4
Info
Bit 5
Info
Bit 6
Stuff
Bit 7
Info
Bit 8
...... Info
Bit 84
14.8 E13 Basics
E13 multiplexing is a two-step process of merging 16 E1 lines into a single E3 line. First, four of the E1
lines are merged into a single E2 rate and then four E2 rates are merged to form the E3. The first step of
this process is called a E12 function since it is merging E1 lines into E2. The second step of this process
is called a E23 function since it is merging E2 lines into a E3. The term E13 implies that both E12 and
E23 are being performed to map 16 E1 lines into the E3. These two steps are independent and will be
discussed separately.
Table 14-5. E Carrier Rates
E CARRIER
NOMINAL DATA
RATE (Mbps)
2.048
LEVEL
E1
E2
8.448
E3
34.368
128 of 133
DS3112
14.9E2 Framing Structure and E12 Multiplexing
The E2 frame structure is made up of four 212-bit sets (Figure 14-7). The four sets are transmitted one
after another (...Set1/Set2/Set3/Set4/Set1...) to make up the complete E2 frame structure. The Frame
Alignment Signal (FAS) is placed in the first 10 bits of Set 1 and is followed by the Remote Alarm
Indication (RAI) bit and a National Bit (Sn). The remainder of Set 1 is filled with bits from the four
tributaries. The four tributaries are bit interleaved starting with a bit from Tributary 1 immediately after
the Sn bit. The first four bits of Sets 2, 3, and 4 are the Justification Control Bits. Bits 5 to 8 of Set 4 are
the Stuffing Bits. The Justification Control bits control when data will be stuffed into the Stuffing Bit
positions. When a majority of the three Justification Control Bits from a particular tributary is set to zero,
the Stuffing Bit position will be used for tributary data. When the Justification Control Bits are majority
decoded to be one, the Stuffing Bit will not be used for tributary data.
14.10E3 Framing Structure and E23 Multiplexing
The E3 frame structure and the E23 multiplexing scheme are almost identical to the E2 framing structure
and the E12 multiplexing scheme. The E3 frame structure is made up of four 384-bit sets (Figure 14-8).
The four sets are transmitted one after another (...Set1/Set2/Set3/Set4/Set1...) to make up the complete E3
frame structure. The Frame Alignment Signal (FAS) is placed in the first 10 bits of Set 1 and is followed
by the Remote Alarm Indication (RAI) bit and a National Bit (Sn). The remainder of Set 1 is filled with
bits from the four tributaries. The four tributaries are bit interleaved starting with a bit from Tributary 1
immediately after the Sn bit. The first four bits of Sets 2, 3, and 4 are the Justification Control Bits. Bits 5
to 8 of Set 4 are the Stuffing Bits. The Justification Control bits control when data will be stuffed into the
Stuffing Bit positions. When a majority of the three Justification Control Bits from a particular tributary
is set to zero, the Stuffing Bit position will be used for tributary data. When the Justification Control Bits
are majority decoded to be one, the Stuffing Bit will not be used for tributary data.
129 of 133
DS3112
Figure 14-7. E2 Frame Structure
Set 1
Bit 1
Bit 212
FAS (1111010000) RAI
Sn
b11
b21
b31
b41
b12 ...bits from the tributaries...
Set 2
Bit 1
Bit 212
c11
c21
c22
c23
c31
c32
c33
c41
c42
c43
...bits from the tributaries...
...bits from the tributaries...
Set 3
Bit 1
c12
Bit 212
Bit 212
Set 4
Bit 1
c13
s1
s2
s3
s4
...bits from the tributaries...
NOTE 1:
NOTE 2:
NOTE 3:
NOTE 4:
BIT 1 OF SET 1 IS TRANSMITTED FIRST.
BJI
CJI
SJ
TRIBUTARY BITS
JUSTIFICATION CONTROL BITS
STUFFING BITS
J = TRIBUTARY NUMBER I = BIT NUMBER
J = TRIBUTARY NUMBER I = CONTROL BIT NUMBER
J = TRIBUTARY NUMBER
Figure 14-8. E3 Frame Structure
Set 1
Bit 1
Bit 384
FAS (1111010000) RAI
Sn
b11
b21
b31
b41
b12
...bits from the tributaries...
Set 2
Bit 1
Bit 384
c11
c21
c22
c22
c31
c32
c32
c41
c42
c42
...bits from the tributaries...
...bits from the tributaries...
Set 3
Bit 1
c12
Bit 384
Bit 384
Set 4
Bit 1
c12
s1
s2
s3
s4
...bits from the tributaries...
NOTE 1:
NOTE 2:
NOTE 3:
NOTE 4:
BIT 1 OF SET 1 IS TRANSMITTED FIRST.
BJI
CJI
SJ
TRIBUTARY BITS
JUSTIFICATION CONTROL BITS
STUFFING BITS
J = TRIBUTARY NUMBER I = BIT NUMBER
J = TRIBUTARY NUMBER I = CONTROL STUFFING BIT NUMBER
J = TRIBUTARY NUMBER
130 of 133
DS3112
14.11G.747 Basics
G.747 multiplexing is a mixture of T3 and E1. It is a two-step process of merging 21 E1 lines into a
single T3 line. First, three of the E1 lines are merged into a single T2 rate and then seven T2 rates are
merged to form the T3 just like the normal T2 to T3 multiplexing scheme. Once the three E1 lines have
been multiplexed together, the resultant 6.312Mbps data stream is treated just like a T2 data stream that
contains four T1 lines. We will only discuss the G.747 multiplexing scheme in this section. See Section
14.6 for details on the T2 to T3 multiplexing scheme (e.g., M23) and the T3 framing structure.
Table 14-6. G.747 Carrier Rates
T OR E
NOMINAL DATA
CARRIER
RATE (Mbps)
LEVEL
E1
T2
T3
2.048
6.312
44.736
131 of 133
DS3112
14.12G.747 Framing Structure and E12 Multiplexing
The G.747 frame structure is made up of five 168-bit sets (Figure 14-9). The five sets are transmitted one
after another (...Set1/Set2/Set3/Set4/Set5/Set1...) to make up the complete G.747 frame structure. The
Frame Alignment Signal (FAS) is placed in the first 9 bits of Set 1. Set 2 contains the Remote Alarm
Indication (RAI) bit and a Parity Bit (PAR) as well as a reserved bit, which is fixed to a one. The PAR bit
will be set to a one when there are odd numbers of ones from the tributaries in the preceding frame and it
will be set to a zero when there is an even number of ones. The parity calculation does not include the
FAS, RAI, reserved bit, or Justification Control Bits. The three tributaries are bit interleaved starting with
a bit from Tributary 1 immediately after the FAS in Set 1. The first three bits of Sets 3, 4, and 5 are the
Justification Control Bits. Bits 4 to 6 of Set 5 are the Stuffing Bits. The Justification Control bits control
when data will be stuffed into the Stuffing Bit positions. When a majority of the three Justification
Control Bits from a particular tributary is set to zero, the Stuffing Bit position will be used for tributary
data. When the Justification Control Bits are majority decoded to be one, the Stuffing Bit will not be used
for tributary data.
Figure 14-9. G.747 Frame Structure
Set 1
Bit 1
FAS (111010000)
Bit 168
b11
b21
b31
b12
b22
b32
b13 ...bits from the tributaries...
Set 2
Bit 1
RAI
Bit 168
PAR
c21
1
...bits from the tributaries...
...bits from the tributaries...
...bits from the tributaries...
Set 3
Bit 1
c11
Bit 168
Bit 168
Bit 168
c31
c32
c33
Set 4
Bit 1
c12
c22
Set 5
Bit 1
c13
c23
s1
s2
s3
...bits from the tributaries...
NOTE 1:
NOTE 2:
NOTE 3:
NOTE 4:
BIT 1 OF SET 1 IS TRANSMITTED FIRST.
BJI
CJI
SJ
TRIBUTARY BITS
JUSTIFICATION CONTROL BITS
STUFFING BITS
J = TRIBUTARY NUMBER I = BIT NUMBER
J = TRIBUTARY NUMBER I = CONTROL STUFFING BIT NUMBER
J = TRIBUTARY NUMBER
132 of 133
DS3112
15 PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for
each package is a link to the latest package outline information.)
15.1 256-Ball PBGA (56-G6002-001)
133 of 133
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
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