DS3232SN- [MAXIM]
Extremely Accurate I2C RTC with Integrated Crystal and SRAM; 超高精度， I²C RTC，集成晶体和SRAM
| 型号： | DS3232SN- |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Extremely Accurate I2C RTC with Integrated Crystal and SRAM |
| 文件： | 总19页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 4; 10/08
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
DS32
General Description
Features
♦ Accuracy 2ppm from 0°C to +40°C
The DS3232 is a low-cost temperature-compensated
crystal oscillator (TCXO) with a very accurate, tempera-
ture-compensated, integrated real-time clock (RTC) and
236 bytes of battery-backed SRAM. Additionally, the
DS3232 incorporates a battery input and maintains accu-
rate timekeeping when main power to the device is inter-
rupted. The integration of the crystal resonator enhances
the long-term accuracy of the device as well as reduces
the piece-part count in a manufacturing line. The DS3232
is available in commercial and industrial temperature
ranges, and is offered in an industry-standard 20-pin,
300-mil SO package.
♦ Accuracy 3.5ppm from -40°C to +85°C
♦ Battery Backup Input for Continuous
Timekeeping
♦ Operating Temperature Ranges
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
♦ 236 Bytes of Battery-Backed SRAM
♦ Low-Power Consumption
♦ Real-Time Clock Counts Seconds, Minutes,
Hours, Day, Date, Month, and Year with Leap Year
Compensation Valid Up to 2099
♦ Two Time-of-Day Alarms
The RTC maintains seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format
with an AM/PM indicator. Two programmable time-of-
day alarms and a programmable square-wave output
are provided. Address and data are transferred serially
♦ Programmable Square-Wave Output
2
♦ Fast (400kHz) I C Interface
♦ 3.3V Operation
♦ Digital Temp Sensor Output: 3°C Accuracy
♦ Register for Aging Trim
♦ RST Input/Output
♦ 300-Mil, 20-Pin SO Package
2
®
through an I C bidirectional bus.
♦ Underwriters Laboratories (UL ) Recognized
A precision temperature-compensated voltage refer-
Ordering Information
ence and comparator circuit monitors the status of V
CC
PIN-
PACKAGE
TOP
MARK
to detect power failures, to provide a reset output, and
to automatically switch to the backup supply when nec-
essary. Additionally, the RST pin is monitored as a
pushbutton input for generating a µP reset.
PART
TEMP RANGE
DS3232S#
0°C to +70°C
20 SO
20 SO
DS3232
DS3232SN#
-40°C to +85°C
DS3232N
# Denotes a RoHS-compliant device that may include lead that
is exempt under the RoHS requirements. Lead finish is JESD97
Category e3, and is compatible with both lead-based and
lead-free soldering processes. A "#" anywhere on the top mark
denotes a RoHS-compliant device.
Applications
Utility Power Meters
GPS
Servers
Telematics
Typical Operating Circuit
Pin Configuration
TOP VIEW
V
CC
V
CC
R
PU
= t / C
R B
N.C.
N.C.
1
2
3
4
5
6
7
8
9
20 SCL
19 N.C.
18 SCL
17 SDA
V
CC
R
R
PU
PU
V
32kHz
CC
SCL
SDA
RST
N.C.
INT/SQW
32kHz
SCL
V
CC
SDA
RST
INT/SQW
RST
16
15 GND
14
V
BAT
DS3232
V
BAT
PUSH-
BUTTON
RESET
μP
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DS3232
N.C.
13 N.C.
12 N.C.
11 N.C.
N.C.
N.C.
N.C.
GND
N.C. 10
SO
UL is a registered trademark of Underwriters Laboratories, Inc.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range...............................-40°C to +85°C
Lead Temperature
Voltage Range on V , V
, 32kHz, SCL, SDA, RST,
CC BAT
INT/SQW Relative to Ground.............................-0.3V to +6.0V
(soldering, 10s) .....................................................+260°C/10s
Soldering Temperature (reflow, 2 times max) .......See IPC/JEDEC
J-STD-020 Specification
Operating Temperature Range
(noncondensing) .............................................-40°C to +85°C
Junction Temperature......................................................+125°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DS32
RECOMMENDED DC OPERATING CONDITIONS
(T = -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
2.3
2.3
TYP
3.3
MAX
5.5
UNITS
V
CC
V
V
BAT
3.0
5.5
0.7 x
V
+
0.3
CC
Logic 1 Input SDA, SCL
Logic 0 Input SDA, SCL
V
V
V
IH
V
CC
+0.3 x
V
V
-0.3
IL
CC
ELECTRICAL CHARACTERISTICS
(V
CC
= 2.3V to 5.5V, V
= active supply (see Table 1), T = -40°C to +85°C, unless otherwise noted.) (Typical values are at V
=
CC
CC
A
3.3V, V
= 3.0V, and T = +25°C, unless otherwise noted.) (Notes 1, 2)
BAT
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
200
UNITS
V
V
= 3.3V
= 5.5V
32kHz output off
CC
Active Supply Current
I
μA
CCA
(Notes 3, 4)
325
CC
2
I C bus inactive, 32kHz
V
V
= 3.3V
= 5.5V
120
160
CC
Standby Supply Current
I
output off, SQW output off
(Note 4)
μA
CCS
CC
2
V
V
= 3.3V
= 5.5V
500
600
2.70
I C bus inactive, 32kHz
CC
Temperature Conversion Current
Power-Fail Voltage
I
μA
V
CCSCONV
output off, SQW output off
CC
V
2.45
2.575
PF
ACTIVE SUPPLY (Table 1 ) (2.3V to 5.5V, T = -40°C to +85°C, unless otherwise noted) (Note 1)
A
Logic 1 Output, 32kHz
Active supply > 3.3V,
I
I
I
= -1mA
= -0.75mA
= -0.14mA
OH
OH
OH
3.3V > active supply > 2.7V,
2.7V > active supply > 2.3V
V
2.0
V
OH
2
_____________________________________________________________________
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
DS32
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.3V to 5.5V, V
= active supply (see Table 1), T = -40°C to +85°C, unless otherwise noted.) (Typical values are at V
=
CC
CC
A
3.3V, V
= 3.0V, and T = +25°C, unless otherwise noted.) (Notes 1, 2)
BAT
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.4
UNITS
Logic 0 Output, INT/SQW, SDA
Logic 0 Output, RST, 32kHz
V
V
I
I
= 3mA
= 1mA
V
V
OL
OL
OL
OL
0.4
Output Leakage Current 32kHz,
INT/SQW, SDA
I
Output high impedance
-1
0
+1
μA
LO
Input Leakage SCL
RST Pin I/O Leakage
TCXO
I
-1
+1
μA
μA
LI
I
RST high impedance (Note 5)
-200
+10
OL
Output Frequency
f
V
= 3.3V or V = 3.3V
BAT
32.768
kHz
%
OUT
CC
Duty Cycle
(Revision A3 Devices)
2.97V ꢀ V < 3.63
31
-2
69
+2
CC
0°C to +40°C
Frequency Stability vs.
Temperature
V = 3.3V or
CC
ꢁf/f
ppm
OUT
-40°C to 0°C and
+40°C to +85°C
V
BAT
= 3.3V
-3.5
+3.5
Frequency Stability vs. Voltage
ꢁf/V
V
= 3.3V or V
= 3.3V
= 3.3V
1
ppm/V
CC
BAT
-40°C
0.7
0.1
0.4
0.8
+25°C
+70°C
+85°C
Trim Register Frequency
Sensitivity per LSB
ꢁf/LSB
Specified at:
ppm
Temperature Accuracy
Crystal Aging
Temp
V
CC
= 3.3V or V
-3
+3
°C
BAT
First year
1.0
5.0
After reflow,
not production tested
ꢁf/f
ppm
0
0–10 years
ELECTRICAL CHARACTERISTICS
(V
CC
= 0V, V = 2.3V to 5.5V, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
BAT A
PARAMETER
SYMBOL
CONDITIONS
EOSC = 0, BBSQW = 0,
MIN
TYP
MAX
80
UNITS
V
V
= 3.3V
= 5.5V
Active Battery Current
(Note 4)
BAT
I
μA
BATA
SCL = 400kHz, BB32kHz = 0
200
BAT
EOSC = 0, BBSQW = 0,
SCL = SDA = 0V,
BB32kHz = 0,
V
= 3.4V
= 5.5V
1.5
1.5
2.5
3.0
BAT
BAT
Timekeeping Battery Current
(Note 4)
I
μA
BATT
V
CRATE0 = CRATE1 = 0
Temperature Conversion Current
Data-Retention Current
I
EOSC = 0, BBSQW = 0, SCL = SDA = 0V
EOSC = 1, SCL = SDA = 0V, +25°C
600
100
μA
nA
BATTC
I
BATTDR
_____________________________________________________________________
3
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
AC ELECTRICAL CHARACTERISTICS
(Active supply (see Table 1) = 2.3V to 5.5V, T = -40°C to +85°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
100
0.04
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
TYP
MAX
400
UNITS
Fast mode
SCL Clock Frequency
f
kHz
SCL
Standard mode
Fast mode
100
Bus Free Time Between STOP
and START Conditions
DS32
t
µs
µs
µs
µs
µs
ns
µs
ns
ns
µs
BUF
Standard mode
Fast mode
Hold Time (Repeated) START
Condition (Note 6)
t
HD:STA
Standard mode
Fast mode
25,000
25,000
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time (Notes 7, 8)
Data Setup Time (Note 9)
Start Setup Time
t
LOW
Standard mode
Fast mode
t
HIGH
Standard mode
Fast mode
0.9
0.9
t
HD:DAT
Standard mode
Fast mode
0
100
250
0.6
4.7
20 +
t
SU:DAT
Standard mode
Fast mode
t
SU:STA
Standard mode
Fast mode
300
1000
300
Rise Time of Both SDA and SCL
Signals (Note 10)
t
R
0.1C
Standard mode
Fast mode
B
Fall Time of Both SDA and SCL
Signals (Note 10)
20 +
t
F
0.1C
Standard mode
Fast mode
B
300
0.6
Setup Time for STOP Condition
t
SU:STO
Standard mode
4.7
Capacitive Load for Each Bus
Line (Note 10)
C
400
pF
pF
ns
B
Capacitance for SDA, SCL
C
10
30
I/O
SP
Pulse Width of Spikes That Must
Be Suppressed by the Input Filter
t
Pushbutton Debounce
Interface Timeout
PB
250
ms
ms
ms
ms
ms
DB
t
(Note 11)
(Note 12)
25
35
IF
Reset Active Time
t
250
100
125
RST
OSF
Oscillator Stop Flag (OSF) Delay
Temperature Conversion Time
t
t
200
CONV
POWER-SWITCH CHARACTERISTICS
(T = -40°C to +85°C)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Fall Time; V
to
to
CC
PF(MAX)
t
300
µs
VCCF
PF(MIN)
V
V
Rise Time; V
PF(MIN)
PF(MAX)
CC
t
0
µs
VCCR
Recovery at Power-Up
t
(Note 13)
125
300
ms
REC
4
_____________________________________________________________________
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
DS32
Pushbutton Reset Timing
RST
PB
DB
t
RST
Power-Switch Timing
V
CC
V
PF(MAX)
V
PF
V
PF
V
PF(MIN)
t
t
VCCR
VCCF
t
REC
RST
_____________________________________________________________________
5
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
2
Data Transfer on I C Serial Bus
SDA
SCL
DS32
t
BUF
t
t
F
SP
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
t
R
t
HD:STA
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH(MIN)
IL(MAX)
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may
cause loss of data.
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3:
I
—SCL clocking at max frequency = 400kHz.
CCA
Note 4: Current is the averaged input current, which includes the temperature conversion current.
Note 5: The RST pin has an internal 50kΩ (nominal) pullup resistor to V
Note 6: After this period, the first clock pulse is generated.
.
CC
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
of the SCL signal)
IH(MIN)
to bridge the undefined region of the falling edge of SCL.
Note 8: The maximum t
needs only to be met if the device does not stretch the low period (t
) of the SCL signal.
HD:DAT
LOW
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement t
≥ 250ns must then be met. This
SU:DAT
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line t
before the SCL line is released.
t
= 1000 + 250 = 1250ns
R(MAX)
SU:DAT
+
Note 10: C —total capacitance of one bus line in pF.
B
2
Note 11: Minimum operating frequency of the I C interface is imposed by the timeout period.
Note 12: The parameter t
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
OSF
CC(MAX)
0V ≤ V
≤ V
and 2.3V ≤ V
≤ 3.4V.
CC
BAT
Note 13: This delay only applies if the oscillator is enabled and running. If the EOSC bit is 1, t
is bypassed and RST immediately
REC
goes high.
6
_____________________________________________________________________
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
DS32
Typical Operating Characteristics
(V
CC
= +3.3V, T = +25°C, unless otherwise noted.)
A
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
150
125
100
75
1000
950
900
850
800
750
700
SCL = SDA = V
RST ACTIVE
CC
V
= 0V
CC
BB32kHz = 0
BBSQW = 0
BSY = 0
50
25
0
2.3
3.3
3.8
2.8
4.3
4.8
5.3
2.3
3.3
3.8
2.8
4.3
4.8
5.3
V
(V)
V
BAT
(V)
CC
SUPPLY CURRENT
vs. TEMPERATURE
FREQUENCY DEVIATION
vs. TEMPERATURE vs. AGING
0.900
0.800
0.700
75
V
= 0V
CC
65
55
45
35
25
15
5
BB32kHz = 0
AGING = -128
V
BAT
= 3.4V
AGING = -33
AGING = 0
V
BAT
= 3.0V
-5
-15
-25
-35
AGING = +127
AGING = +32
0.600
-45
-40
0
20
-20
40
60
80
-40
0
20
-20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
DELTA TIME AND FREQUENCY
vs. TEMPERATURE
DS3232 toc05
20
0
0
CRYSTAL
+20ppm
-20
-40
-60
-80
-20
-40
-60
-80
-100
TYPICAL CRYSTAL,
UNCOMPENSATED
-100
-120
-140
-160
-180
-200
DS3232
ACCURACY
BAND
CRYSTAL
-20ppm
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
_____________________________________________________________________
7
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
Block Diagram
32kHz
X1
X2
OSCILLATOR AND
CAPACITOR ARRAY
INT/SQW
DS32
N
SQUARE-WAVE BUFFER;
INT/SQW CONTROL
CONTROL LOGIC/
DIVIDER
V
CC
RST
VOLTAGE REFERENCE;
DEBOUNCE CIRCUIT;
PUSHBUTTON RESET
N
DS3232
V
CC
TEMPERATURE
SENSOR
CONTROL AND STATUS
REGISTERS
V
BAT
POWER CONTROL
GND
SRAM
SCL
SDA
2
I C INTERFACE AND
CLOCK AND CALENDAR
REGISTERS
ADDRESS REGISTER
DECODE
USER BUFFER
(7 BYTES)
alarm conditions or a square-wave output. The clock/cal-
endar provides seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format
with an AM/PM indicator. The internal registers are
Detailed Description
The DS3232 is a serial RTC driven by a temperature-
compensated 32kHz crystal oscillator. The TCXO pro-
vides a stable and accurate reference clock, and
maintains the RTC to within 2 minutes per year accu-
racy from -40°C to +85°C. The TCXO frequency output
is available at the 32kHz pin. The RTC is a low-power
clock/calendar with two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW provides either an interrupt signal due to
2
accessible though an I C bus interface.
A temperature-compensated voltage reference and
comparator circuit monitors the level of V
to detect
CC
8
_____________________________________________________________________
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
DS32
Pin Description
FUNCTION
PIN
NAME
1, 2,
7–14, 19
N.C.
No Connection. Not connected internally. Must be connected to ground.
32kHz Push-Pull Output. If disabled with either EN32kHz = 0 or BB32kHz = 0, the state of the 32kHz pin
will be low.
3
4
32kHz
V
CC
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1μF to 1.0μF capacitor.
Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor. It can
be left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control
Register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is
determined by RS2 and RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping
registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the
INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms
5
INT/SQW
disabled. The pullup voltage can be up to 5.5V, regardless of the voltage on V . If not used, this pin can
CC
be left floating.
Active-Low Reset. This pin is an open-drain input/output. It indicates the status of V relative to the
CC
V
specification. As V falls below V , the RST pin is driven low. When V exceeds V , for t
, the
PF
CC
PF
CC
PF
RST
RST pin is driven high impedance. The active-low, open-drain output is combined with a debounced
pushbutton input function. This pin can be activated by a pushbutton reset request. It has an internal 50kꢀ
nominal value pullup resistor to V . No external pullup resistors should be connected. If the crystal
6
RST
CC
oscillator is disabled, t
is bypassed and RST immediately goes high.
RST
15
16
GND
Ground
Backup Power-Supply Input. This pin should be decoupled using a 0.1μF to 1.0μF low-leakage capacitor.
2
If the I C interface is inactive whenever the device is powered by the V
input, the decoupling capacitor
BAT
V
BAT
is not required. If V
is not used, connect to ground. Diodes placed in series between the V
pin and
BAT
BAT
the battery can cause improper operation. UL recognized to ensure against reverse charging when used
with a lithium battery. Go to www.maxim-ic.com/qa/info/ul.
2
Serial-Data Input/Output. This pin is the data input/output for the I C serial interface. This open-drain pin
17
SDA
SCL
requires an external pullup resistor. The pullup voltage can be up to 5.5V, regardless of the voltage on V
2
.
CC
Serial-Clock Input. This pin is the clock input for the I C serial interface and is used to synchronize data
movement on the serial interface. A connection to only one of the pins is required. The other pin must be
connected to the same signal or be left floating. Up to 5.5V can be used for this pin, regardless of the
18, 20
voltage on V
.
CC
power failures and to automatically switch to the back-
up supply when necessary. The RST pin provides an
external pushbutton function and acts as an indicator of
a power-fail event. Also available are 236 bytes of gen-
eral-purpose battery-backed SRAM.
32kHz TCXO
The temperature sensor, oscillator, and control logic
form the TCXO. The controller reads the output of the
on-chip temperature sensor and uses a lookup table to
determine the capacitance required, adds the aging
correction in AGE register, and then sets the capaci-
tance selection registers. New values, including
changes to the AGE register, are loaded only when a
change in the temperature value occurs. The tempera-
Operation
The block diagram shows the main elements of the
DS3232. The eight blocks can be grouped into four
functional groups: TCXO, power control, pushbutton
function, and RTC. Their operations are described sep-
arately in the following sections.
ture is read on initial application of V
and once every
CC
64 seconds (default, see the description for CRATE1
and CRATE0 in the control/status register) afterwards.
_____________________________________________________________________
9
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
After the internal timer has expired (PB ), the DS3232
Power Control
This function is provided by a temperature-compensat-
ed voltage reference and a comparator circuit that
DB
continues to monitor the RST line. If the line is still low, the
DS3232 continuously monitors the line looking for a rising
edge. Upon detecting release, the DS3232 forces the
monitors the V
level. When V
is greater than V
,
CC
CC
PF
RST pin low and holds it low for t
.
the part is powered by V . When V
is less than V
RST
CC
CC
PF
but greater than V
, the DS3232 is powered by V
.
BAT
CC
, the
BAT
The same pin, RST, is used to indicate a power-fail con-
dition. When V is lower than V , an internal power-
If V
is less than V
and is less than V
. See Table 1.
CC
PF
BAT
CC
PF
DS32
device is powered by V
fail signal is generated, which forces the RST pin low.
When V returns to a level above V , the RST pin is
CC
PF
Table 1. Power Control
held low for t
to allow the power supply to stabilize.
REC
If the oscillator is not running (see the Power Control
section) when V is applied, t is bypassed and
SUPPLY CONDITION
POWERED BY
CC
REC
V
V
V
V
< V , V
< V
> V
< V
> V
V
BAT
CC
CC
CC
CC
PF CC
BAT
BAT
BAT
BAT
RST immediately goes high.
< V , V
V
PF CC
CC
CC
CC
Assertion of the RST output, whether by pushbutton or
power-fail detection, does not affect the internal opera-
tion of the DS3232.
> V , V
V
PF CC
> V , V
V
PF CC
Real-Time Clock
With the clock source from the TCXO, the RTC provides
seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is automati-
cally adjusted for months with fewer than 31 days, includ-
ing corrections for leap year. The clock operates in either
the 24-hour or 12-hour format with an AM/PM indicator.
To preserve the battery, the first time V
is applied to
BAT
the device, the oscillator does not start up and no tem-
perature conversions take place until V
exceeds V
PF
CC
2
or until a valid I C address is written to the part. After
the first time V
is ramped up, the oscillator starts up
CC
and the V
source powers the oscillator during
BAT
power-down and keeps the oscillator running. When
the DS3232 switches to V , the oscillator may be dis-
The clock provides two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW pin either generates an interrupt due to alarm
condition or outputs a square-wave signal and the
selection is controlled by the bit INTCN.
BAT
abled by setting the EOSC bit.
V
BAT
Operation
There are several modes of operation that affect the
amount of V
current that is drawn. While the device
SRAM
BAT
is powered by V
and the serial interface is active,
BAT
The DS3232 provides 236 bytes of general-purpose
2
active battery current, I
interface is inactive, timekeeping current (I
, is drawn. When the serial
BATA
battery-backed read/write memory. The I C address
), which
ranges from 14h to 0FFh. The SRAM can be written or
BATT
includes the averaged temperature conversion current,
, is used (refer to Application Note 3644: Power
read whenever V
or V
is greater than the mini-
BAT
CC
I
mum operating voltage.
BATTC
Considerations for Accurate Real-Time Clocks for
details). Temperature conversion current, I , is
Address Map
BATTC
specified since the system must be able to support the
periodic higher current pulse and still maintain a valid
Figure 1 shows the address map for the DS3232 time-
keeping registers. During a multibyte access, when the
address pointer reaches the end of the register space
voltage level. Data retention current, I
, is the
BATTDR
2
current drawn by the part when the oscillator is
stopped (EOSC = 1). This mode can be used to mini-
mize battery requirements for times when maintaining
time and date information is not necessary, e.g., while
the end system is waiting to be shipped to a customer.
(0FFh), it wraps around to location 00h. On an I C
START or address pointer incrementing to location 00h,
the current time is transferred to a second set of regis-
ters. The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.
Pushbutton Reset Function
The DS3232 provides for a pushbutton switch to be con-
nected to the RST output pin. When the DS3232 is not in
a reset cycle, it continuously monitors the RST signal for a
low going edge. If an edge transition is detected, the
DS3232 debounces the switch by pulling the RST low.
2
I C Interface
2
The I C interface is accessible whenever either V
or
CC
V
BAT
is at a valid level. If a microcontroller connected to
the DS3232 resets because of a loss of V
or other
CC
10
____________________________________________________________________
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
DS32
Figure 1. Address Map for DS3232 Timekeeping Registers and SRAM
BIT 7
MSB
BIT 0
LSB
ADDRESS
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
FUNCTION
RANGE
00h
01h
0
0
10 Seconds
10 Minutes
AM/PM
10 Hour
0
Seconds
Seconds
Minutes
00–59
00–59
Minutes
Hour
1–12 + AM/PM
02h
0
12/24
10 Hour
0
Hours
00–23
03h
04h
0
0
0
0
0
Day
Day
1–7
10 Date
Date
Month
Year
Date
1–31
Month/
Century
01–12 +
Century
05h
Century
0
0
10 Month
10 Hour
10 Hour
06h
07h
08h
10 Year
Year
00–99
00–59
00–59
A1M1
A1M2
10 Seconds
10 Minutes
AM/PM
Seconds
Minutes
Alarm 1 Seconds
Alarm 1 Minutes
1–12 + AM/PM
09h
A1M3
12/24
Hour
Alarm 1 Hours
00–23
10 Hour
Day
Date
Alarm 1 Day
Alarm 1 Date
1–7
0Ah
0Bh
0Ch
A1M4
A2M2
A2M3
DY/DT
10 Date
1–31
00–59
10 Minutes
AM/PM
Minutes
Alarm 2 Minutes
1–12 + AM/PM
12/24
Hour
Alarm 2 Hours
00–23
10 Hour
Day
Alarm 2 Day
Alarm 2 Date
Control
1–7
1–31
—
0Dh
A2M4
DY/DT
10 Date
Date
0Eh
0Fh
10h
11h
12h
EOSC
OSF
BBSQW
CONV
RS2
RS1
INTCN
BSY
A2IE
A2F
A1IE
A1F
BB32kHz CRATE1 CRATE0 EN32kHz
Control/Status
Aging Offset
MSB of Temp
LSB of Temp
—
SIGN
SIGN
DATA
DATA
DATA
DATA
DATA
DATA
0
DATA
DATA
0
DATA
DATA
0
DATA DATA
DATA DATA
DATA
DATA
0
—
—
0
0
x
0
0
x
—
Reserved for
test
13h
0
x
0
x
0
x
0
x
0
x
0
x
Not used
SRAM
14h–0FFh
00h–0FFh
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.
event, it is possible that the microcontroller and DS3232
being written to the device when the interface timeout is
exceeded, prior to the acknowledge, the incomplete
byte of data is not written.
2
I C communications could become unsynchronized,
e.g., the microcontroller resets while reading data from
the DS3232. When the microcontroller resets, the
Clock and Calendar
2
DS3232 I C interface may be placed into a known state
by toggling SCL until SDA is observed to be at a high
level. At that point the microcontroller should pull SDA
low while SCL is high, generating a START condition.
2
The time and calendar information is obtained by read-
ing the appropriate register bytes. Figure 1 illustrates
the RTC registers. The time and calendar data are set
or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in
binary-coded decimal (BCD) format. The DS3232 can
be run in either 12-hour or 24-hour mode. Bit 6 of the
If SCL is held low for greater than t , the internal I C
IF
interface is reset. This limits the minimum frequency at
2
which the I C interface can be operated. If data is
____________________________________________________________________ 11
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
hours register is defined as the 12- or 24-hour mode
select bit. When high, 12-hour mode is selected. In 12-
hour mode, bit 5 is the AM/PM bit with logic-high being
PM. In 24-hour mode, bit 5 is the second 10-hour bit
(20–23 hours). The century bit (bit 7 of the month regis-
ter) is toggled when the years register overflows from
99 to 00.
Alarms
The DS3232 contains two time-of-day/date alarms. Alarm
1 can be set by writing to registers 07h to 0Ah. Alarm 2
can be set by writing to registers 0Bh to 0Dh. The alarms
can be programmed (by the alarm enable and INTCN
bits of the control register) to activate the INT/SQW output
on an alarm match condition. Bit 7 of each of the time-of-
day/date alarm registers are mask bits (Table 2). When all
the mask bits for each alarm are logic 0, an alarm only
occurs when the values in the timekeeping registers
match the corresponding values stored in the time-of-
day/date alarm registers. The alarms can also be pro-
grammed to repeat every second, minute, hour, day, or
date. Table 2 shows the possible settings. Configurations
not listed in the table result in illogical operation.
DS32
The day-of-week register increments at midnight.
Values that correspond to the day of week are user-
defined but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
When reading or writing the time and date registers, sec-
ondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any START and when the register
pointer rolls over to zero. The time information is read
from these secondary registers, while the clock contin-
ues to run. This eliminates the need to reread the regis-
ters in case the main registers update during a read.
The DY/DT bits (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0 to 5 of
that register reflects the day of the week or the date of
the month. If DY/DT is written to logic 0, the alarm will
be the result of a match with date of the month. If
DY/DT is written to logic 1, the alarm will be the result of
a match with day of the week.
The countdown chain is reset whenever the seconds
register is written. Write transfers occur on the acknowl-
edge from the DS3232. Once the countdown chain is
reset, to avoid rollover issues the remaining time and
date registers must be written within 1 second. The 1Hz
square-wave output, if enabled, transitions high 500ms
after the seconds data transfer, provided the oscillator
is already running.
When the RTC register values match alarm register set-
tings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
set to logic 1. If the corresponding Alarm Interrupt
Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the
INTCN bit is set to logic 1, the alarm condition activates
the INT/SQW signal. The match is tested on the once-
per-second update of the time and date registers.
Table 2. Alarm Mask Bits
ALARM 1 REGISTER MASK BITS (BIT 7)
DY/DT
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
X
X
X
0
1
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Alarm once per second
Alarm when seconds match
Alarm when minutes and seconds match
Alarm when hours, minutes, and seconds match
Alarm when date, hours, minutes, and seconds match
Alarm when day, hours, minutes, and seconds match
ALARM 2 REGISTER MASK BITS (BIT 7)
DY/DT
ALARM RATE
A2M4
A2M3
A2M2
X
X
X
0
1
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Alarm once per minute (00 seconds of every minute)
Alarm when minutes match
Alarm when hours and minutes match
Alarm when date, hours, and minutes match
Alarm when day, hours, and minutes match
12
____________________________________________________________________
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
DS32
Control Register (0Eh)
BIT 7
EOSC
0
BIT 6
BBSQW
0
BIT 5
CONV
0
BIT 4
RS2
1
BIT 3
RS1
1
BIT 2
INTCN
1
BIT 1
A2IE
0
BIT 0
A1IE
0
NAME:
POR*:
*POR is defined as the first application of power to the device, either V
or V
.
BAT
CC
Bits 4 and 3: Rate Select (RS2 and RS1). These bits
control the frequency of the square-wave output when
the square wave has been enabled. The following table
shows the square-wave frequencies that can be select-
ed with the RS bits. These bits are both set to logic 1
(8.192kHz) when power is first applied.
Special-Purpose Registers
The DS3232 has two additional registers (control and
control/status) that control the real-time clock, alarms,
and square-wave output.
Control Register (0Eh)
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped when the DS3232 switches to battery
power. This bit is clear (logic 0) when power is first
SQUARE-WAVE OUTPUT FREQUENCY
SQUARE-WAVE OUTPUT
RS2
RS1
FREQUENCY
applied. When the DS3232 is powered by V , the
CC
0
0
1
1
0
1
0
1
1Hz
oscillator is always on regardless of the status of the
EOSC bit. When EOSC is disabled, all register data is
static.
1.024kHz
4.096kHz
8.192kHz
Bit 6: Battery-Backed Square-Wave Enable
(BBSQW). When set to logic 1 and the DS3232 is
Bit 2: Interrupt Control (INTCN). This bit controls the
INT/SQW signal. When the INTCN bit is set to logic 0, a
square wave is output on the INT/SQW pin. When the
INTCN bit is set to logic 1, a match between the time-
keeping registers and either of the alarm registers acti-
vates the INT/SQW (if the alarm is also enabled). The
corresponding alarm flag is always set regardless of
the state of the INTCN bit. The INTCN bit is set to logic
1 when power is first applied.
being powered by the V
pin, this bit enables the
BAT
square-wave output or interrupt when V
is absent.
CC
When BBSQW is logic 0, the INT/SQW pin goes high
impedance when V falls below the power-fail trip
CC
point. This bit is disabled (logic 0) when power is first
applied.
Bit 5: Convert Temperature (CONV). Setting this bit to
1 forces the temperature sensor to convert the temper-
ature into digital code and execute the TCXO algorithm
to update the capacitance array to the oscillator. This
can only happen when a conversion is not already in
progress. The user should check the status bit BSY
before forcing the controller to start a new TCXO exe-
cution. A user-initiated temperature conversion does
not affect the internal 64-second (default interval)
update cycle.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to
logic 1, this bit permits the alarm 2 flag (A2F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to
logic 1, this bit permits the alarm 1 flag (A1F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the INT/SQW sig-
nal. The A1IE bit is disabled (logic 0) when power is
first applied.
A user-initiated temperature conversion does not affect
the BSY bit for approximately 2ms. The CONV bit
remains at a 1 from the time it is written until the conver-
sion is finished, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring
the status of a user-initiated conversion.
____________________________________________________________________ 13
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
Control/Status Register (0Fh)
BIT 7
OSF
1
BIT 6
BB32kHz
1
BIT 5
CRATE1
0
BIT 4
CRATE0
0
BIT 3
EN32kHz
1
BIT 2
BSY
0
BIT 1
A2F
0
BIT 0
A1F
0
NAME:
POR*:
*POR is defined as the first application of power to the device, either V
or V
.
BAT
CC
DS32
Bit 3: Enable 32kHz Output (EN32kHz). This bit indi-
cates the status of the 32kHz pin. When set to logic 1,
the 32kHz pin is enabled and outputs a 32.768kHz
square-wave signal. When set to logic 0, the 32kHz pin
goes low. The initial power-up state of this bit is logic 1,
and a 32.768kHz square-wave signal appears at the
32kHz pin after a power source is applied to the DS3232
(if the oscillator is running).
Control/Status Register (0Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are
examples of conditions that can cause the OSF bit to
be set:
Bit 2: Busy (BSY). This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the conversion is complete.
1) The first time power is applied.
2) The voltages present on both V
insufficient to support oscillation.
and V
are
BAT
CC
3) The EOSC bit is turned off in battery-backed mode.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
4) External influences on the crystal (i.e., noise, leak-
age, etc.).
This bit remains at logic 1 until written to logic 0.
Bit 6: Battery-Backed 32kHz Output (BB32kHz). This
bit enables the 32kHz output when powered from V
BAT
(provided EN32kHz is enabled). If BB32kHz = 0, the
32kHz output is low when the part is powered by V
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 regis-
ters. If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A1F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
.
BAT
Bits 5 and 4: Conversion Rate (CRATE1 and
CRATE0). These two bits control the sample rate of the
TCXO. The sample rate determines how often the tem-
perature sensor makes a conversion and applies com-
pensation to the oscillator. Decreasing the sample rate
decreases the overall power consumption by decreas-
ing the frequency at which the temperature sensor
operates. However, significant temperature changes
that occur between samples may not be completely
compensated for, which reduce overall accuracy.
When a new conversion rate is written to the register, it
may take up to the new conversion rate time before the
conversions occur at the new rate.
SAMPLE RATE
CRATE1
CRATE0
(seconds)
0
0
1
1
0
1
0
1
64
128
256
512
14
____________________________________________________________________
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
DS32
Aging Offset (10h)
BIT 7
SIGN
0
BIT 6
DATA
0
BIT 5
DATA
0
BIT 4
DATA
0
BIT 3
DATA
0
BIT 2
DATA
0
BIT 1
DATA
0
BIT 0
DATA
0
NAME:
POR*:
Temperature Register (Upper Byte) (11h)
BIT 7
SIGN
0
BIT 6
DATA
0
BIT 5
DATA
0
BIT 4
DATA
0
BIT 3
DATA
0
BIT 2
DATA
0
BIT 1
DATA
0
BIT 0
DATA
0
NAME:
POR*:
Temperature Register (Lower Byte) (12h)
BIT 7
DATA
0
BIT 6
DATA
0
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
POR*:
0
0
0
0
0
0
0
0
0
0
0
0
SRAM (14h–FFh)
BIT 7
D7
BIT 6
D6
BIT 5
D5
BIT 4
D4
BIT 3
D3
BIT 2
D2
BIT 1
D1
BIT 0
D0
NAME:
POR*:
X
X
X
X
X
X
X
X
*POR is defined as the first application of power to the device, either V
or V
.
BAT
CC
one LSB typically provides about 0.1ppm change in
frequency.
Aging Offset Register
The aging offset register takes a user-provided value to
add to or subtract from the oscillator capacitor array.
The data is encoded in two’s complement, with bit 7
representing the sign bit. One LSB represents the
smallest capacitor to be switched in or out of the
capacitance array at the crystal pins. The aging offset
register capacitance value is added or subtracted from
the capacitance value that the device calculates for
each temperature compensation. The offset register is
added to the capacitance array during a normal tem-
perature conversion, if the temperature changes from
the previous conversion, or during a manual user con-
version (setting the CONV bit). To see the effects of the
aging register on the 32kHz output frequency immedi-
ately, a manual conversion should be started after each
aging offset register change.
Use of the aging register is not needed to achieve the
accuracy as defined in the EC tables, but could be
used to help compensate for aging at a given tempera-
ture. See the Typical Operating Characteristics section
for a graph showing the effect of the register on accu-
racy over temperature.
Temperature Registers (11h–12h)
Temperature is represented as a 10-bit code with a res-
olution of 0.25°C and is accessible at location 11h and
12h. The temperature is encoded in two’s complement
format, with bit 7 in the MSB representing the sign bit.
The upper 8 bits, the integer portion, are at location 11h
and the lower 2 bits, the fractional portion, are in the
upper nibble at location 12h. For example,
00011001 01b = +25.25°C. Upon power reset, the reg-
isters are set to a default temperature of 0°C and the
controller starts a temperature conversion.
Positive aging values add capacitance to the array,
slowing the oscillator frequency. Negative values
remove capacitance from the array, increasing the
oscillator frequency.
The temperature is read on initial application of V
or
CC
2
I C access on V
and once every 64 seconds after-
BAT
The change in ppm per LSB is different at different
temperatures. The frequency vs. temperature curve is
shifted by the values used in this register. At +25°C,
wards. The temperature registers are updated after
each user-initiated conversion and on every 64-second
conversion. The temperature registers are read-only.
____________________________________________________________________ 15
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
MSB FIRST
MSB
LSB
MSB
LSB
SDA
SLAVE
ADDRESS
R/W
8
ACK
9
DATA
ACK
9
DATA
ACK/
NACK
DS32
SCL
1–7
1–7
8
1–7
8
9
IDLE
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
STOP CONDITION
REPEATED START
2
Figure 2. I C Data Transfer Overview
2
Data valid: The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
I C Serial Data Bus
2
The DS3232 supports a bidirectional I C bus and data
transmission protocol. A device that sends data onto the
bus is defined as a transmitter and a device receiving
data is defined as a receiver. The device that controls the
message is called a master. The devices that are con-
trolled by the master are slaves. The bus must be con-
trolled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the START
and STOP conditions. The DS3232 operates as a slave
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and
the STOP conditions is not limited, and is determined
by the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
2
on the I C bus. Connections to the bus are made through
the SCL input and open-drain SDA I/O lines. Within the
bus specifications, a standard mode (100kHz maximum
clock rate) and a fast mode (400kHz maximum clock rate)
are defined. The DS3232 works in both modes.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse, which is associ-
ated with this acknowledge bit.
The following bus protocol has been defined (Figure 2):
• Data transfer may be initiated only when the bus is
not busy.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
• During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the state of the
data line from high to low, while the clock line is high,
defines a START condition.
Figures 3 and 4 detail how data transfer is accom-
2
plished on the I C bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
Stop data transfer: A change in the state of the data
line from low to high, while the clock line is high,
defines a STOP condition.
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
16
____________________________________________________________________
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
DS32
<SLAVE
ADDRESS> <R/W> <WORD ADDRESS (n)>
<DATA (n)>
XXXXXXXX
<DATA (n + 1)>
XXXXXXXX
<DATA (n + X)
XXXXXXXX
S
1101000 XXXXXXXX
0
A
A
A
A
A
P
...
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
SLAVE TO MASTER
MASTER TO SLAVE
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
Figure 3. Data Write—Slave Receiver Mode
<SLAVE
ADDRESS> <R/W>
<DATA (n)>
XXXXXXXX
<DATA (n + 1)>
<DATA (n + 2)>
XXXXXXXX
<DATA (n + X)>
XXXXXXXX
S
1101000
1
A
A
XXXXXXXX
A
A
A
P
...
S - START
MASTER TO SLAVE
SLAVE TO MASTER
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
Figure 4. Data Read—Slave Transmitter Mode
<SLAVE
ADDRESS> <R/W>
<WORD ADDRESS (n)> <SLAVE ADDRESS (n)> <R/W>
XXXXXXXX Sr 1101000 A
S
1101000
0
A
A
1
<DATA (n)>
XXXXXXXX
<DATA (n + 1)>
XXXXXXXX
<DATA (n + 2)>
XXXXXXXX
<DATA (n + X)>
XXXXXXXX
A
A
A
A
P
...
S - START
Sr - REPEATED START
A - ACKNOWLEDGE (ACK)
P - STOP
MASTER TO SLAVE
SLAVE TO MASTER
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
Figure 5. Data Write/Read (Write Pointer, Then Read)—Slave Receive and Transmit
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data is transferred with the most
significant bit (MSB) first.
bytes other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
The master device generates all the serial clock puls-
es and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated
START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the
bus will not be released. Data is transferred with the
most significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
____________________________________________________________________ 17
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
The DS3232 can operate in the following two modes:
START condition. The slave address byte contains
the 7-bit DS3232 address, which is 1101000, fol-
lowed by the direction bit (R/W), which is 1 for a
read. After receiving and decoding the slave
address byte, the DS3232 outputs an acknowledge
on SDA. The DS3232 then begins to transmit data
starting with the register address pointed to by the
register pointer. If the register pointer is not written to
before the initiation of a read mode, the first address
that is read is the last one stored in the register point-
er. The DS3232 must receive a not acknowledge to
end a read.
Slave receiver mode (DS3232 write mode): Serial
data and clock are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
Address recognition is performed by hardware after
reception of the slave address and direction bit. The
slave address byte is the first byte received after the
master generates the START condition. The slave
address byte contains the 7-bit DS3232 address,
which is 1101000, followed by the direction bit (R/W),
which is 0 for a write. After receiving and decoding
the slave address byte, the DS3232 outputs an
acknowledge on SDA. After the DS3232 acknowl-
edges the slave address + write bit, the master
transmits a word address to the DS3232. This sets
the register pointer on the DS3232, with the DS3232
acknowledging the transfer. The master may then
transmit zero or more bytes of data, with the DS3232
acknowledging each byte received. The register
pointer increments after each data byte is trans-
ferred. The master generates a STOP condition to
terminate the data write.
DS32
Handling, PC Board Layout,
and Assembly
The DS3232 package contains a quartz tuning-fork
crystal. Pick-and-place equipment can be used, but
precautions should be taken to ensure that excessive
shocks are avoided. Exposure to reflow is limited to 2
times maximum. Ultrasonic cleaning should be avoided
to prevent damage to the crystal.
Avoid running signal traces under the package, unless
a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connect-
ed to ground.
Slave transmitter mode (DS3232 read mode): The
first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction
bit indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the DS3232
while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave
address and direction bit. The slave address byte is
the first byte received after the master generates a
Chip Information
TRANSISTOR COUNT: 48,000
SUBSTRATE CONNECTED TO GROUND
PROCESS: CMOS
Thermal Information
Theta-JA: +55.1°C/W
Theta-JC: +24°C/W
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0042
20 SO
—
18
____________________________________________________________________
2
Extremely Accurate I C RTC with
Integrated Crystal and SRAM
DS32
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
9/05
Initial release.
—
1
11/05
Changed RoHS note wording for the Ordering Information table.
Corrected the Ordering Information part numbers.
1
Changed the reference of Figure 4 to Table 1 in the AC Electrical
Characteristics table.
4
7
Corrected the supply current units from μA to nA and added BSY = 0 to the
Supply Current vs. Supply Voltage graph in the Typical Operating
Characteristics.
2
3/06
Added a sentence about limiting exposure to reflow is 2 times maximum to the
Handling, PC Board Layout, and Assembly section.
17
3
Added the Duty Cycle (Revision A3 Devices) parameter to the Electrical
Characteristics table; added CRATE0 = CRATE1 = 0 conditions to I
.
BAT
Changed the RST pin description to indicate that the pin immediately goes high
if power is applied and the oscillator is disabled.
9
3
10/07
Added a paragraph to the Pushbutton Reset Function section about how the
RST output operation does not affect the device’s internal operation.
10
Corrected the date register range for 04h from 00–31 to 01–31 in Figure 1.
11
1
Updated the Typical Operating Circuit.
Removed the V parameter from the Recommended DC Operating Conditions
PU
table and added verbiage about the pullup to the Pin Description table for
INT/SQW, SDA, and SCL.
2, 9
3
In the Electrical Characteristics table, changed the symbols for Timekeeping
Battery Current, Temperature Conversion Current, and Data-Retention Current
from I
, I , and I
to I
, I
, and I
, respectively.
BAT TC
BATTC
BATT BATTC
BATTDR
4
10/08
Added the Delta Time and Frequency vs. Temperature graph in the Typical
Operating Characteristics section.
7
8
Updated the Block Diagram.
Added the V
Operation section and improved some sections of text for the
BAT
10, 15
17
Aging Offset Register and Temperature Registers (11h–12h) sections.
2
Updated the I C timing diagrams (Figures 3, 4, and 5).
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2008 Maxim Integrated Products
is a registered trademark of Dallas Semiconductor Corporation.
is a registered trademark of Maxim Integrated Products, Inc.
Marichu Quijano
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